1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* Linux PRO/1000 Ethernet Driver main header file */ 30 31 #ifndef _E1000_H_ 32 #define _E1000_H_ 33 34 #include <linux/bitops.h> 35 #include <linux/types.h> 36 #include <linux/timer.h> 37 #include <linux/workqueue.h> 38 #include <linux/io.h> 39 #include <linux/netdevice.h> 40 #include <linux/pci.h> 41 #include <linux/pci-aspm.h> 42 #include <linux/crc32.h> 43 #include <linux/if_vlan.h> 44 45 #include "hw.h" 46 47 struct e1000_info; 48 49 #define e_dbg(format, arg...) \ 50 netdev_dbg(hw->adapter->netdev, format, ## arg) 51 #define e_err(format, arg...) \ 52 netdev_err(adapter->netdev, format, ## arg) 53 #define e_info(format, arg...) \ 54 netdev_info(adapter->netdev, format, ## arg) 55 #define e_warn(format, arg...) \ 56 netdev_warn(adapter->netdev, format, ## arg) 57 #define e_notice(format, arg...) \ 58 netdev_notice(adapter->netdev, format, ## arg) 59 60 61 /* Interrupt modes, as used by the IntMode parameter */ 62 #define E1000E_INT_MODE_LEGACY 0 63 #define E1000E_INT_MODE_MSI 1 64 #define E1000E_INT_MODE_MSIX 2 65 66 /* Tx/Rx descriptor defines */ 67 #define E1000_DEFAULT_TXD 256 68 #define E1000_MAX_TXD 4096 69 #define E1000_MIN_TXD 64 70 71 #define E1000_DEFAULT_RXD 256 72 #define E1000_MAX_RXD 4096 73 #define E1000_MIN_RXD 64 74 75 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 76 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 77 78 /* Early Receive defines */ 79 #define E1000_ERT_2048 0x100 80 81 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 82 83 /* How many Tx Descriptors do we need to call netif_wake_queue ? */ 84 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 85 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 86 87 #define AUTO_ALL_MODES 0 88 #define E1000_EEPROM_APME 0x0400 89 90 #define E1000_MNG_VLAN_NONE (-1) 91 92 /* Number of packet split data buffers (not including the header buffer) */ 93 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 94 95 #define DEFAULT_JUMBO 9234 96 97 /* BM/HV Specific Registers */ 98 #define BM_PORT_CTRL_PAGE 769 99 100 #define PHY_UPPER_SHIFT 21 101 #define BM_PHY_REG(page, reg) \ 102 (((reg) & MAX_PHY_REG_ADDRESS) |\ 103 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 104 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 105 106 /* PHY Wakeup Registers and defines */ 107 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 108 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 109 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 110 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 111 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 112 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 113 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 114 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 115 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 116 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 117 118 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 119 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 120 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 121 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 122 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 123 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 124 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 125 126 #define HV_STATS_PAGE 778 127 #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */ 128 #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 129 #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */ 130 #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 131 #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */ 132 #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 133 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */ 134 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 135 #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */ 136 #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 137 #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 138 #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 139 #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */ 140 #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 141 142 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 143 144 /* BM PHY Copper Specific Status */ 145 #define BM_CS_STATUS 17 146 #define BM_CS_STATUS_LINK_UP 0x0400 147 #define BM_CS_STATUS_RESOLVED 0x0800 148 #define BM_CS_STATUS_SPEED_MASK 0xC000 149 #define BM_CS_STATUS_SPEED_1000 0x8000 150 151 /* 82577 Mobile Phy Status Register */ 152 #define HV_M_STATUS 26 153 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 154 #define HV_M_STATUS_SPEED_MASK 0x0300 155 #define HV_M_STATUS_SPEED_1000 0x0200 156 #define HV_M_STATUS_LINK_UP 0x0040 157 158 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 159 #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 160 161 /* Time to wait before putting the device into D3 if there's no link (in ms). */ 162 #define LINK_TIMEOUT 100 163 164 /* 165 * Count for polling __E1000_RESET condition every 10-20msec. 166 * Experimentation has shown the reset can take approximately 210msec. 167 */ 168 #define E1000_CHECK_RESET_COUNT 25 169 170 #define DEFAULT_RDTR 0 171 #define DEFAULT_RADV 8 172 #define BURST_RDTR 0x20 173 #define BURST_RADV 0x20 174 175 /* 176 * in the case of WTHRESH, it appears at least the 82571/2 hardware 177 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 178 * WTHRESH=4, and since we want 64 bytes at a time written back, set 179 * it to 5 180 */ 181 #define E1000_TXDCTL_DMA_BURST_ENABLE \ 182 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 183 E1000_TXDCTL_COUNT_DESC | \ 184 (5 << 16) | /* wthresh must be +1 more than desired */\ 185 (1 << 8) | /* hthresh */ \ 186 0x1f) /* pthresh */ 187 188 #define E1000_RXDCTL_DMA_BURST_ENABLE \ 189 (0x01000000 | /* set descriptor granularity */ \ 190 (4 << 16) | /* set writeback threshold */ \ 191 (4 << 8) | /* set prefetch threshold */ \ 192 0x20) /* set hthresh */ 193 194 #define E1000_TIDV_FPD (1 << 31) 195 #define E1000_RDTR_FPD (1 << 31) 196 197 enum e1000_boards { 198 board_82571, 199 board_82572, 200 board_82573, 201 board_82574, 202 board_82583, 203 board_80003es2lan, 204 board_ich8lan, 205 board_ich9lan, 206 board_ich10lan, 207 board_pchlan, 208 board_pch2lan, 209 board_pch_lpt, 210 }; 211 212 struct e1000_ps_page { 213 struct page *page; 214 u64 dma; /* must be u64 - written to hw */ 215 }; 216 217 /* 218 * wrappers around a pointer to a socket buffer, 219 * so a DMA handle can be stored along with the buffer 220 */ 221 struct e1000_buffer { 222 dma_addr_t dma; 223 struct sk_buff *skb; 224 union { 225 /* Tx */ 226 struct { 227 unsigned long time_stamp; 228 u16 length; 229 u16 next_to_watch; 230 unsigned int segs; 231 unsigned int bytecount; 232 u16 mapped_as_page; 233 }; 234 /* Rx */ 235 struct { 236 /* arrays of page information for packet split */ 237 struct e1000_ps_page *ps_pages; 238 struct page *page; 239 }; 240 }; 241 }; 242 243 struct e1000_ring { 244 struct e1000_adapter *adapter; /* back pointer to adapter */ 245 void *desc; /* pointer to ring memory */ 246 dma_addr_t dma; /* phys address of ring */ 247 unsigned int size; /* length of ring in bytes */ 248 unsigned int count; /* number of desc. in ring */ 249 250 u16 next_to_use; 251 u16 next_to_clean; 252 253 void __iomem *head; 254 void __iomem *tail; 255 256 /* array of buffer information structs */ 257 struct e1000_buffer *buffer_info; 258 259 char name[IFNAMSIZ + 5]; 260 u32 ims_val; 261 u32 itr_val; 262 void __iomem *itr_register; 263 int set_itr; 264 265 struct sk_buff *rx_skb_top; 266 }; 267 268 /* PHY register snapshot values */ 269 struct e1000_phy_regs { 270 u16 bmcr; /* basic mode control register */ 271 u16 bmsr; /* basic mode status register */ 272 u16 advertise; /* auto-negotiation advertisement */ 273 u16 lpa; /* link partner ability register */ 274 u16 expansion; /* auto-negotiation expansion reg */ 275 u16 ctrl1000; /* 1000BASE-T control register */ 276 u16 stat1000; /* 1000BASE-T status register */ 277 u16 estatus; /* extended status register */ 278 }; 279 280 /* board specific private data structure */ 281 struct e1000_adapter { 282 struct timer_list watchdog_timer; 283 struct timer_list phy_info_timer; 284 struct timer_list blink_timer; 285 286 struct work_struct reset_task; 287 struct work_struct watchdog_task; 288 289 const struct e1000_info *ei; 290 291 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 292 u32 bd_number; 293 u32 rx_buffer_len; 294 u16 mng_vlan_id; 295 u16 link_speed; 296 u16 link_duplex; 297 u16 eeprom_vers; 298 299 /* track device up/down/testing state */ 300 unsigned long state; 301 302 /* Interrupt Throttle Rate */ 303 u32 itr; 304 u32 itr_setting; 305 u16 tx_itr; 306 u16 rx_itr; 307 308 /* 309 * Tx 310 */ 311 struct e1000_ring *tx_ring /* One per active queue */ 312 ____cacheline_aligned_in_smp; 313 u32 tx_fifo_limit; 314 315 struct napi_struct napi; 316 317 unsigned int restart_queue; 318 u32 txd_cmd; 319 320 bool detect_tx_hung; 321 bool tx_hang_recheck; 322 u8 tx_timeout_factor; 323 324 u32 tx_int_delay; 325 u32 tx_abs_int_delay; 326 327 unsigned int total_tx_bytes; 328 unsigned int total_tx_packets; 329 unsigned int total_rx_bytes; 330 unsigned int total_rx_packets; 331 332 /* Tx stats */ 333 u64 tpt_old; 334 u64 colc_old; 335 u32 gotc; 336 u64 gotc_old; 337 u32 tx_timeout_count; 338 u32 tx_fifo_head; 339 u32 tx_head_addr; 340 u32 tx_fifo_size; 341 u32 tx_dma_failed; 342 343 /* 344 * Rx 345 */ 346 bool (*clean_rx) (struct e1000_ring *ring, int *work_done, 347 int work_to_do) ____cacheline_aligned_in_smp; 348 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count, 349 gfp_t gfp); 350 struct e1000_ring *rx_ring; 351 352 u32 rx_int_delay; 353 u32 rx_abs_int_delay; 354 355 /* Rx stats */ 356 u64 hw_csum_err; 357 u64 hw_csum_good; 358 u64 rx_hdr_split; 359 u32 gorc; 360 u64 gorc_old; 361 u32 alloc_rx_buff_failed; 362 u32 rx_dma_failed; 363 364 unsigned int rx_ps_pages; 365 u16 rx_ps_bsize0; 366 u32 max_frame_size; 367 u32 min_frame_size; 368 369 /* OS defined structs */ 370 struct net_device *netdev; 371 struct pci_dev *pdev; 372 373 /* structs defined in e1000_hw.h */ 374 struct e1000_hw hw; 375 376 spinlock_t stats64_lock; 377 struct e1000_hw_stats stats; 378 struct e1000_phy_info phy_info; 379 struct e1000_phy_stats phy_stats; 380 381 /* Snapshot of PHY registers */ 382 struct e1000_phy_regs phy_regs; 383 384 struct e1000_ring test_tx_ring; 385 struct e1000_ring test_rx_ring; 386 u32 test_icr; 387 388 u32 msg_enable; 389 unsigned int num_vectors; 390 struct msix_entry *msix_entries; 391 int int_mode; 392 u32 eiac_mask; 393 394 u32 eeprom_wol; 395 u32 wol; 396 u32 pba; 397 u32 max_hw_frame_size; 398 399 bool fc_autoneg; 400 401 unsigned int flags; 402 unsigned int flags2; 403 struct work_struct downshift_task; 404 struct work_struct update_phy_task; 405 struct work_struct print_hang_task; 406 407 bool idle_check; 408 int phy_hang_count; 409 410 u16 tx_ring_count; 411 u16 rx_ring_count; 412 }; 413 414 struct e1000_info { 415 enum e1000_mac_type mac; 416 unsigned int flags; 417 unsigned int flags2; 418 u32 pba; 419 u32 max_hw_frame_size; 420 s32 (*get_variants)(struct e1000_adapter *); 421 const struct e1000_mac_operations *mac_ops; 422 const struct e1000_phy_operations *phy_ops; 423 const struct e1000_nvm_operations *nvm_ops; 424 }; 425 426 /* hardware capability, feature, and workaround flags */ 427 #define FLAG_HAS_AMT (1 << 0) 428 #define FLAG_HAS_FLASH (1 << 1) 429 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2) 430 #define FLAG_HAS_WOL (1 << 3) 431 /* reserved bit4 */ 432 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) 433 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) 434 #define FLAG_HAS_JUMBO_FRAMES (1 << 7) 435 #define FLAG_READ_ONLY_NVM (1 << 8) 436 #define FLAG_IS_ICH (1 << 9) 437 #define FLAG_HAS_MSIX (1 << 10) 438 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) 439 #define FLAG_IS_QUAD_PORT_A (1 << 12) 440 #define FLAG_IS_QUAD_PORT (1 << 13) 441 /* reserved bit14 */ 442 #define FLAG_APME_IN_WUC (1 << 15) 443 #define FLAG_APME_IN_CTRL3 (1 << 16) 444 #define FLAG_APME_CHECK_PORT_B (1 << 17) 445 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) 446 #define FLAG_NO_WAKE_UCAST (1 << 19) 447 #define FLAG_MNG_PT_ENABLED (1 << 20) 448 #define FLAG_RESET_OVERWRITES_LAA (1 << 21) 449 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22) 450 #define FLAG_TARC_SET_BIT_ZERO (1 << 23) 451 #define FLAG_RX_NEEDS_RESTART (1 << 24) 452 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25) 453 #define FLAG_SMART_POWER_DOWN (1 << 26) 454 #define FLAG_MSI_ENABLED (1 << 27) 455 /* reserved (1 << 28) */ 456 #define FLAG_TSO_FORCE (1 << 29) 457 #define FLAG_RX_RESTART_NOW (1 << 30) 458 #define FLAG_MSI_TEST_FAILED (1 << 31) 459 460 #define FLAG2_CRC_STRIPPING (1 << 0) 461 #define FLAG2_HAS_PHY_WAKEUP (1 << 1) 462 #define FLAG2_IS_DISCARDING (1 << 2) 463 #define FLAG2_DISABLE_ASPM_L1 (1 << 3) 464 #define FLAG2_HAS_PHY_STATS (1 << 4) 465 #define FLAG2_HAS_EEE (1 << 5) 466 #define FLAG2_DMA_BURST (1 << 6) 467 #define FLAG2_DISABLE_ASPM_L0S (1 << 7) 468 #define FLAG2_DISABLE_AIM (1 << 8) 469 #define FLAG2_CHECK_PHY_HANG (1 << 9) 470 #define FLAG2_NO_DISABLE_RX (1 << 10) 471 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11) 472 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12) 473 474 #define E1000_RX_DESC_PS(R, i) \ 475 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 476 #define E1000_RX_DESC_EXT(R, i) \ 477 (&(((union e1000_rx_desc_extended *)((R).desc))[i])) 478 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 479 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 480 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) 481 482 enum e1000_state_t { 483 __E1000_TESTING, 484 __E1000_RESETTING, 485 __E1000_ACCESS_SHARED_RESOURCE, 486 __E1000_DOWN 487 }; 488 489 enum latency_range { 490 lowest_latency = 0, 491 low_latency = 1, 492 bulk_latency = 2, 493 latency_invalid = 255 494 }; 495 496 extern char e1000e_driver_name[]; 497 extern const char e1000e_driver_version[]; 498 499 extern void e1000e_check_options(struct e1000_adapter *adapter); 500 extern void e1000e_set_ethtool_ops(struct net_device *netdev); 501 502 extern int e1000e_up(struct e1000_adapter *adapter); 503 extern void e1000e_down(struct e1000_adapter *adapter); 504 extern void e1000e_reinit_locked(struct e1000_adapter *adapter); 505 extern void e1000e_reset(struct e1000_adapter *adapter); 506 extern void e1000e_power_up_phy(struct e1000_adapter *adapter); 507 extern int e1000e_setup_rx_resources(struct e1000_ring *ring); 508 extern int e1000e_setup_tx_resources(struct e1000_ring *ring); 509 extern void e1000e_free_rx_resources(struct e1000_ring *ring); 510 extern void e1000e_free_tx_resources(struct e1000_ring *ring); 511 extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, 512 struct rtnl_link_stats64 513 *stats); 514 extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); 515 extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); 516 extern void e1000e_get_hw_control(struct e1000_adapter *adapter); 517 extern void e1000e_release_hw_control(struct e1000_adapter *adapter); 518 extern void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); 519 520 extern unsigned int copybreak; 521 522 extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw); 523 524 extern const struct e1000_info e1000_82571_info; 525 extern const struct e1000_info e1000_82572_info; 526 extern const struct e1000_info e1000_82573_info; 527 extern const struct e1000_info e1000_82574_info; 528 extern const struct e1000_info e1000_82583_info; 529 extern const struct e1000_info e1000_ich8_info; 530 extern const struct e1000_info e1000_ich9_info; 531 extern const struct e1000_info e1000_ich10_info; 532 extern const struct e1000_info e1000_pch_info; 533 extern const struct e1000_info e1000_pch2_info; 534 extern const struct e1000_info e1000_pch_lpt_info; 535 extern const struct e1000_info e1000_es2_info; 536 537 extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 538 u32 pba_num_size); 539 540 extern s32 e1000e_commit_phy(struct e1000_hw *hw); 541 542 extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); 543 544 extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw); 545 extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); 546 547 extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); 548 extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 549 bool state); 550 extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 551 extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 552 extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 553 extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); 554 extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 555 extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 556 extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 557 558 extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw); 559 extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); 560 extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); 561 extern s32 e1000e_setup_led_generic(struct e1000_hw *hw); 562 extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); 563 extern s32 e1000e_led_on_generic(struct e1000_hw *hw); 564 extern s32 e1000e_led_off_generic(struct e1000_hw *hw); 565 extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw); 566 extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 567 extern void e1000_set_lan_id_single_port(struct e1000_hw *hw); 568 extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex); 569 extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex); 570 extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw); 571 extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw); 572 extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw); 573 extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw); 574 extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); 575 extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); 576 extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); 577 extern s32 e1000e_setup_link_generic(struct e1000_hw *hw); 578 extern void e1000_clear_vfta_generic(struct e1000_hw *hw); 579 extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); 580 extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 581 u8 *mc_addr_list, 582 u32 mc_addr_count); 583 extern void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 584 extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); 585 extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); 586 extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); 587 extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data); 588 extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw); 589 extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); 590 extern s32 e1000e_force_mac_fc(struct e1000_hw *hw); 591 extern s32 e1000e_blink_led_generic(struct e1000_hw *hw); 592 extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); 593 extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw); 594 extern void e1000e_reset_adaptive(struct e1000_hw *hw); 595 extern void e1000e_update_adaptive(struct e1000_hw *hw); 596 597 extern s32 e1000e_setup_copper_link(struct e1000_hw *hw); 598 extern s32 e1000e_get_phy_id(struct e1000_hw *hw); 599 extern void e1000e_put_hw_semaphore(struct e1000_hw *hw); 600 extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); 601 extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); 602 extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); 603 extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); 604 extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 605 extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 606 extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, 607 u16 *data); 608 extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); 609 extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); 610 extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 611 extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, 612 u16 data); 613 extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw); 614 extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); 615 extern s32 e1000e_get_cfg_done(struct e1000_hw *hw); 616 extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); 617 extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); 618 extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 619 extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 620 extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); 621 extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); 622 extern s32 e1000e_determine_phy_address(struct e1000_hw *hw); 623 extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 624 extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 625 extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, 626 u16 *phy_reg); 627 extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, 628 u16 *phy_reg); 629 extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 630 extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 631 extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 632 extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); 633 extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, 634 u16 data); 635 extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); 636 extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, 637 u16 *data); 638 extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 639 u32 usec_interval, bool *success); 640 extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); 641 extern void e1000_power_up_phy_copper(struct e1000_hw *hw); 642 extern void e1000_power_down_phy_copper(struct e1000_hw *hw); 643 extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 644 extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 645 extern s32 e1000e_check_downshift(struct e1000_hw *hw); 646 extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 647 extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, 648 u16 *data); 649 extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, 650 u16 *data); 651 extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 652 extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, 653 u16 data); 654 extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, 655 u16 data); 656 extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 657 extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 658 extern s32 e1000_check_polarity_82577(struct e1000_hw *hw); 659 extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 660 extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 661 extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 662 663 extern s32 e1000_check_polarity_m88(struct e1000_hw *hw); 664 extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw); 665 extern s32 e1000_check_polarity_ife(struct e1000_hw *hw); 666 extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 667 extern s32 e1000_check_polarity_igp(struct e1000_hw *hw); 668 extern bool e1000_check_phy_82574(struct e1000_hw *hw); 669 670 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 671 { 672 return hw->phy.ops.reset(hw); 673 } 674 675 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 676 { 677 return hw->phy.ops.read_reg(hw, offset, data); 678 } 679 680 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) 681 { 682 return hw->phy.ops.read_reg_locked(hw, offset, data); 683 } 684 685 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 686 { 687 return hw->phy.ops.write_reg(hw, offset, data); 688 } 689 690 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) 691 { 692 return hw->phy.ops.write_reg_locked(hw, offset, data); 693 } 694 695 static inline s32 e1000_get_cable_length(struct e1000_hw *hw) 696 { 697 return hw->phy.ops.get_cable_length(hw); 698 } 699 700 extern s32 e1000e_acquire_nvm(struct e1000_hw *hw); 701 extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 702 extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw); 703 extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); 704 extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 705 extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw); 706 extern void e1000e_release_nvm(struct e1000_hw *hw); 707 extern void e1000e_reload_nvm_generic(struct e1000_hw *hw); 708 extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); 709 710 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 711 { 712 if (hw->mac.ops.read_mac_addr) 713 return hw->mac.ops.read_mac_addr(hw); 714 715 return e1000_read_mac_addr_generic(hw); 716 } 717 718 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 719 { 720 return hw->nvm.ops.validate(hw); 721 } 722 723 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 724 { 725 return hw->nvm.ops.update(hw); 726 } 727 728 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 729 { 730 return hw->nvm.ops.read(hw, offset, words, data); 731 } 732 733 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 734 { 735 return hw->nvm.ops.write(hw, offset, words, data); 736 } 737 738 static inline s32 e1000_get_phy_info(struct e1000_hw *hw) 739 { 740 return hw->phy.ops.get_info(hw); 741 } 742 743 extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); 744 extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); 745 extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); 746 747 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 748 { 749 return readl(hw->hw_addr + reg); 750 } 751 752 #define er32(reg) __er32(hw, E1000_##reg) 753 754 /** 755 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 756 * @hw: pointer to the HW structure 757 * 758 * When updating the MAC CSR registers, the Manageability Engine (ME) could 759 * be accessing the registers at the same time. Normally, this is handled in 760 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 761 * accesses later than it should which could result in the register to have 762 * an incorrect value. Workaround this by checking the FWSM register which 763 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 764 * and try again a number of times. 765 **/ 766 static inline s32 __ew32_prepare(struct e1000_hw *hw) 767 { 768 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 769 770 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 771 udelay(50); 772 773 return i; 774 } 775 776 static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 777 { 778 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 779 __ew32_prepare(hw); 780 781 writel(val, hw->hw_addr + reg); 782 } 783 784 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) 785 786 #define e1e_flush() er32(STATUS) 787 788 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 789 (__ew32((a), (reg + ((offset) << 2)), (value))) 790 791 #define E1000_READ_REG_ARRAY(a, reg, offset) \ 792 (readl((a)->hw_addr + reg + ((offset) << 2))) 793 794 #endif /* _E1000_H_ */ 795