1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _E1000_DEFINES_H_ 30 #define _E1000_DEFINES_H_ 31 32 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 33 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 34 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 35 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 36 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 37 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 38 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 39 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 40 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 41 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 42 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 43 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 44 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 45 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 46 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 47 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 48 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 49 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 50 51 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 52 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 53 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 54 55 /* Definitions for power management and wakeup registers */ 56 /* Wake Up Control */ 57 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 58 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 59 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 60 61 /* Wake Up Filter Control */ 62 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 63 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 64 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 65 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 66 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 67 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 68 69 /* Wake Up Status */ 70 #define E1000_WUS_LNKC E1000_WUFC_LNKC 71 #define E1000_WUS_MAG E1000_WUFC_MAG 72 #define E1000_WUS_EX E1000_WUFC_EX 73 #define E1000_WUS_MC E1000_WUFC_MC 74 #define E1000_WUS_BC E1000_WUFC_BC 75 76 /* Extended Device Control */ 77 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 78 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 79 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 80 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 81 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 82 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 83 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 84 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 85 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 86 #define E1000_CTRL_EXT_EIAME 0x01000000 87 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 88 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 89 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 90 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 91 #define E1000_CTRL_EXT_LSECCK 0x00001000 92 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 93 94 /* Receive Descriptor bit definitions */ 95 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 96 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 97 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 98 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 99 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 100 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 101 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 102 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 103 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 104 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 105 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 106 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 107 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 108 109 #define E1000_RXDEXT_STATERR_CE 0x01000000 110 #define E1000_RXDEXT_STATERR_SE 0x02000000 111 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 112 #define E1000_RXDEXT_STATERR_CXE 0x10000000 113 #define E1000_RXDEXT_STATERR_RXE 0x80000000 114 115 /* mask to determine if packets should be dropped due to frame errors */ 116 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 117 E1000_RXD_ERR_CE | \ 118 E1000_RXD_ERR_SE | \ 119 E1000_RXD_ERR_SEQ | \ 120 E1000_RXD_ERR_CXE | \ 121 E1000_RXD_ERR_RXE) 122 123 /* Same mask, but for extended and packet split descriptors */ 124 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 125 E1000_RXDEXT_STATERR_CE | \ 126 E1000_RXDEXT_STATERR_SE | \ 127 E1000_RXDEXT_STATERR_SEQ | \ 128 E1000_RXDEXT_STATERR_CXE | \ 129 E1000_RXDEXT_STATERR_RXE) 130 131 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 132 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 133 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 134 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 135 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 136 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 137 138 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 139 140 /* Management Control */ 141 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 142 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 143 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 144 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 145 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 146 /* Enable MAC address filtering */ 147 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 148 /* Enable MNG packets to host memory */ 149 #define E1000_MANC_EN_MNG2HOST 0x00200000 150 151 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 152 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 153 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 154 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 155 156 /* Receive Control */ 157 #define E1000_RCTL_EN 0x00000002 /* enable */ 158 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 159 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 160 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 161 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 162 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 163 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 164 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 165 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 166 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 167 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 168 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 169 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 170 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 171 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 172 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 173 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 174 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 175 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 176 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 177 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 178 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 179 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 180 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 181 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 182 #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 183 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 184 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 185 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 186 187 /* 188 * Use byte values for the following shift parameters 189 * Usage: 190 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 191 * E1000_PSRCTL_BSIZE0_MASK) | 192 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 193 * E1000_PSRCTL_BSIZE1_MASK) | 194 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 195 * E1000_PSRCTL_BSIZE2_MASK) | 196 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 197 * E1000_PSRCTL_BSIZE3_MASK)) 198 * where value0 = [128..16256], default=256 199 * value1 = [1024..64512], default=4096 200 * value2 = [0..64512], default=4096 201 * value3 = [0..64512], default=0 202 */ 203 204 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 205 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 206 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 207 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 208 209 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 210 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 211 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 212 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 213 214 /* SWFW_SYNC Definitions */ 215 #define E1000_SWFW_EEP_SM 0x1 216 #define E1000_SWFW_PHY0_SM 0x2 217 #define E1000_SWFW_PHY1_SM 0x4 218 #define E1000_SWFW_CSR_SM 0x8 219 220 /* Device Control */ 221 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 222 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 223 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 224 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 225 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 226 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 227 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 228 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 229 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 230 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 231 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 232 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 233 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 234 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 235 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 236 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 237 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 238 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 239 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 240 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 241 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 242 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 243 244 /* 245 * Bit definitions for the Management Data IO (MDIO) and Management Data 246 * Clock (MDC) pins in the Device Control Register. 247 */ 248 249 /* Device Status */ 250 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 251 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 252 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 253 #define E1000_STATUS_FUNC_SHIFT 2 254 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 255 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 256 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 257 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 258 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 259 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 260 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 261 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 262 263 /* Constants used to interpret the masked PCI-X bus speed. */ 264 265 #define HALF_DUPLEX 1 266 #define FULL_DUPLEX 2 267 268 269 #define ADVERTISE_10_HALF 0x0001 270 #define ADVERTISE_10_FULL 0x0002 271 #define ADVERTISE_100_HALF 0x0004 272 #define ADVERTISE_100_FULL 0x0008 273 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 274 #define ADVERTISE_1000_FULL 0x0020 275 276 /* 1000/H is not supported, nor spec-compliant. */ 277 #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 278 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 279 ADVERTISE_1000_FULL) 280 #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 281 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 282 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 283 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 284 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 285 286 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 287 288 /* LED Control */ 289 #define E1000_PHY_LED0_MODE_MASK 0x00000007 290 #define E1000_PHY_LED0_IVRT 0x00000008 291 #define E1000_PHY_LED0_MASK 0x0000001F 292 293 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 294 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 295 #define E1000_LEDCTL_LED0_IVRT 0x00000040 296 #define E1000_LEDCTL_LED0_BLINK 0x00000080 297 298 #define E1000_LEDCTL_MODE_LINK_UP 0x2 299 #define E1000_LEDCTL_MODE_LED_ON 0xE 300 #define E1000_LEDCTL_MODE_LED_OFF 0xF 301 302 /* Transmit Descriptor bit definitions */ 303 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 304 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 305 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 306 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 307 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 308 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 309 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 310 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 311 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 312 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 313 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 314 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 315 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 316 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 317 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 318 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 319 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 320 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 321 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 322 323 /* Transmit Control */ 324 #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 325 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 326 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 327 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 328 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 329 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 330 331 /* Transmit Arbitration Count */ 332 333 /* SerDes Control */ 334 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 335 336 /* Receive Checksum Control */ 337 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 338 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 339 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 340 341 /* Header split receive */ 342 #define E1000_RFCTL_NFSW_DIS 0x00000040 343 #define E1000_RFCTL_NFSR_DIS 0x00000080 344 #define E1000_RFCTL_ACK_DIS 0x00001000 345 #define E1000_RFCTL_EXTEN 0x00008000 346 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 347 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 348 349 /* Collision related configuration parameters */ 350 #define E1000_COLLISION_THRESHOLD 15 351 #define E1000_CT_SHIFT 4 352 #define E1000_COLLISION_DISTANCE 63 353 #define E1000_COLD_SHIFT 12 354 355 /* Default values for the transmit IPG register */ 356 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 357 358 #define E1000_TIPG_IPGT_MASK 0x000003FF 359 360 #define DEFAULT_82543_TIPG_IPGR1 8 361 #define E1000_TIPG_IPGR1_SHIFT 10 362 363 #define DEFAULT_82543_TIPG_IPGR2 6 364 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 365 #define E1000_TIPG_IPGR2_SHIFT 20 366 367 #define MAX_JUMBO_FRAME_SIZE 0x3F00 368 369 /* Extended Configuration Control and Size */ 370 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 371 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 372 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 373 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 374 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 375 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 376 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 377 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 378 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 379 380 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 381 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 382 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 383 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 384 385 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 386 387 /* PBA constants */ 388 #define E1000_PBA_8K 0x0008 /* 8KB */ 389 #define E1000_PBA_16K 0x0010 /* 16KB */ 390 391 #define E1000_PBS_16K E1000_PBA_16K 392 393 #define IFS_MAX 80 394 #define IFS_MIN 40 395 #define IFS_RATIO 4 396 #define IFS_STEP 10 397 #define MIN_NUM_XMITS 1000 398 399 /* SW Semaphore Register */ 400 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 401 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 402 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 403 404 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 405 406 /* Interrupt Cause Read */ 407 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 408 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 409 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 410 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 411 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 412 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 413 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 414 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 415 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 416 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 417 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 418 419 /* PBA ECC Register */ 420 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 421 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 422 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ 423 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 424 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 425 426 /* 427 * This defines the bits that are set in the Interrupt Mask 428 * Set/Read Register. Each bit is documented below: 429 * o RXT0 = Receiver Timer Interrupt (ring 0) 430 * o TXDW = Transmit Descriptor Written Back 431 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 432 * o RXSEQ = Receive Sequence Error 433 * o LSC = Link Status Change 434 */ 435 #define IMS_ENABLE_MASK ( \ 436 E1000_IMS_RXT0 | \ 437 E1000_IMS_TXDW | \ 438 E1000_IMS_RXDMT0 | \ 439 E1000_IMS_RXSEQ | \ 440 E1000_IMS_LSC) 441 442 /* Interrupt Mask Set */ 443 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 444 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 445 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 446 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 447 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 448 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 449 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 450 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 451 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 452 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 453 454 /* Interrupt Cause Set */ 455 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 456 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 457 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 458 459 /* Transmit Descriptor Control */ 460 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 461 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 462 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 463 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 464 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 465 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 466 /* Enable the counting of desc. still to be processed. */ 467 #define E1000_TXDCTL_COUNT_DESC 0x00400000 468 469 /* Flow Control Constants */ 470 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 471 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 472 #define FLOW_CONTROL_TYPE 0x8808 473 474 /* 802.1q VLAN Packet Size */ 475 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 476 477 /* Receive Address */ 478 /* 479 * Number of high/low register pairs in the RAR. The RAR (Receive Address 480 * Registers) holds the directed and multicast addresses that we monitor. 481 * Technically, we have 16 spots. However, we reserve one of these spots 482 * (RAR[15]) for our directed address used by controllers with 483 * manageability enabled, allowing us room for 15 multicast addresses. 484 */ 485 #define E1000_RAR_ENTRIES 15 486 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 487 #define E1000_RAL_MAC_ADDR_LEN 4 488 #define E1000_RAH_MAC_ADDR_LEN 2 489 490 /* Error Codes */ 491 #define E1000_ERR_NVM 1 492 #define E1000_ERR_PHY 2 493 #define E1000_ERR_CONFIG 3 494 #define E1000_ERR_PARAM 4 495 #define E1000_ERR_MAC_INIT 5 496 #define E1000_ERR_PHY_TYPE 6 497 #define E1000_ERR_RESET 9 498 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 499 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 500 #define E1000_BLK_PHY_RESET 12 501 #define E1000_ERR_SWFW_SYNC 13 502 #define E1000_NOT_IMPLEMENTED 14 503 #define E1000_ERR_INVALID_ARGUMENT 16 504 #define E1000_ERR_NO_SPACE 17 505 #define E1000_ERR_NVM_PBA_SECTION 18 506 507 /* Loop limit on how long we wait for auto-negotiation to complete */ 508 #define FIBER_LINK_UP_LIMIT 50 509 #define COPPER_LINK_UP_LIMIT 10 510 #define PHY_AUTO_NEG_LIMIT 45 511 #define PHY_FORCE_LIMIT 20 512 /* Number of 100 microseconds we wait for PCI Express master disable */ 513 #define MASTER_DISABLE_TIMEOUT 800 514 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 515 #define PHY_CFG_TIMEOUT 100 516 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 517 #define MDIO_OWNERSHIP_TIMEOUT 10 518 /* Number of milliseconds for NVM auto read done after MAC reset. */ 519 #define AUTO_READ_DONE_TIMEOUT 10 520 521 /* Flow Control */ 522 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 523 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 524 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 525 526 /* Transmit Configuration Word */ 527 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 528 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 529 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 530 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 531 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 532 533 /* Receive Configuration Word */ 534 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 535 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 536 #define E1000_RXCW_C 0x20000000 /* Receive config */ 537 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 538 539 /* PCI Express Control */ 540 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 541 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 542 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 543 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 544 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 545 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 546 547 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 548 E1000_GCR_RXDSCW_NO_SNOOP | \ 549 E1000_GCR_RXDSCR_NO_SNOOP | \ 550 E1000_GCR_TXD_NO_SNOOP | \ 551 E1000_GCR_TXDSCW_NO_SNOOP | \ 552 E1000_GCR_TXDSCR_NO_SNOOP) 553 554 /* PHY Control Register */ 555 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 556 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 557 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 558 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 559 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 560 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 561 #define MII_CR_SPEED_1000 0x0040 562 #define MII_CR_SPEED_100 0x2000 563 #define MII_CR_SPEED_10 0x0000 564 565 /* PHY Status Register */ 566 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 567 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 568 569 /* Autoneg Advertisement Register */ 570 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 571 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 572 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 573 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 574 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 575 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 576 577 /* Link Partner Ability Register (Base Page) */ 578 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 579 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 580 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 581 582 /* Autoneg Expansion Register */ 583 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 584 585 /* 1000BASE-T Control Register */ 586 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 587 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 588 /* 0=DTE device */ 589 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 590 /* 0=Configure PHY as Slave */ 591 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 592 /* 0=Automatic Master/Slave config */ 593 594 /* 1000BASE-T Status Register */ 595 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 596 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 597 598 599 /* PHY 1000 MII Register/Bit Definitions */ 600 /* PHY Registers defined by IEEE */ 601 #define PHY_CONTROL 0x00 /* Control Register */ 602 #define PHY_STATUS 0x01 /* Status Register */ 603 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 604 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 605 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 606 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 607 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 608 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 609 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 610 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 611 612 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 613 614 /* NVM Control */ 615 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 616 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 617 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 618 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 619 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 620 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 621 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 622 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 623 /* NVM Addressing bits based on type (0-small, 1-large) */ 624 #define E1000_EECD_ADDR_BITS 0x00000400 625 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 626 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 627 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 628 #define E1000_EECD_SIZE_EX_SHIFT 11 629 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 630 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 631 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 632 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 633 634 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ 635 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 636 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 637 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 638 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 639 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 640 #define E1000_FLASH_UPDATES 2000 641 642 /* NVM Word Offsets */ 643 #define NVM_COMPAT 0x0003 644 #define NVM_ID_LED_SETTINGS 0x0004 645 #define NVM_INIT_CONTROL2_REG 0x000F 646 #define NVM_INIT_CONTROL3_PORT_B 0x0014 647 #define NVM_INIT_3GIO_3 0x001A 648 #define NVM_INIT_CONTROL3_PORT_A 0x0024 649 #define NVM_CFG 0x0012 650 #define NVM_ALT_MAC_ADDR_PTR 0x0037 651 #define NVM_CHECKSUM_REG 0x003F 652 653 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ 654 655 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 656 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 657 658 /* Mask bits for fields in Word 0x0f of the NVM */ 659 #define NVM_WORD0F_PAUSE_MASK 0x3000 660 #define NVM_WORD0F_PAUSE 0x1000 661 #define NVM_WORD0F_ASM_DIR 0x2000 662 663 /* Mask bits for fields in Word 0x1a of the NVM */ 664 #define NVM_WORD1A_ASPM_MASK 0x000C 665 666 /* Mask bits for fields in Word 0x03 of the EEPROM */ 667 #define NVM_COMPAT_LOM 0x0800 668 669 /* length of string needed to store PBA number */ 670 #define E1000_PBANUM_LENGTH 11 671 672 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 673 #define NVM_SUM 0xBABA 674 675 /* PBA (printed board assembly) number words */ 676 #define NVM_PBA_OFFSET_0 8 677 #define NVM_PBA_OFFSET_1 9 678 #define NVM_PBA_PTR_GUARD 0xFAFA 679 #define NVM_WORD_SIZE_BASE_SHIFT 6 680 681 /* NVM Commands - SPI */ 682 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 683 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 684 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 685 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 686 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 687 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 688 689 /* SPI NVM Status Register */ 690 #define NVM_STATUS_RDY_SPI 0x01 691 692 /* Word definitions for ID LED Settings */ 693 #define ID_LED_RESERVED_0000 0x0000 694 #define ID_LED_RESERVED_FFFF 0xFFFF 695 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 696 (ID_LED_OFF1_OFF2 << 8) | \ 697 (ID_LED_DEF1_DEF2 << 4) | \ 698 (ID_LED_DEF1_DEF2)) 699 #define ID_LED_DEF1_DEF2 0x1 700 #define ID_LED_DEF1_ON2 0x2 701 #define ID_LED_DEF1_OFF2 0x3 702 #define ID_LED_ON1_DEF2 0x4 703 #define ID_LED_ON1_ON2 0x5 704 #define ID_LED_ON1_OFF2 0x6 705 #define ID_LED_OFF1_DEF2 0x7 706 #define ID_LED_OFF1_ON2 0x8 707 #define ID_LED_OFF1_OFF2 0x9 708 709 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 710 #define IGP_ACTIVITY_LED_ENABLE 0x0300 711 #define IGP_LED3_MODE 0x07000000 712 713 /* PCI/PCI-X/PCI-EX Config space */ 714 #define PCI_HEADER_TYPE_REGISTER 0x0E 715 #define PCIE_LINK_STATUS 0x12 716 717 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 718 #define PCIE_LINK_WIDTH_MASK 0x3F0 719 #define PCIE_LINK_WIDTH_SHIFT 4 720 721 #define PHY_REVISION_MASK 0xFFFFFFF0 722 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 723 #define MAX_PHY_MULTI_PAGE_REG 0xF 724 725 /* Bit definitions for valid PHY IDs. */ 726 /* 727 * I = Integrated 728 * E = External 729 */ 730 #define M88E1000_E_PHY_ID 0x01410C50 731 #define M88E1000_I_PHY_ID 0x01410C30 732 #define M88E1011_I_PHY_ID 0x01410C20 733 #define IGP01E1000_I_PHY_ID 0x02A80380 734 #define M88E1111_I_PHY_ID 0x01410CC0 735 #define GG82563_E_PHY_ID 0x01410CA0 736 #define IGP03E1000_E_PHY_ID 0x02A80390 737 #define IFE_E_PHY_ID 0x02A80330 738 #define IFE_PLUS_E_PHY_ID 0x02A80320 739 #define IFE_C_E_PHY_ID 0x02A80310 740 #define BME1000_E_PHY_ID 0x01410CB0 741 #define BME1000_E_PHY_ID_R2 0x01410CB1 742 #define I82577_E_PHY_ID 0x01540050 743 #define I82578_E_PHY_ID 0x004DD040 744 #define I82579_E_PHY_ID 0x01540090 745 #define I217_E_PHY_ID 0x015400A0 746 747 /* M88E1000 Specific Registers */ 748 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 749 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 750 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 751 752 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 753 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 754 755 /* M88E1000 PHY Specific Control Register */ 756 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 757 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 758 /* Manual MDI configuration */ 759 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 760 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 761 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 762 /* Auto crossover enabled all speeds */ 763 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 764 /* 765 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold) 766 * 0=Normal 10BASE-T Rx Threshold 767 */ 768 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 769 770 /* M88E1000 PHY Specific Status Register */ 771 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 772 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 773 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 774 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ 775 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 776 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 777 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 778 779 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 780 781 /* 782 * Number of times we will attempt to autonegotiate before downshifting if we 783 * are the master 784 */ 785 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 786 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 787 /* 788 * Number of times we will attempt to autonegotiate before downshifting if we 789 * are the slave 790 */ 791 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 792 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 793 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 794 795 /* M88EC018 Rev 2 specific DownShift settings */ 796 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 797 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 798 799 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 800 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 801 802 /* BME1000 PHY Specific Control Register */ 803 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 804 805 806 #define PHY_PAGE_SHIFT 5 807 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 808 ((reg) & MAX_PHY_REG_ADDRESS)) 809 810 /* 811 * Bits... 812 * 15-5: page 813 * 4-0: register offset 814 */ 815 #define GG82563_PAGE_SHIFT 5 816 #define GG82563_REG(page, reg) \ 817 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 818 #define GG82563_MIN_ALT_REG 30 819 820 /* GG82563 Specific Registers */ 821 #define GG82563_PHY_SPEC_CTRL \ 822 GG82563_REG(0, 16) /* PHY Specific Control */ 823 #define GG82563_PHY_PAGE_SELECT \ 824 GG82563_REG(0, 22) /* Page Select */ 825 #define GG82563_PHY_SPEC_CTRL_2 \ 826 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 827 #define GG82563_PHY_PAGE_SELECT_ALT \ 828 GG82563_REG(0, 29) /* Alternate Page Select */ 829 830 #define GG82563_PHY_MAC_SPEC_CTRL \ 831 GG82563_REG(2, 21) /* MAC Specific Control Register */ 832 833 #define GG82563_PHY_DSP_DISTANCE \ 834 GG82563_REG(5, 26) /* DSP Distance */ 835 836 /* Page 193 - Port Control Registers */ 837 #define GG82563_PHY_KMRN_MODE_CTRL \ 838 GG82563_REG(193, 16) /* Kumeran Mode Control */ 839 #define GG82563_PHY_PWR_MGMT_CTRL \ 840 GG82563_REG(193, 20) /* Power Management Control */ 841 842 /* Page 194 - KMRN Registers */ 843 #define GG82563_PHY_INBAND_CTRL \ 844 GG82563_REG(194, 18) /* Inband Control */ 845 846 /* MDI Control */ 847 #define E1000_MDIC_REG_SHIFT 16 848 #define E1000_MDIC_PHY_SHIFT 21 849 #define E1000_MDIC_OP_WRITE 0x04000000 850 #define E1000_MDIC_OP_READ 0x08000000 851 #define E1000_MDIC_READY 0x10000000 852 #define E1000_MDIC_ERROR 0x40000000 853 854 /* SerDes Control */ 855 #define E1000_GEN_POLL_TIMEOUT 640 856 857 /* FW Semaphore */ 858 #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 859 #define E1000_FWSM_WLOCK_MAC_SHIFT 7 860 861 #endif /* _E1000_DEFINES_H_ */ 862