1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 2*51dce24bSJeff Kirsher /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3dee1ad47SJeff Kirsher 4dee1ad47SJeff Kirsher #ifndef _E1000_DEFINES_H_ 5dee1ad47SJeff Kirsher #define _E1000_DEFINES_H_ 6dee1ad47SJeff Kirsher 7dee1ad47SJeff Kirsher /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 8dee1ad47SJeff Kirsher #define REQ_TX_DESCRIPTOR_MULTIPLE 8 9dee1ad47SJeff Kirsher #define REQ_RX_DESCRIPTOR_MULTIPLE 8 10dee1ad47SJeff Kirsher 11dee1ad47SJeff Kirsher /* Definitions for power management and wakeup registers */ 12dee1ad47SJeff Kirsher /* Wake Up Control */ 13dee1ad47SJeff Kirsher #define E1000_WUC_APME 0x00000001 /* APM Enable */ 14dee1ad47SJeff Kirsher #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 1574f350eeSDavid Ertman #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 1674f350eeSDavid Ertman #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 17dee1ad47SJeff Kirsher #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 18dee1ad47SJeff Kirsher 19dee1ad47SJeff Kirsher /* Wake Up Filter Control */ 20dee1ad47SJeff Kirsher #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 21dee1ad47SJeff Kirsher #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 22dee1ad47SJeff Kirsher #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 23dee1ad47SJeff Kirsher #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 24dee1ad47SJeff Kirsher #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 25dee1ad47SJeff Kirsher #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 26dee1ad47SJeff Kirsher 27dee1ad47SJeff Kirsher /* Wake Up Status */ 28dee1ad47SJeff Kirsher #define E1000_WUS_LNKC E1000_WUFC_LNKC 29dee1ad47SJeff Kirsher #define E1000_WUS_MAG E1000_WUFC_MAG 30dee1ad47SJeff Kirsher #define E1000_WUS_EX E1000_WUFC_EX 31dee1ad47SJeff Kirsher #define E1000_WUS_MC E1000_WUFC_MC 32dee1ad47SJeff Kirsher #define E1000_WUS_BC E1000_WUFC_BC 33dee1ad47SJeff Kirsher 34dee1ad47SJeff Kirsher /* Extended Device Control */ 352fbe4526SBruce Allan #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 36dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 37ba9e186fSBruce Allan #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 38dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 39dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 40dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 41dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 42dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 43dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 44dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_EIAME 0x01000000 45dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 46c29c3ba5SBruce Allan #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 47dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 48dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LSECCK 0x00001000 49dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_PHYPDEN 0x00100000 50dee1ad47SJeff Kirsher 51dee1ad47SJeff Kirsher /* Receive Descriptor bit definitions */ 52dee1ad47SJeff Kirsher #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 53dee1ad47SJeff Kirsher #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 54dee1ad47SJeff Kirsher #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 55dee1ad47SJeff Kirsher #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 56dee1ad47SJeff Kirsher #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 57dee1ad47SJeff Kirsher #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 58dee1ad47SJeff Kirsher #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 59dee1ad47SJeff Kirsher #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 60dee1ad47SJeff Kirsher #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 61dee1ad47SJeff Kirsher #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 62dee1ad47SJeff Kirsher #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 632e1706f2SBruce Allan #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 64dee1ad47SJeff Kirsher #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 65dee1ad47SJeff Kirsher #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 66dee1ad47SJeff Kirsher 67b67e1913SBruce Allan #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 68dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_CE 0x01000000 69dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_SE 0x02000000 70dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_SEQ 0x04000000 71dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_CXE 0x10000000 72dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_RXE 0x80000000 73dee1ad47SJeff Kirsher 74dee1ad47SJeff Kirsher /* mask to determine if packets should be dropped due to frame errors */ 75dee1ad47SJeff Kirsher #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 76dee1ad47SJeff Kirsher E1000_RXD_ERR_CE | \ 77dee1ad47SJeff Kirsher E1000_RXD_ERR_SE | \ 78dee1ad47SJeff Kirsher E1000_RXD_ERR_SEQ | \ 79dee1ad47SJeff Kirsher E1000_RXD_ERR_CXE | \ 80dee1ad47SJeff Kirsher E1000_RXD_ERR_RXE) 81dee1ad47SJeff Kirsher 82dee1ad47SJeff Kirsher /* Same mask, but for extended and packet split descriptors */ 83dee1ad47SJeff Kirsher #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 84dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_CE | \ 85dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_SE | \ 86dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_SEQ | \ 87dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_CXE | \ 88dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_RXE) 89dee1ad47SJeff Kirsher 9070495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 9170495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 9270495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 9370495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 9470495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 9570495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 9670495a50SBruce Allan 97dee1ad47SJeff Kirsher #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 98dee1ad47SJeff Kirsher 99dee1ad47SJeff Kirsher /* Management Control */ 100dee1ad47SJeff Kirsher #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 101dee1ad47SJeff Kirsher #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 102dee1ad47SJeff Kirsher #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 103dee1ad47SJeff Kirsher #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 104dee1ad47SJeff Kirsher #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 105dee1ad47SJeff Kirsher /* Enable MAC address filtering */ 106dee1ad47SJeff Kirsher #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 107dee1ad47SJeff Kirsher /* Enable MNG packets to host memory */ 108dee1ad47SJeff Kirsher #define E1000_MANC_EN_MNG2HOST 0x00200000 109dee1ad47SJeff Kirsher 110dee1ad47SJeff Kirsher #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 111dee1ad47SJeff Kirsher #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 112dee1ad47SJeff Kirsher #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 113dee1ad47SJeff Kirsher #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 114dee1ad47SJeff Kirsher 115dee1ad47SJeff Kirsher /* Receive Control */ 116dee1ad47SJeff Kirsher #define E1000_RCTL_EN 0x00000002 /* enable */ 117dee1ad47SJeff Kirsher #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 118dee1ad47SJeff Kirsher #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 119dee1ad47SJeff Kirsher #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 120dee1ad47SJeff Kirsher #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 121dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 122dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 123dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 124dee1ad47SJeff Kirsher #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 125dee1ad47SJeff Kirsher #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 12679849ebcSDavid Ertman #define E1000_RCTL_RDMTS_HEX 0x00010000 127dee1ad47SJeff Kirsher #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 128dee1ad47SJeff Kirsher #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 129dee1ad47SJeff Kirsher #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 130dee1ad47SJeff Kirsher /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 131dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 132dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 133dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 134dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 135dee1ad47SJeff Kirsher /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 136dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 137dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 138dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 139dee1ad47SJeff Kirsher #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 140dee1ad47SJeff Kirsher #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 141dee1ad47SJeff Kirsher #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 142cf955e6cSBen Greear #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 143dee1ad47SJeff Kirsher #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 144dee1ad47SJeff Kirsher #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 145dee1ad47SJeff Kirsher #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 146dee1ad47SJeff Kirsher 147e921eb1aSBruce Allan /* Use byte values for the following shift parameters 148dee1ad47SJeff Kirsher * Usage: 149dee1ad47SJeff Kirsher * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 150dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE0_MASK) | 151dee1ad47SJeff Kirsher * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 152dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE1_MASK) | 153dee1ad47SJeff Kirsher * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 154dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE2_MASK) | 155dee1ad47SJeff Kirsher * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 156dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE3_MASK)) 157dee1ad47SJeff Kirsher * where value0 = [128..16256], default=256 158dee1ad47SJeff Kirsher * value1 = [1024..64512], default=4096 159dee1ad47SJeff Kirsher * value2 = [0..64512], default=4096 160dee1ad47SJeff Kirsher * value3 = [0..64512], default=0 161dee1ad47SJeff Kirsher */ 162dee1ad47SJeff Kirsher 163dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 164dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 165dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 166dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 167dee1ad47SJeff Kirsher 168dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 169dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 170dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 171dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 172dee1ad47SJeff Kirsher 173dee1ad47SJeff Kirsher /* SWFW_SYNC Definitions */ 174dee1ad47SJeff Kirsher #define E1000_SWFW_EEP_SM 0x1 175dee1ad47SJeff Kirsher #define E1000_SWFW_PHY0_SM 0x2 176dee1ad47SJeff Kirsher #define E1000_SWFW_PHY1_SM 0x4 177dee1ad47SJeff Kirsher #define E1000_SWFW_CSR_SM 0x8 178dee1ad47SJeff Kirsher 179dee1ad47SJeff Kirsher /* Device Control */ 180dee1ad47SJeff Kirsher #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 181dee1ad47SJeff Kirsher #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 182dee1ad47SJeff Kirsher #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 183dee1ad47SJeff Kirsher #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 184dee1ad47SJeff Kirsher #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 185dee1ad47SJeff Kirsher #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 186dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 187dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 188dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 189dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 190dee1ad47SJeff Kirsher #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 191dee1ad47SJeff Kirsher #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 192dee1ad47SJeff Kirsher #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 193dee1ad47SJeff Kirsher #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 19494fb848bSBruce Allan #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 195dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 196dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1973ffcf2cbSBruce Allan #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 1983ffcf2cbSBruce Allan #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ 199dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 200dee1ad47SJeff Kirsher #define E1000_CTRL_RST 0x04000000 /* Global reset */ 201dee1ad47SJeff Kirsher #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 202dee1ad47SJeff Kirsher #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 203dee1ad47SJeff Kirsher #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 204dee1ad47SJeff Kirsher #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 205dee1ad47SJeff Kirsher 2061241f29fSBruce Allan #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 2071241f29fSBruce Allan 2081241f29fSBruce Allan #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 209dee1ad47SJeff Kirsher 210dee1ad47SJeff Kirsher /* Device Status */ 211dee1ad47SJeff Kirsher #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 212dee1ad47SJeff Kirsher #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 213dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 214dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_SHIFT 2 215dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 216dee1ad47SJeff Kirsher #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 217772d05c5SBruce Allan #define E1000_STATUS_SPEED_MASK 0x000000C0 218dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 219dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 220dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 221dee1ad47SJeff Kirsher #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 222dee1ad47SJeff Kirsher #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 223c29c3ba5SBruce Allan #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master Req status */ 224dee1ad47SJeff Kirsher 225dee1ad47SJeff Kirsher #define HALF_DUPLEX 1 226dee1ad47SJeff Kirsher #define FULL_DUPLEX 2 227dee1ad47SJeff Kirsher 228dee1ad47SJeff Kirsher #define ADVERTISE_10_HALF 0x0001 229dee1ad47SJeff Kirsher #define ADVERTISE_10_FULL 0x0002 230dee1ad47SJeff Kirsher #define ADVERTISE_100_HALF 0x0004 231dee1ad47SJeff Kirsher #define ADVERTISE_100_FULL 0x0008 232dee1ad47SJeff Kirsher #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 233dee1ad47SJeff Kirsher #define ADVERTISE_1000_FULL 0x0020 234dee1ad47SJeff Kirsher 235dee1ad47SJeff Kirsher /* 1000/H is not supported, nor spec-compliant. */ 23655c5f55eSBruce Allan #define E1000_ALL_SPEED_DUPLEX ( \ 23755c5f55eSBruce Allan ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 23855c5f55eSBruce Allan ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 23955c5f55eSBruce Allan #define E1000_ALL_NOT_GIG ( \ 24055c5f55eSBruce Allan ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 24155c5f55eSBruce Allan ADVERTISE_100_FULL) 242dee1ad47SJeff Kirsher #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 243dee1ad47SJeff Kirsher #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 244dee1ad47SJeff Kirsher #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 245dee1ad47SJeff Kirsher 246dee1ad47SJeff Kirsher #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 247dee1ad47SJeff Kirsher 248dee1ad47SJeff Kirsher /* LED Control */ 249dee1ad47SJeff Kirsher #define E1000_PHY_LED0_MODE_MASK 0x00000007 250dee1ad47SJeff Kirsher #define E1000_PHY_LED0_IVRT 0x00000008 251dee1ad47SJeff Kirsher #define E1000_PHY_LED0_MASK 0x0000001F 252dee1ad47SJeff Kirsher 253dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 254dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_MODE_SHIFT 0 255dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_IVRT 0x00000040 256dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_BLINK 0x00000080 257dee1ad47SJeff Kirsher 258dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LINK_UP 0x2 259dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LED_ON 0xE 260dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LED_OFF 0xF 261dee1ad47SJeff Kirsher 262dee1ad47SJeff Kirsher /* Transmit Descriptor bit definitions */ 263dee1ad47SJeff Kirsher #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 264dee1ad47SJeff Kirsher #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 265dee1ad47SJeff Kirsher #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 266dee1ad47SJeff Kirsher #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 267dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 268dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 269dee1ad47SJeff Kirsher #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 270dee1ad47SJeff Kirsher #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 271dee1ad47SJeff Kirsher #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 272dee1ad47SJeff Kirsher #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 273dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 274dee1ad47SJeff Kirsher #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 275dee1ad47SJeff Kirsher #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 276dee1ad47SJeff Kirsher #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 277dee1ad47SJeff Kirsher #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 278dee1ad47SJeff Kirsher #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 279dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 280dee1ad47SJeff Kirsher #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 281dee1ad47SJeff Kirsher #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 282b67e1913SBruce Allan #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 283dee1ad47SJeff Kirsher 284dee1ad47SJeff Kirsher /* Transmit Control */ 285dee1ad47SJeff Kirsher #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 286dee1ad47SJeff Kirsher #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 287dee1ad47SJeff Kirsher #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 288dee1ad47SJeff Kirsher #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 289dee1ad47SJeff Kirsher #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 290dee1ad47SJeff Kirsher #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 291dee1ad47SJeff Kirsher 292dee1ad47SJeff Kirsher /* SerDes Control */ 293dee1ad47SJeff Kirsher #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 2943ffcf2cbSBruce Allan #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 295dee1ad47SJeff Kirsher 296dee1ad47SJeff Kirsher /* Receive Checksum Control */ 297dee1ad47SJeff Kirsher #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 298dee1ad47SJeff Kirsher #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 29970495a50SBruce Allan #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 300dee1ad47SJeff Kirsher 301dee1ad47SJeff Kirsher /* Header split receive */ 302dee1ad47SJeff Kirsher #define E1000_RFCTL_NFSW_DIS 0x00000040 303dee1ad47SJeff Kirsher #define E1000_RFCTL_NFSR_DIS 0x00000080 304dee1ad47SJeff Kirsher #define E1000_RFCTL_ACK_DIS 0x00001000 305dee1ad47SJeff Kirsher #define E1000_RFCTL_EXTEN 0x00008000 306dee1ad47SJeff Kirsher #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 307dee1ad47SJeff Kirsher #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 308dee1ad47SJeff Kirsher 309dee1ad47SJeff Kirsher /* Collision related configuration parameters */ 310dee1ad47SJeff Kirsher #define E1000_COLLISION_THRESHOLD 15 311dee1ad47SJeff Kirsher #define E1000_CT_SHIFT 4 312dee1ad47SJeff Kirsher #define E1000_COLLISION_DISTANCE 63 313dee1ad47SJeff Kirsher #define E1000_COLD_SHIFT 12 314dee1ad47SJeff Kirsher 315dee1ad47SJeff Kirsher /* Default values for the transmit IPG register */ 316dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGT_COPPER 8 317dee1ad47SJeff Kirsher 318dee1ad47SJeff Kirsher #define E1000_TIPG_IPGT_MASK 0x000003FF 319dee1ad47SJeff Kirsher 320dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGR1 8 321dee1ad47SJeff Kirsher #define E1000_TIPG_IPGR1_SHIFT 10 322dee1ad47SJeff Kirsher 323dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGR2 6 324dee1ad47SJeff Kirsher #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 325dee1ad47SJeff Kirsher #define E1000_TIPG_IPGR2_SHIFT 20 326dee1ad47SJeff Kirsher 327dee1ad47SJeff Kirsher #define MAX_JUMBO_FRAME_SIZE 0x3F00 328493004d0SDavid Ertman #define E1000_TX_PTR_GAP 0x1F 329dee1ad47SJeff Kirsher 330dee1ad47SJeff Kirsher /* Extended Configuration Control and Size */ 331dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 332dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 333dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 334dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 335dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 336dee1ad47SJeff Kirsher #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 337dee1ad47SJeff Kirsher #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 338dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 339dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 340dee1ad47SJeff Kirsher 341dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 342dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 343dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 344dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 345dee1ad47SJeff Kirsher 346dee1ad47SJeff Kirsher #define E1000_KABGTXD_BGSQLBIAS 0x00050000 347dee1ad47SJeff Kirsher 348203e4151SBruce Allan /* Low Power IDLE Control */ 349203e4151SBruce Allan #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 350203e4151SBruce Allan 351dee1ad47SJeff Kirsher /* PBA constants */ 352dee1ad47SJeff Kirsher #define E1000_PBA_8K 0x0008 /* 8KB */ 353dee1ad47SJeff Kirsher #define E1000_PBA_16K 0x0010 /* 16KB */ 354dee1ad47SJeff Kirsher 3553e35d991SBruce Allan #define E1000_PBA_RXA_MASK 0xFFFF 3563e35d991SBruce Allan 357dee1ad47SJeff Kirsher #define E1000_PBS_16K E1000_PBA_16K 358dee1ad47SJeff Kirsher 35994fb848bSBruce Allan /* Uncorrectable/correctable ECC Error counts and enable bits */ 36094fb848bSBruce Allan #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 36194fb848bSBruce Allan #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 36294fb848bSBruce Allan #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 36394fb848bSBruce Allan #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 36494fb848bSBruce Allan 365dee1ad47SJeff Kirsher #define IFS_MAX 80 366dee1ad47SJeff Kirsher #define IFS_MIN 40 367dee1ad47SJeff Kirsher #define IFS_RATIO 4 368dee1ad47SJeff Kirsher #define IFS_STEP 10 369dee1ad47SJeff Kirsher #define MIN_NUM_XMITS 1000 370dee1ad47SJeff Kirsher 371dee1ad47SJeff Kirsher /* SW Semaphore Register */ 372dee1ad47SJeff Kirsher #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 373dee1ad47SJeff Kirsher #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 374dee1ad47SJeff Kirsher #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 375dee1ad47SJeff Kirsher 376dee1ad47SJeff Kirsher #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 377dee1ad47SJeff Kirsher 378dee1ad47SJeff Kirsher /* Interrupt Cause Read */ 379dee1ad47SJeff Kirsher #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 380dee1ad47SJeff Kirsher #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 381dee1ad47SJeff Kirsher #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 382dee1ad47SJeff Kirsher #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 3834aea7a5cSBenjamin Poirier #define E1000_ICR_RXO 0x00000040 /* Receiver Overrun */ 384dee1ad47SJeff Kirsher #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 385116f4a64SBenjamin Poirier #define E1000_ICR_MDAC 0x00000200 /* MDIO Access Complete */ 386116f4a64SBenjamin Poirier #define E1000_ICR_SRPD 0x00010000 /* Small Receive Packet Detected */ 387116f4a64SBenjamin Poirier #define E1000_ICR_ACK 0x00020000 /* Receive ACK Frame Detected */ 388116f4a64SBenjamin Poirier #define E1000_ICR_MNG 0x00040000 /* Manageability Event Detected */ 38994fb848bSBruce Allan #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 390c29c3ba5SBruce Allan /* If this bit asserted, the driver should claim the interrupt */ 391c29c3ba5SBruce Allan #define E1000_ICR_INT_ASSERTED 0x80000000 392dee1ad47SJeff Kirsher #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 393dee1ad47SJeff Kirsher #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 394dee1ad47SJeff Kirsher #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 395dee1ad47SJeff Kirsher #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 396116f4a64SBenjamin Poirier #define E1000_ICR_OTHER 0x01000000 /* Other Interrupt */ 397dee1ad47SJeff Kirsher 398dee1ad47SJeff Kirsher /* PBA ECC Register */ 399dee1ad47SJeff Kirsher #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 400dee1ad47SJeff Kirsher #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 401dee1ad47SJeff Kirsher #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ 402dee1ad47SJeff Kirsher #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 403dee1ad47SJeff Kirsher #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 404dee1ad47SJeff Kirsher 405e921eb1aSBruce Allan /* This defines the bits that are set in the Interrupt Mask 406dee1ad47SJeff Kirsher * Set/Read Register. Each bit is documented below: 407dee1ad47SJeff Kirsher * o RXT0 = Receiver Timer Interrupt (ring 0) 408dee1ad47SJeff Kirsher * o TXDW = Transmit Descriptor Written Back 409dee1ad47SJeff Kirsher * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 410dee1ad47SJeff Kirsher * o RXSEQ = Receive Sequence Error 411dee1ad47SJeff Kirsher * o LSC = Link Status Change 412dee1ad47SJeff Kirsher */ 413dee1ad47SJeff Kirsher #define IMS_ENABLE_MASK ( \ 414dee1ad47SJeff Kirsher E1000_IMS_RXT0 | \ 415dee1ad47SJeff Kirsher E1000_IMS_TXDW | \ 416dee1ad47SJeff Kirsher E1000_IMS_RXDMT0 | \ 417dee1ad47SJeff Kirsher E1000_IMS_RXSEQ | \ 418dee1ad47SJeff Kirsher E1000_IMS_LSC) 419dee1ad47SJeff Kirsher 420116f4a64SBenjamin Poirier /* These are all of the events related to the OTHER interrupt. 421116f4a64SBenjamin Poirier */ 422116f4a64SBenjamin Poirier #define IMS_OTHER_MASK ( \ 423116f4a64SBenjamin Poirier E1000_IMS_LSC | \ 424116f4a64SBenjamin Poirier E1000_IMS_RXO | \ 425116f4a64SBenjamin Poirier E1000_IMS_MDAC | \ 426116f4a64SBenjamin Poirier E1000_IMS_SRPD | \ 427116f4a64SBenjamin Poirier E1000_IMS_ACK | \ 428116f4a64SBenjamin Poirier E1000_IMS_MNG) 429116f4a64SBenjamin Poirier 430dee1ad47SJeff Kirsher /* Interrupt Mask Set */ 431dee1ad47SJeff Kirsher #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 432dee1ad47SJeff Kirsher #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 433dee1ad47SJeff Kirsher #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 434dee1ad47SJeff Kirsher #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 435116f4a64SBenjamin Poirier #define E1000_IMS_RXO E1000_ICR_RXO /* Receiver Overrun */ 436dee1ad47SJeff Kirsher #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 437116f4a64SBenjamin Poirier #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO Access Complete */ 438116f4a64SBenjamin Poirier #define E1000_IMS_SRPD E1000_ICR_SRPD /* Small Receive Packet */ 439116f4a64SBenjamin Poirier #define E1000_IMS_ACK E1000_ICR_ACK /* Receive ACK Frame Detected */ 440116f4a64SBenjamin Poirier #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability Event */ 44194fb848bSBruce Allan #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 442dee1ad47SJeff Kirsher #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 443dee1ad47SJeff Kirsher #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 444dee1ad47SJeff Kirsher #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 445dee1ad47SJeff Kirsher #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 446a61cfe4fSBenjamin Poirier #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupt */ 447dee1ad47SJeff Kirsher 448dee1ad47SJeff Kirsher /* Interrupt Cause Set */ 449dee1ad47SJeff Kirsher #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 450dee1ad47SJeff Kirsher #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 451dee1ad47SJeff Kirsher #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 452a61cfe4fSBenjamin Poirier #define E1000_ICS_OTHER E1000_ICR_OTHER /* Other Interrupt */ 453dee1ad47SJeff Kirsher 454dee1ad47SJeff Kirsher /* Transmit Descriptor Control */ 455dee1ad47SJeff Kirsher #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 456dee1ad47SJeff Kirsher #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 457dee1ad47SJeff Kirsher #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 458dee1ad47SJeff Kirsher #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 459dee1ad47SJeff Kirsher #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 460dee1ad47SJeff Kirsher #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 461dee1ad47SJeff Kirsher /* Enable the counting of desc. still to be processed. */ 462dee1ad47SJeff Kirsher #define E1000_TXDCTL_COUNT_DESC 0x00400000 463dee1ad47SJeff Kirsher 464dee1ad47SJeff Kirsher /* Flow Control Constants */ 465dee1ad47SJeff Kirsher #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 466dee1ad47SJeff Kirsher #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 467dee1ad47SJeff Kirsher #define FLOW_CONTROL_TYPE 0x8808 468dee1ad47SJeff Kirsher 469dee1ad47SJeff Kirsher /* 802.1q VLAN Packet Size */ 470dee1ad47SJeff Kirsher #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 471dee1ad47SJeff Kirsher 472e921eb1aSBruce Allan /* Receive Address 473dee1ad47SJeff Kirsher * Number of high/low register pairs in the RAR. The RAR (Receive Address 474dee1ad47SJeff Kirsher * Registers) holds the directed and multicast addresses that we monitor. 475dee1ad47SJeff Kirsher * Technically, we have 16 spots. However, we reserve one of these spots 476dee1ad47SJeff Kirsher * (RAR[15]) for our directed address used by controllers with 477dee1ad47SJeff Kirsher * manageability enabled, allowing us room for 15 multicast addresses. 478dee1ad47SJeff Kirsher */ 479dee1ad47SJeff Kirsher #define E1000_RAR_ENTRIES 15 480dee1ad47SJeff Kirsher #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 481dee1ad47SJeff Kirsher #define E1000_RAL_MAC_ADDR_LEN 4 482dee1ad47SJeff Kirsher #define E1000_RAH_MAC_ADDR_LEN 2 483dee1ad47SJeff Kirsher 484dee1ad47SJeff Kirsher /* Error Codes */ 485dee1ad47SJeff Kirsher #define E1000_ERR_NVM 1 486dee1ad47SJeff Kirsher #define E1000_ERR_PHY 2 487dee1ad47SJeff Kirsher #define E1000_ERR_CONFIG 3 488dee1ad47SJeff Kirsher #define E1000_ERR_PARAM 4 489dee1ad47SJeff Kirsher #define E1000_ERR_MAC_INIT 5 490dee1ad47SJeff Kirsher #define E1000_ERR_PHY_TYPE 6 491dee1ad47SJeff Kirsher #define E1000_ERR_RESET 9 492dee1ad47SJeff Kirsher #define E1000_ERR_MASTER_REQUESTS_PENDING 10 493dee1ad47SJeff Kirsher #define E1000_ERR_HOST_INTERFACE_COMMAND 11 494dee1ad47SJeff Kirsher #define E1000_BLK_PHY_RESET 12 495dee1ad47SJeff Kirsher #define E1000_ERR_SWFW_SYNC 13 496dee1ad47SJeff Kirsher #define E1000_NOT_IMPLEMENTED 14 497dee1ad47SJeff Kirsher #define E1000_ERR_INVALID_ARGUMENT 16 498dee1ad47SJeff Kirsher #define E1000_ERR_NO_SPACE 17 499dee1ad47SJeff Kirsher #define E1000_ERR_NVM_PBA_SECTION 18 500dee1ad47SJeff Kirsher 501dee1ad47SJeff Kirsher /* Loop limit on how long we wait for auto-negotiation to complete */ 502dee1ad47SJeff Kirsher #define FIBER_LINK_UP_LIMIT 50 503dee1ad47SJeff Kirsher #define COPPER_LINK_UP_LIMIT 10 504dee1ad47SJeff Kirsher #define PHY_AUTO_NEG_LIMIT 45 505dee1ad47SJeff Kirsher #define PHY_FORCE_LIMIT 20 506dee1ad47SJeff Kirsher /* Number of 100 microseconds we wait for PCI Express master disable */ 507dee1ad47SJeff Kirsher #define MASTER_DISABLE_TIMEOUT 800 508dee1ad47SJeff Kirsher /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 509dee1ad47SJeff Kirsher #define PHY_CFG_TIMEOUT 100 510dee1ad47SJeff Kirsher /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 511dee1ad47SJeff Kirsher #define MDIO_OWNERSHIP_TIMEOUT 10 512dee1ad47SJeff Kirsher /* Number of milliseconds for NVM auto read done after MAC reset. */ 513dee1ad47SJeff Kirsher #define AUTO_READ_DONE_TIMEOUT 10 514dee1ad47SJeff Kirsher 515dee1ad47SJeff Kirsher /* Flow Control */ 516dee1ad47SJeff Kirsher #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 517dee1ad47SJeff Kirsher #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 518dee1ad47SJeff Kirsher #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 519dee1ad47SJeff Kirsher 520dee1ad47SJeff Kirsher /* Transmit Configuration Word */ 521dee1ad47SJeff Kirsher #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 522dee1ad47SJeff Kirsher #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 523dee1ad47SJeff Kirsher #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 524dee1ad47SJeff Kirsher #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 525dee1ad47SJeff Kirsher #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 526dee1ad47SJeff Kirsher 527dee1ad47SJeff Kirsher /* Receive Configuration Word */ 528dee1ad47SJeff Kirsher #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 529dee1ad47SJeff Kirsher #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 530dee1ad47SJeff Kirsher #define E1000_RXCW_C 0x20000000 /* Receive config */ 531dee1ad47SJeff Kirsher #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 532dee1ad47SJeff Kirsher 53301d7ada5SChristopher S. Hall /* HH Time Sync */ 53401d7ada5SChristopher S. Hall #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 53501d7ada5SChristopher S. Hall #define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 53601d7ada5SChristopher S. Hall #define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 53701d7ada5SChristopher S. Hall 538b67e1913SBruce Allan #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 539b67e1913SBruce Allan #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 540b67e1913SBruce Allan 541b67e1913SBruce Allan #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 542b67e1913SBruce Allan #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 543d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 544d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 545d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 546d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 547d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 548b67e1913SBruce Allan #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 549b67e1913SBruce Allan #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 550b67e1913SBruce Allan 551d89777bfSBruce Allan #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 552d89777bfSBruce Allan #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 553d89777bfSBruce Allan 554d89777bfSBruce Allan #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 555d89777bfSBruce Allan #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 556d89777bfSBruce Allan 557b67e1913SBruce Allan #define E1000_TIMINCA_INCPERIOD_SHIFT 24 558b67e1913SBruce Allan #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 559b67e1913SBruce Allan 560dee1ad47SJeff Kirsher /* PCI Express Control */ 561dee1ad47SJeff Kirsher #define E1000_GCR_RXD_NO_SNOOP 0x00000001 562dee1ad47SJeff Kirsher #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 563dee1ad47SJeff Kirsher #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 564dee1ad47SJeff Kirsher #define E1000_GCR_TXD_NO_SNOOP 0x00000008 565dee1ad47SJeff Kirsher #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 566dee1ad47SJeff Kirsher #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 567dee1ad47SJeff Kirsher 568dee1ad47SJeff Kirsher #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 569dee1ad47SJeff Kirsher E1000_GCR_RXDSCW_NO_SNOOP | \ 570dee1ad47SJeff Kirsher E1000_GCR_RXDSCR_NO_SNOOP | \ 571dee1ad47SJeff Kirsher E1000_GCR_TXD_NO_SNOOP | \ 572dee1ad47SJeff Kirsher E1000_GCR_TXDSCW_NO_SNOOP | \ 573dee1ad47SJeff Kirsher E1000_GCR_TXDSCR_NO_SNOOP) 574dee1ad47SJeff Kirsher 575dee1ad47SJeff Kirsher /* NVM Control */ 576dee1ad47SJeff Kirsher #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 577dee1ad47SJeff Kirsher #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 578dee1ad47SJeff Kirsher #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 579dee1ad47SJeff Kirsher #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 580dee1ad47SJeff Kirsher #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 581dee1ad47SJeff Kirsher #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 582dee1ad47SJeff Kirsher #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 583dee1ad47SJeff Kirsher #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 584dee1ad47SJeff Kirsher /* NVM Addressing bits based on type (0-small, 1-large) */ 585dee1ad47SJeff Kirsher #define E1000_EECD_ADDR_BITS 0x00000400 586dee1ad47SJeff Kirsher #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 587dee1ad47SJeff Kirsher #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 588dee1ad47SJeff Kirsher #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 589dee1ad47SJeff Kirsher #define E1000_EECD_SIZE_EX_SHIFT 11 590dee1ad47SJeff Kirsher #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 591dee1ad47SJeff Kirsher #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 592dee1ad47SJeff Kirsher #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 593dee1ad47SJeff Kirsher #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 594dee1ad47SJeff Kirsher 595c29c3ba5SBruce Allan #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM r/w regs */ 596dee1ad47SJeff Kirsher #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 597dee1ad47SJeff Kirsher #define E1000_NVM_RW_REG_START 1 /* Start operation */ 598dee1ad47SJeff Kirsher #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 599c29c3ba5SBruce Allan #define E1000_NVM_POLL_WRITE 1 /* Flag for polling write complete */ 600c29c3ba5SBruce Allan #define E1000_NVM_POLL_READ 0 /* Flag for polling read complete */ 601dee1ad47SJeff Kirsher #define E1000_FLASH_UPDATES 2000 602dee1ad47SJeff Kirsher 603dee1ad47SJeff Kirsher /* NVM Word Offsets */ 604dee1ad47SJeff Kirsher #define NVM_COMPAT 0x0003 605dee1ad47SJeff Kirsher #define NVM_ID_LED_SETTINGS 0x0004 6061cc7a3a1SBruce Allan #define NVM_FUTURE_INIT_WORD1 0x0019 6071cc7a3a1SBruce Allan #define NVM_COMPAT_VALID_CSUM 0x0001 6081cc7a3a1SBruce Allan #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 6091cc7a3a1SBruce Allan 610dee1ad47SJeff Kirsher #define NVM_INIT_CONTROL2_REG 0x000F 611dee1ad47SJeff Kirsher #define NVM_INIT_CONTROL3_PORT_B 0x0014 612dee1ad47SJeff Kirsher #define NVM_INIT_3GIO_3 0x001A 613dee1ad47SJeff Kirsher #define NVM_INIT_CONTROL3_PORT_A 0x0024 614dee1ad47SJeff Kirsher #define NVM_CFG 0x0012 615dee1ad47SJeff Kirsher #define NVM_ALT_MAC_ADDR_PTR 0x0037 616dee1ad47SJeff Kirsher #define NVM_CHECKSUM_REG 0x003F 617dee1ad47SJeff Kirsher 618dee1ad47SJeff Kirsher #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 619dee1ad47SJeff Kirsher #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 620dee1ad47SJeff Kirsher 621dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x0f of the NVM */ 622dee1ad47SJeff Kirsher #define NVM_WORD0F_PAUSE_MASK 0x3000 623dee1ad47SJeff Kirsher #define NVM_WORD0F_PAUSE 0x1000 624dee1ad47SJeff Kirsher #define NVM_WORD0F_ASM_DIR 0x2000 625dee1ad47SJeff Kirsher 626dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x1a of the NVM */ 627dee1ad47SJeff Kirsher #define NVM_WORD1A_ASPM_MASK 0x000C 628dee1ad47SJeff Kirsher 629dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x03 of the EEPROM */ 630dee1ad47SJeff Kirsher #define NVM_COMPAT_LOM 0x0800 631dee1ad47SJeff Kirsher 632dee1ad47SJeff Kirsher /* length of string needed to store PBA number */ 633dee1ad47SJeff Kirsher #define E1000_PBANUM_LENGTH 11 634dee1ad47SJeff Kirsher 635dee1ad47SJeff Kirsher /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 636dee1ad47SJeff Kirsher #define NVM_SUM 0xBABA 637dee1ad47SJeff Kirsher 638dee1ad47SJeff Kirsher /* PBA (printed board assembly) number words */ 639dee1ad47SJeff Kirsher #define NVM_PBA_OFFSET_0 8 640dee1ad47SJeff Kirsher #define NVM_PBA_OFFSET_1 9 641dee1ad47SJeff Kirsher #define NVM_PBA_PTR_GUARD 0xFAFA 642dee1ad47SJeff Kirsher #define NVM_WORD_SIZE_BASE_SHIFT 6 643dee1ad47SJeff Kirsher 644dee1ad47SJeff Kirsher /* NVM Commands - SPI */ 645dee1ad47SJeff Kirsher #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 646dee1ad47SJeff Kirsher #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 647dee1ad47SJeff Kirsher #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 648dee1ad47SJeff Kirsher #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 649dee1ad47SJeff Kirsher #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 650dee1ad47SJeff Kirsher #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 651dee1ad47SJeff Kirsher 652dee1ad47SJeff Kirsher /* SPI NVM Status Register */ 653dee1ad47SJeff Kirsher #define NVM_STATUS_RDY_SPI 0x01 654dee1ad47SJeff Kirsher 655dee1ad47SJeff Kirsher /* Word definitions for ID LED Settings */ 656dee1ad47SJeff Kirsher #define ID_LED_RESERVED_0000 0x0000 657dee1ad47SJeff Kirsher #define ID_LED_RESERVED_FFFF 0xFFFF 658dee1ad47SJeff Kirsher #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 659dee1ad47SJeff Kirsher (ID_LED_OFF1_OFF2 << 8) | \ 660dee1ad47SJeff Kirsher (ID_LED_DEF1_DEF2 << 4) | \ 661dee1ad47SJeff Kirsher (ID_LED_DEF1_DEF2)) 662dee1ad47SJeff Kirsher #define ID_LED_DEF1_DEF2 0x1 663dee1ad47SJeff Kirsher #define ID_LED_DEF1_ON2 0x2 664dee1ad47SJeff Kirsher #define ID_LED_DEF1_OFF2 0x3 665dee1ad47SJeff Kirsher #define ID_LED_ON1_DEF2 0x4 666dee1ad47SJeff Kirsher #define ID_LED_ON1_ON2 0x5 667dee1ad47SJeff Kirsher #define ID_LED_ON1_OFF2 0x6 668dee1ad47SJeff Kirsher #define ID_LED_OFF1_DEF2 0x7 669dee1ad47SJeff Kirsher #define ID_LED_OFF1_ON2 0x8 670dee1ad47SJeff Kirsher #define ID_LED_OFF1_OFF2 0x9 671dee1ad47SJeff Kirsher 672dee1ad47SJeff Kirsher #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 673dee1ad47SJeff Kirsher #define IGP_ACTIVITY_LED_ENABLE 0x0300 674dee1ad47SJeff Kirsher #define IGP_LED3_MODE 0x07000000 675dee1ad47SJeff Kirsher 676dee1ad47SJeff Kirsher /* PCI/PCI-X/PCI-EX Config space */ 677dee1ad47SJeff Kirsher #define PCI_HEADER_TYPE_REGISTER 0x0E 678dee1ad47SJeff Kirsher #define PCIE_LINK_STATUS 0x12 679dee1ad47SJeff Kirsher 680dee1ad47SJeff Kirsher #define PCI_HEADER_TYPE_MULTIFUNC 0x80 681dee1ad47SJeff Kirsher #define PCIE_LINK_WIDTH_MASK 0x3F0 682dee1ad47SJeff Kirsher #define PCIE_LINK_WIDTH_SHIFT 4 683dee1ad47SJeff Kirsher 684dee1ad47SJeff Kirsher #define PHY_REVISION_MASK 0xFFFFFFF0 685dee1ad47SJeff Kirsher #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 686dee1ad47SJeff Kirsher #define MAX_PHY_MULTI_PAGE_REG 0xF 687dee1ad47SJeff Kirsher 688e921eb1aSBruce Allan /* Bit definitions for valid PHY IDs. 689dee1ad47SJeff Kirsher * I = Integrated 690dee1ad47SJeff Kirsher * E = External 691dee1ad47SJeff Kirsher */ 692dee1ad47SJeff Kirsher #define M88E1000_E_PHY_ID 0x01410C50 693dee1ad47SJeff Kirsher #define M88E1000_I_PHY_ID 0x01410C30 694dee1ad47SJeff Kirsher #define M88E1011_I_PHY_ID 0x01410C20 695dee1ad47SJeff Kirsher #define IGP01E1000_I_PHY_ID 0x02A80380 696dee1ad47SJeff Kirsher #define M88E1111_I_PHY_ID 0x01410CC0 697dee1ad47SJeff Kirsher #define GG82563_E_PHY_ID 0x01410CA0 698dee1ad47SJeff Kirsher #define IGP03E1000_E_PHY_ID 0x02A80390 699dee1ad47SJeff Kirsher #define IFE_E_PHY_ID 0x02A80330 700dee1ad47SJeff Kirsher #define IFE_PLUS_E_PHY_ID 0x02A80320 701dee1ad47SJeff Kirsher #define IFE_C_E_PHY_ID 0x02A80310 702dee1ad47SJeff Kirsher #define BME1000_E_PHY_ID 0x01410CB0 703dee1ad47SJeff Kirsher #define BME1000_E_PHY_ID_R2 0x01410CB1 704dee1ad47SJeff Kirsher #define I82577_E_PHY_ID 0x01540050 705dee1ad47SJeff Kirsher #define I82578_E_PHY_ID 0x004DD040 706dee1ad47SJeff Kirsher #define I82579_E_PHY_ID 0x01540090 7072fbe4526SBruce Allan #define I217_E_PHY_ID 0x015400A0 708dee1ad47SJeff Kirsher 709dee1ad47SJeff Kirsher /* M88E1000 Specific Registers */ 710dee1ad47SJeff Kirsher #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 711dee1ad47SJeff Kirsher #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 712dee1ad47SJeff Kirsher #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 713dee1ad47SJeff Kirsher 714dee1ad47SJeff Kirsher #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 715dee1ad47SJeff Kirsher #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 716dee1ad47SJeff Kirsher 717dee1ad47SJeff Kirsher /* M88E1000 PHY Specific Control Register */ 718dee1ad47SJeff Kirsher #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 719dee1ad47SJeff Kirsher #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 720dee1ad47SJeff Kirsher /* Manual MDI configuration */ 721dee1ad47SJeff Kirsher #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 722dee1ad47SJeff Kirsher /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 723dee1ad47SJeff Kirsher #define M88E1000_PSCR_AUTO_X_1000T 0x0040 724dee1ad47SJeff Kirsher /* Auto crossover enabled all speeds */ 725dee1ad47SJeff Kirsher #define M88E1000_PSCR_AUTO_X_MODE 0x0060 726dee1ad47SJeff Kirsher #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 727dee1ad47SJeff Kirsher 728dee1ad47SJeff Kirsher /* M88E1000 PHY Specific Status Register */ 729dee1ad47SJeff Kirsher #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 730dee1ad47SJeff Kirsher #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 731dee1ad47SJeff Kirsher #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 732dee1ad47SJeff Kirsher /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ 733dee1ad47SJeff Kirsher #define M88E1000_PSSR_CABLE_LENGTH 0x0380 734dee1ad47SJeff Kirsher #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 735dee1ad47SJeff Kirsher #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 736dee1ad47SJeff Kirsher 737dee1ad47SJeff Kirsher #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 738dee1ad47SJeff Kirsher 739e921eb1aSBruce Allan /* Number of times we will attempt to autonegotiate before downshifting if we 740dee1ad47SJeff Kirsher * are the master 741dee1ad47SJeff Kirsher */ 742dee1ad47SJeff Kirsher #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 743dee1ad47SJeff Kirsher #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 744e921eb1aSBruce Allan /* Number of times we will attempt to autonegotiate before downshifting if we 745dee1ad47SJeff Kirsher * are the slave 746dee1ad47SJeff Kirsher */ 747dee1ad47SJeff Kirsher #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 748dee1ad47SJeff Kirsher #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 749dee1ad47SJeff Kirsher #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 750dee1ad47SJeff Kirsher 751dee1ad47SJeff Kirsher /* M88EC018 Rev 2 specific DownShift settings */ 752dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 753dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 754dee1ad47SJeff Kirsher 755dee1ad47SJeff Kirsher #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 756dee1ad47SJeff Kirsher #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 757dee1ad47SJeff Kirsher 758dee1ad47SJeff Kirsher /* BME1000 PHY Specific Control Register */ 759dee1ad47SJeff Kirsher #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 760dee1ad47SJeff Kirsher 761e921eb1aSBruce Allan /* Bits... 762dee1ad47SJeff Kirsher * 15-5: page 763dee1ad47SJeff Kirsher * 4-0: register offset 764dee1ad47SJeff Kirsher */ 765dee1ad47SJeff Kirsher #define GG82563_PAGE_SHIFT 5 766dee1ad47SJeff Kirsher #define GG82563_REG(page, reg) \ 767dee1ad47SJeff Kirsher (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 768dee1ad47SJeff Kirsher #define GG82563_MIN_ALT_REG 30 769dee1ad47SJeff Kirsher 770dee1ad47SJeff Kirsher /* GG82563 Specific Registers */ 771dee1ad47SJeff Kirsher #define GG82563_PHY_SPEC_CTRL \ 772dee1ad47SJeff Kirsher GG82563_REG(0, 16) /* PHY Specific Control */ 773dee1ad47SJeff Kirsher #define GG82563_PHY_PAGE_SELECT \ 774dee1ad47SJeff Kirsher GG82563_REG(0, 22) /* Page Select */ 775dee1ad47SJeff Kirsher #define GG82563_PHY_SPEC_CTRL_2 \ 776dee1ad47SJeff Kirsher GG82563_REG(0, 26) /* PHY Specific Control 2 */ 777dee1ad47SJeff Kirsher #define GG82563_PHY_PAGE_SELECT_ALT \ 778dee1ad47SJeff Kirsher GG82563_REG(0, 29) /* Alternate Page Select */ 779dee1ad47SJeff Kirsher 780dee1ad47SJeff Kirsher #define GG82563_PHY_MAC_SPEC_CTRL \ 781dee1ad47SJeff Kirsher GG82563_REG(2, 21) /* MAC Specific Control Register */ 782dee1ad47SJeff Kirsher 783dee1ad47SJeff Kirsher #define GG82563_PHY_DSP_DISTANCE \ 784dee1ad47SJeff Kirsher GG82563_REG(5, 26) /* DSP Distance */ 785dee1ad47SJeff Kirsher 786dee1ad47SJeff Kirsher /* Page 193 - Port Control Registers */ 787dee1ad47SJeff Kirsher #define GG82563_PHY_KMRN_MODE_CTRL \ 788dee1ad47SJeff Kirsher GG82563_REG(193, 16) /* Kumeran Mode Control */ 789dee1ad47SJeff Kirsher #define GG82563_PHY_PWR_MGMT_CTRL \ 790dee1ad47SJeff Kirsher GG82563_REG(193, 20) /* Power Management Control */ 791dee1ad47SJeff Kirsher 792dee1ad47SJeff Kirsher /* Page 194 - KMRN Registers */ 793dee1ad47SJeff Kirsher #define GG82563_PHY_INBAND_CTRL \ 794dee1ad47SJeff Kirsher GG82563_REG(194, 18) /* Inband Control */ 795dee1ad47SJeff Kirsher 796dee1ad47SJeff Kirsher /* MDI Control */ 797bb034512SBruce Allan #define E1000_MDIC_REG_MASK 0x001F0000 798dee1ad47SJeff Kirsher #define E1000_MDIC_REG_SHIFT 16 799dee1ad47SJeff Kirsher #define E1000_MDIC_PHY_SHIFT 21 800dee1ad47SJeff Kirsher #define E1000_MDIC_OP_WRITE 0x04000000 801dee1ad47SJeff Kirsher #define E1000_MDIC_OP_READ 0x08000000 802dee1ad47SJeff Kirsher #define E1000_MDIC_READY 0x10000000 803dee1ad47SJeff Kirsher #define E1000_MDIC_ERROR 0x40000000 804dee1ad47SJeff Kirsher 805dee1ad47SJeff Kirsher /* SerDes Control */ 806dee1ad47SJeff Kirsher #define E1000_GEN_POLL_TIMEOUT 640 807dee1ad47SJeff Kirsher 808dee1ad47SJeff Kirsher #endif /* _E1000_DEFINES_H_ */ 809