1dee1ad47SJeff Kirsher /******************************************************************************* 2dee1ad47SJeff Kirsher 3dee1ad47SJeff Kirsher Intel PRO/1000 Linux driver 4bf67044bSBruce Allan Copyright(c) 1999 - 2013 Intel Corporation. 5dee1ad47SJeff Kirsher 6dee1ad47SJeff Kirsher This program is free software; you can redistribute it and/or modify it 7dee1ad47SJeff Kirsher under the terms and conditions of the GNU General Public License, 8dee1ad47SJeff Kirsher version 2, as published by the Free Software Foundation. 9dee1ad47SJeff Kirsher 10dee1ad47SJeff Kirsher This program is distributed in the hope it will be useful, but WITHOUT 11dee1ad47SJeff Kirsher ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12dee1ad47SJeff Kirsher FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13dee1ad47SJeff Kirsher more details. 14dee1ad47SJeff Kirsher 15dee1ad47SJeff Kirsher You should have received a copy of the GNU General Public License along with 16dee1ad47SJeff Kirsher this program; if not, write to the Free Software Foundation, Inc., 17dee1ad47SJeff Kirsher 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18dee1ad47SJeff Kirsher 19dee1ad47SJeff Kirsher The full GNU General Public License is included in this distribution in 20dee1ad47SJeff Kirsher the file called "COPYING". 21dee1ad47SJeff Kirsher 22dee1ad47SJeff Kirsher Contact Information: 23dee1ad47SJeff Kirsher Linux NICS <linux.nics@intel.com> 24dee1ad47SJeff Kirsher e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25dee1ad47SJeff Kirsher Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26dee1ad47SJeff Kirsher 27dee1ad47SJeff Kirsher *******************************************************************************/ 28dee1ad47SJeff Kirsher 29dee1ad47SJeff Kirsher #ifndef _E1000_DEFINES_H_ 30dee1ad47SJeff Kirsher #define _E1000_DEFINES_H_ 31dee1ad47SJeff Kirsher 32dee1ad47SJeff Kirsher #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 33dee1ad47SJeff Kirsher #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 34dee1ad47SJeff Kirsher #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 35dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 36dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 37dee1ad47SJeff Kirsher #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 38dee1ad47SJeff Kirsher #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 39dee1ad47SJeff Kirsher #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 40dee1ad47SJeff Kirsher #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 41dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 42dee1ad47SJeff Kirsher #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 43dee1ad47SJeff Kirsher #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 44dee1ad47SJeff Kirsher #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 45dee1ad47SJeff Kirsher #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 46dee1ad47SJeff Kirsher #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 47dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 48dee1ad47SJeff Kirsher #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 49dee1ad47SJeff Kirsher #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 50dee1ad47SJeff Kirsher 51dee1ad47SJeff Kirsher /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 52dee1ad47SJeff Kirsher #define REQ_TX_DESCRIPTOR_MULTIPLE 8 53dee1ad47SJeff Kirsher #define REQ_RX_DESCRIPTOR_MULTIPLE 8 54dee1ad47SJeff Kirsher 55dee1ad47SJeff Kirsher /* Definitions for power management and wakeup registers */ 56dee1ad47SJeff Kirsher /* Wake Up Control */ 57dee1ad47SJeff Kirsher #define E1000_WUC_APME 0x00000001 /* APM Enable */ 58dee1ad47SJeff Kirsher #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 59dee1ad47SJeff Kirsher #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 60dee1ad47SJeff Kirsher 61dee1ad47SJeff Kirsher /* Wake Up Filter Control */ 62dee1ad47SJeff Kirsher #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 63dee1ad47SJeff Kirsher #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 64dee1ad47SJeff Kirsher #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 65dee1ad47SJeff Kirsher #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 66dee1ad47SJeff Kirsher #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 67dee1ad47SJeff Kirsher #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 68dee1ad47SJeff Kirsher 69dee1ad47SJeff Kirsher /* Wake Up Status */ 70dee1ad47SJeff Kirsher #define E1000_WUS_LNKC E1000_WUFC_LNKC 71dee1ad47SJeff Kirsher #define E1000_WUS_MAG E1000_WUFC_MAG 72dee1ad47SJeff Kirsher #define E1000_WUS_EX E1000_WUFC_EX 73dee1ad47SJeff Kirsher #define E1000_WUS_MC E1000_WUFC_MC 74dee1ad47SJeff Kirsher #define E1000_WUS_BC E1000_WUFC_BC 75dee1ad47SJeff Kirsher 76dee1ad47SJeff Kirsher /* Extended Device Control */ 772fbe4526SBruce Allan #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 78dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 79ba9e186fSBruce Allan #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 80dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 81dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 82dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 83dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 84dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 85dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 86dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_EIAME 0x01000000 87dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 88dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 89dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 90dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 91dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LSECCK 0x00001000 92dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_PHYPDEN 0x00100000 93dee1ad47SJeff Kirsher 94dee1ad47SJeff Kirsher /* Receive Descriptor bit definitions */ 95dee1ad47SJeff Kirsher #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 96dee1ad47SJeff Kirsher #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 97dee1ad47SJeff Kirsher #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 98dee1ad47SJeff Kirsher #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 99dee1ad47SJeff Kirsher #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 100dee1ad47SJeff Kirsher #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 101dee1ad47SJeff Kirsher #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 102dee1ad47SJeff Kirsher #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 103dee1ad47SJeff Kirsher #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 104dee1ad47SJeff Kirsher #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 105dee1ad47SJeff Kirsher #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 1062e1706f2SBruce Allan #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 107dee1ad47SJeff Kirsher #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 108dee1ad47SJeff Kirsher #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 109dee1ad47SJeff Kirsher 110b67e1913SBruce Allan #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 111dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_CE 0x01000000 112dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_SE 0x02000000 113dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_SEQ 0x04000000 114dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_CXE 0x10000000 115dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_RXE 0x80000000 116dee1ad47SJeff Kirsher 117dee1ad47SJeff Kirsher /* mask to determine if packets should be dropped due to frame errors */ 118dee1ad47SJeff Kirsher #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 119dee1ad47SJeff Kirsher E1000_RXD_ERR_CE | \ 120dee1ad47SJeff Kirsher E1000_RXD_ERR_SE | \ 121dee1ad47SJeff Kirsher E1000_RXD_ERR_SEQ | \ 122dee1ad47SJeff Kirsher E1000_RXD_ERR_CXE | \ 123dee1ad47SJeff Kirsher E1000_RXD_ERR_RXE) 124dee1ad47SJeff Kirsher 125dee1ad47SJeff Kirsher /* Same mask, but for extended and packet split descriptors */ 126dee1ad47SJeff Kirsher #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 127dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_CE | \ 128dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_SE | \ 129dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_SEQ | \ 130dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_CXE | \ 131dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_RXE) 132dee1ad47SJeff Kirsher 13370495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 13470495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 13570495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 13670495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 13770495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 13870495a50SBruce Allan #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 13970495a50SBruce Allan 140dee1ad47SJeff Kirsher #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 141dee1ad47SJeff Kirsher 142dee1ad47SJeff Kirsher /* Management Control */ 143dee1ad47SJeff Kirsher #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 144dee1ad47SJeff Kirsher #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 145dee1ad47SJeff Kirsher #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 146dee1ad47SJeff Kirsher #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 147dee1ad47SJeff Kirsher #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 148dee1ad47SJeff Kirsher /* Enable MAC address filtering */ 149dee1ad47SJeff Kirsher #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 150dee1ad47SJeff Kirsher /* Enable MNG packets to host memory */ 151dee1ad47SJeff Kirsher #define E1000_MANC_EN_MNG2HOST 0x00200000 152dee1ad47SJeff Kirsher 153dee1ad47SJeff Kirsher #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 154dee1ad47SJeff Kirsher #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 155dee1ad47SJeff Kirsher #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 156dee1ad47SJeff Kirsher #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 157dee1ad47SJeff Kirsher 158dee1ad47SJeff Kirsher /* Receive Control */ 159dee1ad47SJeff Kirsher #define E1000_RCTL_EN 0x00000002 /* enable */ 160dee1ad47SJeff Kirsher #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 161dee1ad47SJeff Kirsher #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 162dee1ad47SJeff Kirsher #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 163dee1ad47SJeff Kirsher #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 164dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 165dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 166dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 167dee1ad47SJeff Kirsher #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 168dee1ad47SJeff Kirsher #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 169dee1ad47SJeff Kirsher #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 170dee1ad47SJeff Kirsher #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 171dee1ad47SJeff Kirsher #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 172dee1ad47SJeff Kirsher /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 173dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 174dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 175dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 176dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 177dee1ad47SJeff Kirsher /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 178dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 179dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 180dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 181dee1ad47SJeff Kirsher #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 182dee1ad47SJeff Kirsher #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 183dee1ad47SJeff Kirsher #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 184cf955e6cSBen Greear #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 185dee1ad47SJeff Kirsher #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 186dee1ad47SJeff Kirsher #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 187dee1ad47SJeff Kirsher #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 188dee1ad47SJeff Kirsher 189e921eb1aSBruce Allan /* Use byte values for the following shift parameters 190dee1ad47SJeff Kirsher * Usage: 191dee1ad47SJeff Kirsher * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 192dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE0_MASK) | 193dee1ad47SJeff Kirsher * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 194dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE1_MASK) | 195dee1ad47SJeff Kirsher * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 196dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE2_MASK) | 197dee1ad47SJeff Kirsher * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 198dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE3_MASK)) 199dee1ad47SJeff Kirsher * where value0 = [128..16256], default=256 200dee1ad47SJeff Kirsher * value1 = [1024..64512], default=4096 201dee1ad47SJeff Kirsher * value2 = [0..64512], default=4096 202dee1ad47SJeff Kirsher * value3 = [0..64512], default=0 203dee1ad47SJeff Kirsher */ 204dee1ad47SJeff Kirsher 205dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 206dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 207dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 208dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 209dee1ad47SJeff Kirsher 210dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 211dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 212dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 213dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 214dee1ad47SJeff Kirsher 215dee1ad47SJeff Kirsher /* SWFW_SYNC Definitions */ 216dee1ad47SJeff Kirsher #define E1000_SWFW_EEP_SM 0x1 217dee1ad47SJeff Kirsher #define E1000_SWFW_PHY0_SM 0x2 218dee1ad47SJeff Kirsher #define E1000_SWFW_PHY1_SM 0x4 219dee1ad47SJeff Kirsher #define E1000_SWFW_CSR_SM 0x8 220dee1ad47SJeff Kirsher 221dee1ad47SJeff Kirsher /* Device Control */ 222dee1ad47SJeff Kirsher #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 223dee1ad47SJeff Kirsher #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 224dee1ad47SJeff Kirsher #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 225dee1ad47SJeff Kirsher #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 226dee1ad47SJeff Kirsher #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 227dee1ad47SJeff Kirsher #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 228dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 229dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 230dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 231dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 232dee1ad47SJeff Kirsher #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 233dee1ad47SJeff Kirsher #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 234dee1ad47SJeff Kirsher #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 235dee1ad47SJeff Kirsher #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 23694fb848bSBruce Allan #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 237dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 238dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 239dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 240dee1ad47SJeff Kirsher #define E1000_CTRL_RST 0x04000000 /* Global reset */ 241dee1ad47SJeff Kirsher #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 242dee1ad47SJeff Kirsher #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 243dee1ad47SJeff Kirsher #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 244dee1ad47SJeff Kirsher #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 245dee1ad47SJeff Kirsher 2461241f29fSBruce Allan #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 2471241f29fSBruce Allan 2481241f29fSBruce Allan #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 249dee1ad47SJeff Kirsher 250dee1ad47SJeff Kirsher /* Device Status */ 251dee1ad47SJeff Kirsher #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 252dee1ad47SJeff Kirsher #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 253dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 254dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_SHIFT 2 255dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 256dee1ad47SJeff Kirsher #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 257dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 258dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 259dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 260dee1ad47SJeff Kirsher #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 261dee1ad47SJeff Kirsher #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 262dee1ad47SJeff Kirsher #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 263dee1ad47SJeff Kirsher 264dee1ad47SJeff Kirsher /* Constants used to interpret the masked PCI-X bus speed. */ 265dee1ad47SJeff Kirsher 266dee1ad47SJeff Kirsher #define HALF_DUPLEX 1 267dee1ad47SJeff Kirsher #define FULL_DUPLEX 2 268dee1ad47SJeff Kirsher 269dee1ad47SJeff Kirsher 270dee1ad47SJeff Kirsher #define ADVERTISE_10_HALF 0x0001 271dee1ad47SJeff Kirsher #define ADVERTISE_10_FULL 0x0002 272dee1ad47SJeff Kirsher #define ADVERTISE_100_HALF 0x0004 273dee1ad47SJeff Kirsher #define ADVERTISE_100_FULL 0x0008 274dee1ad47SJeff Kirsher #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 275dee1ad47SJeff Kirsher #define ADVERTISE_1000_FULL 0x0020 276dee1ad47SJeff Kirsher 277dee1ad47SJeff Kirsher /* 1000/H is not supported, nor spec-compliant. */ 278dee1ad47SJeff Kirsher #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 279dee1ad47SJeff Kirsher ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 280dee1ad47SJeff Kirsher ADVERTISE_1000_FULL) 281dee1ad47SJeff Kirsher #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 282dee1ad47SJeff Kirsher ADVERTISE_100_HALF | ADVERTISE_100_FULL) 283dee1ad47SJeff Kirsher #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 284dee1ad47SJeff Kirsher #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 285dee1ad47SJeff Kirsher #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 286dee1ad47SJeff Kirsher 287dee1ad47SJeff Kirsher #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 288dee1ad47SJeff Kirsher 289dee1ad47SJeff Kirsher /* LED Control */ 290dee1ad47SJeff Kirsher #define E1000_PHY_LED0_MODE_MASK 0x00000007 291dee1ad47SJeff Kirsher #define E1000_PHY_LED0_IVRT 0x00000008 292dee1ad47SJeff Kirsher #define E1000_PHY_LED0_MASK 0x0000001F 293dee1ad47SJeff Kirsher 294dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 295dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_MODE_SHIFT 0 296dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_IVRT 0x00000040 297dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_BLINK 0x00000080 298dee1ad47SJeff Kirsher 299dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LINK_UP 0x2 300dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LED_ON 0xE 301dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LED_OFF 0xF 302dee1ad47SJeff Kirsher 303dee1ad47SJeff Kirsher /* Transmit Descriptor bit definitions */ 304dee1ad47SJeff Kirsher #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 305dee1ad47SJeff Kirsher #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 306dee1ad47SJeff Kirsher #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 307dee1ad47SJeff Kirsher #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 308dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 309dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 310dee1ad47SJeff Kirsher #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 311dee1ad47SJeff Kirsher #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 312dee1ad47SJeff Kirsher #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 313dee1ad47SJeff Kirsher #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 314dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 315dee1ad47SJeff Kirsher #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 316dee1ad47SJeff Kirsher #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 317dee1ad47SJeff Kirsher #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 318dee1ad47SJeff Kirsher #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 319dee1ad47SJeff Kirsher #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 320dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 321dee1ad47SJeff Kirsher #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 322dee1ad47SJeff Kirsher #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 323b67e1913SBruce Allan #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 324dee1ad47SJeff Kirsher 325dee1ad47SJeff Kirsher /* Transmit Control */ 326dee1ad47SJeff Kirsher #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 327dee1ad47SJeff Kirsher #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 328dee1ad47SJeff Kirsher #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 329dee1ad47SJeff Kirsher #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 330dee1ad47SJeff Kirsher #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 331dee1ad47SJeff Kirsher #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 332dee1ad47SJeff Kirsher 333dee1ad47SJeff Kirsher /* Transmit Arbitration Count */ 334dee1ad47SJeff Kirsher 335dee1ad47SJeff Kirsher /* SerDes Control */ 336dee1ad47SJeff Kirsher #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 337dee1ad47SJeff Kirsher 338dee1ad47SJeff Kirsher /* Receive Checksum Control */ 339dee1ad47SJeff Kirsher #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 340dee1ad47SJeff Kirsher #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 34170495a50SBruce Allan #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 342dee1ad47SJeff Kirsher 343dee1ad47SJeff Kirsher /* Header split receive */ 344dee1ad47SJeff Kirsher #define E1000_RFCTL_NFSW_DIS 0x00000040 345dee1ad47SJeff Kirsher #define E1000_RFCTL_NFSR_DIS 0x00000080 346dee1ad47SJeff Kirsher #define E1000_RFCTL_ACK_DIS 0x00001000 347dee1ad47SJeff Kirsher #define E1000_RFCTL_EXTEN 0x00008000 348dee1ad47SJeff Kirsher #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 349dee1ad47SJeff Kirsher #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 350dee1ad47SJeff Kirsher 351dee1ad47SJeff Kirsher /* Collision related configuration parameters */ 352dee1ad47SJeff Kirsher #define E1000_COLLISION_THRESHOLD 15 353dee1ad47SJeff Kirsher #define E1000_CT_SHIFT 4 354dee1ad47SJeff Kirsher #define E1000_COLLISION_DISTANCE 63 355dee1ad47SJeff Kirsher #define E1000_COLD_SHIFT 12 356dee1ad47SJeff Kirsher 357dee1ad47SJeff Kirsher /* Default values for the transmit IPG register */ 358dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGT_COPPER 8 359dee1ad47SJeff Kirsher 360dee1ad47SJeff Kirsher #define E1000_TIPG_IPGT_MASK 0x000003FF 361dee1ad47SJeff Kirsher 362dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGR1 8 363dee1ad47SJeff Kirsher #define E1000_TIPG_IPGR1_SHIFT 10 364dee1ad47SJeff Kirsher 365dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGR2 6 366dee1ad47SJeff Kirsher #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 367dee1ad47SJeff Kirsher #define E1000_TIPG_IPGR2_SHIFT 20 368dee1ad47SJeff Kirsher 369dee1ad47SJeff Kirsher #define MAX_JUMBO_FRAME_SIZE 0x3F00 370dee1ad47SJeff Kirsher 371dee1ad47SJeff Kirsher /* Extended Configuration Control and Size */ 372dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 373dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 374dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 375dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 376dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 377dee1ad47SJeff Kirsher #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 378dee1ad47SJeff Kirsher #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 379dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 380dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 381dee1ad47SJeff Kirsher 382dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 383dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 384dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 385dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 386dee1ad47SJeff Kirsher 387dee1ad47SJeff Kirsher #define E1000_KABGTXD_BGSQLBIAS 0x00050000 388dee1ad47SJeff Kirsher 389203e4151SBruce Allan /* Low Power IDLE Control */ 390203e4151SBruce Allan #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 391203e4151SBruce Allan 392dee1ad47SJeff Kirsher /* PBA constants */ 393dee1ad47SJeff Kirsher #define E1000_PBA_8K 0x0008 /* 8KB */ 394dee1ad47SJeff Kirsher #define E1000_PBA_16K 0x0010 /* 16KB */ 395dee1ad47SJeff Kirsher 396*3e35d991SBruce Allan #define E1000_PBA_RXA_MASK 0xFFFF 397*3e35d991SBruce Allan 398dee1ad47SJeff Kirsher #define E1000_PBS_16K E1000_PBA_16K 399dee1ad47SJeff Kirsher 40094fb848bSBruce Allan /* Uncorrectable/correctable ECC Error counts and enable bits */ 40194fb848bSBruce Allan #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 40294fb848bSBruce Allan #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 40394fb848bSBruce Allan #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 40494fb848bSBruce Allan #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 40594fb848bSBruce Allan 406dee1ad47SJeff Kirsher #define IFS_MAX 80 407dee1ad47SJeff Kirsher #define IFS_MIN 40 408dee1ad47SJeff Kirsher #define IFS_RATIO 4 409dee1ad47SJeff Kirsher #define IFS_STEP 10 410dee1ad47SJeff Kirsher #define MIN_NUM_XMITS 1000 411dee1ad47SJeff Kirsher 412dee1ad47SJeff Kirsher /* SW Semaphore Register */ 413dee1ad47SJeff Kirsher #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 414dee1ad47SJeff Kirsher #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 415dee1ad47SJeff Kirsher #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 416dee1ad47SJeff Kirsher 417dee1ad47SJeff Kirsher #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 418dee1ad47SJeff Kirsher 419dee1ad47SJeff Kirsher /* Interrupt Cause Read */ 420dee1ad47SJeff Kirsher #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 421dee1ad47SJeff Kirsher #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 422dee1ad47SJeff Kirsher #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 423dee1ad47SJeff Kirsher #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 424dee1ad47SJeff Kirsher #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 42594fb848bSBruce Allan #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 426dee1ad47SJeff Kirsher #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 427dee1ad47SJeff Kirsher #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 428dee1ad47SJeff Kirsher #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 429dee1ad47SJeff Kirsher #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 430dee1ad47SJeff Kirsher #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 431dee1ad47SJeff Kirsher #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 432dee1ad47SJeff Kirsher 433dee1ad47SJeff Kirsher /* PBA ECC Register */ 434dee1ad47SJeff Kirsher #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 435dee1ad47SJeff Kirsher #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 436dee1ad47SJeff Kirsher #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ 437dee1ad47SJeff Kirsher #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 438dee1ad47SJeff Kirsher #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 439dee1ad47SJeff Kirsher 440e921eb1aSBruce Allan /* This defines the bits that are set in the Interrupt Mask 441dee1ad47SJeff Kirsher * Set/Read Register. Each bit is documented below: 442dee1ad47SJeff Kirsher * o RXT0 = Receiver Timer Interrupt (ring 0) 443dee1ad47SJeff Kirsher * o TXDW = Transmit Descriptor Written Back 444dee1ad47SJeff Kirsher * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 445dee1ad47SJeff Kirsher * o RXSEQ = Receive Sequence Error 446dee1ad47SJeff Kirsher * o LSC = Link Status Change 447dee1ad47SJeff Kirsher */ 448dee1ad47SJeff Kirsher #define IMS_ENABLE_MASK ( \ 449dee1ad47SJeff Kirsher E1000_IMS_RXT0 | \ 450dee1ad47SJeff Kirsher E1000_IMS_TXDW | \ 451dee1ad47SJeff Kirsher E1000_IMS_RXDMT0 | \ 452dee1ad47SJeff Kirsher E1000_IMS_RXSEQ | \ 453dee1ad47SJeff Kirsher E1000_IMS_LSC) 454dee1ad47SJeff Kirsher 455dee1ad47SJeff Kirsher /* Interrupt Mask Set */ 456dee1ad47SJeff Kirsher #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 457dee1ad47SJeff Kirsher #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 458dee1ad47SJeff Kirsher #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 459dee1ad47SJeff Kirsher #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 460dee1ad47SJeff Kirsher #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 46194fb848bSBruce Allan #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 462dee1ad47SJeff Kirsher #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 463dee1ad47SJeff Kirsher #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 464dee1ad47SJeff Kirsher #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 465dee1ad47SJeff Kirsher #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 466dee1ad47SJeff Kirsher #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 467dee1ad47SJeff Kirsher 468dee1ad47SJeff Kirsher /* Interrupt Cause Set */ 469dee1ad47SJeff Kirsher #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 470dee1ad47SJeff Kirsher #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 471dee1ad47SJeff Kirsher #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 472dee1ad47SJeff Kirsher 473dee1ad47SJeff Kirsher /* Transmit Descriptor Control */ 474dee1ad47SJeff Kirsher #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 475dee1ad47SJeff Kirsher #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 476dee1ad47SJeff Kirsher #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 477dee1ad47SJeff Kirsher #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 478dee1ad47SJeff Kirsher #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 479dee1ad47SJeff Kirsher #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 480dee1ad47SJeff Kirsher /* Enable the counting of desc. still to be processed. */ 481dee1ad47SJeff Kirsher #define E1000_TXDCTL_COUNT_DESC 0x00400000 482dee1ad47SJeff Kirsher 483dee1ad47SJeff Kirsher /* Flow Control Constants */ 484dee1ad47SJeff Kirsher #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 485dee1ad47SJeff Kirsher #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 486dee1ad47SJeff Kirsher #define FLOW_CONTROL_TYPE 0x8808 487dee1ad47SJeff Kirsher 488dee1ad47SJeff Kirsher /* 802.1q VLAN Packet Size */ 489dee1ad47SJeff Kirsher #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 490dee1ad47SJeff Kirsher 491e921eb1aSBruce Allan /* Receive Address 492dee1ad47SJeff Kirsher * Number of high/low register pairs in the RAR. The RAR (Receive Address 493dee1ad47SJeff Kirsher * Registers) holds the directed and multicast addresses that we monitor. 494dee1ad47SJeff Kirsher * Technically, we have 16 spots. However, we reserve one of these spots 495dee1ad47SJeff Kirsher * (RAR[15]) for our directed address used by controllers with 496dee1ad47SJeff Kirsher * manageability enabled, allowing us room for 15 multicast addresses. 497dee1ad47SJeff Kirsher */ 498dee1ad47SJeff Kirsher #define E1000_RAR_ENTRIES 15 499dee1ad47SJeff Kirsher #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 500dee1ad47SJeff Kirsher #define E1000_RAL_MAC_ADDR_LEN 4 501dee1ad47SJeff Kirsher #define E1000_RAH_MAC_ADDR_LEN 2 502dee1ad47SJeff Kirsher 503dee1ad47SJeff Kirsher /* Error Codes */ 504dee1ad47SJeff Kirsher #define E1000_ERR_NVM 1 505dee1ad47SJeff Kirsher #define E1000_ERR_PHY 2 506dee1ad47SJeff Kirsher #define E1000_ERR_CONFIG 3 507dee1ad47SJeff Kirsher #define E1000_ERR_PARAM 4 508dee1ad47SJeff Kirsher #define E1000_ERR_MAC_INIT 5 509dee1ad47SJeff Kirsher #define E1000_ERR_PHY_TYPE 6 510dee1ad47SJeff Kirsher #define E1000_ERR_RESET 9 511dee1ad47SJeff Kirsher #define E1000_ERR_MASTER_REQUESTS_PENDING 10 512dee1ad47SJeff Kirsher #define E1000_ERR_HOST_INTERFACE_COMMAND 11 513dee1ad47SJeff Kirsher #define E1000_BLK_PHY_RESET 12 514dee1ad47SJeff Kirsher #define E1000_ERR_SWFW_SYNC 13 515dee1ad47SJeff Kirsher #define E1000_NOT_IMPLEMENTED 14 516dee1ad47SJeff Kirsher #define E1000_ERR_INVALID_ARGUMENT 16 517dee1ad47SJeff Kirsher #define E1000_ERR_NO_SPACE 17 518dee1ad47SJeff Kirsher #define E1000_ERR_NVM_PBA_SECTION 18 519dee1ad47SJeff Kirsher 520dee1ad47SJeff Kirsher /* Loop limit on how long we wait for auto-negotiation to complete */ 521dee1ad47SJeff Kirsher #define FIBER_LINK_UP_LIMIT 50 522dee1ad47SJeff Kirsher #define COPPER_LINK_UP_LIMIT 10 523dee1ad47SJeff Kirsher #define PHY_AUTO_NEG_LIMIT 45 524dee1ad47SJeff Kirsher #define PHY_FORCE_LIMIT 20 525dee1ad47SJeff Kirsher /* Number of 100 microseconds we wait for PCI Express master disable */ 526dee1ad47SJeff Kirsher #define MASTER_DISABLE_TIMEOUT 800 527dee1ad47SJeff Kirsher /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 528dee1ad47SJeff Kirsher #define PHY_CFG_TIMEOUT 100 529dee1ad47SJeff Kirsher /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 530dee1ad47SJeff Kirsher #define MDIO_OWNERSHIP_TIMEOUT 10 531dee1ad47SJeff Kirsher /* Number of milliseconds for NVM auto read done after MAC reset. */ 532dee1ad47SJeff Kirsher #define AUTO_READ_DONE_TIMEOUT 10 533dee1ad47SJeff Kirsher 534dee1ad47SJeff Kirsher /* Flow Control */ 535dee1ad47SJeff Kirsher #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 536dee1ad47SJeff Kirsher #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 537dee1ad47SJeff Kirsher #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 538dee1ad47SJeff Kirsher 539dee1ad47SJeff Kirsher /* Transmit Configuration Word */ 540dee1ad47SJeff Kirsher #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 541dee1ad47SJeff Kirsher #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 542dee1ad47SJeff Kirsher #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 543dee1ad47SJeff Kirsher #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 544dee1ad47SJeff Kirsher #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 545dee1ad47SJeff Kirsher 546dee1ad47SJeff Kirsher /* Receive Configuration Word */ 547dee1ad47SJeff Kirsher #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 548dee1ad47SJeff Kirsher #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 549dee1ad47SJeff Kirsher #define E1000_RXCW_C 0x20000000 /* Receive config */ 550dee1ad47SJeff Kirsher #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 551dee1ad47SJeff Kirsher 552b67e1913SBruce Allan #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 553b67e1913SBruce Allan #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 554b67e1913SBruce Allan #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 555b67e1913SBruce Allan 556b67e1913SBruce Allan #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 557b67e1913SBruce Allan #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 558d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 559d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 560d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 561d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 562d89777bfSBruce Allan #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 563b67e1913SBruce Allan #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 564b67e1913SBruce Allan #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 565b67e1913SBruce Allan 566d89777bfSBruce Allan #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 567d89777bfSBruce Allan #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 568d89777bfSBruce Allan 569d89777bfSBruce Allan #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 570d89777bfSBruce Allan #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 571d89777bfSBruce Allan 572b67e1913SBruce Allan #define E1000_TIMINCA_INCPERIOD_SHIFT 24 573b67e1913SBruce Allan #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 574b67e1913SBruce Allan 575dee1ad47SJeff Kirsher /* PCI Express Control */ 576dee1ad47SJeff Kirsher #define E1000_GCR_RXD_NO_SNOOP 0x00000001 577dee1ad47SJeff Kirsher #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 578dee1ad47SJeff Kirsher #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 579dee1ad47SJeff Kirsher #define E1000_GCR_TXD_NO_SNOOP 0x00000008 580dee1ad47SJeff Kirsher #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 581dee1ad47SJeff Kirsher #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 582dee1ad47SJeff Kirsher 583dee1ad47SJeff Kirsher #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 584dee1ad47SJeff Kirsher E1000_GCR_RXDSCW_NO_SNOOP | \ 585dee1ad47SJeff Kirsher E1000_GCR_RXDSCR_NO_SNOOP | \ 586dee1ad47SJeff Kirsher E1000_GCR_TXD_NO_SNOOP | \ 587dee1ad47SJeff Kirsher E1000_GCR_TXDSCW_NO_SNOOP | \ 588dee1ad47SJeff Kirsher E1000_GCR_TXDSCR_NO_SNOOP) 589dee1ad47SJeff Kirsher 590dee1ad47SJeff Kirsher /* PHY Control Register */ 591dee1ad47SJeff Kirsher #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 592dee1ad47SJeff Kirsher #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 593dee1ad47SJeff Kirsher #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 594dee1ad47SJeff Kirsher #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 595dee1ad47SJeff Kirsher #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 596dee1ad47SJeff Kirsher #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 597dee1ad47SJeff Kirsher #define MII_CR_SPEED_1000 0x0040 598dee1ad47SJeff Kirsher #define MII_CR_SPEED_100 0x2000 599dee1ad47SJeff Kirsher #define MII_CR_SPEED_10 0x0000 600dee1ad47SJeff Kirsher 601dee1ad47SJeff Kirsher /* PHY Status Register */ 602dee1ad47SJeff Kirsher #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 603dee1ad47SJeff Kirsher #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 604dee1ad47SJeff Kirsher 605dee1ad47SJeff Kirsher /* Autoneg Advertisement Register */ 606dee1ad47SJeff Kirsher #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 607dee1ad47SJeff Kirsher #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 608dee1ad47SJeff Kirsher #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 609dee1ad47SJeff Kirsher #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 610dee1ad47SJeff Kirsher #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 611dee1ad47SJeff Kirsher #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 612dee1ad47SJeff Kirsher 613dee1ad47SJeff Kirsher /* Link Partner Ability Register (Base Page) */ 6142fbe4526SBruce Allan #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 615dee1ad47SJeff Kirsher #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 616dee1ad47SJeff Kirsher #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 617dee1ad47SJeff Kirsher 618dee1ad47SJeff Kirsher /* Autoneg Expansion Register */ 619dee1ad47SJeff Kirsher #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 620dee1ad47SJeff Kirsher 621dee1ad47SJeff Kirsher /* 1000BASE-T Control Register */ 622dee1ad47SJeff Kirsher #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 623dee1ad47SJeff Kirsher #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 624dee1ad47SJeff Kirsher /* 0=DTE device */ 625dee1ad47SJeff Kirsher #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 626dee1ad47SJeff Kirsher /* 0=Configure PHY as Slave */ 627dee1ad47SJeff Kirsher #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 628dee1ad47SJeff Kirsher /* 0=Automatic Master/Slave config */ 629dee1ad47SJeff Kirsher 630dee1ad47SJeff Kirsher /* 1000BASE-T Status Register */ 631dee1ad47SJeff Kirsher #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 632dee1ad47SJeff Kirsher #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 633dee1ad47SJeff Kirsher 634dee1ad47SJeff Kirsher 635dee1ad47SJeff Kirsher /* PHY 1000 MII Register/Bit Definitions */ 636dee1ad47SJeff Kirsher /* PHY Registers defined by IEEE */ 637dee1ad47SJeff Kirsher #define PHY_CONTROL 0x00 /* Control Register */ 638dee1ad47SJeff Kirsher #define PHY_STATUS 0x01 /* Status Register */ 639dee1ad47SJeff Kirsher #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 640dee1ad47SJeff Kirsher #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 641dee1ad47SJeff Kirsher #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 642dee1ad47SJeff Kirsher #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 643dee1ad47SJeff Kirsher #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 644dee1ad47SJeff Kirsher #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 645dee1ad47SJeff Kirsher #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 646dee1ad47SJeff Kirsher #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 647dee1ad47SJeff Kirsher 648dee1ad47SJeff Kirsher #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 649dee1ad47SJeff Kirsher 650dee1ad47SJeff Kirsher /* NVM Control */ 651dee1ad47SJeff Kirsher #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 652dee1ad47SJeff Kirsher #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 653dee1ad47SJeff Kirsher #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 654dee1ad47SJeff Kirsher #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 655dee1ad47SJeff Kirsher #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 656dee1ad47SJeff Kirsher #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 657dee1ad47SJeff Kirsher #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 658dee1ad47SJeff Kirsher #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 659dee1ad47SJeff Kirsher /* NVM Addressing bits based on type (0-small, 1-large) */ 660dee1ad47SJeff Kirsher #define E1000_EECD_ADDR_BITS 0x00000400 661dee1ad47SJeff Kirsher #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 662dee1ad47SJeff Kirsher #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 663dee1ad47SJeff Kirsher #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 664dee1ad47SJeff Kirsher #define E1000_EECD_SIZE_EX_SHIFT 11 665dee1ad47SJeff Kirsher #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 666dee1ad47SJeff Kirsher #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 667dee1ad47SJeff Kirsher #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 668dee1ad47SJeff Kirsher #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 669dee1ad47SJeff Kirsher 670dee1ad47SJeff Kirsher #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ 671dee1ad47SJeff Kirsher #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 672dee1ad47SJeff Kirsher #define E1000_NVM_RW_REG_START 1 /* Start operation */ 673dee1ad47SJeff Kirsher #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 674dee1ad47SJeff Kirsher #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 675dee1ad47SJeff Kirsher #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 676dee1ad47SJeff Kirsher #define E1000_FLASH_UPDATES 2000 677dee1ad47SJeff Kirsher 678dee1ad47SJeff Kirsher /* NVM Word Offsets */ 679dee1ad47SJeff Kirsher #define NVM_COMPAT 0x0003 680dee1ad47SJeff Kirsher #define NVM_ID_LED_SETTINGS 0x0004 6811cc7a3a1SBruce Allan #define NVM_FUTURE_INIT_WORD1 0x0019 6821cc7a3a1SBruce Allan #define NVM_COMPAT_VALID_CSUM 0x0001 6831cc7a3a1SBruce Allan #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 6841cc7a3a1SBruce Allan 685dee1ad47SJeff Kirsher #define NVM_INIT_CONTROL2_REG 0x000F 686dee1ad47SJeff Kirsher #define NVM_INIT_CONTROL3_PORT_B 0x0014 687dee1ad47SJeff Kirsher #define NVM_INIT_3GIO_3 0x001A 688dee1ad47SJeff Kirsher #define NVM_INIT_CONTROL3_PORT_A 0x0024 689dee1ad47SJeff Kirsher #define NVM_CFG 0x0012 690dee1ad47SJeff Kirsher #define NVM_ALT_MAC_ADDR_PTR 0x0037 691dee1ad47SJeff Kirsher #define NVM_CHECKSUM_REG 0x003F 692dee1ad47SJeff Kirsher 693dee1ad47SJeff Kirsher #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ 694dee1ad47SJeff Kirsher 695dee1ad47SJeff Kirsher #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 696dee1ad47SJeff Kirsher #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 697dee1ad47SJeff Kirsher 698dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x0f of the NVM */ 699dee1ad47SJeff Kirsher #define NVM_WORD0F_PAUSE_MASK 0x3000 700dee1ad47SJeff Kirsher #define NVM_WORD0F_PAUSE 0x1000 701dee1ad47SJeff Kirsher #define NVM_WORD0F_ASM_DIR 0x2000 702dee1ad47SJeff Kirsher 703dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x1a of the NVM */ 704dee1ad47SJeff Kirsher #define NVM_WORD1A_ASPM_MASK 0x000C 705dee1ad47SJeff Kirsher 706dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x03 of the EEPROM */ 707dee1ad47SJeff Kirsher #define NVM_COMPAT_LOM 0x0800 708dee1ad47SJeff Kirsher 709dee1ad47SJeff Kirsher /* length of string needed to store PBA number */ 710dee1ad47SJeff Kirsher #define E1000_PBANUM_LENGTH 11 711dee1ad47SJeff Kirsher 712dee1ad47SJeff Kirsher /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 713dee1ad47SJeff Kirsher #define NVM_SUM 0xBABA 714dee1ad47SJeff Kirsher 715dee1ad47SJeff Kirsher /* PBA (printed board assembly) number words */ 716dee1ad47SJeff Kirsher #define NVM_PBA_OFFSET_0 8 717dee1ad47SJeff Kirsher #define NVM_PBA_OFFSET_1 9 718dee1ad47SJeff Kirsher #define NVM_PBA_PTR_GUARD 0xFAFA 719dee1ad47SJeff Kirsher #define NVM_WORD_SIZE_BASE_SHIFT 6 720dee1ad47SJeff Kirsher 721dee1ad47SJeff Kirsher /* NVM Commands - SPI */ 722dee1ad47SJeff Kirsher #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 723dee1ad47SJeff Kirsher #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 724dee1ad47SJeff Kirsher #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 725dee1ad47SJeff Kirsher #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 726dee1ad47SJeff Kirsher #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 727dee1ad47SJeff Kirsher #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 728dee1ad47SJeff Kirsher 729dee1ad47SJeff Kirsher /* SPI NVM Status Register */ 730dee1ad47SJeff Kirsher #define NVM_STATUS_RDY_SPI 0x01 731dee1ad47SJeff Kirsher 732dee1ad47SJeff Kirsher /* Word definitions for ID LED Settings */ 733dee1ad47SJeff Kirsher #define ID_LED_RESERVED_0000 0x0000 734dee1ad47SJeff Kirsher #define ID_LED_RESERVED_FFFF 0xFFFF 735dee1ad47SJeff Kirsher #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 736dee1ad47SJeff Kirsher (ID_LED_OFF1_OFF2 << 8) | \ 737dee1ad47SJeff Kirsher (ID_LED_DEF1_DEF2 << 4) | \ 738dee1ad47SJeff Kirsher (ID_LED_DEF1_DEF2)) 739dee1ad47SJeff Kirsher #define ID_LED_DEF1_DEF2 0x1 740dee1ad47SJeff Kirsher #define ID_LED_DEF1_ON2 0x2 741dee1ad47SJeff Kirsher #define ID_LED_DEF1_OFF2 0x3 742dee1ad47SJeff Kirsher #define ID_LED_ON1_DEF2 0x4 743dee1ad47SJeff Kirsher #define ID_LED_ON1_ON2 0x5 744dee1ad47SJeff Kirsher #define ID_LED_ON1_OFF2 0x6 745dee1ad47SJeff Kirsher #define ID_LED_OFF1_DEF2 0x7 746dee1ad47SJeff Kirsher #define ID_LED_OFF1_ON2 0x8 747dee1ad47SJeff Kirsher #define ID_LED_OFF1_OFF2 0x9 748dee1ad47SJeff Kirsher 749dee1ad47SJeff Kirsher #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 750dee1ad47SJeff Kirsher #define IGP_ACTIVITY_LED_ENABLE 0x0300 751dee1ad47SJeff Kirsher #define IGP_LED3_MODE 0x07000000 752dee1ad47SJeff Kirsher 753dee1ad47SJeff Kirsher /* PCI/PCI-X/PCI-EX Config space */ 754dee1ad47SJeff Kirsher #define PCI_HEADER_TYPE_REGISTER 0x0E 755dee1ad47SJeff Kirsher #define PCIE_LINK_STATUS 0x12 756dee1ad47SJeff Kirsher 757dee1ad47SJeff Kirsher #define PCI_HEADER_TYPE_MULTIFUNC 0x80 758dee1ad47SJeff Kirsher #define PCIE_LINK_WIDTH_MASK 0x3F0 759dee1ad47SJeff Kirsher #define PCIE_LINK_WIDTH_SHIFT 4 760dee1ad47SJeff Kirsher 761dee1ad47SJeff Kirsher #define PHY_REVISION_MASK 0xFFFFFFF0 762dee1ad47SJeff Kirsher #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 763dee1ad47SJeff Kirsher #define MAX_PHY_MULTI_PAGE_REG 0xF 764dee1ad47SJeff Kirsher 765e921eb1aSBruce Allan /* Bit definitions for valid PHY IDs. 766dee1ad47SJeff Kirsher * I = Integrated 767dee1ad47SJeff Kirsher * E = External 768dee1ad47SJeff Kirsher */ 769dee1ad47SJeff Kirsher #define M88E1000_E_PHY_ID 0x01410C50 770dee1ad47SJeff Kirsher #define M88E1000_I_PHY_ID 0x01410C30 771dee1ad47SJeff Kirsher #define M88E1011_I_PHY_ID 0x01410C20 772dee1ad47SJeff Kirsher #define IGP01E1000_I_PHY_ID 0x02A80380 773dee1ad47SJeff Kirsher #define M88E1111_I_PHY_ID 0x01410CC0 774dee1ad47SJeff Kirsher #define GG82563_E_PHY_ID 0x01410CA0 775dee1ad47SJeff Kirsher #define IGP03E1000_E_PHY_ID 0x02A80390 776dee1ad47SJeff Kirsher #define IFE_E_PHY_ID 0x02A80330 777dee1ad47SJeff Kirsher #define IFE_PLUS_E_PHY_ID 0x02A80320 778dee1ad47SJeff Kirsher #define IFE_C_E_PHY_ID 0x02A80310 779dee1ad47SJeff Kirsher #define BME1000_E_PHY_ID 0x01410CB0 780dee1ad47SJeff Kirsher #define BME1000_E_PHY_ID_R2 0x01410CB1 781dee1ad47SJeff Kirsher #define I82577_E_PHY_ID 0x01540050 782dee1ad47SJeff Kirsher #define I82578_E_PHY_ID 0x004DD040 783dee1ad47SJeff Kirsher #define I82579_E_PHY_ID 0x01540090 7842fbe4526SBruce Allan #define I217_E_PHY_ID 0x015400A0 785dee1ad47SJeff Kirsher 786dee1ad47SJeff Kirsher /* M88E1000 Specific Registers */ 787dee1ad47SJeff Kirsher #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 788dee1ad47SJeff Kirsher #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 789dee1ad47SJeff Kirsher #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 790dee1ad47SJeff Kirsher 791dee1ad47SJeff Kirsher #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 792dee1ad47SJeff Kirsher #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 793dee1ad47SJeff Kirsher 794dee1ad47SJeff Kirsher /* M88E1000 PHY Specific Control Register */ 795dee1ad47SJeff Kirsher #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 796dee1ad47SJeff Kirsher #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 797dee1ad47SJeff Kirsher /* Manual MDI configuration */ 798dee1ad47SJeff Kirsher #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 799dee1ad47SJeff Kirsher /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 800dee1ad47SJeff Kirsher #define M88E1000_PSCR_AUTO_X_1000T 0x0040 801dee1ad47SJeff Kirsher /* Auto crossover enabled all speeds */ 802dee1ad47SJeff Kirsher #define M88E1000_PSCR_AUTO_X_MODE 0x0060 803e921eb1aSBruce Allan /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold) 804dee1ad47SJeff Kirsher * 0=Normal 10BASE-T Rx Threshold 805dee1ad47SJeff Kirsher */ 806dee1ad47SJeff Kirsher #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 807dee1ad47SJeff Kirsher 808dee1ad47SJeff Kirsher /* M88E1000 PHY Specific Status Register */ 809dee1ad47SJeff Kirsher #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 810dee1ad47SJeff Kirsher #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 811dee1ad47SJeff Kirsher #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 812dee1ad47SJeff Kirsher /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ 813dee1ad47SJeff Kirsher #define M88E1000_PSSR_CABLE_LENGTH 0x0380 814dee1ad47SJeff Kirsher #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 815dee1ad47SJeff Kirsher #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 816dee1ad47SJeff Kirsher 817dee1ad47SJeff Kirsher #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 818dee1ad47SJeff Kirsher 819e921eb1aSBruce Allan /* Number of times we will attempt to autonegotiate before downshifting if we 820dee1ad47SJeff Kirsher * are the master 821dee1ad47SJeff Kirsher */ 822dee1ad47SJeff Kirsher #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 823dee1ad47SJeff Kirsher #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 824e921eb1aSBruce Allan /* Number of times we will attempt to autonegotiate before downshifting if we 825dee1ad47SJeff Kirsher * are the slave 826dee1ad47SJeff Kirsher */ 827dee1ad47SJeff Kirsher #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 828dee1ad47SJeff Kirsher #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 829dee1ad47SJeff Kirsher #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 830dee1ad47SJeff Kirsher 831dee1ad47SJeff Kirsher /* M88EC018 Rev 2 specific DownShift settings */ 832dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 833dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 834dee1ad47SJeff Kirsher 835dee1ad47SJeff Kirsher #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 836dee1ad47SJeff Kirsher #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 837dee1ad47SJeff Kirsher 838dee1ad47SJeff Kirsher /* BME1000 PHY Specific Control Register */ 839dee1ad47SJeff Kirsher #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 840dee1ad47SJeff Kirsher 841203e4151SBruce Allan /* PHY Low Power Idle Control */ 842203e4151SBruce Allan #define I82579_LPI_CTRL PHY_REG(772, 20) 843203e4151SBruce Allan #define I82579_LPI_CTRL_100_ENABLE 0x2000 844203e4151SBruce Allan #define I82579_LPI_CTRL_1000_ENABLE 0x4000 845203e4151SBruce Allan #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 846203e4151SBruce Allan #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 847203e4151SBruce Allan 848203e4151SBruce Allan /* Extended Management Interface (EMI) Registers */ 849203e4151SBruce Allan #define I82579_EMI_ADDR 0x10 850203e4151SBruce Allan #define I82579_EMI_DATA 0x11 851203e4151SBruce Allan #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 852203e4151SBruce Allan #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ 853203e4151SBruce Allan #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ 854203e4151SBruce Allan #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 855203e4151SBruce Allan #define I82579_EEE_PCS_STATUS 0x182D /* IEEE MMD Register 3.1 >> 8 */ 856203e4151SBruce Allan #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ 857203e4151SBruce Allan #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ 858203e4151SBruce Allan #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ 859203e4151SBruce Allan #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */ 860203e4151SBruce Allan #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE supported */ 861203e4151SBruce Allan #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ 862203e4151SBruce Allan #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ 863203e4151SBruce Allan #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ 864203e4151SBruce Allan #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ 865203e4151SBruce Allan 866203e4151SBruce Allan #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ 867203e4151SBruce Allan #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ 868dee1ad47SJeff Kirsher 869dee1ad47SJeff Kirsher #define PHY_PAGE_SHIFT 5 870dee1ad47SJeff Kirsher #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 871dee1ad47SJeff Kirsher ((reg) & MAX_PHY_REG_ADDRESS)) 872dee1ad47SJeff Kirsher 873e921eb1aSBruce Allan /* Bits... 874dee1ad47SJeff Kirsher * 15-5: page 875dee1ad47SJeff Kirsher * 4-0: register offset 876dee1ad47SJeff Kirsher */ 877dee1ad47SJeff Kirsher #define GG82563_PAGE_SHIFT 5 878dee1ad47SJeff Kirsher #define GG82563_REG(page, reg) \ 879dee1ad47SJeff Kirsher (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 880dee1ad47SJeff Kirsher #define GG82563_MIN_ALT_REG 30 881dee1ad47SJeff Kirsher 882dee1ad47SJeff Kirsher /* GG82563 Specific Registers */ 883dee1ad47SJeff Kirsher #define GG82563_PHY_SPEC_CTRL \ 884dee1ad47SJeff Kirsher GG82563_REG(0, 16) /* PHY Specific Control */ 885dee1ad47SJeff Kirsher #define GG82563_PHY_PAGE_SELECT \ 886dee1ad47SJeff Kirsher GG82563_REG(0, 22) /* Page Select */ 887dee1ad47SJeff Kirsher #define GG82563_PHY_SPEC_CTRL_2 \ 888dee1ad47SJeff Kirsher GG82563_REG(0, 26) /* PHY Specific Control 2 */ 889dee1ad47SJeff Kirsher #define GG82563_PHY_PAGE_SELECT_ALT \ 890dee1ad47SJeff Kirsher GG82563_REG(0, 29) /* Alternate Page Select */ 891dee1ad47SJeff Kirsher 892dee1ad47SJeff Kirsher #define GG82563_PHY_MAC_SPEC_CTRL \ 893dee1ad47SJeff Kirsher GG82563_REG(2, 21) /* MAC Specific Control Register */ 894dee1ad47SJeff Kirsher 895dee1ad47SJeff Kirsher #define GG82563_PHY_DSP_DISTANCE \ 896dee1ad47SJeff Kirsher GG82563_REG(5, 26) /* DSP Distance */ 897dee1ad47SJeff Kirsher 898dee1ad47SJeff Kirsher /* Page 193 - Port Control Registers */ 899dee1ad47SJeff Kirsher #define GG82563_PHY_KMRN_MODE_CTRL \ 900dee1ad47SJeff Kirsher GG82563_REG(193, 16) /* Kumeran Mode Control */ 901dee1ad47SJeff Kirsher #define GG82563_PHY_PWR_MGMT_CTRL \ 902dee1ad47SJeff Kirsher GG82563_REG(193, 20) /* Power Management Control */ 903dee1ad47SJeff Kirsher 904dee1ad47SJeff Kirsher /* Page 194 - KMRN Registers */ 905dee1ad47SJeff Kirsher #define GG82563_PHY_INBAND_CTRL \ 906dee1ad47SJeff Kirsher GG82563_REG(194, 18) /* Inband Control */ 907dee1ad47SJeff Kirsher 908dee1ad47SJeff Kirsher /* MDI Control */ 909dee1ad47SJeff Kirsher #define E1000_MDIC_REG_SHIFT 16 910dee1ad47SJeff Kirsher #define E1000_MDIC_PHY_SHIFT 21 911dee1ad47SJeff Kirsher #define E1000_MDIC_OP_WRITE 0x04000000 912dee1ad47SJeff Kirsher #define E1000_MDIC_OP_READ 0x08000000 913dee1ad47SJeff Kirsher #define E1000_MDIC_READY 0x10000000 914dee1ad47SJeff Kirsher #define E1000_MDIC_ERROR 0x40000000 915dee1ad47SJeff Kirsher 916dee1ad47SJeff Kirsher /* SerDes Control */ 917dee1ad47SJeff Kirsher #define E1000_GEN_POLL_TIMEOUT 640 918dee1ad47SJeff Kirsher 9192fbe4526SBruce Allan /* FW Semaphore */ 9202fbe4526SBruce Allan #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 9212fbe4526SBruce Allan #define E1000_FWSM_WLOCK_MAC_SHIFT 7 9222fbe4526SBruce Allan 923dee1ad47SJeff Kirsher #endif /* _E1000_DEFINES_H_ */ 924