1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 2*51dce24bSJeff Kirsher /* Copyright(c) 1999 - 2018 Intel Corporation. */ 321b5a6f8SBruce Allan 421b5a6f8SBruce Allan #ifndef _E1000E_80003ES2LAN_H_ 521b5a6f8SBruce Allan #define _E1000E_80003ES2LAN_H_ 621b5a6f8SBruce Allan 721b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 821b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 921b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 1021b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F 1121b5a6f8SBruce Allan 1221b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 1321b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 1421b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 1521b5a6f8SBruce Allan 1621b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 1721b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 1821b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 1921b5a6f8SBruce Allan 2021b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C 2121b5a6f8SBruce Allan #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 2221b5a6f8SBruce Allan 2321b5a6f8SBruce Allan #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */ 2421b5a6f8SBruce Allan #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 2521b5a6f8SBruce Allan 2621b5a6f8SBruce Allan #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 2721b5a6f8SBruce Allan #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 2821b5a6f8SBruce Allan 2921b5a6f8SBruce Allan /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ 3021b5a6f8SBruce Allan #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */ 3121b5a6f8SBruce Allan #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 3221b5a6f8SBruce Allan #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ 3321b5a6f8SBruce Allan #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ 3421b5a6f8SBruce Allan #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ 3521b5a6f8SBruce Allan 3621b5a6f8SBruce Allan /* PHY Specific Control Register 2 (Page 0, Register 26) */ 3721b5a6f8SBruce Allan #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */ 3821b5a6f8SBruce Allan 3921b5a6f8SBruce Allan /* MAC Specific Control Register (Page 2, Register 21) */ 4021b5a6f8SBruce Allan /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ 4121b5a6f8SBruce Allan #define GG82563_MSCR_TX_CLK_MASK 0x0007 4221b5a6f8SBruce Allan #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 4321b5a6f8SBruce Allan #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 4421b5a6f8SBruce Allan #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 4521b5a6f8SBruce Allan 4621b5a6f8SBruce Allan #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ 4721b5a6f8SBruce Allan 4821b5a6f8SBruce Allan /* DSP Distance Register (Page 5, Register 26) 4921b5a6f8SBruce Allan * 0 = <50M 5021b5a6f8SBruce Allan * 1 = 50-80M 5121b5a6f8SBruce Allan * 2 = 80-100M 5221b5a6f8SBruce Allan * 3 = 110-140M 5321b5a6f8SBruce Allan * 4 = >140M 5421b5a6f8SBruce Allan */ 5521b5a6f8SBruce Allan #define GG82563_DSPD_CABLE_LENGTH 0x0007 5621b5a6f8SBruce Allan 5721b5a6f8SBruce Allan /* Kumeran Mode Control Register (Page 193, Register 16) */ 5821b5a6f8SBruce Allan #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 5921b5a6f8SBruce Allan 6021b5a6f8SBruce Allan /* Max number of times Kumeran read/write should be validated */ 6121b5a6f8SBruce Allan #define GG82563_MAX_KMRN_RETRY 0x5 6221b5a6f8SBruce Allan 6321b5a6f8SBruce Allan /* Power Management Control Register (Page 193, Register 20) */ 6421b5a6f8SBruce Allan /* 1=Enable SERDES Electrical Idle */ 6521b5a6f8SBruce Allan #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 6621b5a6f8SBruce Allan 6721b5a6f8SBruce Allan /* In-Band Control Register (Page 194, Register 18) */ 6821b5a6f8SBruce Allan #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ 6921b5a6f8SBruce Allan 7021b5a6f8SBruce Allan #endif 71