1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2006 Intel Corporation. */ 3 4 /* 5 * e100.c: Intel(R) PRO/100 ethernet driver 6 * 7 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on 8 * original e100 driver, but better described as a munging of 9 * e100, e1000, eepro100, tg3, 8139cp, and other drivers. 10 * 11 * References: 12 * Intel 8255x 10/100 Mbps Ethernet Controller Family, 13 * Open Source Software Developers Manual, 14 * http://sourceforge.net/projects/e1000 15 * 16 * 17 * Theory of Operation 18 * 19 * I. General 20 * 21 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet 22 * controller family, which includes the 82557, 82558, 82559, 82550, 23 * 82551, and 82562 devices. 82558 and greater controllers 24 * integrate the Intel 82555 PHY. The controllers are used in 25 * server and client network interface cards, as well as in 26 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx 27 * configurations. 8255x supports a 32-bit linear addressing 28 * mode and operates at 33Mhz PCI clock rate. 29 * 30 * II. Driver Operation 31 * 32 * Memory-mapped mode is used exclusively to access the device's 33 * shared-memory structure, the Control/Status Registers (CSR). All 34 * setup, configuration, and control of the device, including queuing 35 * of Tx, Rx, and configuration commands is through the CSR. 36 * cmd_lock serializes accesses to the CSR command register. cb_lock 37 * protects the shared Command Block List (CBL). 38 * 39 * 8255x is highly MII-compliant and all access to the PHY go 40 * through the Management Data Interface (MDI). Consequently, the 41 * driver leverages the mii.c library shared with other MII-compliant 42 * devices. 43 * 44 * Big- and Little-Endian byte order as well as 32- and 64-bit 45 * archs are supported. Weak-ordered memory and non-cache-coherent 46 * archs are supported. 47 * 48 * III. Transmit 49 * 50 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked 51 * together in a fixed-size ring (CBL) thus forming the flexible mode 52 * memory structure. A TCB marked with the suspend-bit indicates 53 * the end of the ring. The last TCB processed suspends the 54 * controller, and the controller can be restarted by issue a CU 55 * resume command to continue from the suspend point, or a CU start 56 * command to start at a given position in the ring. 57 * 58 * Non-Tx commands (config, multicast setup, etc) are linked 59 * into the CBL ring along with Tx commands. The common structure 60 * used for both Tx and non-Tx commands is the Command Block (CB). 61 * 62 * cb_to_use is the next CB to use for queuing a command; cb_to_clean 63 * is the next CB to check for completion; cb_to_send is the first 64 * CB to start on in case of a previous failure to resume. CB clean 65 * up happens in interrupt context in response to a CU interrupt. 66 * cbs_avail keeps track of number of free CB resources available. 67 * 68 * Hardware padding of short packets to minimum packet size is 69 * enabled. 82557 pads with 7Eh, while the later controllers pad 70 * with 00h. 71 * 72 * IV. Receive 73 * 74 * The Receive Frame Area (RFA) comprises a ring of Receive Frame 75 * Descriptors (RFD) + data buffer, thus forming the simplified mode 76 * memory structure. Rx skbs are allocated to contain both the RFD 77 * and the data buffer, but the RFD is pulled off before the skb is 78 * indicated. The data buffer is aligned such that encapsulated 79 * protocol headers are u32-aligned. Since the RFD is part of the 80 * mapped shared memory, and completion status is contained within 81 * the RFD, the RFD must be dma_sync'ed to maintain a consistent 82 * view from software and hardware. 83 * 84 * In order to keep updates to the RFD link field from colliding with 85 * hardware writes to mark packets complete, we use the feature that 86 * hardware will not write to a size 0 descriptor and mark the previous 87 * packet as end-of-list (EL). After updating the link, we remove EL 88 * and only then restore the size such that hardware may use the 89 * previous-to-end RFD. 90 * 91 * Under typical operation, the receive unit (RU) is start once, 92 * and the controller happily fills RFDs as frames arrive. If 93 * replacement RFDs cannot be allocated, or the RU goes non-active, 94 * the RU must be restarted. Frame arrival generates an interrupt, 95 * and Rx indication and re-allocation happen in the same context, 96 * therefore no locking is required. A software-generated interrupt 97 * is generated from the watchdog to recover from a failed allocation 98 * scenario where all Rx resources have been indicated and none re- 99 * placed. 100 * 101 * V. Miscellaneous 102 * 103 * VLAN offloading of tagging, stripping and filtering is not 104 * supported, but driver will accommodate the extra 4-byte VLAN tag 105 * for processing by upper layers. Tx/Rx Checksum offloading is not 106 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is 107 * not supported (hardware limitation). 108 * 109 * MagicPacket(tm) WoL support is enabled/disabled via ethtool. 110 * 111 * Thanks to JC (jchapman@katalix.com) for helping with 112 * testing/troubleshooting the development driver. 113 * 114 * TODO: 115 * o several entry points race with dev->close 116 * o check for tx-no-resources/stop Q races with tx clean/wake Q 117 * 118 * FIXES: 119 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com> 120 * - Stratus87247: protect MDI control register manipulations 121 * 2009/06/01 - Andreas Mohr <andi at lisas dot de> 122 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs 123 */ 124 125 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 126 127 #include <linux/hardirq.h> 128 #include <linux/interrupt.h> 129 #include <linux/module.h> 130 #include <linux/moduleparam.h> 131 #include <linux/kernel.h> 132 #include <linux/types.h> 133 #include <linux/sched.h> 134 #include <linux/slab.h> 135 #include <linux/delay.h> 136 #include <linux/init.h> 137 #include <linux/pci.h> 138 #include <linux/dma-mapping.h> 139 #include <linux/dmapool.h> 140 #include <linux/netdevice.h> 141 #include <linux/etherdevice.h> 142 #include <linux/mii.h> 143 #include <linux/if_vlan.h> 144 #include <linux/skbuff.h> 145 #include <linux/ethtool.h> 146 #include <linux/string.h> 147 #include <linux/firmware.h> 148 #include <linux/rtnetlink.h> 149 #include <linux/unaligned.h> 150 151 152 #define DRV_NAME "e100" 153 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" 154 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation" 155 156 #define E100_WATCHDOG_PERIOD (2 * HZ) 157 #define E100_NAPI_WEIGHT 16 158 159 #define FIRMWARE_D101M "e100/d101m_ucode.bin" 160 #define FIRMWARE_D101S "e100/d101s_ucode.bin" 161 #define FIRMWARE_D102E "e100/d102e_ucode.bin" 162 163 MODULE_DESCRIPTION(DRV_DESCRIPTION); 164 MODULE_LICENSE("GPL v2"); 165 MODULE_FIRMWARE(FIRMWARE_D101M); 166 MODULE_FIRMWARE(FIRMWARE_D101S); 167 MODULE_FIRMWARE(FIRMWARE_D102E); 168 169 static int debug = 3; 170 static int eeprom_bad_csum_allow = 0; 171 static int use_io = 0; 172 module_param(debug, int, 0); 173 module_param(eeprom_bad_csum_allow, int, 0444); 174 module_param(use_io, int, 0444); 175 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 176 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums"); 177 MODULE_PARM_DESC(use_io, "Force use of i/o access mode"); 178 179 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) { \ 180 PCI_DEVICE(PCI_VENDOR_ID_INTEL, (device_id)), \ 181 .class = PCI_CLASS_NETWORK_ETHERNET << 8, \ 182 .class_mask = 0xFFFF00, \ 183 .driver_data = (ich) } 184 185 static const struct pci_device_id e100_id_table[] = { 186 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0), 187 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0), 188 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3), 189 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3), 190 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3), 191 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3), 192 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3), 193 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4), 194 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4), 195 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4), 196 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4), 197 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4), 198 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4), 199 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5), 200 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5), 201 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5), 202 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5), 203 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5), 204 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5), 205 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5), 206 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5), 207 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0), 208 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6), 209 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6), 210 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6), 211 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6), 212 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6), 213 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6), 214 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6), 215 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6), 216 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7), 217 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7), 218 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7), 219 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7), 220 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7), 221 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7), 222 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0), 223 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0), 224 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2), 225 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2), 226 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2), 227 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7), 228 { 0, } 229 }; 230 MODULE_DEVICE_TABLE(pci, e100_id_table); 231 232 enum mac { 233 mac_82557_D100_A = 0, 234 mac_82557_D100_B = 1, 235 mac_82557_D100_C = 2, 236 mac_82558_D101_A4 = 4, 237 mac_82558_D101_B0 = 5, 238 mac_82559_D101M = 8, 239 mac_82559_D101S = 9, 240 mac_82550_D102 = 12, 241 mac_82550_D102_C = 13, 242 mac_82551_E = 14, 243 mac_82551_F = 15, 244 mac_82551_10 = 16, 245 mac_unknown = 0xFF, 246 }; 247 248 enum phy { 249 phy_100a = 0x000003E0, 250 phy_100c = 0x035002A8, 251 phy_82555_tx = 0x015002A8, 252 phy_nsc_tx = 0x5C002000, 253 phy_82562_et = 0x033002A8, 254 phy_82562_em = 0x032002A8, 255 phy_82562_ek = 0x031002A8, 256 phy_82562_eh = 0x017002A8, 257 phy_82552_v = 0xd061004d, 258 phy_unknown = 0xFFFFFFFF, 259 }; 260 261 /* CSR (Control/Status Registers) */ 262 struct csr { 263 struct { 264 u8 status; 265 u8 stat_ack; 266 u8 cmd_lo; 267 u8 cmd_hi; 268 u32 gen_ptr; 269 } scb; 270 u32 port; 271 u16 flash_ctrl; 272 u8 eeprom_ctrl_lo; 273 u8 eeprom_ctrl_hi; 274 u32 mdi_ctrl; 275 u32 rx_dma_count; 276 }; 277 278 enum scb_status { 279 rus_no_res = 0x08, 280 rus_ready = 0x10, 281 rus_mask = 0x3C, 282 }; 283 284 enum ru_state { 285 RU_SUSPENDED = 0, 286 RU_RUNNING = 1, 287 RU_UNINITIALIZED = -1, 288 }; 289 290 enum scb_stat_ack { 291 stat_ack_not_ours = 0x00, 292 stat_ack_sw_gen = 0x04, 293 stat_ack_rnr = 0x10, 294 stat_ack_cu_idle = 0x20, 295 stat_ack_frame_rx = 0x40, 296 stat_ack_cu_cmd_done = 0x80, 297 stat_ack_not_present = 0xFF, 298 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), 299 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), 300 }; 301 302 enum scb_cmd_hi { 303 irq_mask_none = 0x00, 304 irq_mask_all = 0x01, 305 irq_sw_gen = 0x02, 306 }; 307 308 enum scb_cmd_lo { 309 cuc_nop = 0x00, 310 ruc_start = 0x01, 311 ruc_load_base = 0x06, 312 cuc_start = 0x10, 313 cuc_resume = 0x20, 314 cuc_dump_addr = 0x40, 315 cuc_dump_stats = 0x50, 316 cuc_load_base = 0x60, 317 cuc_dump_reset = 0x70, 318 }; 319 320 enum cuc_dump { 321 cuc_dump_complete = 0x0000A005, 322 cuc_dump_reset_complete = 0x0000A007, 323 }; 324 325 enum port { 326 software_reset = 0x0000, 327 selftest = 0x0001, 328 selective_reset = 0x0002, 329 }; 330 331 enum eeprom_ctrl_lo { 332 eesk = 0x01, 333 eecs = 0x02, 334 eedi = 0x04, 335 eedo = 0x08, 336 }; 337 338 enum mdi_ctrl { 339 mdi_write = 0x04000000, 340 mdi_read = 0x08000000, 341 mdi_ready = 0x10000000, 342 }; 343 344 enum eeprom_op { 345 op_write = 0x05, 346 op_read = 0x06, 347 op_ewds = 0x10, 348 op_ewen = 0x13, 349 }; 350 351 enum eeprom_offsets { 352 eeprom_cnfg_mdix = 0x03, 353 eeprom_phy_iface = 0x06, 354 eeprom_id = 0x0A, 355 eeprom_config_asf = 0x0D, 356 eeprom_smbus_addr = 0x90, 357 }; 358 359 enum eeprom_cnfg_mdix { 360 eeprom_mdix_enabled = 0x0080, 361 }; 362 363 enum eeprom_phy_iface { 364 NoSuchPhy = 0, 365 I82553AB, 366 I82553C, 367 I82503, 368 DP83840, 369 S80C240, 370 S80C24, 371 I82555, 372 DP83840A = 10, 373 }; 374 375 enum eeprom_id { 376 eeprom_id_wol = 0x0020, 377 }; 378 379 enum eeprom_config_asf { 380 eeprom_asf = 0x8000, 381 eeprom_gcl = 0x4000, 382 }; 383 384 enum cb_status { 385 cb_complete = 0x8000, 386 cb_ok = 0x2000, 387 }; 388 389 /* 390 * cb_command - Command Block flags 391 * @cb_tx_nc: 0: controller does CRC (normal), 1: CRC from skb memory 392 */ 393 enum cb_command { 394 cb_nop = 0x0000, 395 cb_iaaddr = 0x0001, 396 cb_config = 0x0002, 397 cb_multi = 0x0003, 398 cb_tx = 0x0004, 399 cb_ucode = 0x0005, 400 cb_dump = 0x0006, 401 cb_tx_sf = 0x0008, 402 cb_tx_nc = 0x0010, 403 cb_cid = 0x1f00, 404 cb_i = 0x2000, 405 cb_s = 0x4000, 406 cb_el = 0x8000, 407 }; 408 409 struct rfd { 410 __le16 status; 411 __le16 command; 412 __le32 link; 413 __le32 rbd; 414 __le16 actual_size; 415 __le16 size; 416 }; 417 418 struct rx { 419 struct rx *next, *prev; 420 struct sk_buff *skb; 421 dma_addr_t dma_addr; 422 }; 423 424 #if defined(__BIG_ENDIAN_BITFIELD) 425 #define X(a,b) b,a 426 #else 427 #define X(a,b) a,b 428 #endif 429 struct config { 430 /*0*/ u8 X(byte_count:6, pad0:2); 431 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1); 432 /*2*/ u8 adaptive_ifs; 433 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1), 434 term_write_cache_line:1), pad3:4); 435 /*4*/ u8 X(rx_dma_max_count:7, pad4:1); 436 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1); 437 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1), 438 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1), 439 rx_save_overruns : 1), rx_save_bad_frames : 1); 440 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2), 441 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1), 442 tx_dynamic_tbd:1); 443 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1); 444 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1), 445 link_status_wake:1), arp_wake:1), mcmatch_wake:1); 446 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2), 447 loopback:2); 448 /*11*/ u8 X(linear_priority:3, pad11:5); 449 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4); 450 /*13*/ u8 ip_addr_lo; 451 /*14*/ u8 ip_addr_hi; 452 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1), 453 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1), 454 pad15_2:1), crs_or_cdt:1); 455 /*16*/ u8 fc_delay_lo; 456 /*17*/ u8 fc_delay_hi; 457 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1), 458 rx_long_ok:1), fc_priority_threshold:3), pad18:1); 459 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1), 460 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1), 461 full_duplex_force:1), full_duplex_pin:1); 462 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1); 463 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4); 464 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6); 465 u8 pad_d102[9]; 466 }; 467 468 #define E100_MAX_MULTICAST_ADDRS 64 469 struct multi { 470 __le16 count; 471 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/]; 472 }; 473 474 /* Important: keep total struct u32-aligned */ 475 #define UCODE_SIZE 134 476 struct cb { 477 __le16 status; 478 __le16 command; 479 __le32 link; 480 union { 481 u8 iaaddr[ETH_ALEN]; 482 __le32 ucode[UCODE_SIZE]; 483 struct config config; 484 struct multi multi; 485 struct { 486 u32 tbd_array; 487 u16 tcb_byte_count; 488 u8 threshold; 489 u8 tbd_count; 490 struct { 491 __le32 buf_addr; 492 __le16 size; 493 u16 eol; 494 } tbd; 495 } tcb; 496 __le32 dump_buffer_addr; 497 } u; 498 struct cb *next, *prev; 499 dma_addr_t dma_addr; 500 struct sk_buff *skb; 501 }; 502 503 enum loopback { 504 lb_none = 0, lb_mac = 1, lb_phy = 3, 505 }; 506 507 struct stats { 508 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions, 509 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, 510 tx_multiple_collisions, tx_total_collisions; 511 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors, 512 rx_resource_errors, rx_overrun_errors, rx_cdt_errors, 513 rx_short_frame_errors; 514 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; 515 __le16 xmt_tco_frames, rcv_tco_frames; 516 __le32 complete; 517 }; 518 519 struct mem { 520 struct { 521 u32 signature; 522 u32 result; 523 } selftest; 524 struct stats stats; 525 u8 dump_buf[596]; 526 }; 527 528 struct param_range { 529 u32 min; 530 u32 max; 531 u32 count; 532 }; 533 534 struct params { 535 struct param_range rfds; 536 struct param_range cbs; 537 }; 538 539 struct nic { 540 /* Begin: frequently used values: keep adjacent for cache effect */ 541 u32 msg_enable ____cacheline_aligned; 542 struct net_device *netdev; 543 struct pci_dev *pdev; 544 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data); 545 546 struct rx *rxs ____cacheline_aligned; 547 struct rx *rx_to_use; 548 struct rx *rx_to_clean; 549 struct rfd blank_rfd; 550 enum ru_state ru_running; 551 552 spinlock_t cb_lock ____cacheline_aligned; 553 spinlock_t cmd_lock; 554 struct csr __iomem *csr; 555 enum scb_cmd_lo cuc_cmd; 556 unsigned int cbs_avail; 557 struct napi_struct napi; 558 struct cb *cbs; 559 struct cb *cb_to_use; 560 struct cb *cb_to_send; 561 struct cb *cb_to_clean; 562 __le16 tx_command; 563 /* End: frequently used values: keep adjacent for cache effect */ 564 565 enum { 566 ich = (1 << 0), 567 promiscuous = (1 << 1), 568 multicast_all = (1 << 2), 569 wol_magic = (1 << 3), 570 ich_10h_workaround = (1 << 4), 571 } flags ____cacheline_aligned; 572 573 enum mac mac; 574 enum phy phy; 575 struct params params; 576 struct timer_list watchdog; 577 struct mii_if_info mii; 578 struct work_struct tx_timeout_task; 579 enum loopback loopback; 580 581 struct mem *mem; 582 dma_addr_t dma_addr; 583 584 struct dma_pool *cbs_pool; 585 dma_addr_t cbs_dma_addr; 586 u8 adaptive_ifs; 587 u8 tx_threshold; 588 u32 tx_frames; 589 u32 tx_collisions; 590 u32 tx_deferred; 591 u32 tx_single_collisions; 592 u32 tx_multiple_collisions; 593 u32 tx_fc_pause; 594 u32 tx_tco_frames; 595 596 u32 rx_fc_pause; 597 u32 rx_fc_unsupported; 598 u32 rx_tco_frames; 599 u32 rx_short_frame_errors; 600 u32 rx_over_length_errors; 601 602 u16 eeprom_wc; 603 __le16 eeprom[256]; 604 spinlock_t mdio_lock; 605 const struct firmware *fw; 606 }; 607 608 static inline void e100_write_flush(struct nic *nic) 609 { 610 /* Flush previous PCI writes through intermediate bridges 611 * by doing a benign read */ 612 (void)ioread8(&nic->csr->scb.status); 613 } 614 615 static void e100_enable_irq(struct nic *nic) 616 { 617 unsigned long flags; 618 619 spin_lock_irqsave(&nic->cmd_lock, flags); 620 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi); 621 e100_write_flush(nic); 622 spin_unlock_irqrestore(&nic->cmd_lock, flags); 623 } 624 625 static void e100_disable_irq(struct nic *nic) 626 { 627 unsigned long flags; 628 629 spin_lock_irqsave(&nic->cmd_lock, flags); 630 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi); 631 e100_write_flush(nic); 632 spin_unlock_irqrestore(&nic->cmd_lock, flags); 633 } 634 635 static void e100_hw_reset(struct nic *nic) 636 { 637 /* Put CU and RU into idle with a selective reset to get 638 * device off of PCI bus */ 639 iowrite32(selective_reset, &nic->csr->port); 640 e100_write_flush(nic); udelay(20); 641 642 /* Now fully reset device */ 643 iowrite32(software_reset, &nic->csr->port); 644 e100_write_flush(nic); udelay(20); 645 646 /* Mask off our interrupt line - it's unmasked after reset */ 647 e100_disable_irq(nic); 648 } 649 650 static int e100_self_test(struct nic *nic) 651 { 652 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest); 653 654 /* Passing the self-test is a pretty good indication 655 * that the device can DMA to/from host memory */ 656 657 nic->mem->selftest.signature = 0; 658 nic->mem->selftest.result = 0xFFFFFFFF; 659 660 iowrite32(selftest | dma_addr, &nic->csr->port); 661 e100_write_flush(nic); 662 /* Wait 10 msec for self-test to complete */ 663 msleep(10); 664 665 /* Interrupts are enabled after self-test */ 666 e100_disable_irq(nic); 667 668 /* Check results of self-test */ 669 if (nic->mem->selftest.result != 0) { 670 netif_err(nic, hw, nic->netdev, 671 "Self-test failed: result=0x%08X\n", 672 nic->mem->selftest.result); 673 return -ETIMEDOUT; 674 } 675 if (nic->mem->selftest.signature == 0) { 676 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n"); 677 return -ETIMEDOUT; 678 } 679 680 return 0; 681 } 682 683 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data) 684 { 685 u32 cmd_addr_data[3]; 686 u8 ctrl; 687 int i, j; 688 689 /* Three cmds: write/erase enable, write data, write/erase disable */ 690 cmd_addr_data[0] = op_ewen << (addr_len - 2); 691 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) | 692 le16_to_cpu(data); 693 cmd_addr_data[2] = op_ewds << (addr_len - 2); 694 695 /* Bit-bang cmds to write word to eeprom */ 696 for (j = 0; j < 3; j++) { 697 698 /* Chip select */ 699 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo); 700 e100_write_flush(nic); udelay(4); 701 702 for (i = 31; i >= 0; i--) { 703 ctrl = (cmd_addr_data[j] & (1 << i)) ? 704 eecs | eedi : eecs; 705 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo); 706 e100_write_flush(nic); udelay(4); 707 708 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo); 709 e100_write_flush(nic); udelay(4); 710 } 711 /* Wait 10 msec for cmd to complete */ 712 msleep(10); 713 714 /* Chip deselect */ 715 iowrite8(0, &nic->csr->eeprom_ctrl_lo); 716 e100_write_flush(nic); udelay(4); 717 } 718 }; 719 720 /* General technique stolen from the eepro100 driver - very clever */ 721 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr) 722 { 723 u32 cmd_addr_data; 724 u16 data = 0; 725 u8 ctrl; 726 int i; 727 728 cmd_addr_data = ((op_read << *addr_len) | addr) << 16; 729 730 /* Chip select */ 731 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo); 732 e100_write_flush(nic); udelay(4); 733 734 /* Bit-bang to read word from eeprom */ 735 for (i = 31; i >= 0; i--) { 736 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs; 737 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo); 738 e100_write_flush(nic); udelay(4); 739 740 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo); 741 e100_write_flush(nic); udelay(4); 742 743 /* Eeprom drives a dummy zero to EEDO after receiving 744 * complete address. Use this to adjust addr_len. */ 745 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo); 746 if (!(ctrl & eedo) && i > 16) { 747 *addr_len -= (i - 16); 748 i = 17; 749 } 750 751 data = (data << 1) | (ctrl & eedo ? 1 : 0); 752 } 753 754 /* Chip deselect */ 755 iowrite8(0, &nic->csr->eeprom_ctrl_lo); 756 e100_write_flush(nic); udelay(4); 757 758 return cpu_to_le16(data); 759 }; 760 761 /* Load entire EEPROM image into driver cache and validate checksum */ 762 static int e100_eeprom_load(struct nic *nic) 763 { 764 u16 addr, addr_len = 8, checksum = 0; 765 766 /* Try reading with an 8-bit addr len to discover actual addr len */ 767 e100_eeprom_read(nic, &addr_len, 0); 768 nic->eeprom_wc = 1 << addr_len; 769 770 for (addr = 0; addr < nic->eeprom_wc; addr++) { 771 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr); 772 if (addr < nic->eeprom_wc - 1) 773 checksum += le16_to_cpu(nic->eeprom[addr]); 774 } 775 776 /* The checksum, stored in the last word, is calculated such that 777 * the sum of words should be 0xBABA */ 778 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) { 779 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n"); 780 if (!eeprom_bad_csum_allow) 781 return -EAGAIN; 782 } 783 784 return 0; 785 } 786 787 /* Save (portion of) driver EEPROM cache to device and update checksum */ 788 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count) 789 { 790 u16 addr, addr_len = 8, checksum = 0; 791 792 /* Try reading with an 8-bit addr len to discover actual addr len */ 793 e100_eeprom_read(nic, &addr_len, 0); 794 nic->eeprom_wc = 1 << addr_len; 795 796 if (start + count >= nic->eeprom_wc) 797 return -EINVAL; 798 799 for (addr = start; addr < start + count; addr++) 800 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]); 801 802 /* The checksum, stored in the last word, is calculated such that 803 * the sum of words should be 0xBABA */ 804 for (addr = 0; addr < nic->eeprom_wc - 1; addr++) 805 checksum += le16_to_cpu(nic->eeprom[addr]); 806 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum); 807 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1, 808 nic->eeprom[nic->eeprom_wc - 1]); 809 810 return 0; 811 } 812 813 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */ 814 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */ 815 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr) 816 { 817 unsigned long flags; 818 unsigned int i; 819 int err = 0; 820 821 spin_lock_irqsave(&nic->cmd_lock, flags); 822 823 /* Previous command is accepted when SCB clears */ 824 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) { 825 if (likely(!ioread8(&nic->csr->scb.cmd_lo))) 826 break; 827 cpu_relax(); 828 if (unlikely(i > E100_WAIT_SCB_FAST)) 829 udelay(5); 830 } 831 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) { 832 err = -EAGAIN; 833 goto err_unlock; 834 } 835 836 if (unlikely(cmd != cuc_resume)) 837 iowrite32(dma_addr, &nic->csr->scb.gen_ptr); 838 iowrite8(cmd, &nic->csr->scb.cmd_lo); 839 840 err_unlock: 841 spin_unlock_irqrestore(&nic->cmd_lock, flags); 842 843 return err; 844 } 845 846 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb, 847 int (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *)) 848 { 849 struct cb *cb; 850 unsigned long flags; 851 int err; 852 853 spin_lock_irqsave(&nic->cb_lock, flags); 854 855 if (unlikely(!nic->cbs_avail)) { 856 err = -ENOMEM; 857 goto err_unlock; 858 } 859 860 cb = nic->cb_to_use; 861 nic->cb_to_use = cb->next; 862 nic->cbs_avail--; 863 cb->skb = skb; 864 865 err = cb_prepare(nic, cb, skb); 866 if (err) 867 goto err_unlock; 868 869 if (unlikely(!nic->cbs_avail)) 870 err = -ENOSPC; 871 872 873 /* Order is important otherwise we'll be in a race with h/w: 874 * set S-bit in current first, then clear S-bit in previous. */ 875 cb->command |= cpu_to_le16(cb_s); 876 dma_wmb(); 877 cb->prev->command &= cpu_to_le16(~cb_s); 878 879 while (nic->cb_to_send != nic->cb_to_use) { 880 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd, 881 nic->cb_to_send->dma_addr))) { 882 /* Ok, here's where things get sticky. It's 883 * possible that we can't schedule the command 884 * because the controller is too busy, so 885 * let's just queue the command and try again 886 * when another command is scheduled. */ 887 if (err == -ENOSPC) { 888 //request a reset 889 schedule_work(&nic->tx_timeout_task); 890 } 891 break; 892 } else { 893 nic->cuc_cmd = cuc_resume; 894 nic->cb_to_send = nic->cb_to_send->next; 895 } 896 } 897 898 err_unlock: 899 spin_unlock_irqrestore(&nic->cb_lock, flags); 900 901 return err; 902 } 903 904 static int mdio_read(struct net_device *netdev, int addr, int reg) 905 { 906 struct nic *nic = netdev_priv(netdev); 907 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0); 908 } 909 910 static void mdio_write(struct net_device *netdev, int addr, int reg, int data) 911 { 912 struct nic *nic = netdev_priv(netdev); 913 914 nic->mdio_ctrl(nic, addr, mdi_write, reg, data); 915 } 916 917 /* the standard mdio_ctrl() function for usual MII-compliant hardware */ 918 static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data) 919 { 920 u32 data_out = 0; 921 unsigned int i; 922 unsigned long flags; 923 924 925 /* 926 * Stratus87247: we shouldn't be writing the MDI control 927 * register until the Ready bit shows True. Also, since 928 * manipulation of the MDI control registers is a multi-step 929 * procedure it should be done under lock. 930 */ 931 spin_lock_irqsave(&nic->mdio_lock, flags); 932 for (i = 100; i; --i) { 933 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready) 934 break; 935 udelay(20); 936 } 937 if (unlikely(!i)) { 938 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n"); 939 spin_unlock_irqrestore(&nic->mdio_lock, flags); 940 return 0; /* No way to indicate timeout error */ 941 } 942 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl); 943 944 for (i = 0; i < 100; i++) { 945 udelay(20); 946 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready) 947 break; 948 } 949 spin_unlock_irqrestore(&nic->mdio_lock, flags); 950 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 951 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n", 952 dir == mdi_read ? "READ" : "WRITE", 953 addr, reg, data, data_out); 954 return (u16)data_out; 955 } 956 957 /* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */ 958 static u16 mdio_ctrl_phy_82552_v(struct nic *nic, 959 u32 addr, 960 u32 dir, 961 u32 reg, 962 u16 data) 963 { 964 if ((reg == MII_BMCR) && (dir == mdi_write)) { 965 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) { 966 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id, 967 MII_ADVERTISE); 968 969 /* 970 * Workaround Si issue where sometimes the part will not 971 * autoneg to 100Mbps even when advertised. 972 */ 973 if (advert & ADVERTISE_100FULL) 974 data |= BMCR_SPEED100 | BMCR_FULLDPLX; 975 else if (advert & ADVERTISE_100HALF) 976 data |= BMCR_SPEED100; 977 } 978 } 979 return mdio_ctrl_hw(nic, addr, dir, reg, data); 980 } 981 982 /* Fully software-emulated mdio_ctrl() function for cards without 983 * MII-compliant PHYs. 984 * For now, this is mainly geared towards 80c24 support; in case of further 985 * requirements for other types (i82503, ...?) either extend this mechanism 986 * or split it, whichever is cleaner. 987 */ 988 static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic, 989 u32 addr, 990 u32 dir, 991 u32 reg, 992 u16 data) 993 { 994 /* might need to allocate a netdev_priv'ed register array eventually 995 * to be able to record state changes, but for now 996 * some fully hardcoded register handling ought to be ok I guess. */ 997 998 if (dir == mdi_read) { 999 switch (reg) { 1000 case MII_BMCR: 1001 /* Auto-negotiation, right? */ 1002 return BMCR_ANENABLE | 1003 BMCR_FULLDPLX; 1004 case MII_BMSR: 1005 return BMSR_LSTATUS /* for mii_link_ok() */ | 1006 BMSR_ANEGCAPABLE | 1007 BMSR_10FULL; 1008 case MII_ADVERTISE: 1009 /* 80c24 is a "combo card" PHY, right? */ 1010 return ADVERTISE_10HALF | 1011 ADVERTISE_10FULL; 1012 default: 1013 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1014 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n", 1015 dir == mdi_read ? "READ" : "WRITE", 1016 addr, reg, data); 1017 return 0xFFFF; 1018 } 1019 } else { 1020 switch (reg) { 1021 default: 1022 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1023 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n", 1024 dir == mdi_read ? "READ" : "WRITE", 1025 addr, reg, data); 1026 return 0xFFFF; 1027 } 1028 } 1029 } 1030 static inline int e100_phy_supports_mii(struct nic *nic) 1031 { 1032 /* for now, just check it by comparing whether we 1033 are using MII software emulation. 1034 */ 1035 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated); 1036 } 1037 1038 static void e100_get_defaults(struct nic *nic) 1039 { 1040 struct param_range rfds = { .min = 16, .max = 256, .count = 256 }; 1041 struct param_range cbs = { .min = 64, .max = 256, .count = 128 }; 1042 1043 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */ 1044 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision; 1045 if (nic->mac == mac_unknown) 1046 nic->mac = mac_82557_D100_A; 1047 1048 nic->params.rfds = rfds; 1049 nic->params.cbs = cbs; 1050 1051 /* Quadwords to DMA into FIFO before starting frame transmit */ 1052 nic->tx_threshold = 0xE0; 1053 1054 /* no interrupt for every tx completion, delay = 256us if not 557 */ 1055 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf | 1056 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i)); 1057 1058 /* Template for a freshly allocated RFD */ 1059 nic->blank_rfd.command = 0; 1060 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF); 1061 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1062 1063 /* MII setup */ 1064 nic->mii.phy_id_mask = 0x1F; 1065 nic->mii.reg_num_mask = 0x1F; 1066 nic->mii.dev = nic->netdev; 1067 nic->mii.mdio_read = mdio_read; 1068 nic->mii.mdio_write = mdio_write; 1069 } 1070 1071 static int e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb) 1072 { 1073 struct config *config = &cb->u.config; 1074 u8 *c = (u8 *)config; 1075 struct net_device *netdev = nic->netdev; 1076 1077 cb->command = cpu_to_le16(cb_config); 1078 1079 memset(config, 0, sizeof(struct config)); 1080 1081 config->byte_count = 0x16; /* bytes in this struct */ 1082 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */ 1083 config->direct_rx_dma = 0x1; /* reserved */ 1084 config->standard_tcb = 0x1; /* 1=standard, 0=extended */ 1085 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */ 1086 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */ 1087 config->tx_underrun_retry = 0x3; /* # of underrun retries */ 1088 if (e100_phy_supports_mii(nic)) 1089 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */ 1090 config->pad10 = 0x6; 1091 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */ 1092 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */ 1093 config->ifs = 0x6; /* x16 = inter frame spacing */ 1094 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */ 1095 config->pad15_1 = 0x1; 1096 config->pad15_2 = 0x1; 1097 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */ 1098 config->fc_delay_hi = 0x40; /* time delay for fc frame */ 1099 config->tx_padding = 0x1; /* 1=pad short frames */ 1100 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */ 1101 config->pad18 = 0x1; 1102 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */ 1103 config->pad20_1 = 0x1F; 1104 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */ 1105 config->pad21_1 = 0x5; 1106 1107 config->adaptive_ifs = nic->adaptive_ifs; 1108 config->loopback = nic->loopback; 1109 1110 if (nic->mii.force_media && nic->mii.full_duplex) 1111 config->full_duplex_force = 0x1; /* 1=force, 0=auto */ 1112 1113 if (nic->flags & promiscuous || nic->loopback) { 1114 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */ 1115 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */ 1116 config->promiscuous_mode = 0x1; /* 1=on, 0=off */ 1117 } 1118 1119 if (unlikely(netdev->features & NETIF_F_RXFCS)) 1120 config->rx_crc_transfer = 0x1; /* 1=save, 0=discard */ 1121 1122 if (nic->flags & multicast_all) 1123 config->multicast_all = 0x1; /* 1=accept, 0=no */ 1124 1125 /* disable WoL when up */ 1126 if (netif_running(nic->netdev) || !(nic->flags & wol_magic)) 1127 config->magic_packet_disable = 0x1; /* 1=off, 0=on */ 1128 1129 if (nic->mac >= mac_82558_D101_A4) { 1130 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */ 1131 config->mwi_enable = 0x1; /* 1=enable, 0=disable */ 1132 config->standard_tcb = 0x0; /* 1=standard, 0=extended */ 1133 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */ 1134 if (nic->mac >= mac_82559_D101M) { 1135 config->tno_intr = 0x1; /* TCO stats enable */ 1136 /* Enable TCO in extended config */ 1137 if (nic->mac >= mac_82551_10) { 1138 config->byte_count = 0x20; /* extended bytes */ 1139 config->rx_d102_mode = 0x1; /* GMRC for TCO */ 1140 } 1141 } else { 1142 config->standard_stat_counter = 0x0; 1143 } 1144 } 1145 1146 if (netdev->features & NETIF_F_RXALL) { 1147 config->rx_save_overruns = 0x1; /* 1=save, 0=discard */ 1148 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */ 1149 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */ 1150 } 1151 1152 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[00-07]=%8ph\n", 1153 c + 0); 1154 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[08-15]=%8ph\n", 1155 c + 8); 1156 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[16-23]=%8ph\n", 1157 c + 16); 1158 return 0; 1159 } 1160 1161 /************************************************************************* 1162 * CPUSaver parameters 1163 * 1164 * All CPUSaver parameters are 16-bit literals that are part of a 1165 * "move immediate value" instruction. By changing the value of 1166 * the literal in the instruction before the code is loaded, the 1167 * driver can change the algorithm. 1168 * 1169 * INTDELAY - This loads the dead-man timer with its initial value. 1170 * When this timer expires the interrupt is asserted, and the 1171 * timer is reset each time a new packet is received. (see 1172 * BUNDLEMAX below to set the limit on number of chained packets) 1173 * The current default is 0x600 or 1536. Experiments show that 1174 * the value should probably stay within the 0x200 - 0x1000. 1175 * 1176 * BUNDLEMAX - 1177 * This sets the maximum number of frames that will be bundled. In 1178 * some situations, such as the TCP windowing algorithm, it may be 1179 * better to limit the growth of the bundle size than let it go as 1180 * high as it can, because that could cause too much added latency. 1181 * The default is six, because this is the number of packets in the 1182 * default TCP window size. A value of 1 would make CPUSaver indicate 1183 * an interrupt for every frame received. If you do not want to put 1184 * a limit on the bundle size, set this value to xFFFF. 1185 * 1186 * BUNDLESMALL - 1187 * This contains a bit-mask describing the minimum size frame that 1188 * will be bundled. The default masks the lower 7 bits, which means 1189 * that any frame less than 128 bytes in length will not be bundled, 1190 * but will instead immediately generate an interrupt. This does 1191 * not affect the current bundle in any way. Any frame that is 128 1192 * bytes or large will be bundled normally. This feature is meant 1193 * to provide immediate indication of ACK frames in a TCP environment. 1194 * Customers were seeing poor performance when a machine with CPUSaver 1195 * enabled was sending but not receiving. The delay introduced when 1196 * the ACKs were received was enough to reduce total throughput, because 1197 * the sender would sit idle until the ACK was finally seen. 1198 * 1199 * The current default is 0xFF80, which masks out the lower 7 bits. 1200 * This means that any frame which is x7F (127) bytes or smaller 1201 * will cause an immediate interrupt. Because this value must be a 1202 * bit mask, there are only a few valid values that can be used. To 1203 * turn this feature off, the driver can write the value xFFFF to the 1204 * lower word of this instruction (in the same way that the other 1205 * parameters are used). Likewise, a value of 0xF800 (2047) would 1206 * cause an interrupt to be generated for every frame, because all 1207 * standard Ethernet frames are <= 2047 bytes in length. 1208 *************************************************************************/ 1209 1210 /* if you wish to disable the ucode functionality, while maintaining the 1211 * workarounds it provides, set the following defines to: 1212 * BUNDLESMALL 0 1213 * BUNDLEMAX 1 1214 * INTDELAY 1 1215 */ 1216 #define BUNDLESMALL 1 1217 #define BUNDLEMAX (u16)6 1218 #define INTDELAY (u16)1536 /* 0x600 */ 1219 1220 /* Initialize firmware */ 1221 static const struct firmware *e100_request_firmware(struct nic *nic) 1222 { 1223 const char *fw_name; 1224 const struct firmware *fw = nic->fw; 1225 u8 timer, bundle, min_size; 1226 int err = 0; 1227 bool required = false; 1228 1229 /* do not load u-code for ICH devices */ 1230 if (nic->flags & ich) 1231 return NULL; 1232 1233 /* Search for ucode match against h/w revision 1234 * 1235 * Based on comments in the source code for the FreeBSD fxp 1236 * driver, the FIRMWARE_D102E ucode includes both CPUSaver and 1237 * 1238 * "fixes for bugs in the B-step hardware (specifically, bugs 1239 * with Inline Receive)." 1240 * 1241 * So we must fail if it cannot be loaded. 1242 * 1243 * The other microcode files are only required for the optional 1244 * CPUSaver feature. Nice to have, but no reason to fail. 1245 */ 1246 if (nic->mac == mac_82559_D101M) { 1247 fw_name = FIRMWARE_D101M; 1248 } else if (nic->mac == mac_82559_D101S) { 1249 fw_name = FIRMWARE_D101S; 1250 } else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10) { 1251 fw_name = FIRMWARE_D102E; 1252 required = true; 1253 } else { /* No ucode on other devices */ 1254 return NULL; 1255 } 1256 1257 /* If the firmware has not previously been loaded, request a pointer 1258 * to it. If it was previously loaded, we are reinitializing the 1259 * adapter, possibly in a resume from hibernate, in which case 1260 * request_firmware() cannot be used. 1261 */ 1262 if (!fw) 1263 err = request_firmware(&fw, fw_name, &nic->pdev->dev); 1264 1265 if (err) { 1266 if (required) { 1267 netif_err(nic, probe, nic->netdev, 1268 "Failed to load firmware \"%s\": %d\n", 1269 fw_name, err); 1270 return ERR_PTR(err); 1271 } else { 1272 netif_info(nic, probe, nic->netdev, 1273 "CPUSaver disabled. Needs \"%s\": %d\n", 1274 fw_name, err); 1275 return NULL; 1276 } 1277 } 1278 1279 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes 1280 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */ 1281 if (fw->size != UCODE_SIZE * 4 + 3) { 1282 netif_err(nic, probe, nic->netdev, 1283 "Firmware \"%s\" has wrong size %zu\n", 1284 fw_name, fw->size); 1285 release_firmware(fw); 1286 return ERR_PTR(-EINVAL); 1287 } 1288 1289 /* Read timer, bundle and min_size from end of firmware blob */ 1290 timer = fw->data[UCODE_SIZE * 4]; 1291 bundle = fw->data[UCODE_SIZE * 4 + 1]; 1292 min_size = fw->data[UCODE_SIZE * 4 + 2]; 1293 1294 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE || 1295 min_size >= UCODE_SIZE) { 1296 netif_err(nic, probe, nic->netdev, 1297 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n", 1298 fw_name, timer, bundle, min_size); 1299 release_firmware(fw); 1300 return ERR_PTR(-EINVAL); 1301 } 1302 1303 /* OK, firmware is validated and ready to use. Save a pointer 1304 * to it in the nic */ 1305 nic->fw = fw; 1306 return fw; 1307 } 1308 1309 static int e100_setup_ucode(struct nic *nic, struct cb *cb, 1310 struct sk_buff *skb) 1311 { 1312 const struct firmware *fw = (void *)skb; 1313 u8 timer, bundle, min_size; 1314 1315 /* It's not a real skb; we just abused the fact that e100_exec_cb 1316 will pass it through to here... */ 1317 cb->skb = NULL; 1318 1319 /* firmware is stored as little endian already */ 1320 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4); 1321 1322 /* Read timer, bundle and min_size from end of firmware blob */ 1323 timer = fw->data[UCODE_SIZE * 4]; 1324 bundle = fw->data[UCODE_SIZE * 4 + 1]; 1325 min_size = fw->data[UCODE_SIZE * 4 + 2]; 1326 1327 /* Insert user-tunable settings in cb->u.ucode */ 1328 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000); 1329 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY); 1330 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000); 1331 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX); 1332 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000); 1333 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80); 1334 1335 cb->command = cpu_to_le16(cb_ucode | cb_el); 1336 return 0; 1337 } 1338 1339 static inline int e100_load_ucode_wait(struct nic *nic) 1340 { 1341 const struct firmware *fw; 1342 int err = 0, counter = 50; 1343 struct cb *cb = nic->cb_to_clean; 1344 1345 fw = e100_request_firmware(nic); 1346 /* If it's NULL, then no ucode is required */ 1347 if (IS_ERR_OR_NULL(fw)) 1348 return PTR_ERR_OR_ZERO(fw); 1349 1350 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode))) 1351 netif_err(nic, probe, nic->netdev, 1352 "ucode cmd failed with error %d\n", err); 1353 1354 /* must restart cuc */ 1355 nic->cuc_cmd = cuc_start; 1356 1357 /* wait for completion */ 1358 e100_write_flush(nic); 1359 udelay(10); 1360 1361 /* wait for possibly (ouch) 500ms */ 1362 while (!(cb->status & cpu_to_le16(cb_complete))) { 1363 msleep(10); 1364 if (!--counter) break; 1365 } 1366 1367 /* ack any interrupts, something could have been set */ 1368 iowrite8(~0, &nic->csr->scb.stat_ack); 1369 1370 /* if the command failed, or is not OK, notify and return */ 1371 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) { 1372 netif_err(nic, probe, nic->netdev, "ucode load failed\n"); 1373 err = -EPERM; 1374 } 1375 1376 return err; 1377 } 1378 1379 static int e100_setup_iaaddr(struct nic *nic, struct cb *cb, 1380 struct sk_buff *skb) 1381 { 1382 cb->command = cpu_to_le16(cb_iaaddr); 1383 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN); 1384 return 0; 1385 } 1386 1387 static int e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb) 1388 { 1389 cb->command = cpu_to_le16(cb_dump); 1390 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr + 1391 offsetof(struct mem, dump_buf)); 1392 return 0; 1393 } 1394 1395 static int e100_phy_check_without_mii(struct nic *nic) 1396 { 1397 u8 phy_type; 1398 int without_mii; 1399 1400 phy_type = (le16_to_cpu(nic->eeprom[eeprom_phy_iface]) >> 8) & 0x0f; 1401 1402 switch (phy_type) { 1403 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */ 1404 case I82503: /* Non-MII PHY; UNTESTED! */ 1405 case S80C24: /* Non-MII PHY; tested and working */ 1406 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24": 1407 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 1408 * doesn't have a programming interface of any sort. The 1409 * media is sensed automatically based on how the link partner 1410 * is configured. This is, in essence, manual configuration. 1411 */ 1412 netif_info(nic, probe, nic->netdev, 1413 "found MII-less i82503 or 80c24 or other PHY\n"); 1414 1415 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated; 1416 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */ 1417 1418 /* these might be needed for certain MII-less cards... 1419 * nic->flags |= ich; 1420 * nic->flags |= ich_10h_workaround; */ 1421 1422 without_mii = 1; 1423 break; 1424 default: 1425 without_mii = 0; 1426 break; 1427 } 1428 return without_mii; 1429 } 1430 1431 #define NCONFIG_AUTO_SWITCH 0x0080 1432 #define MII_NSC_CONG MII_RESV1 1433 #define NSC_CONG_ENABLE 0x0100 1434 #define NSC_CONG_TXREADY 0x0400 1435 static int e100_phy_init(struct nic *nic) 1436 { 1437 struct net_device *netdev = nic->netdev; 1438 u32 addr; 1439 u16 bmcr, stat, id_lo, id_hi, cong; 1440 1441 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */ 1442 for (addr = 0; addr < 32; addr++) { 1443 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr; 1444 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR); 1445 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR); 1446 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR); 1447 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0)))) 1448 break; 1449 } 1450 if (addr == 32) { 1451 /* uhoh, no PHY detected: check whether we seem to be some 1452 * weird, rare variant which is *known* to not have any MII. 1453 * But do this AFTER MII checking only, since this does 1454 * lookup of EEPROM values which may easily be unreliable. */ 1455 if (e100_phy_check_without_mii(nic)) 1456 return 0; /* simply return and hope for the best */ 1457 else { 1458 /* for unknown cases log a fatal error */ 1459 netif_err(nic, hw, nic->netdev, 1460 "Failed to locate any known PHY, aborting\n"); 1461 return -EAGAIN; 1462 } 1463 } else 1464 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1465 "phy_addr = %d\n", nic->mii.phy_id); 1466 1467 /* Get phy ID */ 1468 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1); 1469 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2); 1470 nic->phy = (u32)id_hi << 16 | (u32)id_lo; 1471 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1472 "phy ID = 0x%08X\n", nic->phy); 1473 1474 /* Select the phy and isolate the rest */ 1475 for (addr = 0; addr < 32; addr++) { 1476 if (addr != nic->mii.phy_id) { 1477 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE); 1478 } else if (nic->phy != phy_82552_v) { 1479 bmcr = mdio_read(netdev, addr, MII_BMCR); 1480 mdio_write(netdev, addr, MII_BMCR, 1481 bmcr & ~BMCR_ISOLATE); 1482 } 1483 } 1484 /* 1485 * Workaround for 82552: 1486 * Clear the ISOLATE bit on selected phy_id last (mirrored on all 1487 * other phy_id's) using bmcr value from addr discovery loop above. 1488 */ 1489 if (nic->phy == phy_82552_v) 1490 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, 1491 bmcr & ~BMCR_ISOLATE); 1492 1493 /* Handle National tx phys */ 1494 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF 1495 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) { 1496 /* Disable congestion control */ 1497 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG); 1498 cong |= NSC_CONG_TXREADY; 1499 cong &= ~NSC_CONG_ENABLE; 1500 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong); 1501 } 1502 1503 if (nic->phy == phy_82552_v) { 1504 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE); 1505 1506 /* assign special tweaked mdio_ctrl() function */ 1507 nic->mdio_ctrl = mdio_ctrl_phy_82552_v; 1508 1509 /* Workaround Si not advertising flow-control during autoneg */ 1510 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1511 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert); 1512 1513 /* Reset for the above changes to take effect */ 1514 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR); 1515 bmcr |= BMCR_RESET; 1516 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr); 1517 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) && 1518 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) && 1519 (le16_to_cpu(nic->eeprom[eeprom_cnfg_mdix]) & eeprom_mdix_enabled))) { 1520 /* enable/disable MDI/MDI-X auto-switching. */ 1521 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, 1522 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH); 1523 } 1524 1525 return 0; 1526 } 1527 1528 static int e100_hw_init(struct nic *nic) 1529 { 1530 int err = 0; 1531 1532 e100_hw_reset(nic); 1533 1534 netif_err(nic, hw, nic->netdev, "e100_hw_init\n"); 1535 if ((err = e100_self_test(nic))) 1536 return err; 1537 1538 if ((err = e100_phy_init(nic))) 1539 return err; 1540 if ((err = e100_exec_cmd(nic, cuc_load_base, 0))) 1541 return err; 1542 if ((err = e100_exec_cmd(nic, ruc_load_base, 0))) 1543 return err; 1544 if ((err = e100_load_ucode_wait(nic))) 1545 return err; 1546 if ((err = e100_exec_cb(nic, NULL, e100_configure))) 1547 return err; 1548 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr))) 1549 return err; 1550 if ((err = e100_exec_cmd(nic, cuc_dump_addr, 1551 nic->dma_addr + offsetof(struct mem, stats)))) 1552 return err; 1553 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0))) 1554 return err; 1555 1556 e100_disable_irq(nic); 1557 1558 return 0; 1559 } 1560 1561 static int e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb) 1562 { 1563 struct net_device *netdev = nic->netdev; 1564 struct netdev_hw_addr *ha; 1565 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS); 1566 1567 cb->command = cpu_to_le16(cb_multi); 1568 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN); 1569 i = 0; 1570 netdev_for_each_mc_addr(ha, netdev) { 1571 if (i == count) 1572 break; 1573 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr, 1574 ETH_ALEN); 1575 } 1576 return 0; 1577 } 1578 1579 static void e100_set_multicast_list(struct net_device *netdev) 1580 { 1581 struct nic *nic = netdev_priv(netdev); 1582 1583 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, 1584 "mc_count=%d, flags=0x%04X\n", 1585 netdev_mc_count(netdev), netdev->flags); 1586 1587 if (netdev->flags & IFF_PROMISC) 1588 nic->flags |= promiscuous; 1589 else 1590 nic->flags &= ~promiscuous; 1591 1592 if (netdev->flags & IFF_ALLMULTI || 1593 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS) 1594 nic->flags |= multicast_all; 1595 else 1596 nic->flags &= ~multicast_all; 1597 1598 e100_exec_cb(nic, NULL, e100_configure); 1599 e100_exec_cb(nic, NULL, e100_multi); 1600 } 1601 1602 static void e100_update_stats(struct nic *nic) 1603 { 1604 struct net_device *dev = nic->netdev; 1605 struct net_device_stats *ns = &dev->stats; 1606 struct stats *s = &nic->mem->stats; 1607 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause : 1608 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames : 1609 &s->complete; 1610 1611 /* Device's stats reporting may take several microseconds to 1612 * complete, so we're always waiting for results of the 1613 * previous command. */ 1614 1615 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) { 1616 *complete = 0; 1617 nic->tx_frames = le32_to_cpu(s->tx_good_frames); 1618 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions); 1619 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions); 1620 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions); 1621 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs); 1622 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns); 1623 ns->collisions += nic->tx_collisions; 1624 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) + 1625 le32_to_cpu(s->tx_lost_crs); 1626 nic->rx_short_frame_errors += 1627 le32_to_cpu(s->rx_short_frame_errors); 1628 ns->rx_length_errors = nic->rx_short_frame_errors + 1629 nic->rx_over_length_errors; 1630 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors); 1631 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors); 1632 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors); 1633 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors); 1634 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors); 1635 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) + 1636 le32_to_cpu(s->rx_alignment_errors) + 1637 le32_to_cpu(s->rx_short_frame_errors) + 1638 le32_to_cpu(s->rx_cdt_errors); 1639 nic->tx_deferred += le32_to_cpu(s->tx_deferred); 1640 nic->tx_single_collisions += 1641 le32_to_cpu(s->tx_single_collisions); 1642 nic->tx_multiple_collisions += 1643 le32_to_cpu(s->tx_multiple_collisions); 1644 if (nic->mac >= mac_82558_D101_A4) { 1645 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause); 1646 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause); 1647 nic->rx_fc_unsupported += 1648 le32_to_cpu(s->fc_rcv_unsupported); 1649 if (nic->mac >= mac_82559_D101M) { 1650 nic->tx_tco_frames += 1651 le16_to_cpu(s->xmt_tco_frames); 1652 nic->rx_tco_frames += 1653 le16_to_cpu(s->rcv_tco_frames); 1654 } 1655 } 1656 } 1657 1658 1659 if (e100_exec_cmd(nic, cuc_dump_reset, 0)) 1660 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 1661 "exec cuc_dump_reset failed\n"); 1662 } 1663 1664 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex) 1665 { 1666 /* Adjust inter-frame-spacing (IFS) between two transmits if 1667 * we're getting collisions on a half-duplex connection. */ 1668 1669 if (duplex == DUPLEX_HALF) { 1670 u32 prev = nic->adaptive_ifs; 1671 u32 min_frames = (speed == SPEED_100) ? 1000 : 100; 1672 1673 if ((nic->tx_frames / 32 < nic->tx_collisions) && 1674 (nic->tx_frames > min_frames)) { 1675 if (nic->adaptive_ifs < 60) 1676 nic->adaptive_ifs += 5; 1677 } else if (nic->tx_frames < min_frames) { 1678 if (nic->adaptive_ifs >= 5) 1679 nic->adaptive_ifs -= 5; 1680 } 1681 if (nic->adaptive_ifs != prev) 1682 e100_exec_cb(nic, NULL, e100_configure); 1683 } 1684 } 1685 1686 static void e100_watchdog(struct timer_list *t) 1687 { 1688 struct nic *nic = timer_container_of(nic, t, watchdog); 1689 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; 1690 u32 speed; 1691 1692 netif_printk(nic, timer, KERN_DEBUG, nic->netdev, 1693 "right now = %ld\n", jiffies); 1694 1695 /* mii library handles link maintenance tasks */ 1696 1697 mii_ethtool_gset(&nic->mii, &cmd); 1698 speed = ethtool_cmd_speed(&cmd); 1699 1700 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) { 1701 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n", 1702 speed == SPEED_100 ? 100 : 10, 1703 cmd.duplex == DUPLEX_FULL ? "Full" : "Half"); 1704 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) { 1705 netdev_info(nic->netdev, "NIC Link is Down\n"); 1706 } 1707 1708 mii_check_link(&nic->mii); 1709 1710 /* Software generated interrupt to recover from (rare) Rx 1711 * allocation failure. 1712 * Unfortunately have to use a spinlock to not re-enable interrupts 1713 * accidentally, due to hardware that shares a register between the 1714 * interrupt mask bit and the SW Interrupt generation bit */ 1715 spin_lock_irq(&nic->cmd_lock); 1716 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi); 1717 e100_write_flush(nic); 1718 spin_unlock_irq(&nic->cmd_lock); 1719 1720 e100_update_stats(nic); 1721 e100_adjust_adaptive_ifs(nic, speed, cmd.duplex); 1722 1723 if (nic->mac <= mac_82557_D100_C) 1724 /* Issue a multicast command to workaround a 557 lock up */ 1725 e100_set_multicast_list(nic->netdev); 1726 1727 if (nic->flags & ich && speed == SPEED_10 && cmd.duplex == DUPLEX_HALF) 1728 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */ 1729 nic->flags |= ich_10h_workaround; 1730 else 1731 nic->flags &= ~ich_10h_workaround; 1732 1733 mod_timer(&nic->watchdog, 1734 round_jiffies(jiffies + E100_WATCHDOG_PERIOD)); 1735 } 1736 1737 static int e100_xmit_prepare(struct nic *nic, struct cb *cb, 1738 struct sk_buff *skb) 1739 { 1740 dma_addr_t dma_addr; 1741 cb->command = nic->tx_command; 1742 1743 dma_addr = dma_map_single(&nic->pdev->dev, skb->data, skb->len, 1744 DMA_TO_DEVICE); 1745 /* If we can't map the skb, have the upper layer try later */ 1746 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) 1747 return -ENOMEM; 1748 1749 /* 1750 * Use the last 4 bytes of the SKB payload packet as the CRC, used for 1751 * testing, ie sending frames with bad CRC. 1752 */ 1753 if (unlikely(skb->no_fcs)) 1754 cb->command |= cpu_to_le16(cb_tx_nc); 1755 else 1756 cb->command &= ~cpu_to_le16(cb_tx_nc); 1757 1758 /* interrupt every 16 packets regardless of delay */ 1759 if ((nic->cbs_avail & ~15) == nic->cbs_avail) 1760 cb->command |= cpu_to_le16(cb_i); 1761 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd); 1762 cb->u.tcb.tcb_byte_count = 0; 1763 cb->u.tcb.threshold = nic->tx_threshold; 1764 cb->u.tcb.tbd_count = 1; 1765 cb->u.tcb.tbd.buf_addr = cpu_to_le32(dma_addr); 1766 cb->u.tcb.tbd.size = cpu_to_le16(skb->len); 1767 skb_tx_timestamp(skb); 1768 return 0; 1769 } 1770 1771 static netdev_tx_t e100_xmit_frame(struct sk_buff *skb, 1772 struct net_device *netdev) 1773 { 1774 struct nic *nic = netdev_priv(netdev); 1775 int err; 1776 1777 if (nic->flags & ich_10h_workaround) { 1778 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang. 1779 Issue a NOP command followed by a 1us delay before 1780 issuing the Tx command. */ 1781 if (e100_exec_cmd(nic, cuc_nop, 0)) 1782 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 1783 "exec cuc_nop failed\n"); 1784 udelay(1); 1785 } 1786 1787 err = e100_exec_cb(nic, skb, e100_xmit_prepare); 1788 1789 switch (err) { 1790 case -ENOSPC: 1791 /* We queued the skb, but now we're out of space. */ 1792 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 1793 "No space for CB\n"); 1794 netif_stop_queue(netdev); 1795 break; 1796 case -ENOMEM: 1797 /* This is a hard error - log it. */ 1798 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 1799 "Out of Tx resources, returning skb\n"); 1800 netif_stop_queue(netdev); 1801 return NETDEV_TX_BUSY; 1802 } 1803 1804 return NETDEV_TX_OK; 1805 } 1806 1807 static int e100_tx_clean(struct nic *nic) 1808 { 1809 struct net_device *dev = nic->netdev; 1810 struct cb *cb; 1811 int tx_cleaned = 0; 1812 1813 spin_lock(&nic->cb_lock); 1814 1815 /* Clean CBs marked complete */ 1816 for (cb = nic->cb_to_clean; 1817 cb->status & cpu_to_le16(cb_complete); 1818 cb = nic->cb_to_clean = cb->next) { 1819 dma_rmb(); /* read skb after status */ 1820 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev, 1821 "cb[%d]->status = 0x%04X\n", 1822 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)), 1823 cb->status); 1824 1825 if (likely(cb->skb != NULL)) { 1826 dev->stats.tx_packets++; 1827 dev->stats.tx_bytes += cb->skb->len; 1828 1829 dma_unmap_single(&nic->pdev->dev, 1830 le32_to_cpu(cb->u.tcb.tbd.buf_addr), 1831 le16_to_cpu(cb->u.tcb.tbd.size), 1832 DMA_TO_DEVICE); 1833 dev_kfree_skb_any(cb->skb); 1834 cb->skb = NULL; 1835 tx_cleaned = 1; 1836 } 1837 cb->status = 0; 1838 nic->cbs_avail++; 1839 } 1840 1841 spin_unlock(&nic->cb_lock); 1842 1843 /* Recover from running out of Tx resources in xmit_frame */ 1844 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev))) 1845 netif_wake_queue(nic->netdev); 1846 1847 return tx_cleaned; 1848 } 1849 1850 static void e100_clean_cbs(struct nic *nic) 1851 { 1852 if (nic->cbs) { 1853 while (nic->cbs_avail != nic->params.cbs.count) { 1854 struct cb *cb = nic->cb_to_clean; 1855 if (cb->skb) { 1856 dma_unmap_single(&nic->pdev->dev, 1857 le32_to_cpu(cb->u.tcb.tbd.buf_addr), 1858 le16_to_cpu(cb->u.tcb.tbd.size), 1859 DMA_TO_DEVICE); 1860 dev_kfree_skb(cb->skb); 1861 } 1862 nic->cb_to_clean = nic->cb_to_clean->next; 1863 nic->cbs_avail++; 1864 } 1865 dma_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr); 1866 nic->cbs = NULL; 1867 nic->cbs_avail = 0; 1868 } 1869 nic->cuc_cmd = cuc_start; 1870 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = 1871 nic->cbs; 1872 } 1873 1874 static int e100_alloc_cbs(struct nic *nic) 1875 { 1876 struct cb *cb; 1877 unsigned int i, count = nic->params.cbs.count; 1878 1879 nic->cuc_cmd = cuc_start; 1880 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL; 1881 nic->cbs_avail = 0; 1882 1883 nic->cbs = dma_pool_zalloc(nic->cbs_pool, GFP_KERNEL, 1884 &nic->cbs_dma_addr); 1885 if (!nic->cbs) 1886 return -ENOMEM; 1887 1888 for (cb = nic->cbs, i = 0; i < count; cb++, i++) { 1889 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs; 1890 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1; 1891 1892 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb); 1893 cb->link = cpu_to_le32(nic->cbs_dma_addr + 1894 ((i+1) % count) * sizeof(struct cb)); 1895 } 1896 1897 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs; 1898 nic->cbs_avail = count; 1899 1900 return 0; 1901 } 1902 1903 static inline void e100_start_receiver(struct nic *nic, struct rx *rx) 1904 { 1905 if (!nic->rxs) return; 1906 if (RU_SUSPENDED != nic->ru_running) return; 1907 1908 /* handle init time starts */ 1909 if (!rx) rx = nic->rxs; 1910 1911 /* (Re)start RU if suspended or idle and RFA is non-NULL */ 1912 if (rx->skb) { 1913 e100_exec_cmd(nic, ruc_start, rx->dma_addr); 1914 nic->ru_running = RU_RUNNING; 1915 } 1916 } 1917 1918 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 1919 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx) 1920 { 1921 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN))) 1922 return -ENOMEM; 1923 1924 /* Init, and map the RFD. */ 1925 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd)); 1926 rx->dma_addr = dma_map_single(&nic->pdev->dev, rx->skb->data, 1927 RFD_BUF_LEN, DMA_BIDIRECTIONAL); 1928 1929 if (dma_mapping_error(&nic->pdev->dev, rx->dma_addr)) { 1930 dev_kfree_skb_any(rx->skb); 1931 rx->skb = NULL; 1932 rx->dma_addr = 0; 1933 return -ENOMEM; 1934 } 1935 1936 /* Link the RFD to end of RFA by linking previous RFD to 1937 * this one. We are safe to touch the previous RFD because 1938 * it is protected by the before last buffer's el bit being set */ 1939 if (rx->prev->skb) { 1940 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data; 1941 put_unaligned_le32(rx->dma_addr, &prev_rfd->link); 1942 dma_sync_single_for_device(&nic->pdev->dev, 1943 rx->prev->dma_addr, 1944 sizeof(struct rfd), 1945 DMA_BIDIRECTIONAL); 1946 } 1947 1948 return 0; 1949 } 1950 1951 static int e100_rx_indicate(struct nic *nic, struct rx *rx, 1952 unsigned int *work_done, unsigned int work_to_do) 1953 { 1954 struct net_device *dev = nic->netdev; 1955 struct sk_buff *skb = rx->skb; 1956 struct rfd *rfd = (struct rfd *)skb->data; 1957 u16 rfd_status, actual_size; 1958 u16 fcs_pad = 0; 1959 1960 if (unlikely(work_done && *work_done >= work_to_do)) 1961 return -EAGAIN; 1962 1963 /* Need to sync before taking a peek at cb_complete bit */ 1964 dma_sync_single_for_cpu(&nic->pdev->dev, rx->dma_addr, 1965 sizeof(struct rfd), DMA_BIDIRECTIONAL); 1966 rfd_status = le16_to_cpu(rfd->status); 1967 1968 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev, 1969 "status=0x%04X\n", rfd_status); 1970 dma_rmb(); /* read size after status bit */ 1971 1972 /* If data isn't ready, nothing to indicate */ 1973 if (unlikely(!(rfd_status & cb_complete))) { 1974 /* If the next buffer has the el bit, but we think the receiver 1975 * is still running, check to see if it really stopped while 1976 * we had interrupts off. 1977 * This allows for a fast restart without re-enabling 1978 * interrupts */ 1979 if ((le16_to_cpu(rfd->command) & cb_el) && 1980 (RU_RUNNING == nic->ru_running)) 1981 1982 if (ioread8(&nic->csr->scb.status) & rus_no_res) 1983 nic->ru_running = RU_SUSPENDED; 1984 dma_sync_single_for_device(&nic->pdev->dev, rx->dma_addr, 1985 sizeof(struct rfd), 1986 DMA_FROM_DEVICE); 1987 return -ENODATA; 1988 } 1989 1990 /* Get actual data size */ 1991 if (unlikely(dev->features & NETIF_F_RXFCS)) 1992 fcs_pad = 4; 1993 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF; 1994 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd))) 1995 actual_size = RFD_BUF_LEN - sizeof(struct rfd); 1996 1997 /* Get data */ 1998 dma_unmap_single(&nic->pdev->dev, rx->dma_addr, RFD_BUF_LEN, 1999 DMA_BIDIRECTIONAL); 2000 2001 /* If this buffer has the el bit, but we think the receiver 2002 * is still running, check to see if it really stopped while 2003 * we had interrupts off. 2004 * This allows for a fast restart without re-enabling interrupts. 2005 * This can happen when the RU sees the size change but also sees 2006 * the el bit set. */ 2007 if ((le16_to_cpu(rfd->command) & cb_el) && 2008 (RU_RUNNING == nic->ru_running)) { 2009 2010 if (ioread8(&nic->csr->scb.status) & rus_no_res) 2011 nic->ru_running = RU_SUSPENDED; 2012 } 2013 2014 /* Pull off the RFD and put the actual data (minus eth hdr) */ 2015 skb_reserve(skb, sizeof(struct rfd)); 2016 skb_put(skb, actual_size); 2017 skb->protocol = eth_type_trans(skb, nic->netdev); 2018 2019 /* If we are receiving all frames, then don't bother 2020 * checking for errors. 2021 */ 2022 if (unlikely(dev->features & NETIF_F_RXALL)) { 2023 if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad) 2024 /* Received oversized frame, but keep it. */ 2025 nic->rx_over_length_errors++; 2026 goto process_skb; 2027 } 2028 2029 if (unlikely(!(rfd_status & cb_ok))) { 2030 /* Don't indicate if hardware indicates errors */ 2031 dev_kfree_skb_any(skb); 2032 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad) { 2033 /* Don't indicate oversized frames */ 2034 nic->rx_over_length_errors++; 2035 dev_kfree_skb_any(skb); 2036 } else { 2037 process_skb: 2038 dev->stats.rx_packets++; 2039 dev->stats.rx_bytes += (actual_size - fcs_pad); 2040 netif_receive_skb(skb); 2041 if (work_done) 2042 (*work_done)++; 2043 } 2044 2045 rx->skb = NULL; 2046 2047 return 0; 2048 } 2049 2050 static void e100_rx_clean(struct nic *nic, unsigned int *work_done, 2051 unsigned int work_to_do) 2052 { 2053 struct rx *rx; 2054 int restart_required = 0, err = 0; 2055 struct rx *old_before_last_rx, *new_before_last_rx; 2056 struct rfd *old_before_last_rfd, *new_before_last_rfd; 2057 2058 /* Indicate newly arrived packets */ 2059 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) { 2060 err = e100_rx_indicate(nic, rx, work_done, work_to_do); 2061 /* Hit quota or no more to clean */ 2062 if (-EAGAIN == err || -ENODATA == err) 2063 break; 2064 } 2065 2066 2067 /* On EAGAIN, hit quota so have more work to do, restart once 2068 * cleanup is complete. 2069 * Else, are we already rnr? then pay attention!!! this ensures that 2070 * the state machine progression never allows a start with a 2071 * partially cleaned list, avoiding a race between hardware 2072 * and rx_to_clean when in NAPI mode */ 2073 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running) 2074 restart_required = 1; 2075 2076 old_before_last_rx = nic->rx_to_use->prev->prev; 2077 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data; 2078 2079 /* Alloc new skbs to refill list */ 2080 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) { 2081 if (unlikely(e100_rx_alloc_skb(nic, rx))) 2082 break; /* Better luck next time (see watchdog) */ 2083 } 2084 2085 new_before_last_rx = nic->rx_to_use->prev->prev; 2086 if (new_before_last_rx != old_before_last_rx) { 2087 /* Set the el-bit on the buffer that is before the last buffer. 2088 * This lets us update the next pointer on the last buffer 2089 * without worrying about hardware touching it. 2090 * We set the size to 0 to prevent hardware from touching this 2091 * buffer. 2092 * When the hardware hits the before last buffer with el-bit 2093 * and size of 0, it will RNR interrupt, the RUS will go into 2094 * the No Resources state. It will not complete nor write to 2095 * this buffer. */ 2096 new_before_last_rfd = 2097 (struct rfd *)new_before_last_rx->skb->data; 2098 new_before_last_rfd->size = 0; 2099 new_before_last_rfd->command |= cpu_to_le16(cb_el); 2100 dma_sync_single_for_device(&nic->pdev->dev, 2101 new_before_last_rx->dma_addr, 2102 sizeof(struct rfd), 2103 DMA_BIDIRECTIONAL); 2104 2105 /* Now that we have a new stopping point, we can clear the old 2106 * stopping point. We must sync twice to get the proper 2107 * ordering on the hardware side of things. */ 2108 old_before_last_rfd->command &= ~cpu_to_le16(cb_el); 2109 dma_sync_single_for_device(&nic->pdev->dev, 2110 old_before_last_rx->dma_addr, 2111 sizeof(struct rfd), 2112 DMA_BIDIRECTIONAL); 2113 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN 2114 + ETH_FCS_LEN); 2115 dma_sync_single_for_device(&nic->pdev->dev, 2116 old_before_last_rx->dma_addr, 2117 sizeof(struct rfd), 2118 DMA_BIDIRECTIONAL); 2119 } 2120 2121 if (restart_required) { 2122 // ack the rnr? 2123 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack); 2124 e100_start_receiver(nic, nic->rx_to_clean); 2125 if (work_done) 2126 (*work_done)++; 2127 } 2128 } 2129 2130 static void e100_rx_clean_list(struct nic *nic) 2131 { 2132 struct rx *rx; 2133 unsigned int i, count = nic->params.rfds.count; 2134 2135 nic->ru_running = RU_UNINITIALIZED; 2136 2137 if (nic->rxs) { 2138 for (rx = nic->rxs, i = 0; i < count; rx++, i++) { 2139 if (rx->skb) { 2140 dma_unmap_single(&nic->pdev->dev, 2141 rx->dma_addr, RFD_BUF_LEN, 2142 DMA_BIDIRECTIONAL); 2143 dev_kfree_skb(rx->skb); 2144 } 2145 } 2146 kfree(nic->rxs); 2147 nic->rxs = NULL; 2148 } 2149 2150 nic->rx_to_use = nic->rx_to_clean = NULL; 2151 } 2152 2153 static int e100_rx_alloc_list(struct nic *nic) 2154 { 2155 struct rx *rx; 2156 unsigned int i, count = nic->params.rfds.count; 2157 struct rfd *before_last; 2158 2159 nic->rx_to_use = nic->rx_to_clean = NULL; 2160 nic->ru_running = RU_UNINITIALIZED; 2161 2162 if (!(nic->rxs = kzalloc_objs(struct rx, count))) 2163 return -ENOMEM; 2164 2165 for (rx = nic->rxs, i = 0; i < count; rx++, i++) { 2166 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs; 2167 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1; 2168 if (e100_rx_alloc_skb(nic, rx)) { 2169 e100_rx_clean_list(nic); 2170 return -ENOMEM; 2171 } 2172 } 2173 /* Set the el-bit on the buffer that is before the last buffer. 2174 * This lets us update the next pointer on the last buffer without 2175 * worrying about hardware touching it. 2176 * We set the size to 0 to prevent hardware from touching this buffer. 2177 * When the hardware hits the before last buffer with el-bit and size 2178 * of 0, it will RNR interrupt, the RU will go into the No Resources 2179 * state. It will not complete nor write to this buffer. */ 2180 rx = nic->rxs->prev->prev; 2181 before_last = (struct rfd *)rx->skb->data; 2182 before_last->command |= cpu_to_le16(cb_el); 2183 before_last->size = 0; 2184 dma_sync_single_for_device(&nic->pdev->dev, rx->dma_addr, 2185 sizeof(struct rfd), DMA_BIDIRECTIONAL); 2186 2187 nic->rx_to_use = nic->rx_to_clean = nic->rxs; 2188 nic->ru_running = RU_SUSPENDED; 2189 2190 return 0; 2191 } 2192 2193 static irqreturn_t e100_intr(int irq, void *dev_id) 2194 { 2195 struct net_device *netdev = dev_id; 2196 struct nic *nic = netdev_priv(netdev); 2197 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack); 2198 2199 netif_printk(nic, intr, KERN_DEBUG, nic->netdev, 2200 "stat_ack = 0x%02X\n", stat_ack); 2201 2202 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */ 2203 stat_ack == stat_ack_not_present) /* Hardware is ejected */ 2204 return IRQ_NONE; 2205 2206 /* Ack interrupt(s) */ 2207 iowrite8(stat_ack, &nic->csr->scb.stat_ack); 2208 2209 /* We hit Receive No Resource (RNR); restart RU after cleaning */ 2210 if (stat_ack & stat_ack_rnr) 2211 nic->ru_running = RU_SUSPENDED; 2212 2213 if (likely(napi_schedule_prep(&nic->napi))) { 2214 e100_disable_irq(nic); 2215 __napi_schedule(&nic->napi); 2216 } 2217 2218 return IRQ_HANDLED; 2219 } 2220 2221 static int e100_poll(struct napi_struct *napi, int budget) 2222 { 2223 struct nic *nic = container_of(napi, struct nic, napi); 2224 unsigned int work_done = 0; 2225 2226 e100_rx_clean(nic, &work_done, budget); 2227 e100_tx_clean(nic); 2228 2229 /* If budget fully consumed, continue polling */ 2230 if (work_done == budget) 2231 return budget; 2232 2233 /* only re-enable interrupt if stack agrees polling is really done */ 2234 if (likely(napi_complete_done(napi, work_done))) 2235 e100_enable_irq(nic); 2236 2237 return work_done; 2238 } 2239 2240 #ifdef CONFIG_NET_POLL_CONTROLLER 2241 static void e100_netpoll(struct net_device *netdev) 2242 { 2243 struct nic *nic = netdev_priv(netdev); 2244 2245 e100_disable_irq(nic); 2246 e100_intr(nic->pdev->irq, netdev); 2247 e100_tx_clean(nic); 2248 e100_enable_irq(nic); 2249 } 2250 #endif 2251 2252 static int e100_set_mac_address(struct net_device *netdev, void *p) 2253 { 2254 struct nic *nic = netdev_priv(netdev); 2255 struct sockaddr *addr = p; 2256 2257 if (!is_valid_ether_addr(addr->sa_data)) 2258 return -EADDRNOTAVAIL; 2259 2260 eth_hw_addr_set(netdev, addr->sa_data); 2261 e100_exec_cb(nic, NULL, e100_setup_iaaddr); 2262 2263 return 0; 2264 } 2265 2266 static int e100_asf(struct nic *nic) 2267 { 2268 /* ASF can be enabled from eeprom */ 2269 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) && 2270 (le16_to_cpu(nic->eeprom[eeprom_config_asf]) & eeprom_asf) && 2271 !(le16_to_cpu(nic->eeprom[eeprom_config_asf]) & eeprom_gcl) && 2272 ((le16_to_cpu(nic->eeprom[eeprom_smbus_addr]) & 0xFF) != 0xFE); 2273 } 2274 2275 static int e100_up(struct nic *nic) 2276 { 2277 int err; 2278 2279 if ((err = e100_rx_alloc_list(nic))) 2280 return err; 2281 if ((err = e100_alloc_cbs(nic))) 2282 goto err_rx_clean_list; 2283 if ((err = e100_hw_init(nic))) 2284 goto err_clean_cbs; 2285 e100_set_multicast_list(nic->netdev); 2286 e100_start_receiver(nic, NULL); 2287 mod_timer(&nic->watchdog, jiffies); 2288 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED, 2289 nic->netdev->name, nic->netdev))) 2290 goto err_no_irq; 2291 netif_wake_queue(nic->netdev); 2292 napi_enable(&nic->napi); 2293 /* enable ints _after_ enabling poll, preventing a race between 2294 * disable ints+schedule */ 2295 e100_enable_irq(nic); 2296 return 0; 2297 2298 err_no_irq: 2299 timer_delete_sync(&nic->watchdog); 2300 err_clean_cbs: 2301 e100_clean_cbs(nic); 2302 err_rx_clean_list: 2303 e100_rx_clean_list(nic); 2304 return err; 2305 } 2306 2307 static void e100_down(struct nic *nic) 2308 { 2309 /* wait here for poll to complete */ 2310 napi_disable(&nic->napi); 2311 netif_stop_queue(nic->netdev); 2312 e100_hw_reset(nic); 2313 free_irq(nic->pdev->irq, nic->netdev); 2314 timer_delete_sync(&nic->watchdog); 2315 netif_carrier_off(nic->netdev); 2316 e100_clean_cbs(nic); 2317 e100_rx_clean_list(nic); 2318 } 2319 2320 static void e100_tx_timeout(struct net_device *netdev, unsigned int txqueue) 2321 { 2322 struct nic *nic = netdev_priv(netdev); 2323 2324 /* Reset outside of interrupt context, to avoid request_irq 2325 * in interrupt context */ 2326 schedule_work(&nic->tx_timeout_task); 2327 } 2328 2329 static void e100_tx_timeout_task(struct work_struct *work) 2330 { 2331 struct nic *nic = container_of(work, struct nic, tx_timeout_task); 2332 struct net_device *netdev = nic->netdev; 2333 2334 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev, 2335 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status)); 2336 2337 rtnl_lock(); 2338 if (netif_running(netdev)) { 2339 e100_down(netdev_priv(netdev)); 2340 e100_up(netdev_priv(netdev)); 2341 } 2342 rtnl_unlock(); 2343 } 2344 2345 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode) 2346 { 2347 int err; 2348 struct sk_buff *skb; 2349 2350 /* Use driver resources to perform internal MAC or PHY 2351 * loopback test. A single packet is prepared and transmitted 2352 * in loopback mode, and the test passes if the received 2353 * packet compares byte-for-byte to the transmitted packet. */ 2354 2355 if ((err = e100_rx_alloc_list(nic))) 2356 return err; 2357 if ((err = e100_alloc_cbs(nic))) 2358 goto err_clean_rx; 2359 2360 /* ICH PHY loopback is broken so do MAC loopback instead */ 2361 if (nic->flags & ich && loopback_mode == lb_phy) 2362 loopback_mode = lb_mac; 2363 2364 nic->loopback = loopback_mode; 2365 if ((err = e100_hw_init(nic))) 2366 goto err_loopback_none; 2367 2368 if (loopback_mode == lb_phy) 2369 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 2370 BMCR_LOOPBACK); 2371 2372 e100_start_receiver(nic, NULL); 2373 2374 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) { 2375 err = -ENOMEM; 2376 goto err_loopback_none; 2377 } 2378 skb_put(skb, ETH_DATA_LEN); 2379 memset(skb->data, 0xFF, ETH_DATA_LEN); 2380 e100_xmit_frame(skb, nic->netdev); 2381 2382 msleep(10); 2383 2384 dma_sync_single_for_cpu(&nic->pdev->dev, nic->rx_to_clean->dma_addr, 2385 RFD_BUF_LEN, DMA_BIDIRECTIONAL); 2386 2387 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd), 2388 skb->data, ETH_DATA_LEN)) 2389 err = -EAGAIN; 2390 2391 err_loopback_none: 2392 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0); 2393 nic->loopback = lb_none; 2394 e100_clean_cbs(nic); 2395 e100_hw_reset(nic); 2396 err_clean_rx: 2397 e100_rx_clean_list(nic); 2398 return err; 2399 } 2400 2401 #define MII_LED_CONTROL 0x1B 2402 #define E100_82552_LED_OVERRIDE 0x19 2403 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */ 2404 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */ 2405 2406 static int e100_get_link_ksettings(struct net_device *netdev, 2407 struct ethtool_link_ksettings *cmd) 2408 { 2409 struct nic *nic = netdev_priv(netdev); 2410 2411 mii_ethtool_get_link_ksettings(&nic->mii, cmd); 2412 2413 return 0; 2414 } 2415 2416 static int e100_set_link_ksettings(struct net_device *netdev, 2417 const struct ethtool_link_ksettings *cmd) 2418 { 2419 struct nic *nic = netdev_priv(netdev); 2420 int err; 2421 2422 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET); 2423 err = mii_ethtool_set_link_ksettings(&nic->mii, cmd); 2424 e100_exec_cb(nic, NULL, e100_configure); 2425 2426 return err; 2427 } 2428 2429 static void e100_get_drvinfo(struct net_device *netdev, 2430 struct ethtool_drvinfo *info) 2431 { 2432 struct nic *nic = netdev_priv(netdev); 2433 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 2434 strscpy(info->bus_info, pci_name(nic->pdev), 2435 sizeof(info->bus_info)); 2436 } 2437 2438 #define E100_PHY_REGS 0x1D 2439 static int e100_get_regs_len(struct net_device *netdev) 2440 { 2441 struct nic *nic = netdev_priv(netdev); 2442 2443 /* We know the number of registers, and the size of the dump buffer. 2444 * Calculate the total size in bytes. 2445 */ 2446 return (1 + E100_PHY_REGS) * sizeof(u32) + sizeof(nic->mem->dump_buf); 2447 } 2448 2449 static void e100_get_regs(struct net_device *netdev, 2450 struct ethtool_regs *regs, void *p) 2451 { 2452 struct nic *nic = netdev_priv(netdev); 2453 u32 *buff = p; 2454 int i; 2455 2456 regs->version = (1 << 24) | nic->pdev->revision; 2457 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 | 2458 ioread8(&nic->csr->scb.cmd_lo) << 16 | 2459 ioread16(&nic->csr->scb.status); 2460 for (i = 0; i < E100_PHY_REGS; i++) 2461 /* Note that we read the registers in reverse order. This 2462 * ordering is the ABI apparently used by ethtool and other 2463 * applications. 2464 */ 2465 buff[1 + i] = mdio_read(netdev, nic->mii.phy_id, 2466 E100_PHY_REGS - 1 - i); 2467 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf)); 2468 e100_exec_cb(nic, NULL, e100_dump); 2469 msleep(10); 2470 memcpy(&buff[1 + E100_PHY_REGS], nic->mem->dump_buf, 2471 sizeof(nic->mem->dump_buf)); 2472 } 2473 2474 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2475 { 2476 struct nic *nic = netdev_priv(netdev); 2477 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0; 2478 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0; 2479 } 2480 2481 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2482 { 2483 struct nic *nic = netdev_priv(netdev); 2484 2485 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) || 2486 !device_can_wakeup(&nic->pdev->dev)) 2487 return -EOPNOTSUPP; 2488 2489 if (wol->wolopts) 2490 nic->flags |= wol_magic; 2491 else 2492 nic->flags &= ~wol_magic; 2493 2494 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts); 2495 2496 e100_exec_cb(nic, NULL, e100_configure); 2497 2498 return 0; 2499 } 2500 2501 static u32 e100_get_msglevel(struct net_device *netdev) 2502 { 2503 struct nic *nic = netdev_priv(netdev); 2504 return nic->msg_enable; 2505 } 2506 2507 static void e100_set_msglevel(struct net_device *netdev, u32 value) 2508 { 2509 struct nic *nic = netdev_priv(netdev); 2510 nic->msg_enable = value; 2511 } 2512 2513 static int e100_nway_reset(struct net_device *netdev) 2514 { 2515 struct nic *nic = netdev_priv(netdev); 2516 return mii_nway_restart(&nic->mii); 2517 } 2518 2519 static u32 e100_get_link(struct net_device *netdev) 2520 { 2521 struct nic *nic = netdev_priv(netdev); 2522 return mii_link_ok(&nic->mii); 2523 } 2524 2525 static int e100_get_eeprom_len(struct net_device *netdev) 2526 { 2527 struct nic *nic = netdev_priv(netdev); 2528 return nic->eeprom_wc << 1; 2529 } 2530 2531 #define E100_EEPROM_MAGIC 0x1234 2532 static int e100_get_eeprom(struct net_device *netdev, 2533 struct ethtool_eeprom *eeprom, u8 *bytes) 2534 { 2535 struct nic *nic = netdev_priv(netdev); 2536 2537 eeprom->magic = E100_EEPROM_MAGIC; 2538 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len); 2539 2540 return 0; 2541 } 2542 2543 static int e100_set_eeprom(struct net_device *netdev, 2544 struct ethtool_eeprom *eeprom, u8 *bytes) 2545 { 2546 struct nic *nic = netdev_priv(netdev); 2547 2548 if (eeprom->magic != E100_EEPROM_MAGIC) 2549 return -EINVAL; 2550 2551 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len); 2552 2553 return e100_eeprom_save(nic, eeprom->offset >> 1, 2554 (eeprom->len >> 1) + 1); 2555 } 2556 2557 static void e100_get_ringparam(struct net_device *netdev, 2558 struct ethtool_ringparam *ring, 2559 struct kernel_ethtool_ringparam *kernel_ring, 2560 struct netlink_ext_ack *extack) 2561 { 2562 struct nic *nic = netdev_priv(netdev); 2563 struct param_range *rfds = &nic->params.rfds; 2564 struct param_range *cbs = &nic->params.cbs; 2565 2566 ring->rx_max_pending = rfds->max; 2567 ring->tx_max_pending = cbs->max; 2568 ring->rx_pending = rfds->count; 2569 ring->tx_pending = cbs->count; 2570 } 2571 2572 static int e100_set_ringparam(struct net_device *netdev, 2573 struct ethtool_ringparam *ring, 2574 struct kernel_ethtool_ringparam *kernel_ring, 2575 struct netlink_ext_ack *extack) 2576 { 2577 struct nic *nic = netdev_priv(netdev); 2578 struct param_range *rfds = &nic->params.rfds; 2579 struct param_range *cbs = &nic->params.cbs; 2580 2581 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 2582 return -EINVAL; 2583 2584 if (netif_running(netdev)) 2585 e100_down(nic); 2586 rfds->count = max(ring->rx_pending, rfds->min); 2587 rfds->count = min(rfds->count, rfds->max); 2588 cbs->count = max(ring->tx_pending, cbs->min); 2589 cbs->count = min(cbs->count, cbs->max); 2590 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n", 2591 rfds->count, cbs->count); 2592 if (netif_running(netdev)) 2593 e100_up(nic); 2594 2595 return 0; 2596 } 2597 2598 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = { 2599 "Link test (on/offline)", 2600 "Eeprom test (on/offline)", 2601 "Self test (offline)", 2602 "Mac loopback (offline)", 2603 "Phy loopback (offline)", 2604 }; 2605 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test) 2606 2607 static void e100_diag_test(struct net_device *netdev, 2608 struct ethtool_test *test, u64 *data) 2609 { 2610 struct ethtool_cmd cmd; 2611 struct nic *nic = netdev_priv(netdev); 2612 int i; 2613 2614 memset(data, 0, E100_TEST_LEN * sizeof(u64)); 2615 data[0] = !mii_link_ok(&nic->mii); 2616 data[1] = e100_eeprom_load(nic); 2617 if (test->flags & ETH_TEST_FL_OFFLINE) { 2618 2619 /* save speed, duplex & autoneg settings */ 2620 mii_ethtool_gset(&nic->mii, &cmd); 2621 2622 if (netif_running(netdev)) 2623 e100_down(nic); 2624 data[2] = e100_self_test(nic); 2625 data[3] = e100_loopback_test(nic, lb_mac); 2626 data[4] = e100_loopback_test(nic, lb_phy); 2627 2628 /* restore speed, duplex & autoneg settings */ 2629 mii_ethtool_sset(&nic->mii, &cmd); 2630 2631 if (netif_running(netdev)) 2632 e100_up(nic); 2633 } 2634 for (i = 0; i < E100_TEST_LEN; i++) 2635 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0; 2636 2637 msleep_interruptible(4 * 1000); 2638 } 2639 2640 static int e100_set_phys_id(struct net_device *netdev, 2641 enum ethtool_phys_id_state state) 2642 { 2643 struct nic *nic = netdev_priv(netdev); 2644 enum led_state { 2645 led_on = 0x01, 2646 led_off = 0x04, 2647 led_on_559 = 0x05, 2648 led_on_557 = 0x07, 2649 }; 2650 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE : 2651 MII_LED_CONTROL; 2652 u16 leds = 0; 2653 2654 switch (state) { 2655 case ETHTOOL_ID_ACTIVE: 2656 return 2; 2657 2658 case ETHTOOL_ID_ON: 2659 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_ON : 2660 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559; 2661 break; 2662 2663 case ETHTOOL_ID_OFF: 2664 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_OFF : led_off; 2665 break; 2666 2667 case ETHTOOL_ID_INACTIVE: 2668 break; 2669 } 2670 2671 mdio_write(netdev, nic->mii.phy_id, led_reg, leds); 2672 return 0; 2673 } 2674 2675 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = { 2676 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", 2677 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", 2678 "rx_length_errors", "rx_over_errors", "rx_crc_errors", 2679 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", 2680 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", 2681 "tx_heartbeat_errors", "tx_window_errors", 2682 /* device-specific stats */ 2683 "tx_deferred", "tx_single_collisions", "tx_multi_collisions", 2684 "tx_flow_control_pause", "rx_flow_control_pause", 2685 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets", 2686 "rx_short_frame_errors", "rx_over_length_errors", 2687 }; 2688 #define E100_NET_STATS_LEN 21 2689 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats) 2690 2691 static int e100_get_sset_count(struct net_device *netdev, int sset) 2692 { 2693 switch (sset) { 2694 case ETH_SS_TEST: 2695 return E100_TEST_LEN; 2696 case ETH_SS_STATS: 2697 return E100_STATS_LEN; 2698 default: 2699 return -EOPNOTSUPP; 2700 } 2701 } 2702 2703 static void e100_get_ethtool_stats(struct net_device *netdev, 2704 struct ethtool_stats *stats, u64 *data) 2705 { 2706 struct nic *nic = netdev_priv(netdev); 2707 int i; 2708 2709 for (i = 0; i < E100_NET_STATS_LEN; i++) 2710 data[i] = ((unsigned long *)&netdev->stats)[i]; 2711 2712 data[i++] = nic->tx_deferred; 2713 data[i++] = nic->tx_single_collisions; 2714 data[i++] = nic->tx_multiple_collisions; 2715 data[i++] = nic->tx_fc_pause; 2716 data[i++] = nic->rx_fc_pause; 2717 data[i++] = nic->rx_fc_unsupported; 2718 data[i++] = nic->tx_tco_frames; 2719 data[i++] = nic->rx_tco_frames; 2720 data[i++] = nic->rx_short_frame_errors; 2721 data[i++] = nic->rx_over_length_errors; 2722 } 2723 2724 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2725 { 2726 switch (stringset) { 2727 case ETH_SS_TEST: 2728 memcpy(data, e100_gstrings_test, sizeof(e100_gstrings_test)); 2729 break; 2730 case ETH_SS_STATS: 2731 memcpy(data, e100_gstrings_stats, sizeof(e100_gstrings_stats)); 2732 break; 2733 } 2734 } 2735 2736 static const struct ethtool_ops e100_ethtool_ops = { 2737 .get_drvinfo = e100_get_drvinfo, 2738 .get_regs_len = e100_get_regs_len, 2739 .get_regs = e100_get_regs, 2740 .get_wol = e100_get_wol, 2741 .set_wol = e100_set_wol, 2742 .get_msglevel = e100_get_msglevel, 2743 .set_msglevel = e100_set_msglevel, 2744 .nway_reset = e100_nway_reset, 2745 .get_link = e100_get_link, 2746 .get_eeprom_len = e100_get_eeprom_len, 2747 .get_eeprom = e100_get_eeprom, 2748 .set_eeprom = e100_set_eeprom, 2749 .get_ringparam = e100_get_ringparam, 2750 .set_ringparam = e100_set_ringparam, 2751 .self_test = e100_diag_test, 2752 .get_strings = e100_get_strings, 2753 .set_phys_id = e100_set_phys_id, 2754 .get_ethtool_stats = e100_get_ethtool_stats, 2755 .get_sset_count = e100_get_sset_count, 2756 .get_ts_info = ethtool_op_get_ts_info, 2757 .get_link_ksettings = e100_get_link_ksettings, 2758 .set_link_ksettings = e100_set_link_ksettings, 2759 }; 2760 2761 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2762 { 2763 struct nic *nic = netdev_priv(netdev); 2764 2765 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL); 2766 } 2767 2768 static int e100_alloc(struct nic *nic) 2769 { 2770 nic->mem = dma_alloc_coherent(&nic->pdev->dev, sizeof(struct mem), 2771 &nic->dma_addr, GFP_KERNEL); 2772 return nic->mem ? 0 : -ENOMEM; 2773 } 2774 2775 static void e100_free(struct nic *nic) 2776 { 2777 if (nic->mem) { 2778 dma_free_coherent(&nic->pdev->dev, sizeof(struct mem), 2779 nic->mem, nic->dma_addr); 2780 nic->mem = NULL; 2781 } 2782 } 2783 2784 static int e100_open(struct net_device *netdev) 2785 { 2786 struct nic *nic = netdev_priv(netdev); 2787 int err = 0; 2788 2789 netif_carrier_off(netdev); 2790 if ((err = e100_up(nic))) 2791 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n"); 2792 return err; 2793 } 2794 2795 static int e100_close(struct net_device *netdev) 2796 { 2797 e100_down(netdev_priv(netdev)); 2798 return 0; 2799 } 2800 2801 static int e100_set_features(struct net_device *netdev, 2802 netdev_features_t features) 2803 { 2804 struct nic *nic = netdev_priv(netdev); 2805 netdev_features_t changed = features ^ netdev->features; 2806 2807 if (!(changed & (NETIF_F_RXFCS | NETIF_F_RXALL))) 2808 return 0; 2809 2810 netdev->features = features; 2811 e100_exec_cb(nic, NULL, e100_configure); 2812 return 1; 2813 } 2814 2815 static const struct net_device_ops e100_netdev_ops = { 2816 .ndo_open = e100_open, 2817 .ndo_stop = e100_close, 2818 .ndo_start_xmit = e100_xmit_frame, 2819 .ndo_validate_addr = eth_validate_addr, 2820 .ndo_set_rx_mode = e100_set_multicast_list, 2821 .ndo_set_mac_address = e100_set_mac_address, 2822 .ndo_eth_ioctl = e100_do_ioctl, 2823 .ndo_tx_timeout = e100_tx_timeout, 2824 #ifdef CONFIG_NET_POLL_CONTROLLER 2825 .ndo_poll_controller = e100_netpoll, 2826 #endif 2827 .ndo_set_features = e100_set_features, 2828 }; 2829 2830 static int e100_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2831 { 2832 struct net_device *netdev; 2833 struct nic *nic; 2834 int err; 2835 2836 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) 2837 return -ENOMEM; 2838 2839 netdev->hw_features |= NETIF_F_RXFCS; 2840 netdev->priv_flags |= IFF_SUPP_NOFCS; 2841 netdev->hw_features |= NETIF_F_RXALL; 2842 2843 netdev->netdev_ops = &e100_netdev_ops; 2844 netdev->ethtool_ops = &e100_ethtool_ops; 2845 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD; 2846 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 2847 2848 nic = netdev_priv(netdev); 2849 netif_napi_add_weight(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT); 2850 nic->netdev = netdev; 2851 nic->pdev = pdev; 2852 nic->msg_enable = (1 << debug) - 1; 2853 nic->mdio_ctrl = mdio_ctrl_hw; 2854 pci_set_drvdata(pdev, netdev); 2855 2856 if ((err = pci_enable_device(pdev))) { 2857 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n"); 2858 goto err_out_free_dev; 2859 } 2860 2861 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2862 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n"); 2863 err = -ENODEV; 2864 goto err_out_disable_pdev; 2865 } 2866 2867 if ((err = pci_request_regions(pdev, DRV_NAME))) { 2868 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n"); 2869 goto err_out_disable_pdev; 2870 } 2871 2872 if ((err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) { 2873 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n"); 2874 goto err_out_free_res; 2875 } 2876 2877 SET_NETDEV_DEV(netdev, &pdev->dev); 2878 2879 if (use_io) 2880 netif_info(nic, probe, nic->netdev, "using i/o access mode\n"); 2881 2882 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr)); 2883 if (!nic->csr) { 2884 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n"); 2885 err = -ENOMEM; 2886 goto err_out_free_res; 2887 } 2888 2889 if (ent->driver_data) 2890 nic->flags |= ich; 2891 else 2892 nic->flags &= ~ich; 2893 2894 e100_get_defaults(nic); 2895 2896 /* D100 MAC doesn't allow rx of vlan packets with normal MTU */ 2897 if (nic->mac < mac_82558_D101_A4) 2898 netdev->features |= NETIF_F_VLAN_CHALLENGED; 2899 2900 /* locks must be initialized before calling hw_reset */ 2901 spin_lock_init(&nic->cb_lock); 2902 spin_lock_init(&nic->cmd_lock); 2903 spin_lock_init(&nic->mdio_lock); 2904 2905 /* Reset the device before pci_set_master() in case device is in some 2906 * funky state and has an interrupt pending - hint: we don't have the 2907 * interrupt handler registered yet. */ 2908 e100_hw_reset(nic); 2909 2910 pci_set_master(pdev); 2911 2912 timer_setup(&nic->watchdog, e100_watchdog, 0); 2913 2914 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task); 2915 2916 if ((err = e100_alloc(nic))) { 2917 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n"); 2918 goto err_out_iounmap; 2919 } 2920 2921 if ((err = e100_eeprom_load(nic))) 2922 goto err_out_free; 2923 2924 e100_phy_init(nic); 2925 2926 eth_hw_addr_set(netdev, (u8 *)nic->eeprom); 2927 if (!is_valid_ether_addr(netdev->dev_addr)) { 2928 if (!eeprom_bad_csum_allow) { 2929 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n"); 2930 err = -EAGAIN; 2931 goto err_out_free; 2932 } else { 2933 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n"); 2934 } 2935 } 2936 2937 /* Wol magic packet can be enabled from eeprom */ 2938 if ((nic->mac >= mac_82558_D101_A4) && 2939 (le16_to_cpu(nic->eeprom[eeprom_id]) & eeprom_id_wol)) { 2940 nic->flags |= wol_magic; 2941 device_set_wakeup_enable(&pdev->dev, true); 2942 } 2943 2944 /* ack any pending wake events, disable PME */ 2945 pci_pme_active(pdev, false); 2946 2947 strcpy(netdev->name, "eth%d"); 2948 if ((err = register_netdev(netdev))) { 2949 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n"); 2950 goto err_out_free; 2951 } 2952 nic->cbs_pool = dma_pool_create(netdev->name, 2953 &nic->pdev->dev, 2954 nic->params.cbs.max * sizeof(struct cb), 2955 sizeof(u32), 2956 0); 2957 if (!nic->cbs_pool) { 2958 netif_err(nic, probe, nic->netdev, "Cannot create DMA pool, aborting\n"); 2959 err = -ENOMEM; 2960 goto err_out_pool; 2961 } 2962 netif_info(nic, probe, nic->netdev, 2963 "addr 0x%llx, irq %d, MAC addr %pM\n", 2964 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0), 2965 pdev->irq, netdev->dev_addr); 2966 2967 return 0; 2968 2969 err_out_pool: 2970 unregister_netdev(netdev); 2971 err_out_free: 2972 e100_free(nic); 2973 err_out_iounmap: 2974 pci_iounmap(pdev, nic->csr); 2975 err_out_free_res: 2976 pci_release_regions(pdev); 2977 err_out_disable_pdev: 2978 pci_disable_device(pdev); 2979 err_out_free_dev: 2980 free_netdev(netdev); 2981 return err; 2982 } 2983 2984 static void e100_remove(struct pci_dev *pdev) 2985 { 2986 struct net_device *netdev = pci_get_drvdata(pdev); 2987 2988 if (netdev) { 2989 struct nic *nic = netdev_priv(netdev); 2990 unregister_netdev(netdev); 2991 e100_free(nic); 2992 pci_iounmap(pdev, nic->csr); 2993 dma_pool_destroy(nic->cbs_pool); 2994 free_netdev(netdev); 2995 pci_release_regions(pdev); 2996 pci_disable_device(pdev); 2997 } 2998 } 2999 3000 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */ 3001 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */ 3002 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */ 3003 static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake) 3004 { 3005 struct net_device *netdev = pci_get_drvdata(pdev); 3006 struct nic *nic = netdev_priv(netdev); 3007 3008 netif_device_detach(netdev); 3009 3010 if (netif_running(netdev)) 3011 e100_down(nic); 3012 3013 if ((nic->flags & wol_magic) | e100_asf(nic)) { 3014 /* enable reverse auto-negotiation */ 3015 if (nic->phy == phy_82552_v) { 3016 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id, 3017 E100_82552_SMARTSPEED); 3018 3019 mdio_write(netdev, nic->mii.phy_id, 3020 E100_82552_SMARTSPEED, smartspeed | 3021 E100_82552_REV_ANEG | E100_82552_ANEG_NOW); 3022 } 3023 *enable_wake = true; 3024 } else { 3025 *enable_wake = false; 3026 } 3027 3028 pci_disable_device(pdev); 3029 } 3030 3031 static int __e100_power_off(struct pci_dev *pdev, bool wake) 3032 { 3033 if (wake) 3034 return pci_prepare_to_sleep(pdev); 3035 3036 pci_wake_from_d3(pdev, false); 3037 pci_set_power_state(pdev, PCI_D3hot); 3038 3039 return 0; 3040 } 3041 3042 static int e100_suspend(struct device *dev_d) 3043 { 3044 bool wake; 3045 3046 __e100_shutdown(to_pci_dev(dev_d), &wake); 3047 3048 return 0; 3049 } 3050 3051 static int e100_resume(struct device *dev_d) 3052 { 3053 struct net_device *netdev = dev_get_drvdata(dev_d); 3054 struct nic *nic = netdev_priv(netdev); 3055 int err; 3056 3057 err = pci_enable_device(to_pci_dev(dev_d)); 3058 if (err) { 3059 netdev_err(netdev, "Resume cannot enable PCI device, aborting\n"); 3060 return err; 3061 } 3062 pci_set_master(to_pci_dev(dev_d)); 3063 3064 /* disable reverse auto-negotiation */ 3065 if (nic->phy == phy_82552_v) { 3066 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id, 3067 E100_82552_SMARTSPEED); 3068 3069 mdio_write(netdev, nic->mii.phy_id, 3070 E100_82552_SMARTSPEED, 3071 smartspeed & ~(E100_82552_REV_ANEG)); 3072 } 3073 3074 if (netif_running(netdev)) 3075 e100_up(nic); 3076 3077 netif_device_attach(netdev); 3078 3079 return 0; 3080 } 3081 3082 static void e100_shutdown(struct pci_dev *pdev) 3083 { 3084 bool wake; 3085 __e100_shutdown(pdev, &wake); 3086 if (system_state == SYSTEM_POWER_OFF) 3087 __e100_power_off(pdev, wake); 3088 } 3089 3090 /* ------------------ PCI Error Recovery infrastructure -------------- */ 3091 /** 3092 * e100_io_error_detected - called when PCI error is detected. 3093 * @pdev: Pointer to PCI device 3094 * @state: The current pci connection state 3095 */ 3096 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 3097 { 3098 struct net_device *netdev = pci_get_drvdata(pdev); 3099 struct nic *nic = netdev_priv(netdev); 3100 3101 netif_device_detach(netdev); 3102 3103 if (state == pci_channel_io_perm_failure) 3104 return PCI_ERS_RESULT_DISCONNECT; 3105 3106 if (netif_running(netdev)) 3107 e100_down(nic); 3108 pci_disable_device(pdev); 3109 3110 /* Request a slot reset. */ 3111 return PCI_ERS_RESULT_NEED_RESET; 3112 } 3113 3114 /** 3115 * e100_io_slot_reset - called after the pci bus has been reset. 3116 * @pdev: Pointer to PCI device 3117 * 3118 * Restart the card from scratch. 3119 */ 3120 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev) 3121 { 3122 struct net_device *netdev = pci_get_drvdata(pdev); 3123 struct nic *nic = netdev_priv(netdev); 3124 3125 if (pci_enable_device(pdev)) { 3126 pr_err("Cannot re-enable PCI device after reset\n"); 3127 return PCI_ERS_RESULT_DISCONNECT; 3128 } 3129 pci_set_master(pdev); 3130 3131 /* Only one device per card can do a reset */ 3132 if (0 != PCI_FUNC(pdev->devfn)) 3133 return PCI_ERS_RESULT_RECOVERED; 3134 e100_hw_reset(nic); 3135 e100_phy_init(nic); 3136 3137 return PCI_ERS_RESULT_RECOVERED; 3138 } 3139 3140 /** 3141 * e100_io_resume - resume normal operations 3142 * @pdev: Pointer to PCI device 3143 * 3144 * Resume normal operations after an error recovery 3145 * sequence has been completed. 3146 */ 3147 static void e100_io_resume(struct pci_dev *pdev) 3148 { 3149 struct net_device *netdev = pci_get_drvdata(pdev); 3150 struct nic *nic = netdev_priv(netdev); 3151 3152 /* ack any pending wake events, disable PME */ 3153 pci_enable_wake(pdev, PCI_D0, 0); 3154 3155 netif_device_attach(netdev); 3156 if (netif_running(netdev)) { 3157 e100_open(netdev); 3158 mod_timer(&nic->watchdog, jiffies); 3159 } 3160 } 3161 3162 static const struct pci_error_handlers e100_err_handler = { 3163 .error_detected = e100_io_error_detected, 3164 .slot_reset = e100_io_slot_reset, 3165 .resume = e100_io_resume, 3166 }; 3167 3168 static DEFINE_SIMPLE_DEV_PM_OPS(e100_pm_ops, e100_suspend, e100_resume); 3169 3170 static struct pci_driver e100_driver = { 3171 .name = DRV_NAME, 3172 .id_table = e100_id_table, 3173 .probe = e100_probe, 3174 .remove = e100_remove, 3175 3176 /* Power Management hooks */ 3177 .driver.pm = pm_sleep_ptr(&e100_pm_ops), 3178 3179 .shutdown = e100_shutdown, 3180 .err_handler = &e100_err_handler, 3181 }; 3182 3183 static int __init e100_init_module(void) 3184 { 3185 if (((1 << debug) - 1) & NETIF_MSG_DRV) { 3186 pr_info("%s\n", DRV_DESCRIPTION); 3187 pr_info("%s\n", DRV_COPYRIGHT); 3188 } 3189 return pci_register_driver(&e100_driver); 3190 } 3191 3192 static void __exit e100_cleanup_module(void) 3193 { 3194 pci_unregister_driver(&e100_driver); 3195 } 3196 3197 module_init(e100_init_module); 3198 module_exit(e100_cleanup_module); 3199