1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/net/ethernet/ibm/emac/mal.c 4 * 5 * Memory Access Layer (MAL) support 6 * 7 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 8 * <benh@kernel.crashing.org> 9 * 10 * Based on the arch/ppc version of the driver: 11 * 12 * Copyright (c) 2004, 2005 Zultys Technologies. 13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 14 * 15 * Based on original work by 16 * Benjamin Herrenschmidt <benh@kernel.crashing.org>, 17 * David Gibson <hermes@gibson.dropbear.id.au>, 18 * 19 * Armin Kuster <akuster@mvista.com> 20 * Copyright 2002 MontaVista Softare Inc. 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/slab.h> 25 #include <linux/of.h> 26 #include <linux/of_irq.h> 27 #include <linux/platform_device.h> 28 29 #include "core.h" 30 #include <asm/dcr-regs.h> 31 32 static int mal_count; 33 34 int mal_register_commac(struct mal_instance *mal, struct mal_commac *commac) 35 { 36 unsigned long flags; 37 38 netdev_lock(mal->napi.dev); 39 spin_lock_irqsave(&mal->lock, flags); 40 41 MAL_DBG(mal, "reg(%08x, %08x)" NL, 42 commac->tx_chan_mask, commac->rx_chan_mask); 43 44 /* Don't let multiple commacs claim the same channel(s) */ 45 if ((mal->tx_chan_mask & commac->tx_chan_mask) || 46 (mal->rx_chan_mask & commac->rx_chan_mask)) { 47 spin_unlock_irqrestore(&mal->lock, flags); 48 netdev_unlock(mal->napi.dev); 49 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n", 50 mal->index); 51 return -EBUSY; 52 } 53 54 if (list_empty(&mal->list)) 55 napi_enable_locked(&mal->napi); 56 mal->tx_chan_mask |= commac->tx_chan_mask; 57 mal->rx_chan_mask |= commac->rx_chan_mask; 58 list_add(&commac->list, &mal->list); 59 60 spin_unlock_irqrestore(&mal->lock, flags); 61 netdev_unlock(mal->napi.dev); 62 63 return 0; 64 } 65 66 void mal_unregister_commac(struct mal_instance *mal, 67 struct mal_commac *commac) 68 { 69 unsigned long flags; 70 bool disable_napi; 71 72 netdev_lock(mal->napi.dev); 73 spin_lock_irqsave(&mal->lock, flags); 74 75 MAL_DBG(mal, "unreg(%08x, %08x)" NL, 76 commac->tx_chan_mask, commac->rx_chan_mask); 77 78 mal->tx_chan_mask &= ~commac->tx_chan_mask; 79 mal->rx_chan_mask &= ~commac->rx_chan_mask; 80 list_del_init(&commac->list); 81 disable_napi = list_empty(&mal->list); 82 83 spin_unlock_irqrestore(&mal->lock, flags); 84 if (disable_napi) 85 napi_disable_locked(&mal->napi); 86 netdev_unlock(mal->napi.dev); 87 } 88 89 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size) 90 { 91 BUG_ON(channel < 0 || channel >= mal->num_rx_chans || 92 size > MAL_MAX_RX_SIZE); 93 94 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size); 95 96 if (size & 0xf) { 97 printk(KERN_WARNING 98 "mal%d: incorrect RX size %lu for the channel %d\n", 99 mal->index, size, channel); 100 return -EINVAL; 101 } 102 103 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4); 104 return 0; 105 } 106 107 int mal_tx_bd_offset(struct mal_instance *mal, int channel) 108 { 109 BUG_ON(channel < 0 || channel >= mal->num_tx_chans); 110 111 return channel * NUM_TX_BUFF; 112 } 113 114 int mal_rx_bd_offset(struct mal_instance *mal, int channel) 115 { 116 BUG_ON(channel < 0 || channel >= mal->num_rx_chans); 117 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF; 118 } 119 120 void mal_enable_tx_channel(struct mal_instance *mal, int channel) 121 { 122 unsigned long flags; 123 124 spin_lock_irqsave(&mal->lock, flags); 125 126 MAL_DBG(mal, "enable_tx(%d)" NL, channel); 127 128 set_mal_dcrn(mal, MAL_TXCASR, 129 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel)); 130 131 spin_unlock_irqrestore(&mal->lock, flags); 132 } 133 134 void mal_disable_tx_channel(struct mal_instance *mal, int channel) 135 { 136 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel)); 137 138 MAL_DBG(mal, "disable_tx(%d)" NL, channel); 139 } 140 141 void mal_enable_rx_channel(struct mal_instance *mal, int channel) 142 { 143 unsigned long flags; 144 145 /* 146 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple 147 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value 148 * for the bitmask 149 */ 150 if (!(channel % 8)) 151 channel >>= 3; 152 153 spin_lock_irqsave(&mal->lock, flags); 154 155 MAL_DBG(mal, "enable_rx(%d)" NL, channel); 156 157 set_mal_dcrn(mal, MAL_RXCASR, 158 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel)); 159 160 spin_unlock_irqrestore(&mal->lock, flags); 161 } 162 163 void mal_disable_rx_channel(struct mal_instance *mal, int channel) 164 { 165 /* 166 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple 167 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value 168 * for the bitmask 169 */ 170 if (!(channel % 8)) 171 channel >>= 3; 172 173 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel)); 174 175 MAL_DBG(mal, "disable_rx(%d)" NL, channel); 176 } 177 178 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac) 179 { 180 unsigned long flags; 181 182 spin_lock_irqsave(&mal->lock, flags); 183 184 MAL_DBG(mal, "poll_add(%p)" NL, commac); 185 186 /* starts disabled */ 187 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags); 188 189 list_add_tail(&commac->poll_list, &mal->poll_list); 190 191 spin_unlock_irqrestore(&mal->lock, flags); 192 } 193 194 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac) 195 { 196 unsigned long flags; 197 198 spin_lock_irqsave(&mal->lock, flags); 199 200 MAL_DBG(mal, "poll_del(%p)" NL, commac); 201 202 list_del(&commac->poll_list); 203 204 spin_unlock_irqrestore(&mal->lock, flags); 205 } 206 207 /* synchronized by mal_poll() */ 208 static inline void mal_enable_eob_irq(struct mal_instance *mal) 209 { 210 MAL_DBG2(mal, "enable_irq" NL); 211 212 // XXX might want to cache MAL_CFG as the DCR read can be slooooow 213 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE); 214 } 215 216 /* synchronized by NAPI state */ 217 static inline void mal_disable_eob_irq(struct mal_instance *mal) 218 { 219 // XXX might want to cache MAL_CFG as the DCR read can be slooooow 220 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE); 221 222 MAL_DBG2(mal, "disable_irq" NL); 223 } 224 225 static irqreturn_t mal_serr(int irq, void *dev_instance) 226 { 227 struct mal_instance *mal = dev_instance; 228 229 u32 esr = get_mal_dcrn(mal, MAL_ESR); 230 231 /* Clear the error status register */ 232 set_mal_dcrn(mal, MAL_ESR, esr); 233 234 MAL_DBG(mal, "SERR %08x" NL, esr); 235 236 if (esr & MAL_ESR_EVB) { 237 if (esr & MAL_ESR_DE) { 238 /* We ignore Descriptor error, 239 * TXDE or RXDE interrupt will be generated anyway. 240 */ 241 return IRQ_HANDLED; 242 } 243 244 if (esr & MAL_ESR_PEIN) { 245 /* PLB error, it's probably buggy hardware or 246 * incorrect physical address in BD (i.e. bug) 247 */ 248 if (net_ratelimit()) 249 printk(KERN_ERR 250 "mal%d: system error, " 251 "PLB (ESR = 0x%08x)\n", 252 mal->index, esr); 253 return IRQ_HANDLED; 254 } 255 256 /* OPB error, it's probably buggy hardware or incorrect 257 * EBC setup 258 */ 259 if (net_ratelimit()) 260 printk(KERN_ERR 261 "mal%d: system error, OPB (ESR = 0x%08x)\n", 262 mal->index, esr); 263 } 264 return IRQ_HANDLED; 265 } 266 267 static inline void mal_schedule_poll(struct mal_instance *mal) 268 { 269 if (likely(napi_schedule_prep(&mal->napi))) { 270 MAL_DBG2(mal, "schedule_poll" NL); 271 spin_lock(&mal->lock); 272 mal_disable_eob_irq(mal); 273 spin_unlock(&mal->lock); 274 __napi_schedule(&mal->napi); 275 } else 276 MAL_DBG2(mal, "already in poll" NL); 277 } 278 279 static irqreturn_t mal_txeob(int irq, void *dev_instance) 280 { 281 struct mal_instance *mal = dev_instance; 282 283 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR); 284 285 MAL_DBG2(mal, "txeob %08x" NL, r); 286 287 mal_schedule_poll(mal); 288 set_mal_dcrn(mal, MAL_TXEOBISR, r); 289 290 #ifdef CONFIG_PPC_DCR_NATIVE 291 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT)) 292 mtdcri(SDR0, DCRN_SDR_ICINTSTAT, 293 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICTX)); 294 #endif 295 296 return IRQ_HANDLED; 297 } 298 299 static irqreturn_t mal_rxeob(int irq, void *dev_instance) 300 { 301 struct mal_instance *mal = dev_instance; 302 303 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR); 304 305 MAL_DBG2(mal, "rxeob %08x" NL, r); 306 307 mal_schedule_poll(mal); 308 set_mal_dcrn(mal, MAL_RXEOBISR, r); 309 310 #ifdef CONFIG_PPC_DCR_NATIVE 311 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT)) 312 mtdcri(SDR0, DCRN_SDR_ICINTSTAT, 313 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICRX)); 314 #endif 315 316 return IRQ_HANDLED; 317 } 318 319 static irqreturn_t mal_txde(int irq, void *dev_instance) 320 { 321 struct mal_instance *mal = dev_instance; 322 323 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR); 324 set_mal_dcrn(mal, MAL_TXDEIR, deir); 325 326 MAL_DBG(mal, "txde %08x" NL, deir); 327 328 if (net_ratelimit()) 329 printk(KERN_ERR 330 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n", 331 mal->index, deir); 332 333 return IRQ_HANDLED; 334 } 335 336 static irqreturn_t mal_rxde(int irq, void *dev_instance) 337 { 338 struct mal_instance *mal = dev_instance; 339 struct list_head *l; 340 341 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR); 342 343 MAL_DBG(mal, "rxde %08x" NL, deir); 344 345 list_for_each(l, &mal->list) { 346 struct mal_commac *mc = list_entry(l, struct mal_commac, list); 347 if (deir & mc->rx_chan_mask) { 348 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags); 349 mc->ops->rxde(mc->dev); 350 } 351 } 352 353 mal_schedule_poll(mal); 354 set_mal_dcrn(mal, MAL_RXDEIR, deir); 355 356 return IRQ_HANDLED; 357 } 358 359 static irqreturn_t mal_int(int irq, void *dev_instance) 360 { 361 struct mal_instance *mal = dev_instance; 362 u32 esr = get_mal_dcrn(mal, MAL_ESR); 363 364 if (esr & MAL_ESR_EVB) { 365 /* descriptor error */ 366 if (esr & MAL_ESR_DE) { 367 if (esr & MAL_ESR_CIDT) 368 return mal_rxde(irq, dev_instance); 369 else 370 return mal_txde(irq, dev_instance); 371 } else { /* SERR */ 372 return mal_serr(irq, dev_instance); 373 } 374 } 375 return IRQ_HANDLED; 376 } 377 378 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac) 379 { 380 /* Spinlock-type semantics: only one caller disable poll at a time */ 381 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags)) 382 msleep(1); 383 384 /* Synchronize with the MAL NAPI poller */ 385 napi_synchronize(&mal->napi); 386 } 387 388 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac) 389 { 390 smp_wmb(); 391 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags); 392 393 /* Feels better to trigger a poll here to catch up with events that 394 * may have happened on this channel while disabled. It will most 395 * probably be delayed until the next interrupt but that's mostly a 396 * non-issue in the context where this is called. 397 */ 398 napi_schedule(&mal->napi); 399 } 400 401 static int mal_poll(struct napi_struct *napi, int budget) 402 { 403 struct mal_instance *mal = container_of(napi, struct mal_instance, napi); 404 struct list_head *l; 405 int received = 0; 406 unsigned long flags; 407 408 MAL_DBG2(mal, "poll(%d)" NL, budget); 409 410 /* Process TX skbs */ 411 list_for_each(l, &mal->poll_list) { 412 struct mal_commac *mc = 413 list_entry(l, struct mal_commac, poll_list); 414 mc->ops->poll_tx(mc->dev); 415 } 416 417 /* Process RX skbs. 418 * 419 * We _might_ need something more smart here to enforce polling 420 * fairness. 421 */ 422 list_for_each(l, &mal->poll_list) { 423 struct mal_commac *mc = 424 list_entry(l, struct mal_commac, poll_list); 425 int n; 426 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags))) 427 continue; 428 n = mc->ops->poll_rx(mc->dev, budget - received); 429 if (n) { 430 received += n; 431 if (received >= budget) 432 return budget; 433 } 434 } 435 436 if (napi_complete_done(napi, received)) { 437 /* We need to disable IRQs to protect from RXDE IRQ here */ 438 spin_lock_irqsave(&mal->lock, flags); 439 mal_enable_eob_irq(mal); 440 spin_unlock_irqrestore(&mal->lock, flags); 441 } 442 443 /* Check for "rotting" packet(s) */ 444 list_for_each(l, &mal->poll_list) { 445 struct mal_commac *mc = 446 list_entry(l, struct mal_commac, poll_list); 447 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags))) 448 continue; 449 if (unlikely(mc->ops->peek_rx(mc->dev) || 450 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) { 451 MAL_DBG2(mal, "rotting packet" NL); 452 if (!napi_schedule(napi)) 453 goto more_work; 454 455 spin_lock_irqsave(&mal->lock, flags); 456 mal_disable_eob_irq(mal); 457 spin_unlock_irqrestore(&mal->lock, flags); 458 } 459 mc->ops->poll_tx(mc->dev); 460 } 461 462 more_work: 463 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received); 464 return received; 465 } 466 467 static void mal_reset(struct mal_instance *mal) 468 { 469 int n = 10; 470 471 MAL_DBG(mal, "reset" NL); 472 473 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR); 474 475 /* Wait for reset to complete (1 system clock) */ 476 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n) 477 --n; 478 479 if (unlikely(!n)) 480 printk(KERN_ERR "mal%d: reset timeout\n", mal->index); 481 } 482 483 int mal_get_regs_len(struct mal_instance *mal) 484 { 485 return sizeof(struct emac_ethtool_regs_subhdr) + 486 sizeof(struct mal_regs); 487 } 488 489 void *mal_dump_regs(struct mal_instance *mal, void *buf) 490 { 491 struct emac_ethtool_regs_subhdr *hdr = buf; 492 struct mal_regs *regs = (struct mal_regs *)(hdr + 1); 493 int i; 494 495 hdr->version = mal->version; 496 hdr->index = mal->index; 497 498 regs->tx_count = mal->num_tx_chans; 499 regs->rx_count = mal->num_rx_chans; 500 501 regs->cfg = get_mal_dcrn(mal, MAL_CFG); 502 regs->esr = get_mal_dcrn(mal, MAL_ESR); 503 regs->ier = get_mal_dcrn(mal, MAL_IER); 504 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR); 505 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR); 506 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR); 507 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR); 508 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR); 509 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR); 510 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR); 511 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR); 512 513 for (i = 0; i < regs->tx_count; ++i) 514 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i)); 515 516 for (i = 0; i < regs->rx_count; ++i) { 517 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i)); 518 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i)); 519 } 520 return regs + 1; 521 } 522 523 static int mal_probe(struct platform_device *ofdev) 524 { 525 struct mal_instance *mal; 526 int err = 0, i, bd_size; 527 int index = mal_count++; 528 unsigned int dcr_base; 529 const u32 *prop; 530 u32 cfg; 531 unsigned long irqflags; 532 irq_handler_t hdlr_serr, hdlr_txde, hdlr_rxde; 533 534 mal = devm_kzalloc(&ofdev->dev, sizeof(struct mal_instance), 535 GFP_KERNEL); 536 if (!mal) 537 return -ENOMEM; 538 539 mal->index = index; 540 mal->ofdev = ofdev; 541 mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1; 542 543 MAL_DBG(mal, "probe" NL); 544 545 prop = of_get_property(ofdev->dev.of_node, "num-tx-chans", NULL); 546 if (prop == NULL) { 547 printk(KERN_ERR 548 "mal%d: can't find MAL num-tx-chans property!\n", 549 index); 550 return -ENODEV; 551 } 552 mal->num_tx_chans = prop[0]; 553 554 prop = of_get_property(ofdev->dev.of_node, "num-rx-chans", NULL); 555 if (prop == NULL) { 556 printk(KERN_ERR 557 "mal%d: can't find MAL num-rx-chans property!\n", 558 index); 559 return -ENODEV; 560 } 561 mal->num_rx_chans = prop[0]; 562 563 dcr_base = dcr_resource_start(ofdev->dev.of_node, 0); 564 if (dcr_base == 0) { 565 printk(KERN_ERR 566 "mal%d: can't find DCR resource!\n", index); 567 return -ENODEV; 568 } 569 mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100); 570 if (!DCR_MAP_OK(mal->dcr_host)) { 571 printk(KERN_ERR 572 "mal%d: failed to map DCRs !\n", index); 573 return -ENODEV; 574 } 575 576 if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-405ez")) { 577 #if defined(CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT) && \ 578 defined(CONFIG_IBM_EMAC_MAL_COMMON_ERR) 579 mal->features |= (MAL_FTR_CLEAR_ICINTSTAT | 580 MAL_FTR_COMMON_ERR_INT); 581 #else 582 printk(KERN_ERR "%pOF: Support for 405EZ not enabled!\n", 583 ofdev->dev.of_node); 584 err = -ENODEV; 585 goto fail_unmap; 586 #endif 587 } 588 589 INIT_LIST_HEAD(&mal->poll_list); 590 INIT_LIST_HEAD(&mal->list); 591 spin_lock_init(&mal->lock); 592 593 mal->dummy_dev = alloc_netdev_dummy(0); 594 if (!mal->dummy_dev) { 595 err = -ENOMEM; 596 goto fail_unmap; 597 } 598 599 netif_napi_add_weight(mal->dummy_dev, &mal->napi, mal_poll, 600 CONFIG_IBM_EMAC_POLL_WEIGHT); 601 602 /* Load power-on reset defaults */ 603 mal_reset(mal); 604 605 /* Set the MAL configuration register */ 606 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT; 607 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA; 608 609 /* Current Axon is not happy with priority being non-0, it can 610 * deadlock, fix it up here 611 */ 612 if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-axon")) 613 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10); 614 615 /* Apply configuration */ 616 set_mal_dcrn(mal, MAL_CFG, cfg); 617 618 /* Allocate space for BD rings */ 619 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32); 620 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32); 621 622 bd_size = sizeof(struct mal_descriptor) * 623 (NUM_TX_BUFF * mal->num_tx_chans + 624 NUM_RX_BUFF * mal->num_rx_chans); 625 mal->bd_virt = dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma, 626 GFP_KERNEL); 627 if (mal->bd_virt == NULL) { 628 err = -ENOMEM; 629 goto fail_dummy; 630 } 631 632 for (i = 0; i < mal->num_tx_chans; ++i) 633 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma + 634 sizeof(struct mal_descriptor) * 635 mal_tx_bd_offset(mal, i)); 636 637 for (i = 0; i < mal->num_rx_chans; ++i) 638 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma + 639 sizeof(struct mal_descriptor) * 640 mal_rx_bd_offset(mal, i)); 641 642 mal->txeob_irq = platform_get_irq(ofdev, 0); 643 mal->rxeob_irq = platform_get_irq(ofdev, 1); 644 mal->serr_irq = platform_get_irq(ofdev, 2); 645 if (mal->txeob_irq < 0 || mal->rxeob_irq < 0 || mal->serr_irq < 0) { 646 err = mal->txeob_irq < 0 ? mal->txeob_irq : 647 mal->rxeob_irq < 0 ? mal->rxeob_irq : mal->serr_irq; 648 goto fail2; 649 } 650 651 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) { 652 mal->txde_irq = mal->rxde_irq = mal->serr_irq; 653 irqflags = IRQF_SHARED; 654 hdlr_serr = hdlr_txde = hdlr_rxde = mal_int; 655 } else { 656 mal->txde_irq = platform_get_irq(ofdev, 3); 657 mal->rxde_irq = platform_get_irq(ofdev, 4); 658 if (mal->txde_irq < 0 || mal->rxde_irq < 0) { 659 err = mal->txde_irq < 0 ? mal->txde_irq : mal->rxde_irq; 660 goto fail2; 661 } 662 irqflags = 0; 663 hdlr_serr = mal_serr; 664 hdlr_txde = mal_txde; 665 hdlr_rxde = mal_rxde; 666 } 667 668 err = devm_request_irq(&ofdev->dev, mal->serr_irq, hdlr_serr, irqflags, 669 "MAL SERR", mal); 670 if (err) 671 goto fail2; 672 err = devm_request_irq(&ofdev->dev, mal->txde_irq, hdlr_txde, irqflags, 673 "MAL TX DE", mal); 674 if (err) 675 goto fail2; 676 err = devm_request_irq(&ofdev->dev, mal->txeob_irq, mal_txeob, 0, 677 "MAL TX EOB", mal); 678 if (err) 679 goto fail2; 680 err = devm_request_irq(&ofdev->dev, mal->rxde_irq, hdlr_rxde, irqflags, 681 "MAL RX DE", mal); 682 if (err) 683 goto fail2; 684 err = devm_request_irq(&ofdev->dev, mal->rxeob_irq, mal_rxeob, 0, 685 "MAL RX EOB", mal); 686 if (err) 687 goto fail2; 688 689 /* Enable all MAL SERR interrupt sources */ 690 set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS); 691 692 /* Enable EOB interrupt */ 693 mal_enable_eob_irq(mal); 694 695 printk(KERN_INFO 696 "MAL v%d %pOF, %d TX channels, %d RX channels\n", 697 mal->version, ofdev->dev.of_node, 698 mal->num_tx_chans, mal->num_rx_chans); 699 700 /* Advertise this instance to the rest of the world */ 701 wmb(); 702 platform_set_drvdata(ofdev, mal); 703 704 return 0; 705 706 fail2: 707 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma); 708 fail_dummy: 709 free_netdev(mal->dummy_dev); 710 fail_unmap: 711 dcr_unmap(mal->dcr_host, 0x100); 712 return err; 713 } 714 715 static void mal_remove(struct platform_device *ofdev) 716 { 717 struct mal_instance *mal = platform_get_drvdata(ofdev); 718 719 MAL_DBG(mal, "remove" NL); 720 721 /* Synchronize with scheduled polling */ 722 if (!list_empty(&mal->list)) { 723 napi_disable(&mal->napi); 724 /* This is *very* bad */ 725 WARN(1, KERN_EMERG 726 "mal%d: commac list is not empty on remove!\n", 727 mal->index); 728 } 729 730 mal_reset(mal); 731 732 free_netdev(mal->dummy_dev); 733 734 dcr_unmap(mal->dcr_host, 0x100); 735 736 dma_free_coherent(&ofdev->dev, 737 sizeof(struct mal_descriptor) * 738 (NUM_TX_BUFF * mal->num_tx_chans + 739 NUM_RX_BUFF * mal->num_rx_chans), 740 mal->bd_virt, mal->bd_dma); 741 } 742 743 static const struct of_device_id mal_platform_match[] = 744 { 745 { 746 .compatible = "ibm,mcmal", 747 }, 748 { 749 .compatible = "ibm,mcmal2", 750 }, 751 /* Backward compat */ 752 { 753 .type = "mcmal-dma", 754 .compatible = "ibm,mcmal", 755 }, 756 { 757 .type = "mcmal-dma", 758 .compatible = "ibm,mcmal2", 759 }, 760 {}, 761 }; 762 763 static struct platform_driver mal_of_driver = { 764 .driver = { 765 .name = "mcmal", 766 .of_match_table = mal_platform_match, 767 }, 768 .probe = mal_probe, 769 .remove = mal_remove, 770 }; 771 772 int __init mal_init(void) 773 { 774 return platform_driver_register(&mal_of_driver); 775 } 776 777 void mal_exit(void) 778 { 779 platform_driver_unregister(&mal_of_driver); 780 } 781