1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/net/ethernet/ibm/emac/core.c 4 * 5 * Driver for PowerPC 4xx on-chip ethernet controller. 6 * 7 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 8 * <benh@kernel.crashing.org> 9 * 10 * Based on the arch/ppc version of the driver: 11 * 12 * Copyright (c) 2004, 2005 Zultys Technologies. 13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 14 * 15 * Based on original work by 16 * Matt Porter <mporter@kernel.crashing.org> 17 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> 18 * Armin Kuster <akuster@mvista.com> 19 * Johnnie Peters <jpeters@mvista.com> 20 */ 21 22 #include <linux/module.h> 23 #include <linux/sched.h> 24 #include <linux/string.h> 25 #include <linux/errno.h> 26 #include <linux/delay.h> 27 #include <linux/types.h> 28 #include <linux/pci.h> 29 #include <linux/etherdevice.h> 30 #include <linux/skbuff.h> 31 #include <linux/crc32.h> 32 #include <linux/ethtool.h> 33 #include <linux/if_vlan.h> 34 #include <linux/mii.h> 35 #include <linux/bitops.h> 36 #include <linux/of.h> 37 #include <linux/of_address.h> 38 #include <linux/of_irq.h> 39 #include <linux/of_net.h> 40 #include <linux/of_mdio.h> 41 #include <linux/of_platform.h> 42 #include <linux/platform_device.h> 43 #include <linux/slab.h> 44 45 #include <asm/processor.h> 46 #include <asm/io.h> 47 #include <asm/dma.h> 48 #include <linux/uaccess.h> 49 #include <asm/dcr.h> 50 #include <asm/dcr-regs.h> 51 52 #include "core.h" 53 54 /* 55 * Lack of dma_unmap_???? calls is intentional. 56 * 57 * API-correct usage requires additional support state information to be 58 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to 59 * EMAC design (e.g. TX buffer passed from network stack can be split into 60 * several BDs, dma_map_single/dma_map_page can be used to map particular BD), 61 * maintaining such information will add additional overhead. 62 * Current DMA API implementation for 4xx processors only ensures cache coherency 63 * and dma_unmap_???? routines are empty and are likely to stay this way. 64 * I decided to omit dma_unmap_??? calls because I don't want to add additional 65 * complexity just for the sake of following some abstract API, when it doesn't 66 * add any real benefit to the driver. I understand that this decision maybe 67 * controversial, but I really tried to make code API-correct and efficient 68 * at the same time and didn't come up with code I liked :(. --ebs 69 */ 70 71 #define DRV_NAME "emac" 72 #define DRV_VERSION "3.54" 73 #define DRV_DESC "PPC 4xx OCP EMAC driver" 74 75 MODULE_DESCRIPTION(DRV_DESC); 76 MODULE_AUTHOR 77 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>"); 78 MODULE_LICENSE("GPL"); 79 80 /* minimum number of free TX descriptors required to wake up TX process */ 81 #define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4) 82 83 /* If packet size is less than this number, we allocate small skb and copy packet 84 * contents into it instead of just sending original big skb up 85 */ 86 #define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD 87 88 /* Since multiple EMACs share MDIO lines in various ways, we need 89 * to avoid re-using the same PHY ID in cases where the arch didn't 90 * setup precise phy_map entries 91 * 92 * XXX This is something that needs to be reworked as we can have multiple 93 * EMAC "sets" (multiple ASICs containing several EMACs) though we can 94 * probably require in that case to have explicit PHY IDs in the device-tree 95 */ 96 static u32 busy_phy_map; 97 static DEFINE_MUTEX(emac_phy_map_lock); 98 99 /* Having stable interface names is a doomed idea. However, it would be nice 100 * if we didn't have completely random interface names at boot too :-) It's 101 * just a matter of making everybody's life easier. Since we are doing 102 * threaded probing, it's a bit harder though. The base idea here is that 103 * we make up a list of all emacs in the device-tree before we register the 104 * driver. Every emac will then wait for the previous one in the list to 105 * initialize before itself. We should also keep that list ordered by 106 * cell_index. 107 * That list is only 4 entries long, meaning that additional EMACs don't 108 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased. 109 */ 110 111 #define EMAC_BOOT_LIST_SIZE 4 112 static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE]; 113 114 /* I don't want to litter system log with timeout errors 115 * when we have brain-damaged PHY. 116 */ 117 static inline void emac_report_timeout_error(struct emac_instance *dev, 118 const char *error) 119 { 120 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX | 121 EMAC_FTR_460EX_PHY_CLK_FIX | 122 EMAC_FTR_440EP_PHY_CLK_FIX)) 123 DBG(dev, "%s" NL, error); 124 else if (net_ratelimit()) 125 printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error); 126 } 127 128 /* EMAC PHY clock workaround: 129 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, 130 * which allows controlling each EMAC clock 131 */ 132 static inline void emac_rx_clk_tx(struct emac_instance *dev) 133 { 134 #ifdef CONFIG_PPC_DCR_NATIVE 135 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX)) 136 dcri_clrset(SDR0, SDR0_MFR, 137 0, SDR0_MFR_ECS >> dev->cell_index); 138 #endif 139 } 140 141 static inline void emac_rx_clk_default(struct emac_instance *dev) 142 { 143 #ifdef CONFIG_PPC_DCR_NATIVE 144 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX)) 145 dcri_clrset(SDR0, SDR0_MFR, 146 SDR0_MFR_ECS >> dev->cell_index, 0); 147 #endif 148 } 149 150 /* PHY polling intervals */ 151 #define PHY_POLL_LINK_ON HZ 152 #define PHY_POLL_LINK_OFF (HZ / 5) 153 154 /* Graceful stop timeouts in us. 155 * We should allow up to 1 frame time (full-duplex, ignoring collisions) 156 */ 157 #define STOP_TIMEOUT_10 1230 158 #define STOP_TIMEOUT_100 124 159 #define STOP_TIMEOUT_1000 13 160 #define STOP_TIMEOUT_1000_JUMBO 73 161 162 static unsigned char default_mcast_addr[] = { 163 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01 164 }; 165 166 /* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */ 167 static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = { 168 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum", 169 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom", 170 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu", 171 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet", 172 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error", 173 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range", 174 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun", 175 "rx_bad_packet", "rx_runt_packet", "rx_short_event", 176 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long", 177 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors", 178 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral", 179 "tx_bd_excessive_collisions", "tx_bd_late_collision", 180 "tx_bd_multple_collisions", "tx_bd_single_collision", 181 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe", 182 "tx_errors" 183 }; 184 185 static irqreturn_t emac_irq(int irq, void *dev_instance); 186 static void emac_clean_tx_ring(struct emac_instance *dev); 187 static void __emac_set_multicast_list(struct emac_instance *dev); 188 189 static inline int emac_phy_supports_gige(int phy_mode) 190 { 191 return phy_interface_mode_is_rgmii(phy_mode) || 192 phy_mode == PHY_INTERFACE_MODE_GMII || 193 phy_mode == PHY_INTERFACE_MODE_SGMII || 194 phy_mode == PHY_INTERFACE_MODE_TBI || 195 phy_mode == PHY_INTERFACE_MODE_RTBI; 196 } 197 198 static inline int emac_phy_gpcs(int phy_mode) 199 { 200 return phy_mode == PHY_INTERFACE_MODE_SGMII || 201 phy_mode == PHY_INTERFACE_MODE_TBI || 202 phy_mode == PHY_INTERFACE_MODE_RTBI; 203 } 204 205 static inline void emac_tx_enable(struct emac_instance *dev) 206 { 207 struct emac_regs __iomem *p = dev->emacp; 208 u32 r; 209 210 DBG(dev, "tx_enable" NL); 211 212 r = in_be32(&p->mr0); 213 if (!(r & EMAC_MR0_TXE)) 214 out_be32(&p->mr0, r | EMAC_MR0_TXE); 215 } 216 217 static void emac_tx_disable(struct emac_instance *dev) 218 { 219 struct emac_regs __iomem *p = dev->emacp; 220 u32 r; 221 222 DBG(dev, "tx_disable" NL); 223 224 r = in_be32(&p->mr0); 225 if (r & EMAC_MR0_TXE) { 226 int n = dev->stop_timeout; 227 out_be32(&p->mr0, r & ~EMAC_MR0_TXE); 228 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) { 229 udelay(1); 230 --n; 231 } 232 if (unlikely(!n)) 233 emac_report_timeout_error(dev, "TX disable timeout"); 234 } 235 } 236 237 static void emac_rx_enable(struct emac_instance *dev) 238 { 239 struct emac_regs __iomem *p = dev->emacp; 240 u32 r; 241 242 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) 243 goto out; 244 245 DBG(dev, "rx_enable" NL); 246 247 r = in_be32(&p->mr0); 248 if (!(r & EMAC_MR0_RXE)) { 249 if (unlikely(!(r & EMAC_MR0_RXI))) { 250 /* Wait if previous async disable is still in progress */ 251 int n = dev->stop_timeout; 252 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) { 253 udelay(1); 254 --n; 255 } 256 if (unlikely(!n)) 257 emac_report_timeout_error(dev, 258 "RX disable timeout"); 259 } 260 out_be32(&p->mr0, r | EMAC_MR0_RXE); 261 } 262 out: 263 ; 264 } 265 266 static void emac_rx_disable(struct emac_instance *dev) 267 { 268 struct emac_regs __iomem *p = dev->emacp; 269 u32 r; 270 271 DBG(dev, "rx_disable" NL); 272 273 r = in_be32(&p->mr0); 274 if (r & EMAC_MR0_RXE) { 275 int n = dev->stop_timeout; 276 out_be32(&p->mr0, r & ~EMAC_MR0_RXE); 277 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) { 278 udelay(1); 279 --n; 280 } 281 if (unlikely(!n)) 282 emac_report_timeout_error(dev, "RX disable timeout"); 283 } 284 } 285 286 static inline void emac_netif_stop(struct emac_instance *dev) 287 { 288 netif_tx_lock_bh(dev->ndev); 289 netif_addr_lock(dev->ndev); 290 dev->no_mcast = 1; 291 netif_addr_unlock(dev->ndev); 292 netif_tx_unlock_bh(dev->ndev); 293 netif_trans_update(dev->ndev); /* prevent tx timeout */ 294 mal_poll_disable(dev->mal, &dev->commac); 295 netif_tx_disable(dev->ndev); 296 } 297 298 static inline void emac_netif_start(struct emac_instance *dev) 299 { 300 netif_tx_lock_bh(dev->ndev); 301 netif_addr_lock(dev->ndev); 302 dev->no_mcast = 0; 303 if (dev->mcast_pending && netif_running(dev->ndev)) 304 __emac_set_multicast_list(dev); 305 netif_addr_unlock(dev->ndev); 306 netif_tx_unlock_bh(dev->ndev); 307 308 netif_wake_queue(dev->ndev); 309 310 /* NOTE: unconditional netif_wake_queue is only appropriate 311 * so long as all callers are assured to have free tx slots 312 * (taken from tg3... though the case where that is wrong is 313 * not terribly harmful) 314 */ 315 mal_poll_enable(dev->mal, &dev->commac); 316 } 317 318 static inline void emac_rx_disable_async(struct emac_instance *dev) 319 { 320 struct emac_regs __iomem *p = dev->emacp; 321 u32 r; 322 323 DBG(dev, "rx_disable_async" NL); 324 325 r = in_be32(&p->mr0); 326 if (r & EMAC_MR0_RXE) 327 out_be32(&p->mr0, r & ~EMAC_MR0_RXE); 328 } 329 330 static int emac_reset(struct emac_instance *dev) 331 { 332 struct emac_regs __iomem *p = dev->emacp; 333 int n = 20; 334 bool __maybe_unused try_internal_clock = false; 335 336 DBG(dev, "reset" NL); 337 338 if (!dev->reset_failed) { 339 /* 40x erratum suggests stopping RX channel before reset, 340 * we stop TX as well 341 */ 342 emac_rx_disable(dev); 343 emac_tx_disable(dev); 344 } 345 346 #ifdef CONFIG_PPC_DCR_NATIVE 347 do_retry: 348 /* 349 * PPC460EX/GT Embedded Processor Advanced User's Manual 350 * section 28.10.1 Mode Register 0 (EMACx_MR0) states: 351 * Note: The PHY must provide a TX Clk in order to perform a soft reset 352 * of the EMAC. If none is present, select the internal clock 353 * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1). 354 * After a soft reset, select the external clock. 355 * 356 * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the 357 * ethernet cable is not attached. This causes the reset to timeout 358 * and the PHY detection code in emac_init_phy() is unable to 359 * communicate and detect the AR8035-A PHY. As a result, the emac 360 * driver bails out early and the user has no ethernet. 361 * In order to stay compatible with existing configurations, the 362 * driver will temporarily switch to the internal clock, after 363 * the first reset fails. 364 */ 365 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { 366 if (try_internal_clock || (dev->phy_address == 0xffffffff && 367 dev->phy_map == 0xffffffff)) { 368 /* No PHY: select internal loop clock before reset */ 369 dcri_clrset(SDR0, SDR0_ETH_CFG, 370 0, SDR0_ETH_CFG_ECS << dev->cell_index); 371 } else { 372 /* PHY present: select external clock before reset */ 373 dcri_clrset(SDR0, SDR0_ETH_CFG, 374 SDR0_ETH_CFG_ECS << dev->cell_index, 0); 375 } 376 } 377 #endif 378 379 out_be32(&p->mr0, EMAC_MR0_SRST); 380 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n) 381 --n; 382 383 #ifdef CONFIG_PPC_DCR_NATIVE 384 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { 385 if (!n && !try_internal_clock) { 386 /* first attempt has timed out. */ 387 n = 20; 388 try_internal_clock = true; 389 goto do_retry; 390 } 391 392 if (try_internal_clock || (dev->phy_address == 0xffffffff && 393 dev->phy_map == 0xffffffff)) { 394 /* No PHY: restore external clock source after reset */ 395 dcri_clrset(SDR0, SDR0_ETH_CFG, 396 SDR0_ETH_CFG_ECS << dev->cell_index, 0); 397 } 398 } 399 #endif 400 401 if (n) { 402 dev->reset_failed = 0; 403 return 0; 404 } else { 405 emac_report_timeout_error(dev, "reset timeout"); 406 dev->reset_failed = 1; 407 return -ETIMEDOUT; 408 } 409 } 410 411 static void emac_hash_mc(struct emac_instance *dev) 412 { 413 u32 __iomem *gaht_base = emac_gaht_base(dev); 414 const int regs = EMAC_XAHT_REGS(dev); 415 u32 gaht_temp[EMAC_XAHT_MAX_REGS]; 416 struct netdev_hw_addr *ha; 417 int i; 418 419 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev)); 420 421 memset(gaht_temp, 0, sizeof (gaht_temp)); 422 423 netdev_for_each_mc_addr(ha, dev->ndev) { 424 int slot, reg, mask; 425 DBG2(dev, "mc %pM" NL, ha->addr); 426 427 slot = EMAC_XAHT_CRC_TO_SLOT(dev, 428 ether_crc(ETH_ALEN, ha->addr)); 429 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot); 430 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot); 431 432 gaht_temp[reg] |= mask; 433 } 434 435 for (i = 0; i < regs; i++) 436 out_be32(gaht_base + i, gaht_temp[i]); 437 } 438 439 static inline u32 emac_iff2rmr(struct net_device *ndev) 440 { 441 struct emac_instance *dev = netdev_priv(ndev); 442 u32 r; 443 444 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE; 445 446 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 447 r |= EMAC4_RMR_BASE; 448 else 449 r |= EMAC_RMR_BASE; 450 451 if (ndev->flags & IFF_PROMISC) 452 r |= EMAC_RMR_PME; 453 else if (ndev->flags & IFF_ALLMULTI || 454 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev))) 455 r |= EMAC_RMR_PMME; 456 else if (!netdev_mc_empty(ndev)) 457 r |= EMAC_RMR_MAE; 458 459 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) { 460 r &= ~EMAC4_RMR_MJS_MASK; 461 r |= EMAC4_RMR_MJS(ndev->mtu + VLAN_HLEN); 462 } 463 464 return r; 465 } 466 467 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 468 { 469 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT; 470 471 DBG2(dev, "__emac_calc_base_mr1" NL); 472 473 switch(tx_size) { 474 case 2048: 475 ret |= EMAC_MR1_TFS_2K; 476 break; 477 default: 478 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n", 479 dev->ndev->name, tx_size); 480 } 481 482 switch(rx_size) { 483 case 16384: 484 ret |= EMAC_MR1_RFS_16K; 485 break; 486 case 4096: 487 ret |= EMAC_MR1_RFS_4K; 488 break; 489 default: 490 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n", 491 dev->ndev->name, rx_size); 492 } 493 494 return ret; 495 } 496 497 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 498 { 499 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR | 500 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000); 501 502 DBG2(dev, "__emac4_calc_base_mr1" NL); 503 504 switch(tx_size) { 505 case 16384: 506 ret |= EMAC4_MR1_TFS_16K; 507 break; 508 case 8192: 509 ret |= EMAC4_MR1_TFS_8K; 510 break; 511 case 4096: 512 ret |= EMAC4_MR1_TFS_4K; 513 break; 514 case 2048: 515 ret |= EMAC4_MR1_TFS_2K; 516 break; 517 default: 518 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n", 519 dev->ndev->name, tx_size); 520 } 521 522 switch(rx_size) { 523 case 16384: 524 ret |= EMAC4_MR1_RFS_16K; 525 break; 526 case 8192: 527 ret |= EMAC4_MR1_RFS_8K; 528 break; 529 case 4096: 530 ret |= EMAC4_MR1_RFS_4K; 531 break; 532 case 2048: 533 ret |= EMAC4_MR1_RFS_2K; 534 break; 535 default: 536 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n", 537 dev->ndev->name, rx_size); 538 } 539 540 return ret; 541 } 542 543 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 544 { 545 return emac_has_feature(dev, EMAC_FTR_EMAC4) ? 546 __emac4_calc_base_mr1(dev, tx_size, rx_size) : 547 __emac_calc_base_mr1(dev, tx_size, rx_size); 548 } 549 550 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size) 551 { 552 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 553 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4; 554 else 555 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT; 556 } 557 558 static inline u32 emac_calc_rwmr(struct emac_instance *dev, 559 unsigned int low, unsigned int high) 560 { 561 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 562 return (low << 22) | ( (high & 0x3ff) << 6); 563 else 564 return (low << 23) | ( (high & 0x1ff) << 7); 565 } 566 567 static int emac_configure(struct emac_instance *dev) 568 { 569 struct emac_regs __iomem *p = dev->emacp; 570 struct net_device *ndev = dev->ndev; 571 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev); 572 u32 r, mr1 = 0; 573 574 DBG(dev, "configure" NL); 575 576 if (!link) { 577 out_be32(&p->mr1, in_be32(&p->mr1) 578 | EMAC_MR1_FDE | EMAC_MR1_ILE); 579 udelay(100); 580 } else if (emac_reset(dev) < 0) 581 return -ETIMEDOUT; 582 583 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 584 tah_reset(dev->tah_dev); 585 586 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n", 587 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause); 588 589 /* Default fifo sizes */ 590 tx_size = dev->tx_fifo_size; 591 rx_size = dev->rx_fifo_size; 592 593 /* No link, force loopback */ 594 if (!link) 595 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE; 596 597 /* Check for full duplex */ 598 else if (dev->phy.duplex == DUPLEX_FULL) 599 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001; 600 601 /* Adjust fifo sizes, mr1 and timeouts based on link speed */ 602 dev->stop_timeout = STOP_TIMEOUT_10; 603 switch (dev->phy.speed) { 604 case SPEED_1000: 605 if (emac_phy_gpcs(dev->phy.mode)) { 606 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA( 607 (dev->phy.gpcs_address != 0xffffffff) ? 608 dev->phy.gpcs_address : dev->phy.address); 609 610 /* Put some arbitrary OUI, Manuf & Rev IDs so we can 611 * identify this GPCS PHY later. 612 */ 613 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef); 614 } else 615 mr1 |= EMAC_MR1_MF_1000; 616 617 /* Extended fifo sizes */ 618 tx_size = dev->tx_fifo_size_gige; 619 rx_size = dev->rx_fifo_size_gige; 620 621 if (dev->ndev->mtu > ETH_DATA_LEN) { 622 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 623 mr1 |= EMAC4_MR1_JPSM; 624 else 625 mr1 |= EMAC_MR1_JPSM; 626 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO; 627 } else 628 dev->stop_timeout = STOP_TIMEOUT_1000; 629 break; 630 case SPEED_100: 631 mr1 |= EMAC_MR1_MF_100; 632 dev->stop_timeout = STOP_TIMEOUT_100; 633 break; 634 default: /* make gcc happy */ 635 break; 636 } 637 638 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 639 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port, 640 dev->phy.speed); 641 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 642 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed); 643 644 /* on 40x erratum forces us to NOT use integrated flow control, 645 * let's hope it works on 44x ;) 646 */ 647 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) && 648 dev->phy.duplex == DUPLEX_FULL) { 649 if (dev->phy.pause) 650 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP; 651 else if (dev->phy.asym_pause) 652 mr1 |= EMAC_MR1_APP; 653 } 654 655 /* Add base settings & fifo sizes & program MR1 */ 656 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size); 657 out_be32(&p->mr1, mr1); 658 659 /* Set individual MAC address */ 660 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]); 661 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) | 662 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) | 663 ndev->dev_addr[5]); 664 665 /* VLAN Tag Protocol ID */ 666 out_be32(&p->vtpid, 0x8100); 667 668 /* Receive mode register */ 669 r = emac_iff2rmr(ndev); 670 if (r & EMAC_RMR_MAE) 671 emac_hash_mc(dev); 672 out_be32(&p->rmr, r); 673 674 /* FIFOs thresholds */ 675 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 676 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1, 677 tx_size / 2 / dev->fifo_entry_size); 678 else 679 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1, 680 tx_size / 2 / dev->fifo_entry_size); 681 out_be32(&p->tmr1, r); 682 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2)); 683 684 /* PAUSE frame is sent when RX FIFO reaches its high-water mark, 685 there should be still enough space in FIFO to allow the our link 686 partner time to process this frame and also time to send PAUSE 687 frame itself. 688 689 Here is the worst case scenario for the RX FIFO "headroom" 690 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap): 691 692 1) One maximum-length frame on TX 1522 bytes 693 2) One PAUSE frame time 64 bytes 694 3) PAUSE frame decode time allowance 64 bytes 695 4) One maximum-length frame on RX 1522 bytes 696 5) Round-trip propagation delay of the link (100Mb) 15 bytes 697 ---------- 698 3187 bytes 699 700 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes) 701 low-water mark to RX_FIFO_SIZE / 8 (512 bytes) 702 */ 703 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size, 704 rx_size / 4 / dev->fifo_entry_size); 705 out_be32(&p->rwmr, r); 706 707 /* Set PAUSE timer to the maximum */ 708 out_be32(&p->ptr, 0xffff); 709 710 /* IRQ sources */ 711 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE | 712 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE | 713 EMAC_ISR_IRE | EMAC_ISR_TE; 714 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 715 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE | 716 EMAC4_ISR_RXOE | */; 717 out_be32(&p->iser, r); 718 719 /* We need to take GPCS PHY out of isolate mode after EMAC reset */ 720 if (emac_phy_gpcs(dev->phy.mode)) { 721 if (dev->phy.gpcs_address != 0xffffffff) 722 emac_mii_reset_gpcs(&dev->phy); 723 else 724 emac_mii_reset_phy(&dev->phy); 725 } 726 727 return 0; 728 } 729 730 static void emac_reinitialize(struct emac_instance *dev) 731 { 732 DBG(dev, "reinitialize" NL); 733 734 emac_netif_stop(dev); 735 if (!emac_configure(dev)) { 736 emac_tx_enable(dev); 737 emac_rx_enable(dev); 738 } 739 emac_netif_start(dev); 740 } 741 742 static void emac_full_tx_reset(struct emac_instance *dev) 743 { 744 DBG(dev, "full_tx_reset" NL); 745 746 emac_tx_disable(dev); 747 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan); 748 emac_clean_tx_ring(dev); 749 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0; 750 751 emac_configure(dev); 752 753 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan); 754 emac_tx_enable(dev); 755 emac_rx_enable(dev); 756 } 757 758 static void emac_reset_work(struct work_struct *work) 759 { 760 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work); 761 762 DBG(dev, "reset_work" NL); 763 764 mutex_lock(&dev->link_lock); 765 if (dev->opened) { 766 emac_netif_stop(dev); 767 emac_full_tx_reset(dev); 768 emac_netif_start(dev); 769 } 770 mutex_unlock(&dev->link_lock); 771 } 772 773 static void emac_tx_timeout(struct net_device *ndev, unsigned int txqueue) 774 { 775 struct emac_instance *dev = netdev_priv(ndev); 776 777 DBG(dev, "tx_timeout" NL); 778 779 schedule_work(&dev->reset_work); 780 } 781 782 783 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr) 784 { 785 int done = !!(stacr & EMAC_STACR_OC); 786 787 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 788 done = !done; 789 790 return done; 791 }; 792 793 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg) 794 { 795 struct emac_regs __iomem *p = dev->emacp; 796 u32 r = 0; 797 int n, err = -ETIMEDOUT; 798 799 mutex_lock(&dev->mdio_lock); 800 801 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg); 802 803 /* Enable proper MDIO port */ 804 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 805 zmii_get_mdio(dev->zmii_dev, dev->zmii_port); 806 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 807 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port); 808 809 /* Wait for management interface to become idle */ 810 n = 20; 811 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 812 udelay(1); 813 if (!--n) { 814 DBG2(dev, " -> timeout wait idle\n"); 815 goto bail; 816 } 817 } 818 819 /* Issue read command */ 820 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 821 r = EMAC4_STACR_BASE(dev->opb_bus_freq); 822 else 823 r = EMAC_STACR_BASE(dev->opb_bus_freq); 824 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 825 r |= EMAC_STACR_OC; 826 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR)) 827 r |= EMACX_STACR_STAC_READ; 828 else 829 r |= EMAC_STACR_STAC_READ; 830 r |= (reg & EMAC_STACR_PRA_MASK) 831 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT); 832 out_be32(&p->stacr, r); 833 834 /* Wait for read to complete */ 835 n = 200; 836 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) { 837 udelay(1); 838 if (!--n) { 839 DBG2(dev, " -> timeout wait complete\n"); 840 goto bail; 841 } 842 } 843 844 if (unlikely(r & EMAC_STACR_PHYE)) { 845 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg); 846 err = -EREMOTEIO; 847 goto bail; 848 } 849 850 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK); 851 852 DBG2(dev, "mdio_read -> %04x" NL, r); 853 err = 0; 854 bail: 855 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 856 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port); 857 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 858 zmii_put_mdio(dev->zmii_dev, dev->zmii_port); 859 mutex_unlock(&dev->mdio_lock); 860 861 return err == 0 ? r : err; 862 } 863 864 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg, 865 u16 val) 866 { 867 struct emac_regs __iomem *p = dev->emacp; 868 u32 r = 0; 869 int n; 870 871 mutex_lock(&dev->mdio_lock); 872 873 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val); 874 875 /* Enable proper MDIO port */ 876 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 877 zmii_get_mdio(dev->zmii_dev, dev->zmii_port); 878 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 879 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port); 880 881 /* Wait for management interface to be idle */ 882 n = 20; 883 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 884 udelay(1); 885 if (!--n) { 886 DBG2(dev, " -> timeout wait idle\n"); 887 goto bail; 888 } 889 } 890 891 /* Issue write command */ 892 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 893 r = EMAC4_STACR_BASE(dev->opb_bus_freq); 894 else 895 r = EMAC_STACR_BASE(dev->opb_bus_freq); 896 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 897 r |= EMAC_STACR_OC; 898 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR)) 899 r |= EMACX_STACR_STAC_WRITE; 900 else 901 r |= EMAC_STACR_STAC_WRITE; 902 r |= (reg & EMAC_STACR_PRA_MASK) | 903 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) | 904 (val << EMAC_STACR_PHYD_SHIFT); 905 out_be32(&p->stacr, r); 906 907 /* Wait for write to complete */ 908 n = 200; 909 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 910 udelay(1); 911 if (!--n) { 912 DBG2(dev, " -> timeout wait complete\n"); 913 goto bail; 914 } 915 } 916 bail: 917 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 918 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port); 919 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 920 zmii_put_mdio(dev->zmii_dev, dev->zmii_port); 921 mutex_unlock(&dev->mdio_lock); 922 } 923 924 static int emac_mdio_read(struct net_device *ndev, int id, int reg) 925 { 926 struct emac_instance *dev = netdev_priv(ndev); 927 int res; 928 929 res = __emac_mdio_read((dev->mdio_instance && 930 dev->phy.gpcs_address != id) ? 931 dev->mdio_instance : dev, 932 (u8) id, (u8) reg); 933 return res; 934 } 935 936 static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val) 937 { 938 struct emac_instance *dev = netdev_priv(ndev); 939 940 __emac_mdio_write((dev->mdio_instance && 941 dev->phy.gpcs_address != id) ? 942 dev->mdio_instance : dev, 943 (u8) id, (u8) reg, (u16) val); 944 } 945 946 /* Tx lock BH */ 947 static void __emac_set_multicast_list(struct emac_instance *dev) 948 { 949 struct emac_regs __iomem *p = dev->emacp; 950 u32 rmr = emac_iff2rmr(dev->ndev); 951 952 DBG(dev, "__multicast %08x" NL, rmr); 953 954 /* I decided to relax register access rules here to avoid 955 * full EMAC reset. 956 * 957 * There is a real problem with EMAC4 core if we use MWSW_001 bit 958 * in MR1 register and do a full EMAC reset. 959 * One TX BD status update is delayed and, after EMAC reset, it 960 * never happens, resulting in TX hung (it'll be recovered by TX 961 * timeout handler eventually, but this is just gross). 962 * So we either have to do full TX reset or try to cheat here :) 963 * 964 * The only required change is to RX mode register, so I *think* all 965 * we need is just to stop RX channel. This seems to work on all 966 * tested SoCs. --ebs 967 * 968 */ 969 dev->mcast_pending = 0; 970 emac_rx_disable(dev); 971 if (rmr & EMAC_RMR_MAE) 972 emac_hash_mc(dev); 973 out_be32(&p->rmr, rmr); 974 emac_rx_enable(dev); 975 } 976 977 /* Tx lock BH */ 978 static void emac_set_multicast_list(struct net_device *ndev) 979 { 980 struct emac_instance *dev = netdev_priv(ndev); 981 982 DBG(dev, "multicast" NL); 983 984 BUG_ON(!netif_running(dev->ndev)); 985 986 if (dev->no_mcast) { 987 dev->mcast_pending = 1; 988 return; 989 } 990 991 mutex_lock(&dev->link_lock); 992 __emac_set_multicast_list(dev); 993 mutex_unlock(&dev->link_lock); 994 } 995 996 static int emac_set_mac_address(struct net_device *ndev, void *sa) 997 { 998 struct emac_instance *dev = netdev_priv(ndev); 999 struct sockaddr *addr = sa; 1000 struct emac_regs __iomem *p = dev->emacp; 1001 1002 if (!is_valid_ether_addr(addr->sa_data)) 1003 return -EADDRNOTAVAIL; 1004 1005 mutex_lock(&dev->link_lock); 1006 1007 eth_hw_addr_set(ndev, addr->sa_data); 1008 1009 emac_rx_disable(dev); 1010 emac_tx_disable(dev); 1011 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]); 1012 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) | 1013 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) | 1014 ndev->dev_addr[5]); 1015 emac_tx_enable(dev); 1016 emac_rx_enable(dev); 1017 1018 mutex_unlock(&dev->link_lock); 1019 1020 return 0; 1021 } 1022 1023 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu) 1024 { 1025 int rx_sync_size = emac_rx_sync_size(new_mtu); 1026 int rx_skb_size = emac_rx_skb_size(new_mtu); 1027 int i, ret = 0; 1028 int mr1_jumbo_bit_change = 0; 1029 1030 mutex_lock(&dev->link_lock); 1031 emac_netif_stop(dev); 1032 emac_rx_disable(dev); 1033 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan); 1034 1035 if (dev->rx_sg_skb) { 1036 ++dev->estats.rx_dropped_resize; 1037 dev_kfree_skb(dev->rx_sg_skb); 1038 dev->rx_sg_skb = NULL; 1039 } 1040 1041 /* Make a first pass over RX ring and mark BDs ready, dropping 1042 * non-processed packets on the way. We need this as a separate pass 1043 * to simplify error recovery in the case of allocation failure later. 1044 */ 1045 for (i = 0; i < NUM_RX_BUFF; ++i) { 1046 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST) 1047 ++dev->estats.rx_dropped_resize; 1048 1049 dev->rx_desc[i].data_len = 0; 1050 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY | 1051 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1052 } 1053 1054 /* Reallocate RX ring only if bigger skb buffers are required */ 1055 if (rx_skb_size <= dev->rx_skb_size) 1056 goto skip; 1057 1058 /* Second pass, allocate new skbs */ 1059 for (i = 0; i < NUM_RX_BUFF; ++i) { 1060 struct sk_buff *skb; 1061 1062 skb = netdev_alloc_skb_ip_align(dev->ndev, rx_skb_size); 1063 if (!skb) { 1064 ret = -ENOMEM; 1065 goto oom; 1066 } 1067 1068 BUG_ON(!dev->rx_skb[i]); 1069 dev_kfree_skb(dev->rx_skb[i]); 1070 1071 dev->rx_desc[i].data_ptr = 1072 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN, 1073 rx_sync_size, DMA_FROM_DEVICE) 1074 + NET_IP_ALIGN; 1075 dev->rx_skb[i] = skb; 1076 } 1077 skip: 1078 /* Check if we need to change "Jumbo" bit in MR1 */ 1079 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) { 1080 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) || 1081 (dev->ndev->mtu > ETH_DATA_LEN); 1082 } else { 1083 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^ 1084 (dev->ndev->mtu > ETH_DATA_LEN); 1085 } 1086 1087 if (mr1_jumbo_bit_change) { 1088 /* This is to prevent starting RX channel in emac_rx_enable() */ 1089 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1090 1091 WRITE_ONCE(dev->ndev->mtu, new_mtu); 1092 emac_full_tx_reset(dev); 1093 } 1094 1095 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu)); 1096 oom: 1097 /* Restart RX */ 1098 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1099 dev->rx_slot = 0; 1100 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1101 emac_rx_enable(dev); 1102 emac_netif_start(dev); 1103 mutex_unlock(&dev->link_lock); 1104 1105 return ret; 1106 } 1107 1108 /* Process ctx, rtnl_lock semaphore */ 1109 static int emac_change_mtu(struct net_device *ndev, int new_mtu) 1110 { 1111 struct emac_instance *dev = netdev_priv(ndev); 1112 int ret = 0; 1113 1114 DBG(dev, "change_mtu(%d)" NL, new_mtu); 1115 1116 if (netif_running(ndev)) { 1117 /* Check if we really need to reinitialize RX ring */ 1118 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu)) 1119 ret = emac_resize_rx_ring(dev, new_mtu); 1120 } 1121 1122 if (!ret) { 1123 WRITE_ONCE(ndev->mtu, new_mtu); 1124 dev->rx_skb_size = emac_rx_skb_size(new_mtu); 1125 dev->rx_sync_size = emac_rx_sync_size(new_mtu); 1126 } 1127 1128 return ret; 1129 } 1130 1131 static void emac_clean_tx_ring(struct emac_instance *dev) 1132 { 1133 int i; 1134 1135 for (i = 0; i < NUM_TX_BUFF; ++i) { 1136 if (dev->tx_skb[i]) { 1137 dev_kfree_skb(dev->tx_skb[i]); 1138 dev->tx_skb[i] = NULL; 1139 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY) 1140 ++dev->estats.tx_dropped; 1141 } 1142 dev->tx_desc[i].ctrl = 0; 1143 dev->tx_desc[i].data_ptr = 0; 1144 } 1145 } 1146 1147 static void emac_clean_rx_ring(struct emac_instance *dev) 1148 { 1149 int i; 1150 1151 for (i = 0; i < NUM_RX_BUFF; ++i) 1152 if (dev->rx_skb[i]) { 1153 dev->rx_desc[i].ctrl = 0; 1154 dev_kfree_skb(dev->rx_skb[i]); 1155 dev->rx_skb[i] = NULL; 1156 dev->rx_desc[i].data_ptr = 0; 1157 } 1158 1159 if (dev->rx_sg_skb) { 1160 dev_kfree_skb(dev->rx_sg_skb); 1161 dev->rx_sg_skb = NULL; 1162 } 1163 } 1164 1165 static void emac_clear_mal_desc(struct mal_descriptor *desc, int count) 1166 { 1167 int i; 1168 1169 for (i = 0; i < count; i++) { 1170 WRITE_ONCE(desc[i].ctrl, 0); 1171 WRITE_ONCE(desc[i].data_len, 0); 1172 WRITE_ONCE(desc[i].data_ptr, 0); 1173 } 1174 } 1175 1176 static int 1177 __emac_prepare_rx_skb(struct sk_buff *skb, struct emac_instance *dev, int slot) 1178 { 1179 if (unlikely(!skb)) 1180 return -ENOMEM; 1181 1182 dev->rx_skb[slot] = skb; 1183 dev->rx_desc[slot].data_len = 0; 1184 1185 dev->rx_desc[slot].data_ptr = 1186 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN, 1187 dev->rx_sync_size, DMA_FROM_DEVICE) + NET_IP_ALIGN; 1188 wmb(); 1189 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY | 1190 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1191 1192 return 0; 1193 } 1194 1195 static int 1196 emac_alloc_rx_skb(struct emac_instance *dev, int slot) 1197 { 1198 struct sk_buff *skb; 1199 1200 skb = __netdev_alloc_skb_ip_align(dev->ndev, dev->rx_skb_size, 1201 GFP_KERNEL); 1202 1203 return __emac_prepare_rx_skb(skb, dev, slot); 1204 } 1205 1206 static int 1207 emac_alloc_rx_skb_napi(struct emac_instance *dev, int slot) 1208 { 1209 struct sk_buff *skb; 1210 1211 skb = napi_alloc_skb(&dev->mal->napi, dev->rx_skb_size); 1212 1213 return __emac_prepare_rx_skb(skb, dev, slot); 1214 } 1215 1216 static void emac_print_link_status(struct emac_instance *dev) 1217 { 1218 if (netif_carrier_ok(dev->ndev)) 1219 printk(KERN_INFO "%s: link is up, %d %s%s\n", 1220 dev->ndev->name, dev->phy.speed, 1221 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX", 1222 dev->phy.pause ? ", pause enabled" : 1223 dev->phy.asym_pause ? ", asymmetric pause enabled" : ""); 1224 else 1225 printk(KERN_INFO "%s: link is down\n", dev->ndev->name); 1226 } 1227 1228 /* Process ctx, rtnl_lock semaphore */ 1229 static int emac_open(struct net_device *ndev) 1230 { 1231 struct emac_instance *dev = netdev_priv(ndev); 1232 int i; 1233 1234 DBG(dev, "open" NL); 1235 1236 /* Allocate RX ring */ 1237 for (i = 0; i < NUM_RX_BUFF; ++i) 1238 if (emac_alloc_rx_skb(dev, i)) { 1239 printk(KERN_ERR "%s: failed to allocate RX ring\n", 1240 ndev->name); 1241 goto oom; 1242 } 1243 1244 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0; 1245 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1246 dev->rx_sg_skb = NULL; 1247 1248 mutex_lock(&dev->link_lock); 1249 dev->opened = 1; 1250 1251 /* Start PHY polling now. 1252 */ 1253 if (dev->phy.address >= 0) { 1254 int link_poll_interval; 1255 if (dev->phy.def->ops->poll_link(&dev->phy)) { 1256 dev->phy.def->ops->read_link(&dev->phy); 1257 emac_rx_clk_default(dev); 1258 netif_carrier_on(dev->ndev); 1259 link_poll_interval = PHY_POLL_LINK_ON; 1260 } else { 1261 emac_rx_clk_tx(dev); 1262 netif_carrier_off(dev->ndev); 1263 link_poll_interval = PHY_POLL_LINK_OFF; 1264 } 1265 dev->link_polling = 1; 1266 wmb(); 1267 schedule_delayed_work(&dev->link_work, link_poll_interval); 1268 emac_print_link_status(dev); 1269 } else 1270 netif_carrier_on(dev->ndev); 1271 1272 /* Required for Pause packet support in EMAC */ 1273 dev_mc_add_global(ndev, default_mcast_addr); 1274 1275 emac_configure(dev); 1276 mal_poll_add(dev->mal, &dev->commac); 1277 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan); 1278 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu)); 1279 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1280 emac_tx_enable(dev); 1281 emac_rx_enable(dev); 1282 emac_netif_start(dev); 1283 1284 mutex_unlock(&dev->link_lock); 1285 1286 return 0; 1287 oom: 1288 emac_clean_rx_ring(dev); 1289 return -ENOMEM; 1290 } 1291 1292 /* BHs disabled */ 1293 #if 0 1294 static int emac_link_differs(struct emac_instance *dev) 1295 { 1296 u32 r = in_be32(&dev->emacp->mr1); 1297 1298 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF; 1299 int speed, pause, asym_pause; 1300 1301 if (r & EMAC_MR1_MF_1000) 1302 speed = SPEED_1000; 1303 else if (r & EMAC_MR1_MF_100) 1304 speed = SPEED_100; 1305 else 1306 speed = SPEED_10; 1307 1308 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) { 1309 case (EMAC_MR1_EIFC | EMAC_MR1_APP): 1310 pause = 1; 1311 asym_pause = 0; 1312 break; 1313 case EMAC_MR1_APP: 1314 pause = 0; 1315 asym_pause = 1; 1316 break; 1317 default: 1318 pause = asym_pause = 0; 1319 } 1320 return speed != dev->phy.speed || duplex != dev->phy.duplex || 1321 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause; 1322 } 1323 #endif 1324 1325 static void emac_link_timer(struct work_struct *work) 1326 { 1327 struct emac_instance *dev = 1328 container_of(to_delayed_work(work), 1329 struct emac_instance, link_work); 1330 int link_poll_interval; 1331 1332 mutex_lock(&dev->link_lock); 1333 DBG2(dev, "link timer" NL); 1334 1335 if (!dev->opened) 1336 goto bail; 1337 1338 if (dev->phy.def->ops->poll_link(&dev->phy)) { 1339 if (!netif_carrier_ok(dev->ndev)) { 1340 emac_rx_clk_default(dev); 1341 /* Get new link parameters */ 1342 dev->phy.def->ops->read_link(&dev->phy); 1343 1344 netif_carrier_on(dev->ndev); 1345 emac_netif_stop(dev); 1346 emac_full_tx_reset(dev); 1347 emac_netif_start(dev); 1348 emac_print_link_status(dev); 1349 } 1350 link_poll_interval = PHY_POLL_LINK_ON; 1351 } else { 1352 if (netif_carrier_ok(dev->ndev)) { 1353 emac_rx_clk_tx(dev); 1354 netif_carrier_off(dev->ndev); 1355 netif_tx_disable(dev->ndev); 1356 emac_reinitialize(dev); 1357 emac_print_link_status(dev); 1358 } 1359 link_poll_interval = PHY_POLL_LINK_OFF; 1360 } 1361 schedule_delayed_work(&dev->link_work, link_poll_interval); 1362 bail: 1363 mutex_unlock(&dev->link_lock); 1364 } 1365 1366 static void emac_force_link_update(struct emac_instance *dev) 1367 { 1368 netif_carrier_off(dev->ndev); 1369 smp_rmb(); 1370 if (dev->link_polling) { 1371 cancel_delayed_work_sync(&dev->link_work); 1372 if (dev->link_polling) 1373 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF); 1374 } 1375 } 1376 1377 /* Process ctx, rtnl_lock semaphore */ 1378 static int emac_close(struct net_device *ndev) 1379 { 1380 struct emac_instance *dev = netdev_priv(ndev); 1381 1382 DBG(dev, "close" NL); 1383 1384 if (dev->phy.address >= 0) { 1385 dev->link_polling = 0; 1386 cancel_delayed_work_sync(&dev->link_work); 1387 } 1388 mutex_lock(&dev->link_lock); 1389 emac_netif_stop(dev); 1390 dev->opened = 0; 1391 mutex_unlock(&dev->link_lock); 1392 1393 emac_rx_disable(dev); 1394 emac_tx_disable(dev); 1395 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan); 1396 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan); 1397 mal_poll_del(dev->mal, &dev->commac); 1398 1399 emac_clean_tx_ring(dev); 1400 emac_clean_rx_ring(dev); 1401 1402 netif_carrier_off(ndev); 1403 1404 return 0; 1405 } 1406 1407 static inline u16 emac_tx_csum(struct emac_instance *dev, 1408 struct sk_buff *skb) 1409 { 1410 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) && 1411 (skb->ip_summed == CHECKSUM_PARTIAL)) { 1412 ++dev->stats.tx_packets_csum; 1413 return EMAC_TX_CTRL_TAH_CSUM; 1414 } 1415 return 0; 1416 } 1417 1418 static inline netdev_tx_t emac_xmit_finish(struct emac_instance *dev, int len) 1419 { 1420 struct emac_regs __iomem *p = dev->emacp; 1421 struct net_device *ndev = dev->ndev; 1422 1423 /* Send the packet out. If the if makes a significant perf 1424 * difference, then we can store the TMR0 value in "dev" 1425 * instead 1426 */ 1427 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 1428 out_be32(&p->tmr0, EMAC4_TMR0_XMIT); 1429 else 1430 out_be32(&p->tmr0, EMAC_TMR0_XMIT); 1431 1432 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) { 1433 netif_stop_queue(ndev); 1434 DBG2(dev, "stopped TX queue" NL); 1435 } 1436 1437 netif_trans_update(ndev); 1438 ++dev->stats.tx_packets; 1439 dev->stats.tx_bytes += len; 1440 1441 return NETDEV_TX_OK; 1442 } 1443 1444 /* Tx lock BH */ 1445 static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1446 { 1447 struct emac_instance *dev = netdev_priv(ndev); 1448 unsigned int len = skb->len; 1449 int slot; 1450 1451 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY | 1452 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb); 1453 1454 slot = dev->tx_slot++; 1455 if (dev->tx_slot == NUM_TX_BUFF) { 1456 dev->tx_slot = 0; 1457 ctrl |= MAL_TX_CTRL_WRAP; 1458 } 1459 1460 DBG2(dev, "xmit(%u) %d" NL, len, slot); 1461 1462 dev->tx_skb[slot] = skb; 1463 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev, 1464 skb->data, len, 1465 DMA_TO_DEVICE); 1466 dev->tx_desc[slot].data_len = (u16) len; 1467 wmb(); 1468 dev->tx_desc[slot].ctrl = ctrl; 1469 1470 return emac_xmit_finish(dev, len); 1471 } 1472 1473 static inline int emac_xmit_split(struct emac_instance *dev, int slot, 1474 u32 pd, int len, int last, u16 base_ctrl) 1475 { 1476 while (1) { 1477 u16 ctrl = base_ctrl; 1478 int chunk = min(len, MAL_MAX_TX_SIZE); 1479 len -= chunk; 1480 1481 slot = (slot + 1) % NUM_TX_BUFF; 1482 1483 if (last && !len) 1484 ctrl |= MAL_TX_CTRL_LAST; 1485 if (slot == NUM_TX_BUFF - 1) 1486 ctrl |= MAL_TX_CTRL_WRAP; 1487 1488 dev->tx_skb[slot] = NULL; 1489 dev->tx_desc[slot].data_ptr = pd; 1490 dev->tx_desc[slot].data_len = (u16) chunk; 1491 dev->tx_desc[slot].ctrl = ctrl; 1492 ++dev->tx_cnt; 1493 1494 if (!len) 1495 break; 1496 1497 pd += chunk; 1498 } 1499 return slot; 1500 } 1501 1502 /* Tx lock BH disabled (SG version for TAH equipped EMACs) */ 1503 static netdev_tx_t 1504 emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev) 1505 { 1506 struct emac_instance *dev = netdev_priv(ndev); 1507 int nr_frags = skb_shinfo(skb)->nr_frags; 1508 int len = skb->len, chunk; 1509 int slot, i; 1510 u16 ctrl; 1511 u32 pd; 1512 1513 /* This is common "fast" path */ 1514 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE)) 1515 return emac_start_xmit(skb, ndev); 1516 1517 len -= skb->data_len; 1518 1519 /* Note, this is only an *estimation*, we can still run out of empty 1520 * slots because of the additional fragmentation into 1521 * MAL_MAX_TX_SIZE-sized chunks 1522 */ 1523 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF)) 1524 goto stop_queue; 1525 1526 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY | 1527 emac_tx_csum(dev, skb); 1528 slot = dev->tx_slot; 1529 1530 /* skb data */ 1531 dev->tx_skb[slot] = NULL; 1532 chunk = min(len, MAL_MAX_TX_SIZE); 1533 dev->tx_desc[slot].data_ptr = pd = 1534 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE); 1535 dev->tx_desc[slot].data_len = (u16) chunk; 1536 len -= chunk; 1537 if (unlikely(len)) 1538 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags, 1539 ctrl); 1540 /* skb fragments */ 1541 for (i = 0; i < nr_frags; ++i) { 1542 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1543 len = skb_frag_size(frag); 1544 1545 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF)) 1546 goto undo_frame; 1547 1548 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len, 1549 DMA_TO_DEVICE); 1550 1551 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1, 1552 ctrl); 1553 } 1554 1555 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot); 1556 1557 /* Attach skb to the last slot so we don't release it too early */ 1558 dev->tx_skb[slot] = skb; 1559 1560 /* Send the packet out */ 1561 if (dev->tx_slot == NUM_TX_BUFF - 1) 1562 ctrl |= MAL_TX_CTRL_WRAP; 1563 wmb(); 1564 dev->tx_desc[dev->tx_slot].ctrl = ctrl; 1565 dev->tx_slot = (slot + 1) % NUM_TX_BUFF; 1566 1567 return emac_xmit_finish(dev, skb->len); 1568 1569 undo_frame: 1570 /* Well, too bad. Our previous estimation was overly optimistic. 1571 * Undo everything. 1572 */ 1573 while (slot != dev->tx_slot) { 1574 dev->tx_desc[slot].ctrl = 0; 1575 --dev->tx_cnt; 1576 if (--slot < 0) 1577 slot = NUM_TX_BUFF - 1; 1578 } 1579 ++dev->estats.tx_undo; 1580 1581 stop_queue: 1582 netif_stop_queue(ndev); 1583 DBG2(dev, "stopped TX queue" NL); 1584 return NETDEV_TX_BUSY; 1585 } 1586 1587 /* Tx lock BHs */ 1588 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl) 1589 { 1590 struct emac_error_stats *st = &dev->estats; 1591 1592 DBG(dev, "BD TX error %04x" NL, ctrl); 1593 1594 ++st->tx_bd_errors; 1595 if (ctrl & EMAC_TX_ST_BFCS) 1596 ++st->tx_bd_bad_fcs; 1597 if (ctrl & EMAC_TX_ST_LCS) 1598 ++st->tx_bd_carrier_loss; 1599 if (ctrl & EMAC_TX_ST_ED) 1600 ++st->tx_bd_excessive_deferral; 1601 if (ctrl & EMAC_TX_ST_EC) 1602 ++st->tx_bd_excessive_collisions; 1603 if (ctrl & EMAC_TX_ST_LC) 1604 ++st->tx_bd_late_collision; 1605 if (ctrl & EMAC_TX_ST_MC) 1606 ++st->tx_bd_multple_collisions; 1607 if (ctrl & EMAC_TX_ST_SC) 1608 ++st->tx_bd_single_collision; 1609 if (ctrl & EMAC_TX_ST_UR) 1610 ++st->tx_bd_underrun; 1611 if (ctrl & EMAC_TX_ST_SQE) 1612 ++st->tx_bd_sqe; 1613 } 1614 1615 static void emac_poll_tx(void *param) 1616 { 1617 struct emac_instance *dev = param; 1618 u32 bad_mask; 1619 1620 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot); 1621 1622 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 1623 bad_mask = EMAC_IS_BAD_TX_TAH; 1624 else 1625 bad_mask = EMAC_IS_BAD_TX; 1626 1627 netif_tx_lock_bh(dev->ndev); 1628 if (dev->tx_cnt) { 1629 u16 ctrl; 1630 int slot = dev->ack_slot, n = 0; 1631 again: 1632 ctrl = dev->tx_desc[slot].ctrl; 1633 if (!(ctrl & MAL_TX_CTRL_READY)) { 1634 struct sk_buff *skb = dev->tx_skb[slot]; 1635 ++n; 1636 1637 if (skb) { 1638 dev_kfree_skb(skb); 1639 dev->tx_skb[slot] = NULL; 1640 } 1641 slot = (slot + 1) % NUM_TX_BUFF; 1642 1643 if (unlikely(ctrl & bad_mask)) 1644 emac_parse_tx_error(dev, ctrl); 1645 1646 if (--dev->tx_cnt) 1647 goto again; 1648 } 1649 if (n) { 1650 dev->ack_slot = slot; 1651 if (netif_queue_stopped(dev->ndev) && 1652 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH) 1653 netif_wake_queue(dev->ndev); 1654 1655 DBG2(dev, "tx %d pkts" NL, n); 1656 } 1657 } 1658 netif_tx_unlock_bh(dev->ndev); 1659 } 1660 1661 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot, 1662 int len) 1663 { 1664 struct sk_buff *skb = dev->rx_skb[slot]; 1665 1666 DBG2(dev, "recycle %d %d" NL, slot, len); 1667 1668 if (len) 1669 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN, 1670 SKB_DATA_ALIGN(len + NET_IP_ALIGN), 1671 DMA_FROM_DEVICE); 1672 1673 dev->rx_desc[slot].data_len = 0; 1674 wmb(); 1675 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY | 1676 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1677 } 1678 1679 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl) 1680 { 1681 struct emac_error_stats *st = &dev->estats; 1682 1683 DBG(dev, "BD RX error %04x" NL, ctrl); 1684 1685 ++st->rx_bd_errors; 1686 if (ctrl & EMAC_RX_ST_OE) 1687 ++st->rx_bd_overrun; 1688 if (ctrl & EMAC_RX_ST_BP) 1689 ++st->rx_bd_bad_packet; 1690 if (ctrl & EMAC_RX_ST_RP) 1691 ++st->rx_bd_runt_packet; 1692 if (ctrl & EMAC_RX_ST_SE) 1693 ++st->rx_bd_short_event; 1694 if (ctrl & EMAC_RX_ST_AE) 1695 ++st->rx_bd_alignment_error; 1696 if (ctrl & EMAC_RX_ST_BFCS) 1697 ++st->rx_bd_bad_fcs; 1698 if (ctrl & EMAC_RX_ST_PTL) 1699 ++st->rx_bd_packet_too_long; 1700 if (ctrl & EMAC_RX_ST_ORE) 1701 ++st->rx_bd_out_of_range; 1702 if (ctrl & EMAC_RX_ST_IRE) 1703 ++st->rx_bd_in_range; 1704 } 1705 1706 static inline void emac_rx_csum(struct emac_instance *dev, 1707 struct sk_buff *skb, u16 ctrl) 1708 { 1709 #ifdef CONFIG_IBM_EMAC_TAH 1710 if (!ctrl && dev->tah_dev) { 1711 skb->ip_summed = CHECKSUM_UNNECESSARY; 1712 ++dev->stats.rx_packets_csum; 1713 } 1714 #endif 1715 } 1716 1717 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot) 1718 { 1719 if (likely(dev->rx_sg_skb != NULL)) { 1720 int len = dev->rx_desc[slot].data_len; 1721 int tot_len = dev->rx_sg_skb->len + len; 1722 1723 if (unlikely(tot_len + NET_IP_ALIGN > dev->rx_skb_size)) { 1724 ++dev->estats.rx_dropped_mtu; 1725 dev_kfree_skb(dev->rx_sg_skb); 1726 dev->rx_sg_skb = NULL; 1727 } else { 1728 memcpy(skb_tail_pointer(dev->rx_sg_skb), 1729 dev->rx_skb[slot]->data, len); 1730 skb_put(dev->rx_sg_skb, len); 1731 emac_recycle_rx_skb(dev, slot, len); 1732 return 0; 1733 } 1734 } 1735 emac_recycle_rx_skb(dev, slot, 0); 1736 return -1; 1737 } 1738 1739 /* NAPI poll context */ 1740 static int emac_poll_rx(void *param, int budget) 1741 { 1742 struct emac_instance *dev = param; 1743 int slot = dev->rx_slot, received = 0; 1744 1745 DBG2(dev, "poll_rx(%d)" NL, budget); 1746 1747 again: 1748 while (budget > 0) { 1749 int len; 1750 struct sk_buff *skb; 1751 u16 ctrl = dev->rx_desc[slot].ctrl; 1752 1753 if (ctrl & MAL_RX_CTRL_EMPTY) 1754 break; 1755 1756 skb = dev->rx_skb[slot]; 1757 mb(); 1758 len = dev->rx_desc[slot].data_len; 1759 1760 if (unlikely(!MAL_IS_SINGLE_RX(ctrl))) 1761 goto sg; 1762 1763 ctrl &= EMAC_BAD_RX_MASK; 1764 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) { 1765 emac_parse_rx_error(dev, ctrl); 1766 ++dev->estats.rx_dropped_error; 1767 emac_recycle_rx_skb(dev, slot, 0); 1768 len = 0; 1769 goto next; 1770 } 1771 1772 if (len < ETH_HLEN) { 1773 ++dev->estats.rx_dropped_stack; 1774 emac_recycle_rx_skb(dev, slot, len); 1775 goto next; 1776 } 1777 1778 if (len && len < EMAC_RX_COPY_THRESH) { 1779 struct sk_buff *copy_skb; 1780 1781 copy_skb = napi_alloc_skb(&dev->mal->napi, len); 1782 if (unlikely(!copy_skb)) 1783 goto oom; 1784 1785 memcpy(copy_skb->data - NET_IP_ALIGN, 1786 skb->data - NET_IP_ALIGN, 1787 len + NET_IP_ALIGN); 1788 emac_recycle_rx_skb(dev, slot, len); 1789 skb = copy_skb; 1790 } else if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) 1791 goto oom; 1792 1793 skb_put(skb, len); 1794 push_packet: 1795 skb->protocol = eth_type_trans(skb, dev->ndev); 1796 emac_rx_csum(dev, skb, ctrl); 1797 1798 napi_gro_receive(&dev->mal->napi, skb); 1799 next: 1800 ++dev->stats.rx_packets; 1801 skip: 1802 dev->stats.rx_bytes += len; 1803 slot = (slot + 1) % NUM_RX_BUFF; 1804 --budget; 1805 ++received; 1806 continue; 1807 sg: 1808 if (ctrl & MAL_RX_CTRL_FIRST) { 1809 BUG_ON(dev->rx_sg_skb); 1810 if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) { 1811 DBG(dev, "rx OOM %d" NL, slot); 1812 ++dev->estats.rx_dropped_oom; 1813 emac_recycle_rx_skb(dev, slot, 0); 1814 } else { 1815 dev->rx_sg_skb = skb; 1816 skb_put(skb, len); 1817 } 1818 } else if (!emac_rx_sg_append(dev, slot) && 1819 (ctrl & MAL_RX_CTRL_LAST)) { 1820 1821 skb = dev->rx_sg_skb; 1822 dev->rx_sg_skb = NULL; 1823 1824 ctrl &= EMAC_BAD_RX_MASK; 1825 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) { 1826 emac_parse_rx_error(dev, ctrl); 1827 ++dev->estats.rx_dropped_error; 1828 dev_kfree_skb(skb); 1829 len = 0; 1830 } else 1831 goto push_packet; 1832 } 1833 goto skip; 1834 oom: 1835 DBG(dev, "rx OOM %d" NL, slot); 1836 /* Drop the packet and recycle skb */ 1837 ++dev->estats.rx_dropped_oom; 1838 emac_recycle_rx_skb(dev, slot, 0); 1839 goto next; 1840 } 1841 1842 if (received) { 1843 DBG2(dev, "rx %d BDs" NL, received); 1844 dev->rx_slot = slot; 1845 } 1846 1847 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) { 1848 mb(); 1849 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) { 1850 DBG2(dev, "rx restart" NL); 1851 received = 0; 1852 goto again; 1853 } 1854 1855 if (dev->rx_sg_skb) { 1856 DBG2(dev, "dropping partial rx packet" NL); 1857 ++dev->estats.rx_dropped_error; 1858 dev_kfree_skb(dev->rx_sg_skb); 1859 dev->rx_sg_skb = NULL; 1860 } 1861 1862 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1863 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1864 emac_rx_enable(dev); 1865 dev->rx_slot = 0; 1866 } 1867 return received; 1868 } 1869 1870 /* NAPI poll context */ 1871 static int emac_peek_rx(void *param) 1872 { 1873 struct emac_instance *dev = param; 1874 1875 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY); 1876 } 1877 1878 /* NAPI poll context */ 1879 static int emac_peek_rx_sg(void *param) 1880 { 1881 struct emac_instance *dev = param; 1882 1883 int slot = dev->rx_slot; 1884 while (1) { 1885 u16 ctrl = dev->rx_desc[slot].ctrl; 1886 if (ctrl & MAL_RX_CTRL_EMPTY) 1887 return 0; 1888 else if (ctrl & MAL_RX_CTRL_LAST) 1889 return 1; 1890 1891 slot = (slot + 1) % NUM_RX_BUFF; 1892 1893 /* I'm just being paranoid here :) */ 1894 if (unlikely(slot == dev->rx_slot)) 1895 return 0; 1896 } 1897 } 1898 1899 /* Hard IRQ */ 1900 static void emac_rxde(void *param) 1901 { 1902 struct emac_instance *dev = param; 1903 1904 ++dev->estats.rx_stopped; 1905 emac_rx_disable_async(dev); 1906 } 1907 1908 /* Hard IRQ */ 1909 static irqreturn_t emac_irq(int irq, void *dev_instance) 1910 { 1911 struct emac_instance *dev = dev_instance; 1912 struct emac_regs __iomem *p = dev->emacp; 1913 struct emac_error_stats *st = &dev->estats; 1914 u32 isr; 1915 1916 spin_lock(&dev->lock); 1917 1918 isr = in_be32(&p->isr); 1919 out_be32(&p->isr, isr); 1920 1921 DBG(dev, "isr = %08x" NL, isr); 1922 1923 if (isr & EMAC4_ISR_TXPE) 1924 ++st->tx_parity; 1925 if (isr & EMAC4_ISR_RXPE) 1926 ++st->rx_parity; 1927 if (isr & EMAC4_ISR_TXUE) 1928 ++st->tx_underrun; 1929 if (isr & EMAC4_ISR_RXOE) 1930 ++st->rx_fifo_overrun; 1931 if (isr & EMAC_ISR_OVR) 1932 ++st->rx_overrun; 1933 if (isr & EMAC_ISR_BP) 1934 ++st->rx_bad_packet; 1935 if (isr & EMAC_ISR_RP) 1936 ++st->rx_runt_packet; 1937 if (isr & EMAC_ISR_SE) 1938 ++st->rx_short_event; 1939 if (isr & EMAC_ISR_ALE) 1940 ++st->rx_alignment_error; 1941 if (isr & EMAC_ISR_BFCS) 1942 ++st->rx_bad_fcs; 1943 if (isr & EMAC_ISR_PTLE) 1944 ++st->rx_packet_too_long; 1945 if (isr & EMAC_ISR_ORE) 1946 ++st->rx_out_of_range; 1947 if (isr & EMAC_ISR_IRE) 1948 ++st->rx_in_range; 1949 if (isr & EMAC_ISR_SQE) 1950 ++st->tx_sqe; 1951 if (isr & EMAC_ISR_TE) 1952 ++st->tx_errors; 1953 1954 spin_unlock(&dev->lock); 1955 1956 return IRQ_HANDLED; 1957 } 1958 1959 static struct net_device_stats *emac_stats(struct net_device *ndev) 1960 { 1961 struct emac_instance *dev = netdev_priv(ndev); 1962 struct emac_stats *st = &dev->stats; 1963 struct emac_error_stats *est = &dev->estats; 1964 struct net_device_stats *nst = &ndev->stats; 1965 unsigned long flags; 1966 1967 DBG2(dev, "stats" NL); 1968 1969 /* Compute "legacy" statistics */ 1970 spin_lock_irqsave(&dev->lock, flags); 1971 nst->rx_packets = (unsigned long)st->rx_packets; 1972 nst->rx_bytes = (unsigned long)st->rx_bytes; 1973 nst->tx_packets = (unsigned long)st->tx_packets; 1974 nst->tx_bytes = (unsigned long)st->tx_bytes; 1975 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom + 1976 est->rx_dropped_error + 1977 est->rx_dropped_resize + 1978 est->rx_dropped_mtu); 1979 nst->tx_dropped = (unsigned long)est->tx_dropped; 1980 1981 nst->rx_errors = (unsigned long)est->rx_bd_errors; 1982 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun + 1983 est->rx_fifo_overrun + 1984 est->rx_overrun); 1985 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error + 1986 est->rx_alignment_error); 1987 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs + 1988 est->rx_bad_fcs); 1989 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet + 1990 est->rx_bd_short_event + 1991 est->rx_bd_packet_too_long + 1992 est->rx_bd_out_of_range + 1993 est->rx_bd_in_range + 1994 est->rx_runt_packet + 1995 est->rx_short_event + 1996 est->rx_packet_too_long + 1997 est->rx_out_of_range + 1998 est->rx_in_range); 1999 2000 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors); 2001 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun + 2002 est->tx_underrun); 2003 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss; 2004 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral + 2005 est->tx_bd_excessive_collisions + 2006 est->tx_bd_late_collision + 2007 est->tx_bd_multple_collisions); 2008 spin_unlock_irqrestore(&dev->lock, flags); 2009 return nst; 2010 } 2011 2012 static struct mal_commac_ops emac_commac_ops = { 2013 .poll_tx = &emac_poll_tx, 2014 .poll_rx = &emac_poll_rx, 2015 .peek_rx = &emac_peek_rx, 2016 .rxde = &emac_rxde, 2017 }; 2018 2019 static struct mal_commac_ops emac_commac_sg_ops = { 2020 .poll_tx = &emac_poll_tx, 2021 .poll_rx = &emac_poll_rx, 2022 .peek_rx = &emac_peek_rx_sg, 2023 .rxde = &emac_rxde, 2024 }; 2025 2026 /* Ethtool support */ 2027 static int emac_ethtool_get_link_ksettings(struct net_device *ndev, 2028 struct ethtool_link_ksettings *cmd) 2029 { 2030 struct emac_instance *dev = netdev_priv(ndev); 2031 u32 supported, advertising; 2032 2033 supported = dev->phy.features; 2034 cmd->base.port = PORT_MII; 2035 cmd->base.phy_address = dev->phy.address; 2036 2037 mutex_lock(&dev->link_lock); 2038 advertising = dev->phy.advertising; 2039 cmd->base.autoneg = dev->phy.autoneg; 2040 cmd->base.speed = dev->phy.speed; 2041 cmd->base.duplex = dev->phy.duplex; 2042 mutex_unlock(&dev->link_lock); 2043 2044 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 2045 supported); 2046 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 2047 advertising); 2048 2049 return 0; 2050 } 2051 2052 static int 2053 emac_ethtool_set_link_ksettings(struct net_device *ndev, 2054 const struct ethtool_link_ksettings *cmd) 2055 { 2056 struct emac_instance *dev = netdev_priv(ndev); 2057 u32 f = dev->phy.features; 2058 u32 advertising; 2059 2060 ethtool_convert_link_mode_to_legacy_u32(&advertising, 2061 cmd->link_modes.advertising); 2062 2063 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL, 2064 cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising); 2065 2066 /* Basic sanity checks */ 2067 if (dev->phy.address < 0) 2068 return -EOPNOTSUPP; 2069 if (cmd->base.autoneg != AUTONEG_ENABLE && 2070 cmd->base.autoneg != AUTONEG_DISABLE) 2071 return -EINVAL; 2072 if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0) 2073 return -EINVAL; 2074 if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL) 2075 return -EINVAL; 2076 2077 if (cmd->base.autoneg == AUTONEG_DISABLE) { 2078 switch (cmd->base.speed) { 2079 case SPEED_10: 2080 if (cmd->base.duplex == DUPLEX_HALF && 2081 !(f & SUPPORTED_10baseT_Half)) 2082 return -EINVAL; 2083 if (cmd->base.duplex == DUPLEX_FULL && 2084 !(f & SUPPORTED_10baseT_Full)) 2085 return -EINVAL; 2086 break; 2087 case SPEED_100: 2088 if (cmd->base.duplex == DUPLEX_HALF && 2089 !(f & SUPPORTED_100baseT_Half)) 2090 return -EINVAL; 2091 if (cmd->base.duplex == DUPLEX_FULL && 2092 !(f & SUPPORTED_100baseT_Full)) 2093 return -EINVAL; 2094 break; 2095 case SPEED_1000: 2096 if (cmd->base.duplex == DUPLEX_HALF && 2097 !(f & SUPPORTED_1000baseT_Half)) 2098 return -EINVAL; 2099 if (cmd->base.duplex == DUPLEX_FULL && 2100 !(f & SUPPORTED_1000baseT_Full)) 2101 return -EINVAL; 2102 break; 2103 default: 2104 return -EINVAL; 2105 } 2106 2107 mutex_lock(&dev->link_lock); 2108 dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed, 2109 cmd->base.duplex); 2110 mutex_unlock(&dev->link_lock); 2111 2112 } else { 2113 if (!(f & SUPPORTED_Autoneg)) 2114 return -EINVAL; 2115 2116 mutex_lock(&dev->link_lock); 2117 dev->phy.def->ops->setup_aneg(&dev->phy, 2118 (advertising & f) | 2119 (dev->phy.advertising & 2120 (ADVERTISED_Pause | 2121 ADVERTISED_Asym_Pause))); 2122 mutex_unlock(&dev->link_lock); 2123 } 2124 emac_force_link_update(dev); 2125 2126 return 0; 2127 } 2128 2129 static void 2130 emac_ethtool_get_ringparam(struct net_device *ndev, 2131 struct ethtool_ringparam *rp, 2132 struct kernel_ethtool_ringparam *kernel_rp, 2133 struct netlink_ext_ack *extack) 2134 { 2135 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF; 2136 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF; 2137 } 2138 2139 static void emac_ethtool_get_pauseparam(struct net_device *ndev, 2140 struct ethtool_pauseparam *pp) 2141 { 2142 struct emac_instance *dev = netdev_priv(ndev); 2143 2144 mutex_lock(&dev->link_lock); 2145 if ((dev->phy.features & SUPPORTED_Autoneg) && 2146 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause))) 2147 pp->autoneg = 1; 2148 2149 if (dev->phy.duplex == DUPLEX_FULL) { 2150 if (dev->phy.pause) 2151 pp->rx_pause = pp->tx_pause = 1; 2152 else if (dev->phy.asym_pause) 2153 pp->tx_pause = 1; 2154 } 2155 mutex_unlock(&dev->link_lock); 2156 } 2157 2158 static int emac_get_regs_len(struct emac_instance *dev) 2159 { 2160 return sizeof(struct emac_ethtool_regs_subhdr) + 2161 sizeof(struct emac_regs); 2162 } 2163 2164 static int emac_ethtool_get_regs_len(struct net_device *ndev) 2165 { 2166 struct emac_instance *dev = netdev_priv(ndev); 2167 int size; 2168 2169 size = sizeof(struct emac_ethtool_regs_hdr) + 2170 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal); 2171 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 2172 size += zmii_get_regs_len(dev->zmii_dev); 2173 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 2174 size += rgmii_get_regs_len(dev->rgmii_dev); 2175 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 2176 size += tah_get_regs_len(dev->tah_dev); 2177 2178 return size; 2179 } 2180 2181 static void *emac_dump_regs(struct emac_instance *dev, void *buf) 2182 { 2183 struct emac_ethtool_regs_subhdr *hdr = buf; 2184 2185 hdr->index = dev->cell_index; 2186 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) { 2187 hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER; 2188 } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) { 2189 hdr->version = EMAC4_ETHTOOL_REGS_VER; 2190 } else { 2191 hdr->version = EMAC_ETHTOOL_REGS_VER; 2192 } 2193 memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs)); 2194 return (void *)(hdr + 1) + sizeof(struct emac_regs); 2195 } 2196 2197 static void emac_ethtool_get_regs(struct net_device *ndev, 2198 struct ethtool_regs *regs, void *buf) 2199 { 2200 struct emac_instance *dev = netdev_priv(ndev); 2201 struct emac_ethtool_regs_hdr *hdr = buf; 2202 2203 hdr->components = 0; 2204 buf = hdr + 1; 2205 2206 buf = mal_dump_regs(dev->mal, buf); 2207 buf = emac_dump_regs(dev, buf); 2208 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) { 2209 hdr->components |= EMAC_ETHTOOL_REGS_ZMII; 2210 buf = zmii_dump_regs(dev->zmii_dev, buf); 2211 } 2212 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) { 2213 hdr->components |= EMAC_ETHTOOL_REGS_RGMII; 2214 buf = rgmii_dump_regs(dev->rgmii_dev, buf); 2215 } 2216 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) { 2217 hdr->components |= EMAC_ETHTOOL_REGS_TAH; 2218 buf = tah_dump_regs(dev->tah_dev, buf); 2219 } 2220 } 2221 2222 static int emac_ethtool_nway_reset(struct net_device *ndev) 2223 { 2224 struct emac_instance *dev = netdev_priv(ndev); 2225 int res = 0; 2226 2227 DBG(dev, "nway_reset" NL); 2228 2229 if (dev->phy.address < 0) 2230 return -EOPNOTSUPP; 2231 2232 mutex_lock(&dev->link_lock); 2233 if (!dev->phy.autoneg) { 2234 res = -EINVAL; 2235 goto out; 2236 } 2237 2238 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising); 2239 out: 2240 mutex_unlock(&dev->link_lock); 2241 emac_force_link_update(dev); 2242 return res; 2243 } 2244 2245 static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset) 2246 { 2247 if (stringset == ETH_SS_STATS) 2248 return EMAC_ETHTOOL_STATS_COUNT; 2249 else 2250 return -EINVAL; 2251 } 2252 2253 static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset, 2254 u8 * buf) 2255 { 2256 if (stringset == ETH_SS_STATS) 2257 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys)); 2258 } 2259 2260 static void emac_ethtool_get_ethtool_stats(struct net_device *ndev, 2261 struct ethtool_stats *estats, 2262 u64 * tmp_stats) 2263 { 2264 struct emac_instance *dev = netdev_priv(ndev); 2265 2266 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats)); 2267 tmp_stats += sizeof(dev->stats) / sizeof(u64); 2268 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats)); 2269 } 2270 2271 static void emac_ethtool_get_drvinfo(struct net_device *ndev, 2272 struct ethtool_drvinfo *info) 2273 { 2274 struct emac_instance *dev = netdev_priv(ndev); 2275 2276 strscpy(info->driver, "ibm_emac", sizeof(info->driver)); 2277 strscpy(info->version, DRV_VERSION, sizeof(info->version)); 2278 snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %pOF", 2279 dev->cell_index, dev->ofdev->dev.of_node); 2280 } 2281 2282 static const struct ethtool_ops emac_ethtool_ops = { 2283 .get_drvinfo = emac_ethtool_get_drvinfo, 2284 2285 .get_regs_len = emac_ethtool_get_regs_len, 2286 .get_regs = emac_ethtool_get_regs, 2287 2288 .nway_reset = emac_ethtool_nway_reset, 2289 2290 .get_ringparam = emac_ethtool_get_ringparam, 2291 .get_pauseparam = emac_ethtool_get_pauseparam, 2292 2293 .get_strings = emac_ethtool_get_strings, 2294 .get_sset_count = emac_ethtool_get_sset_count, 2295 .get_ethtool_stats = emac_ethtool_get_ethtool_stats, 2296 2297 .get_link = ethtool_op_get_link, 2298 .get_link_ksettings = emac_ethtool_get_link_ksettings, 2299 .set_link_ksettings = emac_ethtool_set_link_ksettings, 2300 }; 2301 2302 static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2303 { 2304 struct emac_instance *dev = netdev_priv(ndev); 2305 struct mii_ioctl_data *data = if_mii(rq); 2306 2307 DBG(dev, "ioctl %08x" NL, cmd); 2308 2309 if (dev->phy.address < 0) 2310 return -EOPNOTSUPP; 2311 2312 switch (cmd) { 2313 case SIOCGMIIPHY: 2314 data->phy_id = dev->phy.address; 2315 fallthrough; 2316 case SIOCGMIIREG: 2317 data->val_out = emac_mdio_read(ndev, dev->phy.address, 2318 data->reg_num); 2319 return 0; 2320 2321 case SIOCSMIIREG: 2322 emac_mdio_write(ndev, dev->phy.address, data->reg_num, 2323 data->val_in); 2324 return 0; 2325 default: 2326 return -EOPNOTSUPP; 2327 } 2328 } 2329 2330 struct emac_depentry { 2331 u32 phandle; 2332 struct device_node *node; 2333 struct platform_device *ofdev; 2334 void *drvdata; 2335 }; 2336 2337 #define EMAC_DEP_MAL_IDX 0 2338 #define EMAC_DEP_ZMII_IDX 1 2339 #define EMAC_DEP_RGMII_IDX 2 2340 #define EMAC_DEP_TAH_IDX 3 2341 #define EMAC_DEP_MDIO_IDX 4 2342 #define EMAC_DEP_PREV_IDX 5 2343 #define EMAC_DEP_COUNT 6 2344 2345 static int emac_check_deps(struct emac_instance *dev, 2346 struct emac_depentry *deps) 2347 { 2348 int i, there = 0; 2349 struct device_node *np; 2350 2351 for (i = 0; i < EMAC_DEP_COUNT; i++) { 2352 /* no dependency on that item, allright */ 2353 if (deps[i].phandle == 0) { 2354 there++; 2355 continue; 2356 } 2357 /* special case for blist as the dependency might go away */ 2358 if (i == EMAC_DEP_PREV_IDX) { 2359 np = *(dev->blist - 1); 2360 if (np == NULL) { 2361 deps[i].phandle = 0; 2362 there++; 2363 continue; 2364 } 2365 if (deps[i].node == NULL) 2366 deps[i].node = of_node_get(np); 2367 } 2368 if (deps[i].node == NULL) 2369 deps[i].node = of_find_node_by_phandle(deps[i].phandle); 2370 if (deps[i].node == NULL) 2371 continue; 2372 if (deps[i].ofdev == NULL) 2373 deps[i].ofdev = of_find_device_by_node(deps[i].node); 2374 if (deps[i].ofdev == NULL) 2375 continue; 2376 if (deps[i].drvdata == NULL) 2377 deps[i].drvdata = platform_get_drvdata(deps[i].ofdev); 2378 if (deps[i].drvdata != NULL) 2379 there++; 2380 } 2381 if (there != EMAC_DEP_COUNT) 2382 return -EPROBE_DEFER; 2383 return 0; 2384 } 2385 2386 static void emac_put_deps(struct emac_instance *dev) 2387 { 2388 platform_device_put(dev->mal_dev); 2389 platform_device_put(dev->zmii_dev); 2390 platform_device_put(dev->rgmii_dev); 2391 platform_device_put(dev->mdio_dev); 2392 platform_device_put(dev->tah_dev); 2393 } 2394 2395 static int emac_wait_deps(struct emac_instance *dev) 2396 { 2397 struct emac_depentry deps[EMAC_DEP_COUNT]; 2398 int i, err; 2399 2400 memset(&deps, 0, sizeof(deps)); 2401 2402 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph; 2403 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph; 2404 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph; 2405 if (dev->tah_ph) 2406 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph; 2407 if (dev->mdio_ph) 2408 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph; 2409 if (dev->blist && dev->blist > emac_boot_list) 2410 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu; 2411 err = emac_check_deps(dev, deps); 2412 for (i = 0; i < EMAC_DEP_COUNT; i++) { 2413 of_node_put(deps[i].node); 2414 if (err) 2415 platform_device_put(deps[i].ofdev); 2416 } 2417 if (!err) { 2418 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev; 2419 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev; 2420 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev; 2421 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev; 2422 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev; 2423 } 2424 platform_device_put(deps[EMAC_DEP_PREV_IDX].ofdev); 2425 return err; 2426 } 2427 2428 static int emac_read_uint_prop(struct device_node *np, const char *name, 2429 u32 *val, int fatal) 2430 { 2431 int err; 2432 2433 err = of_property_read_u32(np, name, val); 2434 if (err) { 2435 if (fatal) 2436 pr_err("%pOF: missing %s property", np, name); 2437 return err; 2438 } 2439 return 0; 2440 } 2441 2442 static void emac_adjust_link(struct net_device *ndev) 2443 { 2444 struct emac_instance *dev = netdev_priv(ndev); 2445 struct phy_device *phy = ndev->phydev; 2446 2447 dev->phy.autoneg = phy->autoneg; 2448 dev->phy.speed = phy->speed; 2449 dev->phy.duplex = phy->duplex; 2450 dev->phy.pause = phy->pause; 2451 dev->phy.asym_pause = phy->asym_pause; 2452 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.advertising, 2453 phy->advertising); 2454 } 2455 2456 static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum) 2457 { 2458 int ret = emac_mdio_read(bus->priv, addr, regnum); 2459 /* This is a workaround for powered down ports/phys. 2460 * In the wild, this was seen on the Cisco Meraki MX60(W). 2461 * This hardware disables ports as part of the handoff 2462 * procedure. Accessing the ports will lead to errors 2463 * (-ETIMEDOUT, -EREMOTEIO) that do more harm than good. 2464 */ 2465 return ret < 0 ? 0xffff : ret; 2466 } 2467 2468 static int emac_mii_bus_write(struct mii_bus *bus, int addr, 2469 int regnum, u16 val) 2470 { 2471 emac_mdio_write(bus->priv, addr, regnum, val); 2472 return 0; 2473 } 2474 2475 static int emac_mii_bus_reset(struct mii_bus *bus) 2476 { 2477 struct emac_instance *dev = netdev_priv(bus->priv); 2478 2479 return emac_reset(dev); 2480 } 2481 2482 static int emac_mdio_phy_start_aneg(struct mii_phy *phy, 2483 struct phy_device *phy_dev) 2484 { 2485 phy_dev->autoneg = phy->autoneg; 2486 phy_dev->speed = phy->speed; 2487 phy_dev->duplex = phy->duplex; 2488 ethtool_convert_legacy_u32_to_link_mode(phy_dev->advertising, 2489 phy->advertising); 2490 return phy_start_aneg(phy_dev); 2491 } 2492 2493 static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise) 2494 { 2495 struct net_device *ndev = phy->dev; 2496 2497 phy->autoneg = AUTONEG_ENABLE; 2498 phy->advertising = advertise; 2499 return emac_mdio_phy_start_aneg(phy, ndev->phydev); 2500 } 2501 2502 static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd) 2503 { 2504 struct net_device *ndev = phy->dev; 2505 2506 phy->autoneg = AUTONEG_DISABLE; 2507 phy->speed = speed; 2508 phy->duplex = fd; 2509 return emac_mdio_phy_start_aneg(phy, ndev->phydev); 2510 } 2511 2512 static int emac_mdio_poll_link(struct mii_phy *phy) 2513 { 2514 struct net_device *ndev = phy->dev; 2515 struct emac_instance *dev = netdev_priv(ndev); 2516 int res; 2517 2518 res = phy_read_status(ndev->phydev); 2519 if (res) { 2520 dev_err(&dev->ofdev->dev, "link update failed (%d).", res); 2521 return ethtool_op_get_link(ndev); 2522 } 2523 2524 return ndev->phydev->link; 2525 } 2526 2527 static int emac_mdio_read_link(struct mii_phy *phy) 2528 { 2529 struct net_device *ndev = phy->dev; 2530 struct phy_device *phy_dev = ndev->phydev; 2531 int res; 2532 2533 res = phy_read_status(phy_dev); 2534 if (res) 2535 return res; 2536 2537 phy->speed = phy_dev->speed; 2538 phy->duplex = phy_dev->duplex; 2539 phy->pause = phy_dev->pause; 2540 phy->asym_pause = phy_dev->asym_pause; 2541 return 0; 2542 } 2543 2544 static int emac_mdio_init_phy(struct mii_phy *phy) 2545 { 2546 struct net_device *ndev = phy->dev; 2547 2548 phy_start(ndev->phydev); 2549 return phy_init_hw(ndev->phydev); 2550 } 2551 2552 static const struct mii_phy_ops emac_dt_mdio_phy_ops = { 2553 .init = emac_mdio_init_phy, 2554 .setup_aneg = emac_mdio_setup_aneg, 2555 .setup_forced = emac_mdio_setup_forced, 2556 .poll_link = emac_mdio_poll_link, 2557 .read_link = emac_mdio_read_link, 2558 }; 2559 2560 static int emac_dt_mdio_probe(struct emac_instance *dev) 2561 { 2562 struct device_node *mii_np; 2563 struct mii_bus *bus; 2564 int res; 2565 2566 mii_np = of_get_available_child_by_name(dev->ofdev->dev.of_node, "mdio"); 2567 if (!mii_np) { 2568 dev_err(&dev->ofdev->dev, "no mdio definition found."); 2569 return -ENODEV; 2570 } 2571 2572 bus = devm_mdiobus_alloc(&dev->ofdev->dev); 2573 if (!bus) { 2574 res = -ENOMEM; 2575 goto put_node; 2576 } 2577 2578 bus->priv = dev->ndev; 2579 bus->parent = dev->ndev->dev.parent; 2580 bus->name = "emac_mdio"; 2581 bus->read = &emac_mii_bus_read; 2582 bus->write = &emac_mii_bus_write; 2583 bus->reset = &emac_mii_bus_reset; 2584 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name); 2585 res = devm_of_mdiobus_register(&dev->ofdev->dev, bus, mii_np); 2586 if (res) { 2587 dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)", 2588 bus->name, res); 2589 } 2590 2591 put_node: 2592 of_node_put(mii_np); 2593 return res; 2594 } 2595 2596 static int emac_dt_phy_connect(struct emac_instance *dev, 2597 struct device_node *phy_handle) 2598 { 2599 struct phy_device *phy_dev; 2600 2601 dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def), 2602 GFP_KERNEL); 2603 if (!dev->phy.def) 2604 return -ENOMEM; 2605 2606 phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link, 0, 2607 dev->phy_mode); 2608 if (!phy_dev) { 2609 dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n"); 2610 return -ENODEV; 2611 } 2612 2613 dev->phy.def->phy_id = phy_dev->drv->phy_id; 2614 dev->phy.def->phy_id_mask = phy_dev->drv->phy_id_mask; 2615 dev->phy.def->name = phy_dev->drv->name; 2616 dev->phy.def->ops = &emac_dt_mdio_phy_ops; 2617 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.features, 2618 phy_dev->supported); 2619 dev->phy.address = phy_dev->mdio.addr; 2620 dev->phy.mode = phy_dev->interface; 2621 return 0; 2622 } 2623 2624 static int emac_dt_phy_probe(struct emac_instance *dev) 2625 { 2626 struct device_node *np = dev->ofdev->dev.of_node; 2627 struct device_node *phy_handle; 2628 int res = 1; 2629 2630 phy_handle = of_parse_phandle(np, "phy-handle", 0); 2631 2632 if (phy_handle) { 2633 res = emac_dt_mdio_probe(dev); 2634 if (!res) { 2635 res = emac_dt_phy_connect(dev, phy_handle); 2636 } 2637 } 2638 2639 of_node_put(phy_handle); 2640 return res; 2641 } 2642 2643 static int emac_init_phy(struct emac_instance *dev) 2644 { 2645 struct device_node *np = dev->ofdev->dev.of_node; 2646 struct net_device *ndev = dev->ndev; 2647 u32 phy_map, adv; 2648 int i; 2649 2650 dev->phy.dev = ndev; 2651 dev->phy.mode = dev->phy_mode; 2652 2653 /* PHY-less configuration. */ 2654 if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) || 2655 of_phy_is_fixed_link(np)) { 2656 emac_reset(dev); 2657 2658 /* PHY-less configuration. */ 2659 dev->phy.address = -1; 2660 dev->phy.features = SUPPORTED_MII; 2661 if (emac_phy_supports_gige(dev->phy_mode)) 2662 dev->phy.features |= SUPPORTED_1000baseT_Full; 2663 else 2664 dev->phy.features |= SUPPORTED_100baseT_Full; 2665 dev->phy.pause = 1; 2666 2667 if (of_phy_is_fixed_link(np)) { 2668 int res = emac_dt_mdio_probe(dev); 2669 2670 if (res) 2671 return res; 2672 2673 res = of_phy_register_fixed_link(np); 2674 ndev->phydev = of_phy_find_device(np); 2675 if (res || !ndev->phydev) 2676 return res ? res : -EINVAL; 2677 emac_adjust_link(dev->ndev); 2678 put_device(&ndev->phydev->mdio.dev); 2679 } 2680 return 0; 2681 } 2682 2683 mutex_lock(&emac_phy_map_lock); 2684 phy_map = dev->phy_map | busy_phy_map; 2685 2686 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map); 2687 2688 dev->phy.mdio_read = emac_mdio_read; 2689 dev->phy.mdio_write = emac_mdio_write; 2690 2691 /* Enable internal clock source */ 2692 #ifdef CONFIG_PPC_DCR_NATIVE 2693 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2694 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); 2695 #endif 2696 /* PHY clock workaround */ 2697 emac_rx_clk_tx(dev); 2698 2699 /* Enable internal clock source on 440GX*/ 2700 #ifdef CONFIG_PPC_DCR_NATIVE 2701 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2702 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); 2703 #endif 2704 /* Configure EMAC with defaults so we can at least use MDIO 2705 * This is needed mostly for 440GX 2706 */ 2707 if (emac_phy_gpcs(dev->phy.mode)) { 2708 /* XXX 2709 * Make GPCS PHY address equal to EMAC index. 2710 * We probably should take into account busy_phy_map 2711 * and/or phy_map here. 2712 * 2713 * Note that the busy_phy_map is currently global 2714 * while it should probably be per-ASIC... 2715 */ 2716 dev->phy.gpcs_address = dev->gpcs_address; 2717 if (dev->phy.gpcs_address == 0xffffffff) 2718 dev->phy.address = dev->cell_index; 2719 } 2720 2721 emac_configure(dev); 2722 2723 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) { 2724 int res = emac_dt_phy_probe(dev); 2725 2726 switch (res) { 2727 case 1: 2728 /* No phy-handle property configured. 2729 * Continue with the existing phy probe 2730 * and setup code. 2731 */ 2732 break; 2733 2734 case 0: 2735 mutex_unlock(&emac_phy_map_lock); 2736 goto init_phy; 2737 2738 default: 2739 mutex_unlock(&emac_phy_map_lock); 2740 dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n", 2741 res); 2742 return res; 2743 } 2744 } 2745 2746 if (dev->phy_address != 0xffffffff) 2747 phy_map = ~(1 << dev->phy_address); 2748 2749 for (i = 0; i < 0x20; phy_map >>= 1, ++i) 2750 if (!(phy_map & 1)) { 2751 int r; 2752 busy_phy_map |= 1 << i; 2753 2754 /* Quick check if there is a PHY at the address */ 2755 r = emac_mdio_read(dev->ndev, i, MII_BMCR); 2756 if (r == 0xffff || r < 0) 2757 continue; 2758 if (!emac_mii_phy_probe(&dev->phy, i)) 2759 break; 2760 } 2761 2762 /* Enable external clock source */ 2763 #ifdef CONFIG_PPC_DCR_NATIVE 2764 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2765 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0); 2766 #endif 2767 mutex_unlock(&emac_phy_map_lock); 2768 if (i == 0x20) { 2769 printk(KERN_WARNING "%pOF: can't find PHY!\n", np); 2770 return -ENXIO; 2771 } 2772 2773 init_phy: 2774 /* Init PHY */ 2775 if (dev->phy.def->ops->init) 2776 dev->phy.def->ops->init(&dev->phy); 2777 2778 /* Disable any PHY features not supported by the platform */ 2779 dev->phy.def->features &= ~dev->phy_feat_exc; 2780 dev->phy.features &= ~dev->phy_feat_exc; 2781 2782 /* Setup initial link parameters */ 2783 if (dev->phy.features & SUPPORTED_Autoneg) { 2784 adv = dev->phy.features; 2785 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x)) 2786 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 2787 /* Restart autonegotiation */ 2788 dev->phy.def->ops->setup_aneg(&dev->phy, adv); 2789 } else { 2790 u32 f = dev->phy.def->features; 2791 int speed = SPEED_10, fd = DUPLEX_HALF; 2792 2793 /* Select highest supported speed/duplex */ 2794 if (f & SUPPORTED_1000baseT_Full) { 2795 speed = SPEED_1000; 2796 fd = DUPLEX_FULL; 2797 } else if (f & SUPPORTED_1000baseT_Half) 2798 speed = SPEED_1000; 2799 else if (f & SUPPORTED_100baseT_Full) { 2800 speed = SPEED_100; 2801 fd = DUPLEX_FULL; 2802 } else if (f & SUPPORTED_100baseT_Half) 2803 speed = SPEED_100; 2804 else if (f & SUPPORTED_10baseT_Full) 2805 fd = DUPLEX_FULL; 2806 2807 /* Force link parameters */ 2808 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd); 2809 } 2810 return 0; 2811 } 2812 2813 static int emac_init_config(struct emac_instance *dev) 2814 { 2815 struct device_node *np = dev->ofdev->dev.of_node; 2816 int err; 2817 2818 /* Read config from device-tree */ 2819 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1)) 2820 return -ENXIO; 2821 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1)) 2822 return -ENXIO; 2823 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1)) 2824 return -ENXIO; 2825 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1)) 2826 return -ENXIO; 2827 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0)) 2828 dev->max_mtu = ETH_DATA_LEN; 2829 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0)) 2830 dev->rx_fifo_size = 2048; 2831 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0)) 2832 dev->tx_fifo_size = 2048; 2833 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0)) 2834 dev->rx_fifo_size_gige = dev->rx_fifo_size; 2835 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0)) 2836 dev->tx_fifo_size_gige = dev->tx_fifo_size; 2837 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0)) 2838 dev->phy_address = 0xffffffff; 2839 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0)) 2840 dev->phy_map = 0xffffffff; 2841 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0)) 2842 dev->gpcs_address = 0xffffffff; 2843 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1)) 2844 return -ENXIO; 2845 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0)) 2846 dev->tah_ph = 0; 2847 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0)) 2848 dev->tah_port = 0; 2849 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0)) 2850 dev->mdio_ph = 0; 2851 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0)) 2852 dev->zmii_ph = 0; 2853 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0)) 2854 dev->zmii_port = 0xffffffff; 2855 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0)) 2856 dev->rgmii_ph = 0; 2857 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0)) 2858 dev->rgmii_port = 0xffffffff; 2859 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0)) 2860 dev->fifo_entry_size = 16; 2861 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0)) 2862 dev->mal_burst_size = 256; 2863 2864 /* PHY mode needs some decoding */ 2865 err = of_get_phy_mode(np, &dev->phy_mode); 2866 if (err) 2867 dev->phy_mode = PHY_INTERFACE_MODE_NA; 2868 2869 /* Check EMAC version */ 2870 if (of_device_is_compatible(np, "ibm,emac4sync")) { 2871 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC); 2872 if (of_device_is_compatible(np, "ibm,emac-460ex") || 2873 of_device_is_compatible(np, "ibm,emac-460gt")) 2874 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX; 2875 if (of_device_is_compatible(np, "ibm,emac-405ex") || 2876 of_device_is_compatible(np, "ibm,emac-405exr")) 2877 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; 2878 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) { 2879 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE | 2880 EMAC_FTR_APM821XX_NO_HALF_DUPLEX | 2881 EMAC_FTR_460EX_PHY_CLK_FIX); 2882 } 2883 } else if (of_device_is_compatible(np, "ibm,emac4")) { 2884 dev->features |= EMAC_FTR_EMAC4; 2885 if (of_device_is_compatible(np, "ibm,emac-440gx")) 2886 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX; 2887 } else { 2888 if (of_device_is_compatible(np, "ibm,emac-440ep") || 2889 of_device_is_compatible(np, "ibm,emac-440gr")) 2890 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; 2891 if (of_device_is_compatible(np, "ibm,emac-405ez")) { 2892 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL 2893 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x; 2894 #else 2895 printk(KERN_ERR "%pOF: Flow control not disabled!\n", 2896 np); 2897 return -ENXIO; 2898 #endif 2899 } 2900 2901 } 2902 2903 /* Fixup some feature bits based on the device tree */ 2904 if (of_property_read_bool(np, "has-inverted-stacr-oc")) 2905 dev->features |= EMAC_FTR_STACR_OC_INVERT; 2906 if (of_property_read_bool(np, "has-new-stacr-staopc")) 2907 dev->features |= EMAC_FTR_HAS_NEW_STACR; 2908 2909 /* CAB lacks the appropriate properties */ 2910 if (of_device_is_compatible(np, "ibm,emac-axon")) 2911 dev->features |= EMAC_FTR_HAS_NEW_STACR | 2912 EMAC_FTR_STACR_OC_INVERT; 2913 2914 /* Enable TAH/ZMII/RGMII features as found */ 2915 if (dev->tah_ph != 0) { 2916 #ifdef CONFIG_IBM_EMAC_TAH 2917 dev->features |= EMAC_FTR_HAS_TAH; 2918 #else 2919 printk(KERN_ERR "%pOF: TAH support not enabled !\n", np); 2920 return -ENXIO; 2921 #endif 2922 } 2923 2924 if (dev->zmii_ph != 0) { 2925 #ifdef CONFIG_IBM_EMAC_ZMII 2926 dev->features |= EMAC_FTR_HAS_ZMII; 2927 #else 2928 printk(KERN_ERR "%pOF: ZMII support not enabled !\n", np); 2929 return -ENXIO; 2930 #endif 2931 } 2932 2933 if (dev->rgmii_ph != 0) { 2934 #ifdef CONFIG_IBM_EMAC_RGMII 2935 dev->features |= EMAC_FTR_HAS_RGMII; 2936 #else 2937 printk(KERN_ERR "%pOF: RGMII support not enabled !\n", np); 2938 return -ENXIO; 2939 #endif 2940 } 2941 2942 /* Read MAC-address */ 2943 err = of_get_ethdev_address(np, dev->ndev); 2944 if (err == -EPROBE_DEFER) 2945 return err; 2946 if (err) { 2947 dev_warn(&dev->ofdev->dev, "Can't get valid mac-address. Generating random."); 2948 eth_hw_addr_random(dev->ndev); 2949 } 2950 2951 /* IAHT and GAHT filter parameterization */ 2952 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) { 2953 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT; 2954 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT; 2955 } else { 2956 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT; 2957 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT; 2958 } 2959 2960 /* This should never happen */ 2961 if (WARN_ON(EMAC_XAHT_REGS(dev) > EMAC_XAHT_MAX_REGS)) 2962 return -ENXIO; 2963 2964 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE); 2965 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige); 2966 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige); 2967 DBG(dev, "max_mtu : %d\n", dev->max_mtu); 2968 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq); 2969 2970 return 0; 2971 } 2972 2973 static const struct net_device_ops emac_netdev_ops = { 2974 .ndo_open = emac_open, 2975 .ndo_stop = emac_close, 2976 .ndo_get_stats = emac_stats, 2977 .ndo_set_rx_mode = emac_set_multicast_list, 2978 .ndo_eth_ioctl = emac_ioctl, 2979 .ndo_tx_timeout = emac_tx_timeout, 2980 .ndo_validate_addr = eth_validate_addr, 2981 .ndo_set_mac_address = emac_set_mac_address, 2982 .ndo_start_xmit = emac_start_xmit, 2983 }; 2984 2985 static const struct net_device_ops emac_gige_netdev_ops = { 2986 .ndo_open = emac_open, 2987 .ndo_stop = emac_close, 2988 .ndo_get_stats = emac_stats, 2989 .ndo_set_rx_mode = emac_set_multicast_list, 2990 .ndo_eth_ioctl = emac_ioctl, 2991 .ndo_tx_timeout = emac_tx_timeout, 2992 .ndo_validate_addr = eth_validate_addr, 2993 .ndo_set_mac_address = emac_set_mac_address, 2994 .ndo_start_xmit = emac_start_xmit_sg, 2995 .ndo_change_mtu = emac_change_mtu, 2996 }; 2997 2998 static int emac_probe(struct platform_device *ofdev) 2999 { 3000 struct net_device *ndev; 3001 struct emac_instance *dev; 3002 struct device_node *np = ofdev->dev.of_node; 3003 struct device_node **blist = NULL; 3004 int err, i; 3005 3006 /* Skip unused/unwired EMACS. We leave the check for an unused 3007 * property here for now, but new flat device trees should set a 3008 * status property to "disabled" instead. 3009 */ 3010 if (of_property_read_bool(np, "unused") || !of_device_is_available(np)) 3011 return -ENODEV; 3012 3013 /* Find ourselves in the bootlist if we are there */ 3014 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++) 3015 if (emac_boot_list[i] == np) 3016 blist = &emac_boot_list[i]; 3017 3018 /* Allocate our net_device structure */ 3019 err = -ENOMEM; 3020 ndev = devm_alloc_etherdev(&ofdev->dev, sizeof(struct emac_instance)); 3021 if (!ndev) 3022 goto err_gone; 3023 3024 dev = netdev_priv(ndev); 3025 dev->ndev = ndev; 3026 dev->ofdev = ofdev; 3027 dev->blist = blist; 3028 SET_NETDEV_DEV(ndev, &ofdev->dev); 3029 3030 /* Initialize some embedded data structures */ 3031 err = devm_mutex_init(&ofdev->dev, &dev->mdio_lock); 3032 if (err) 3033 goto err_gone; 3034 3035 err = devm_mutex_init(&ofdev->dev, &dev->link_lock); 3036 if (err) 3037 goto err_gone; 3038 3039 spin_lock_init(&dev->lock); 3040 INIT_WORK(&dev->reset_work, emac_reset_work); 3041 3042 /* Init various config data based on device-tree */ 3043 err = emac_init_config(dev); 3044 if (err) 3045 goto err_gone; 3046 3047 /* Setup error IRQ handler */ 3048 dev->emac_irq = platform_get_irq(ofdev, 0); 3049 if (dev->emac_irq < 0) { 3050 err = dev->emac_irq; 3051 goto err_gone; 3052 } 3053 3054 err = devm_request_irq(&ofdev->dev, dev->emac_irq, emac_irq, 0, "EMAC", 3055 dev); 3056 if (err) { 3057 dev_err_probe(&ofdev->dev, err, "failed to request IRQ %d", 3058 dev->emac_irq); 3059 goto err_gone; 3060 } 3061 3062 ndev->irq = dev->emac_irq; 3063 3064 dev->emacp = devm_platform_ioremap_resource(ofdev, 0); 3065 if (IS_ERR(dev->emacp)) { 3066 dev_err(&ofdev->dev, "can't map device registers"); 3067 err = PTR_ERR(dev->emacp); 3068 goto err_gone; 3069 } 3070 3071 /* Wait for dependent devices */ 3072 err = emac_wait_deps(dev); 3073 if (err) 3074 goto err_gone; 3075 dev->mal = platform_get_drvdata(dev->mal_dev); 3076 if (dev->mdio_dev != NULL) 3077 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev); 3078 3079 /* Register with MAL */ 3080 dev->commac.ops = &emac_commac_ops; 3081 dev->commac.dev = dev; 3082 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan); 3083 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan); 3084 err = mal_register_commac(dev->mal, &dev->commac); 3085 if (err) { 3086 printk(KERN_ERR "%pOF: failed to register with mal %pOF!\n", 3087 np, dev->mal_dev->dev.of_node); 3088 goto err_rel_deps; 3089 } 3090 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu); 3091 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu); 3092 3093 /* Get pointers to BD rings */ 3094 dev->tx_desc = 3095 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan); 3096 dev->rx_desc = 3097 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan); 3098 3099 DBG(dev, "tx_desc %p" NL, dev->tx_desc); 3100 DBG(dev, "rx_desc %p" NL, dev->rx_desc); 3101 3102 /* Clean rings */ 3103 emac_clear_mal_desc(dev->tx_desc, NUM_TX_BUFF); 3104 emac_clear_mal_desc(dev->rx_desc, NUM_RX_BUFF); 3105 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *)); 3106 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *)); 3107 3108 /* Attach to ZMII, if needed */ 3109 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) && 3110 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0) 3111 goto err_unreg_commac; 3112 3113 /* Attach to RGMII, if needed */ 3114 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) && 3115 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0) 3116 goto err_detach_zmii; 3117 3118 /* Attach to TAH, if needed */ 3119 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) && 3120 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0) 3121 goto err_detach_rgmii; 3122 3123 /* Set some link defaults before we can find out real parameters */ 3124 dev->phy.speed = SPEED_100; 3125 dev->phy.duplex = DUPLEX_FULL; 3126 dev->phy.autoneg = AUTONEG_DISABLE; 3127 dev->phy.pause = dev->phy.asym_pause = 0; 3128 dev->stop_timeout = STOP_TIMEOUT_100; 3129 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer); 3130 3131 /* Some SoCs like APM821xx does not support Half Duplex mode. */ 3132 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) { 3133 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half | 3134 SUPPORTED_100baseT_Half | 3135 SUPPORTED_10baseT_Half); 3136 } 3137 3138 /* Find PHY if any */ 3139 err = emac_init_phy(dev); 3140 if (err != 0) 3141 goto err_detach_tah; 3142 3143 if (dev->tah_dev) { 3144 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG; 3145 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM; 3146 } 3147 ndev->watchdog_timeo = 5 * HZ; 3148 if (emac_phy_supports_gige(dev->phy_mode)) { 3149 ndev->netdev_ops = &emac_gige_netdev_ops; 3150 dev->commac.ops = &emac_commac_sg_ops; 3151 } else 3152 ndev->netdev_ops = &emac_netdev_ops; 3153 ndev->ethtool_ops = &emac_ethtool_ops; 3154 3155 /* MTU range: 46 - 1500 or whatever is in OF */ 3156 ndev->min_mtu = EMAC_MIN_MTU; 3157 ndev->max_mtu = dev->max_mtu; 3158 3159 netif_carrier_off(ndev); 3160 3161 err = devm_register_netdev(&ofdev->dev, ndev); 3162 if (err) { 3163 printk(KERN_ERR "%pOF: failed to register net device (%d)!\n", 3164 np, err); 3165 goto err_detach_tah; 3166 } 3167 3168 /* Set our drvdata last as we don't want them visible until we are 3169 * fully initialized 3170 */ 3171 wmb(); 3172 platform_set_drvdata(ofdev, dev); 3173 3174 printk(KERN_INFO "%s: EMAC-%d %pOF, MAC %pM\n", 3175 ndev->name, dev->cell_index, np, ndev->dev_addr); 3176 3177 if (dev->phy_mode == PHY_INTERFACE_MODE_SGMII) 3178 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name); 3179 3180 if (dev->phy.address >= 0) 3181 printk("%s: found %s PHY (0x%02x)\n", ndev->name, 3182 dev->phy.def->name, dev->phy.address); 3183 3184 /* Life is good */ 3185 return 0; 3186 3187 /* I have a bad feeling about this ... */ 3188 3189 err_detach_tah: 3190 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 3191 tah_detach(dev->tah_dev, dev->tah_port); 3192 err_detach_rgmii: 3193 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 3194 rgmii_detach(dev->rgmii_dev, dev->rgmii_port); 3195 err_detach_zmii: 3196 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 3197 zmii_detach(dev->zmii_dev, dev->zmii_port); 3198 err_unreg_commac: 3199 mal_unregister_commac(dev->mal, &dev->commac); 3200 err_rel_deps: 3201 emac_put_deps(dev); 3202 err_gone: 3203 if (blist) 3204 *blist = NULL; 3205 return err; 3206 } 3207 3208 static void emac_remove(struct platform_device *ofdev) 3209 { 3210 struct emac_instance *dev = platform_get_drvdata(ofdev); 3211 3212 DBG(dev, "remove" NL); 3213 3214 cancel_work_sync(&dev->reset_work); 3215 3216 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 3217 tah_detach(dev->tah_dev, dev->tah_port); 3218 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 3219 rgmii_detach(dev->rgmii_dev, dev->rgmii_port); 3220 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 3221 zmii_detach(dev->zmii_dev, dev->zmii_port); 3222 3223 busy_phy_map &= ~(1 << dev->phy.address); 3224 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map); 3225 3226 mal_unregister_commac(dev->mal, &dev->commac); 3227 emac_put_deps(dev); 3228 } 3229 3230 /* XXX Features in here should be replaced by properties... */ 3231 static const struct of_device_id emac_match[] = 3232 { 3233 { 3234 .type = "network", 3235 .compatible = "ibm,emac", 3236 }, 3237 { 3238 .type = "network", 3239 .compatible = "ibm,emac4", 3240 }, 3241 { 3242 .type = "network", 3243 .compatible = "ibm,emac4sync", 3244 }, 3245 {}, 3246 }; 3247 MODULE_DEVICE_TABLE(of, emac_match); 3248 3249 static struct platform_driver emac_driver = { 3250 .driver = { 3251 .name = "emac", 3252 .of_match_table = emac_match, 3253 }, 3254 .probe = emac_probe, 3255 .remove = emac_remove, 3256 }; 3257 3258 static void __init emac_make_bootlist(void) 3259 { 3260 struct device_node *np = NULL; 3261 int j, max, i = 0; 3262 int cell_indices[EMAC_BOOT_LIST_SIZE]; 3263 3264 /* Collect EMACs */ 3265 while((np = of_find_all_nodes(np)) != NULL) { 3266 u32 idx; 3267 3268 if (of_match_node(emac_match, np) == NULL) 3269 continue; 3270 if (of_property_read_bool(np, "unused")) 3271 continue; 3272 if (of_property_read_u32(np, "cell-index", &idx)) 3273 continue; 3274 cell_indices[i] = idx; 3275 emac_boot_list[i++] = of_node_get(np); 3276 if (i >= EMAC_BOOT_LIST_SIZE) { 3277 of_node_put(np); 3278 break; 3279 } 3280 } 3281 max = i; 3282 3283 /* Bubble sort them (doh, what a creative algorithm :-) */ 3284 for (i = 0; max > 1 && (i < (max - 1)); i++) 3285 for (j = i; j < max; j++) { 3286 if (cell_indices[i] > cell_indices[j]) { 3287 swap(emac_boot_list[i], emac_boot_list[j]); 3288 swap(cell_indices[i], cell_indices[j]); 3289 } 3290 } 3291 } 3292 3293 static int __init emac_init(void) 3294 { 3295 int rc; 3296 3297 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n"); 3298 3299 /* Build EMAC boot list */ 3300 emac_make_bootlist(); 3301 3302 /* Init submodules */ 3303 rc = mal_init(); 3304 if (rc) 3305 goto err; 3306 rc = zmii_init(); 3307 if (rc) 3308 goto err_mal; 3309 rc = rgmii_init(); 3310 if (rc) 3311 goto err_zmii; 3312 rc = tah_init(); 3313 if (rc) 3314 goto err_rgmii; 3315 rc = platform_driver_register(&emac_driver); 3316 if (rc) 3317 goto err_tah; 3318 3319 return 0; 3320 3321 err_tah: 3322 tah_exit(); 3323 err_rgmii: 3324 rgmii_exit(); 3325 err_zmii: 3326 zmii_exit(); 3327 err_mal: 3328 mal_exit(); 3329 err: 3330 return rc; 3331 } 3332 3333 static void __exit emac_exit(void) 3334 { 3335 int i; 3336 3337 platform_driver_unregister(&emac_driver); 3338 3339 tah_exit(); 3340 rgmii_exit(); 3341 zmii_exit(); 3342 mal_exit(); 3343 3344 /* Destroy EMAC boot list */ 3345 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++) 3346 of_node_put(emac_boot_list[i]); 3347 } 3348 3349 module_init(emac_init); 3350 module_exit(emac_exit); 3351