1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/net/ethernet/ibm/emac/core.c 4 * 5 * Driver for PowerPC 4xx on-chip ethernet controller. 6 * 7 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 8 * <benh@kernel.crashing.org> 9 * 10 * Based on the arch/ppc version of the driver: 11 * 12 * Copyright (c) 2004, 2005 Zultys Technologies. 13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 14 * 15 * Based on original work by 16 * Matt Porter <mporter@kernel.crashing.org> 17 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> 18 * Armin Kuster <akuster@mvista.com> 19 * Johnnie Peters <jpeters@mvista.com> 20 */ 21 22 #include <linux/module.h> 23 #include <linux/sched.h> 24 #include <linux/string.h> 25 #include <linux/errno.h> 26 #include <linux/delay.h> 27 #include <linux/types.h> 28 #include <linux/pci.h> 29 #include <linux/etherdevice.h> 30 #include <linux/skbuff.h> 31 #include <linux/crc32.h> 32 #include <linux/ethtool.h> 33 #include <linux/if_vlan.h> 34 #include <linux/mii.h> 35 #include <linux/bitops.h> 36 #include <linux/of.h> 37 #include <linux/of_address.h> 38 #include <linux/of_irq.h> 39 #include <linux/of_net.h> 40 #include <linux/of_mdio.h> 41 #include <linux/of_platform.h> 42 #include <linux/platform_device.h> 43 #include <linux/slab.h> 44 45 #include <asm/processor.h> 46 #include <asm/io.h> 47 #include <asm/dma.h> 48 #include <linux/uaccess.h> 49 #include <asm/dcr.h> 50 #include <asm/dcr-regs.h> 51 52 #include "core.h" 53 54 /* 55 * Lack of dma_unmap_???? calls is intentional. 56 * 57 * API-correct usage requires additional support state information to be 58 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to 59 * EMAC design (e.g. TX buffer passed from network stack can be split into 60 * several BDs, dma_map_single/dma_map_page can be used to map particular BD), 61 * maintaining such information will add additional overhead. 62 * Current DMA API implementation for 4xx processors only ensures cache coherency 63 * and dma_unmap_???? routines are empty and are likely to stay this way. 64 * I decided to omit dma_unmap_??? calls because I don't want to add additional 65 * complexity just for the sake of following some abstract API, when it doesn't 66 * add any real benefit to the driver. I understand that this decision maybe 67 * controversial, but I really tried to make code API-correct and efficient 68 * at the same time and didn't come up with code I liked :(. --ebs 69 */ 70 71 #define DRV_NAME "emac" 72 #define DRV_VERSION "3.54" 73 #define DRV_DESC "PPC 4xx OCP EMAC driver" 74 75 MODULE_DESCRIPTION(DRV_DESC); 76 MODULE_AUTHOR 77 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>"); 78 MODULE_LICENSE("GPL"); 79 80 /* minimum number of free TX descriptors required to wake up TX process */ 81 #define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4) 82 83 /* If packet size is less than this number, we allocate small skb and copy packet 84 * contents into it instead of just sending original big skb up 85 */ 86 #define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD 87 88 /* Since multiple EMACs share MDIO lines in various ways, we need 89 * to avoid re-using the same PHY ID in cases where the arch didn't 90 * setup precise phy_map entries 91 * 92 * XXX This is something that needs to be reworked as we can have multiple 93 * EMAC "sets" (multiple ASICs containing several EMACs) though we can 94 * probably require in that case to have explicit PHY IDs in the device-tree 95 */ 96 static u32 busy_phy_map; 97 static DEFINE_MUTEX(emac_phy_map_lock); 98 99 /* Having stable interface names is a doomed idea. However, it would be nice 100 * if we didn't have completely random interface names at boot too :-) It's 101 * just a matter of making everybody's life easier. Since we are doing 102 * threaded probing, it's a bit harder though. The base idea here is that 103 * we make up a list of all emacs in the device-tree before we register the 104 * driver. Every emac will then wait for the previous one in the list to 105 * initialize before itself. We should also keep that list ordered by 106 * cell_index. 107 * That list is only 4 entries long, meaning that additional EMACs don't 108 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased. 109 */ 110 111 #define EMAC_BOOT_LIST_SIZE 4 112 static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE]; 113 114 /* I don't want to litter system log with timeout errors 115 * when we have brain-damaged PHY. 116 */ 117 static inline void emac_report_timeout_error(struct emac_instance *dev, 118 const char *error) 119 { 120 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX | 121 EMAC_FTR_460EX_PHY_CLK_FIX | 122 EMAC_FTR_440EP_PHY_CLK_FIX)) 123 DBG(dev, "%s" NL, error); 124 else if (net_ratelimit()) 125 printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error); 126 } 127 128 /* EMAC PHY clock workaround: 129 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, 130 * which allows controlling each EMAC clock 131 */ 132 static inline void emac_rx_clk_tx(struct emac_instance *dev) 133 { 134 #ifdef CONFIG_PPC_DCR_NATIVE 135 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX)) 136 dcri_clrset(SDR0, SDR0_MFR, 137 0, SDR0_MFR_ECS >> dev->cell_index); 138 #endif 139 } 140 141 static inline void emac_rx_clk_default(struct emac_instance *dev) 142 { 143 #ifdef CONFIG_PPC_DCR_NATIVE 144 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX)) 145 dcri_clrset(SDR0, SDR0_MFR, 146 SDR0_MFR_ECS >> dev->cell_index, 0); 147 #endif 148 } 149 150 /* PHY polling intervals */ 151 #define PHY_POLL_LINK_ON HZ 152 #define PHY_POLL_LINK_OFF (HZ / 5) 153 154 /* Graceful stop timeouts in us. 155 * We should allow up to 1 frame time (full-duplex, ignoring collisions) 156 */ 157 #define STOP_TIMEOUT_10 1230 158 #define STOP_TIMEOUT_100 124 159 #define STOP_TIMEOUT_1000 13 160 #define STOP_TIMEOUT_1000_JUMBO 73 161 162 static unsigned char default_mcast_addr[] = { 163 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01 164 }; 165 166 /* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */ 167 static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = { 168 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum", 169 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom", 170 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu", 171 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet", 172 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error", 173 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range", 174 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun", 175 "rx_bad_packet", "rx_runt_packet", "rx_short_event", 176 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long", 177 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors", 178 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral", 179 "tx_bd_excessive_collisions", "tx_bd_late_collision", 180 "tx_bd_multple_collisions", "tx_bd_single_collision", 181 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe", 182 "tx_errors" 183 }; 184 185 static irqreturn_t emac_irq(int irq, void *dev_instance); 186 static void emac_clean_tx_ring(struct emac_instance *dev); 187 static void __emac_set_multicast_list(struct emac_instance *dev); 188 189 static inline int emac_phy_supports_gige(int phy_mode) 190 { 191 return phy_interface_mode_is_rgmii(phy_mode) || 192 phy_mode == PHY_INTERFACE_MODE_GMII || 193 phy_mode == PHY_INTERFACE_MODE_SGMII || 194 phy_mode == PHY_INTERFACE_MODE_TBI || 195 phy_mode == PHY_INTERFACE_MODE_RTBI; 196 } 197 198 static inline int emac_phy_gpcs(int phy_mode) 199 { 200 return phy_mode == PHY_INTERFACE_MODE_SGMII || 201 phy_mode == PHY_INTERFACE_MODE_TBI || 202 phy_mode == PHY_INTERFACE_MODE_RTBI; 203 } 204 205 static inline void emac_tx_enable(struct emac_instance *dev) 206 { 207 struct emac_regs __iomem *p = dev->emacp; 208 u32 r; 209 210 DBG(dev, "tx_enable" NL); 211 212 r = in_be32(&p->mr0); 213 if (!(r & EMAC_MR0_TXE)) 214 out_be32(&p->mr0, r | EMAC_MR0_TXE); 215 } 216 217 static void emac_tx_disable(struct emac_instance *dev) 218 { 219 struct emac_regs __iomem *p = dev->emacp; 220 u32 r; 221 222 DBG(dev, "tx_disable" NL); 223 224 r = in_be32(&p->mr0); 225 if (r & EMAC_MR0_TXE) { 226 int n = dev->stop_timeout; 227 out_be32(&p->mr0, r & ~EMAC_MR0_TXE); 228 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) { 229 udelay(1); 230 --n; 231 } 232 if (unlikely(!n)) 233 emac_report_timeout_error(dev, "TX disable timeout"); 234 } 235 } 236 237 static void emac_rx_enable(struct emac_instance *dev) 238 { 239 struct emac_regs __iomem *p = dev->emacp; 240 u32 r; 241 242 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) 243 goto out; 244 245 DBG(dev, "rx_enable" NL); 246 247 r = in_be32(&p->mr0); 248 if (!(r & EMAC_MR0_RXE)) { 249 if (unlikely(!(r & EMAC_MR0_RXI))) { 250 /* Wait if previous async disable is still in progress */ 251 int n = dev->stop_timeout; 252 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) { 253 udelay(1); 254 --n; 255 } 256 if (unlikely(!n)) 257 emac_report_timeout_error(dev, 258 "RX disable timeout"); 259 } 260 out_be32(&p->mr0, r | EMAC_MR0_RXE); 261 } 262 out: 263 ; 264 } 265 266 static void emac_rx_disable(struct emac_instance *dev) 267 { 268 struct emac_regs __iomem *p = dev->emacp; 269 u32 r; 270 271 DBG(dev, "rx_disable" NL); 272 273 r = in_be32(&p->mr0); 274 if (r & EMAC_MR0_RXE) { 275 int n = dev->stop_timeout; 276 out_be32(&p->mr0, r & ~EMAC_MR0_RXE); 277 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) { 278 udelay(1); 279 --n; 280 } 281 if (unlikely(!n)) 282 emac_report_timeout_error(dev, "RX disable timeout"); 283 } 284 } 285 286 static inline void emac_netif_stop(struct emac_instance *dev) 287 { 288 netif_tx_lock_bh(dev->ndev); 289 netif_addr_lock(dev->ndev); 290 dev->no_mcast = 1; 291 netif_addr_unlock(dev->ndev); 292 netif_tx_unlock_bh(dev->ndev); 293 netif_trans_update(dev->ndev); /* prevent tx timeout */ 294 mal_poll_disable(dev->mal, &dev->commac); 295 netif_tx_disable(dev->ndev); 296 } 297 298 static inline void emac_netif_start(struct emac_instance *dev) 299 { 300 netif_tx_lock_bh(dev->ndev); 301 netif_addr_lock(dev->ndev); 302 dev->no_mcast = 0; 303 if (dev->mcast_pending && netif_running(dev->ndev)) 304 __emac_set_multicast_list(dev); 305 netif_addr_unlock(dev->ndev); 306 netif_tx_unlock_bh(dev->ndev); 307 308 netif_wake_queue(dev->ndev); 309 310 /* NOTE: unconditional netif_wake_queue is only appropriate 311 * so long as all callers are assured to have free tx slots 312 * (taken from tg3... though the case where that is wrong is 313 * not terribly harmful) 314 */ 315 mal_poll_enable(dev->mal, &dev->commac); 316 } 317 318 static inline void emac_rx_disable_async(struct emac_instance *dev) 319 { 320 struct emac_regs __iomem *p = dev->emacp; 321 u32 r; 322 323 DBG(dev, "rx_disable_async" NL); 324 325 r = in_be32(&p->mr0); 326 if (r & EMAC_MR0_RXE) 327 out_be32(&p->mr0, r & ~EMAC_MR0_RXE); 328 } 329 330 static int emac_reset(struct emac_instance *dev) 331 { 332 struct emac_regs __iomem *p = dev->emacp; 333 int n = 20; 334 bool __maybe_unused try_internal_clock = false; 335 336 DBG(dev, "reset" NL); 337 338 if (!dev->reset_failed) { 339 /* 40x erratum suggests stopping RX channel before reset, 340 * we stop TX as well 341 */ 342 emac_rx_disable(dev); 343 emac_tx_disable(dev); 344 } 345 346 #ifdef CONFIG_PPC_DCR_NATIVE 347 do_retry: 348 /* 349 * PPC460EX/GT Embedded Processor Advanced User's Manual 350 * section 28.10.1 Mode Register 0 (EMACx_MR0) states: 351 * Note: The PHY must provide a TX Clk in order to perform a soft reset 352 * of the EMAC. If none is present, select the internal clock 353 * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1). 354 * After a soft reset, select the external clock. 355 * 356 * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the 357 * ethernet cable is not attached. This causes the reset to timeout 358 * and the PHY detection code in emac_init_phy() is unable to 359 * communicate and detect the AR8035-A PHY. As a result, the emac 360 * driver bails out early and the user has no ethernet. 361 * In order to stay compatible with existing configurations, the 362 * driver will temporarily switch to the internal clock, after 363 * the first reset fails. 364 */ 365 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { 366 if (try_internal_clock || (dev->phy_address == 0xffffffff && 367 dev->phy_map == 0xffffffff)) { 368 /* No PHY: select internal loop clock before reset */ 369 dcri_clrset(SDR0, SDR0_ETH_CFG, 370 0, SDR0_ETH_CFG_ECS << dev->cell_index); 371 } else { 372 /* PHY present: select external clock before reset */ 373 dcri_clrset(SDR0, SDR0_ETH_CFG, 374 SDR0_ETH_CFG_ECS << dev->cell_index, 0); 375 } 376 } 377 #endif 378 379 out_be32(&p->mr0, EMAC_MR0_SRST); 380 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n) 381 --n; 382 383 #ifdef CONFIG_PPC_DCR_NATIVE 384 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { 385 if (!n && !try_internal_clock) { 386 /* first attempt has timed out. */ 387 n = 20; 388 try_internal_clock = true; 389 goto do_retry; 390 } 391 392 if (try_internal_clock || (dev->phy_address == 0xffffffff && 393 dev->phy_map == 0xffffffff)) { 394 /* No PHY: restore external clock source after reset */ 395 dcri_clrset(SDR0, SDR0_ETH_CFG, 396 SDR0_ETH_CFG_ECS << dev->cell_index, 0); 397 } 398 } 399 #endif 400 401 if (n) { 402 dev->reset_failed = 0; 403 return 0; 404 } else { 405 emac_report_timeout_error(dev, "reset timeout"); 406 dev->reset_failed = 1; 407 return -ETIMEDOUT; 408 } 409 } 410 411 static void emac_hash_mc(struct emac_instance *dev) 412 { 413 u32 __iomem *gaht_base = emac_gaht_base(dev); 414 const int regs = EMAC_XAHT_REGS(dev); 415 u32 gaht_temp[EMAC_XAHT_MAX_REGS]; 416 struct netdev_hw_addr *ha; 417 int i; 418 419 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev)); 420 421 memset(gaht_temp, 0, sizeof (gaht_temp)); 422 423 netdev_for_each_mc_addr(ha, dev->ndev) { 424 int slot, reg, mask; 425 DBG2(dev, "mc %pM" NL, ha->addr); 426 427 slot = EMAC_XAHT_CRC_TO_SLOT(dev, 428 ether_crc(ETH_ALEN, ha->addr)); 429 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot); 430 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot); 431 432 gaht_temp[reg] |= mask; 433 } 434 435 for (i = 0; i < regs; i++) 436 out_be32(gaht_base + i, gaht_temp[i]); 437 } 438 439 static inline u32 emac_iff2rmr(struct net_device *ndev) 440 { 441 struct emac_instance *dev = netdev_priv(ndev); 442 u32 r; 443 444 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE; 445 446 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 447 r |= EMAC4_RMR_BASE; 448 else 449 r |= EMAC_RMR_BASE; 450 451 if (ndev->flags & IFF_PROMISC) 452 r |= EMAC_RMR_PME; 453 else if (ndev->flags & IFF_ALLMULTI || 454 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev))) 455 r |= EMAC_RMR_PMME; 456 else if (!netdev_mc_empty(ndev)) 457 r |= EMAC_RMR_MAE; 458 459 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) { 460 r &= ~EMAC4_RMR_MJS_MASK; 461 r |= EMAC4_RMR_MJS(ndev->mtu + VLAN_HLEN); 462 } 463 464 return r; 465 } 466 467 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 468 { 469 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT; 470 471 DBG2(dev, "__emac_calc_base_mr1" NL); 472 473 switch(tx_size) { 474 case 2048: 475 ret |= EMAC_MR1_TFS_2K; 476 break; 477 default: 478 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n", 479 dev->ndev->name, tx_size); 480 } 481 482 switch(rx_size) { 483 case 16384: 484 ret |= EMAC_MR1_RFS_16K; 485 break; 486 case 4096: 487 ret |= EMAC_MR1_RFS_4K; 488 break; 489 default: 490 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n", 491 dev->ndev->name, rx_size); 492 } 493 494 return ret; 495 } 496 497 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 498 { 499 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR | 500 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000); 501 502 DBG2(dev, "__emac4_calc_base_mr1" NL); 503 504 switch(tx_size) { 505 case 16384: 506 ret |= EMAC4_MR1_TFS_16K; 507 break; 508 case 8192: 509 ret |= EMAC4_MR1_TFS_8K; 510 break; 511 case 4096: 512 ret |= EMAC4_MR1_TFS_4K; 513 break; 514 case 2048: 515 ret |= EMAC4_MR1_TFS_2K; 516 break; 517 default: 518 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n", 519 dev->ndev->name, tx_size); 520 } 521 522 switch(rx_size) { 523 case 16384: 524 ret |= EMAC4_MR1_RFS_16K; 525 break; 526 case 8192: 527 ret |= EMAC4_MR1_RFS_8K; 528 break; 529 case 4096: 530 ret |= EMAC4_MR1_RFS_4K; 531 break; 532 case 2048: 533 ret |= EMAC4_MR1_RFS_2K; 534 break; 535 default: 536 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n", 537 dev->ndev->name, rx_size); 538 } 539 540 return ret; 541 } 542 543 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 544 { 545 return emac_has_feature(dev, EMAC_FTR_EMAC4) ? 546 __emac4_calc_base_mr1(dev, tx_size, rx_size) : 547 __emac_calc_base_mr1(dev, tx_size, rx_size); 548 } 549 550 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size) 551 { 552 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 553 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4; 554 else 555 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT; 556 } 557 558 static inline u32 emac_calc_rwmr(struct emac_instance *dev, 559 unsigned int low, unsigned int high) 560 { 561 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 562 return (low << 22) | ( (high & 0x3ff) << 6); 563 else 564 return (low << 23) | ( (high & 0x1ff) << 7); 565 } 566 567 static int emac_configure(struct emac_instance *dev) 568 { 569 struct emac_regs __iomem *p = dev->emacp; 570 struct net_device *ndev = dev->ndev; 571 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev); 572 u32 r, mr1 = 0; 573 574 DBG(dev, "configure" NL); 575 576 if (!link) { 577 out_be32(&p->mr1, in_be32(&p->mr1) 578 | EMAC_MR1_FDE | EMAC_MR1_ILE); 579 udelay(100); 580 } else if (emac_reset(dev) < 0) 581 return -ETIMEDOUT; 582 583 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 584 tah_reset(dev->tah_dev); 585 586 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n", 587 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause); 588 589 /* Default fifo sizes */ 590 tx_size = dev->tx_fifo_size; 591 rx_size = dev->rx_fifo_size; 592 593 /* No link, force loopback */ 594 if (!link) 595 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE; 596 597 /* Check for full duplex */ 598 else if (dev->phy.duplex == DUPLEX_FULL) 599 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001; 600 601 /* Adjust fifo sizes, mr1 and timeouts based on link speed */ 602 dev->stop_timeout = STOP_TIMEOUT_10; 603 switch (dev->phy.speed) { 604 case SPEED_1000: 605 if (emac_phy_gpcs(dev->phy.mode)) { 606 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA( 607 (dev->phy.gpcs_address != 0xffffffff) ? 608 dev->phy.gpcs_address : dev->phy.address); 609 610 /* Put some arbitrary OUI, Manuf & Rev IDs so we can 611 * identify this GPCS PHY later. 612 */ 613 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef); 614 } else 615 mr1 |= EMAC_MR1_MF_1000; 616 617 /* Extended fifo sizes */ 618 tx_size = dev->tx_fifo_size_gige; 619 rx_size = dev->rx_fifo_size_gige; 620 621 if (dev->ndev->mtu > ETH_DATA_LEN) { 622 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 623 mr1 |= EMAC4_MR1_JPSM; 624 else 625 mr1 |= EMAC_MR1_JPSM; 626 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO; 627 } else 628 dev->stop_timeout = STOP_TIMEOUT_1000; 629 break; 630 case SPEED_100: 631 mr1 |= EMAC_MR1_MF_100; 632 dev->stop_timeout = STOP_TIMEOUT_100; 633 break; 634 default: /* make gcc happy */ 635 break; 636 } 637 638 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 639 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port, 640 dev->phy.speed); 641 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 642 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed); 643 644 /* on 40x erratum forces us to NOT use integrated flow control, 645 * let's hope it works on 44x ;) 646 */ 647 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) && 648 dev->phy.duplex == DUPLEX_FULL) { 649 if (dev->phy.pause) 650 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP; 651 else if (dev->phy.asym_pause) 652 mr1 |= EMAC_MR1_APP; 653 } 654 655 /* Add base settings & fifo sizes & program MR1 */ 656 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size); 657 out_be32(&p->mr1, mr1); 658 659 /* Set individual MAC address */ 660 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]); 661 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) | 662 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) | 663 ndev->dev_addr[5]); 664 665 /* VLAN Tag Protocol ID */ 666 out_be32(&p->vtpid, 0x8100); 667 668 /* Receive mode register */ 669 r = emac_iff2rmr(ndev); 670 if (r & EMAC_RMR_MAE) 671 emac_hash_mc(dev); 672 out_be32(&p->rmr, r); 673 674 /* FIFOs thresholds */ 675 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 676 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1, 677 tx_size / 2 / dev->fifo_entry_size); 678 else 679 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1, 680 tx_size / 2 / dev->fifo_entry_size); 681 out_be32(&p->tmr1, r); 682 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2)); 683 684 /* PAUSE frame is sent when RX FIFO reaches its high-water mark, 685 there should be still enough space in FIFO to allow the our link 686 partner time to process this frame and also time to send PAUSE 687 frame itself. 688 689 Here is the worst case scenario for the RX FIFO "headroom" 690 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap): 691 692 1) One maximum-length frame on TX 1522 bytes 693 2) One PAUSE frame time 64 bytes 694 3) PAUSE frame decode time allowance 64 bytes 695 4) One maximum-length frame on RX 1522 bytes 696 5) Round-trip propagation delay of the link (100Mb) 15 bytes 697 ---------- 698 3187 bytes 699 700 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes) 701 low-water mark to RX_FIFO_SIZE / 8 (512 bytes) 702 */ 703 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size, 704 rx_size / 4 / dev->fifo_entry_size); 705 out_be32(&p->rwmr, r); 706 707 /* Set PAUSE timer to the maximum */ 708 out_be32(&p->ptr, 0xffff); 709 710 /* IRQ sources */ 711 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE | 712 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE | 713 EMAC_ISR_IRE | EMAC_ISR_TE; 714 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 715 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE | 716 EMAC4_ISR_RXOE | */; 717 out_be32(&p->iser, r); 718 719 /* We need to take GPCS PHY out of isolate mode after EMAC reset */ 720 if (emac_phy_gpcs(dev->phy.mode)) { 721 if (dev->phy.gpcs_address != 0xffffffff) 722 emac_mii_reset_gpcs(&dev->phy); 723 else 724 emac_mii_reset_phy(&dev->phy); 725 } 726 727 return 0; 728 } 729 730 static void emac_reinitialize(struct emac_instance *dev) 731 { 732 DBG(dev, "reinitialize" NL); 733 734 emac_netif_stop(dev); 735 if (!emac_configure(dev)) { 736 emac_tx_enable(dev); 737 emac_rx_enable(dev); 738 } 739 emac_netif_start(dev); 740 } 741 742 static void emac_full_tx_reset(struct emac_instance *dev) 743 { 744 DBG(dev, "full_tx_reset" NL); 745 746 emac_tx_disable(dev); 747 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan); 748 emac_clean_tx_ring(dev); 749 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0; 750 751 emac_configure(dev); 752 753 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan); 754 emac_tx_enable(dev); 755 emac_rx_enable(dev); 756 } 757 758 static void emac_reset_work(struct work_struct *work) 759 { 760 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work); 761 762 DBG(dev, "reset_work" NL); 763 764 mutex_lock(&dev->link_lock); 765 if (dev->opened) { 766 emac_netif_stop(dev); 767 emac_full_tx_reset(dev); 768 emac_netif_start(dev); 769 } 770 mutex_unlock(&dev->link_lock); 771 } 772 773 static void emac_tx_timeout(struct net_device *ndev, unsigned int txqueue) 774 { 775 struct emac_instance *dev = netdev_priv(ndev); 776 777 DBG(dev, "tx_timeout" NL); 778 779 schedule_work(&dev->reset_work); 780 } 781 782 783 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr) 784 { 785 int done = !!(stacr & EMAC_STACR_OC); 786 787 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 788 done = !done; 789 790 return done; 791 }; 792 793 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg) 794 { 795 struct emac_regs __iomem *p = dev->emacp; 796 u32 r = 0; 797 int n, err = -ETIMEDOUT; 798 799 mutex_lock(&dev->mdio_lock); 800 801 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg); 802 803 /* Enable proper MDIO port */ 804 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 805 zmii_get_mdio(dev->zmii_dev, dev->zmii_port); 806 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 807 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port); 808 809 /* Wait for management interface to become idle */ 810 n = 20; 811 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 812 udelay(1); 813 if (!--n) { 814 DBG2(dev, " -> timeout wait idle\n"); 815 goto bail; 816 } 817 } 818 819 /* Issue read command */ 820 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 821 r = EMAC4_STACR_BASE(dev->opb_bus_freq); 822 else 823 r = EMAC_STACR_BASE(dev->opb_bus_freq); 824 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 825 r |= EMAC_STACR_OC; 826 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR)) 827 r |= EMACX_STACR_STAC_READ; 828 else 829 r |= EMAC_STACR_STAC_READ; 830 r |= (reg & EMAC_STACR_PRA_MASK) 831 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT); 832 out_be32(&p->stacr, r); 833 834 /* Wait for read to complete */ 835 n = 200; 836 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) { 837 udelay(1); 838 if (!--n) { 839 DBG2(dev, " -> timeout wait complete\n"); 840 goto bail; 841 } 842 } 843 844 if (unlikely(r & EMAC_STACR_PHYE)) { 845 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg); 846 err = -EREMOTEIO; 847 goto bail; 848 } 849 850 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK); 851 852 DBG2(dev, "mdio_read -> %04x" NL, r); 853 err = 0; 854 bail: 855 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 856 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port); 857 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 858 zmii_put_mdio(dev->zmii_dev, dev->zmii_port); 859 mutex_unlock(&dev->mdio_lock); 860 861 return err == 0 ? r : err; 862 } 863 864 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg, 865 u16 val) 866 { 867 struct emac_regs __iomem *p = dev->emacp; 868 u32 r = 0; 869 int n; 870 871 mutex_lock(&dev->mdio_lock); 872 873 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val); 874 875 /* Enable proper MDIO port */ 876 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 877 zmii_get_mdio(dev->zmii_dev, dev->zmii_port); 878 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 879 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port); 880 881 /* Wait for management interface to be idle */ 882 n = 20; 883 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 884 udelay(1); 885 if (!--n) { 886 DBG2(dev, " -> timeout wait idle\n"); 887 goto bail; 888 } 889 } 890 891 /* Issue write command */ 892 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 893 r = EMAC4_STACR_BASE(dev->opb_bus_freq); 894 else 895 r = EMAC_STACR_BASE(dev->opb_bus_freq); 896 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 897 r |= EMAC_STACR_OC; 898 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR)) 899 r |= EMACX_STACR_STAC_WRITE; 900 else 901 r |= EMAC_STACR_STAC_WRITE; 902 r |= (reg & EMAC_STACR_PRA_MASK) | 903 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) | 904 (val << EMAC_STACR_PHYD_SHIFT); 905 out_be32(&p->stacr, r); 906 907 /* Wait for write to complete */ 908 n = 200; 909 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 910 udelay(1); 911 if (!--n) { 912 DBG2(dev, " -> timeout wait complete\n"); 913 goto bail; 914 } 915 } 916 bail: 917 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 918 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port); 919 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 920 zmii_put_mdio(dev->zmii_dev, dev->zmii_port); 921 mutex_unlock(&dev->mdio_lock); 922 } 923 924 static int emac_mdio_read(struct net_device *ndev, int id, int reg) 925 { 926 struct emac_instance *dev = netdev_priv(ndev); 927 int res; 928 929 res = __emac_mdio_read((dev->mdio_instance && 930 dev->phy.gpcs_address != id) ? 931 dev->mdio_instance : dev, 932 (u8) id, (u8) reg); 933 return res; 934 } 935 936 static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val) 937 { 938 struct emac_instance *dev = netdev_priv(ndev); 939 940 __emac_mdio_write((dev->mdio_instance && 941 dev->phy.gpcs_address != id) ? 942 dev->mdio_instance : dev, 943 (u8) id, (u8) reg, (u16) val); 944 } 945 946 /* Tx lock BH */ 947 static void __emac_set_multicast_list(struct emac_instance *dev) 948 { 949 struct emac_regs __iomem *p = dev->emacp; 950 u32 rmr = emac_iff2rmr(dev->ndev); 951 952 DBG(dev, "__multicast %08x" NL, rmr); 953 954 /* I decided to relax register access rules here to avoid 955 * full EMAC reset. 956 * 957 * There is a real problem with EMAC4 core if we use MWSW_001 bit 958 * in MR1 register and do a full EMAC reset. 959 * One TX BD status update is delayed and, after EMAC reset, it 960 * never happens, resulting in TX hung (it'll be recovered by TX 961 * timeout handler eventually, but this is just gross). 962 * So we either have to do full TX reset or try to cheat here :) 963 * 964 * The only required change is to RX mode register, so I *think* all 965 * we need is just to stop RX channel. This seems to work on all 966 * tested SoCs. --ebs 967 * 968 */ 969 dev->mcast_pending = 0; 970 emac_rx_disable(dev); 971 if (rmr & EMAC_RMR_MAE) 972 emac_hash_mc(dev); 973 out_be32(&p->rmr, rmr); 974 emac_rx_enable(dev); 975 } 976 977 /* Tx lock BH */ 978 static void emac_set_multicast_list(struct net_device *ndev) 979 { 980 struct emac_instance *dev = netdev_priv(ndev); 981 982 DBG(dev, "multicast" NL); 983 984 BUG_ON(!netif_running(dev->ndev)); 985 986 if (dev->no_mcast) { 987 dev->mcast_pending = 1; 988 return; 989 } 990 991 mutex_lock(&dev->link_lock); 992 __emac_set_multicast_list(dev); 993 mutex_unlock(&dev->link_lock); 994 } 995 996 static int emac_set_mac_address(struct net_device *ndev, void *sa) 997 { 998 struct emac_instance *dev = netdev_priv(ndev); 999 struct sockaddr *addr = sa; 1000 struct emac_regs __iomem *p = dev->emacp; 1001 1002 if (!is_valid_ether_addr(addr->sa_data)) 1003 return -EADDRNOTAVAIL; 1004 1005 mutex_lock(&dev->link_lock); 1006 1007 eth_hw_addr_set(ndev, addr->sa_data); 1008 1009 emac_rx_disable(dev); 1010 emac_tx_disable(dev); 1011 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]); 1012 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) | 1013 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) | 1014 ndev->dev_addr[5]); 1015 emac_tx_enable(dev); 1016 emac_rx_enable(dev); 1017 1018 mutex_unlock(&dev->link_lock); 1019 1020 return 0; 1021 } 1022 1023 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu) 1024 { 1025 int rx_sync_size = emac_rx_sync_size(new_mtu); 1026 int rx_skb_size = emac_rx_skb_size(new_mtu); 1027 int i, ret = 0; 1028 int mr1_jumbo_bit_change = 0; 1029 1030 mutex_lock(&dev->link_lock); 1031 emac_netif_stop(dev); 1032 emac_rx_disable(dev); 1033 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan); 1034 1035 if (dev->rx_sg_skb) { 1036 ++dev->estats.rx_dropped_resize; 1037 dev_kfree_skb(dev->rx_sg_skb); 1038 dev->rx_sg_skb = NULL; 1039 } 1040 1041 /* Make a first pass over RX ring and mark BDs ready, dropping 1042 * non-processed packets on the way. We need this as a separate pass 1043 * to simplify error recovery in the case of allocation failure later. 1044 */ 1045 for (i = 0; i < NUM_RX_BUFF; ++i) { 1046 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST) 1047 ++dev->estats.rx_dropped_resize; 1048 1049 dev->rx_desc[i].data_len = 0; 1050 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY | 1051 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1052 } 1053 1054 /* Reallocate RX ring only if bigger skb buffers are required */ 1055 if (rx_skb_size <= dev->rx_skb_size) 1056 goto skip; 1057 1058 /* Second pass, allocate new skbs */ 1059 for (i = 0; i < NUM_RX_BUFF; ++i) { 1060 struct sk_buff *skb; 1061 1062 skb = netdev_alloc_skb_ip_align(dev->ndev, rx_skb_size); 1063 if (!skb) { 1064 ret = -ENOMEM; 1065 goto oom; 1066 } 1067 1068 BUG_ON(!dev->rx_skb[i]); 1069 dev_kfree_skb(dev->rx_skb[i]); 1070 1071 dev->rx_desc[i].data_ptr = 1072 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN, 1073 rx_sync_size, DMA_FROM_DEVICE) 1074 + NET_IP_ALIGN; 1075 dev->rx_skb[i] = skb; 1076 } 1077 skip: 1078 /* Check if we need to change "Jumbo" bit in MR1 */ 1079 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) { 1080 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) || 1081 (dev->ndev->mtu > ETH_DATA_LEN); 1082 } else { 1083 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^ 1084 (dev->ndev->mtu > ETH_DATA_LEN); 1085 } 1086 1087 if (mr1_jumbo_bit_change) { 1088 /* This is to prevent starting RX channel in emac_rx_enable() */ 1089 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1090 1091 WRITE_ONCE(dev->ndev->mtu, new_mtu); 1092 emac_full_tx_reset(dev); 1093 } 1094 1095 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu)); 1096 oom: 1097 /* Restart RX */ 1098 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1099 dev->rx_slot = 0; 1100 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1101 emac_rx_enable(dev); 1102 emac_netif_start(dev); 1103 mutex_unlock(&dev->link_lock); 1104 1105 return ret; 1106 } 1107 1108 /* Process ctx, rtnl_lock semaphore */ 1109 static int emac_change_mtu(struct net_device *ndev, int new_mtu) 1110 { 1111 struct emac_instance *dev = netdev_priv(ndev); 1112 int ret = 0; 1113 1114 DBG(dev, "change_mtu(%d)" NL, new_mtu); 1115 1116 if (netif_running(ndev)) { 1117 /* Check if we really need to reinitialize RX ring */ 1118 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu)) 1119 ret = emac_resize_rx_ring(dev, new_mtu); 1120 } 1121 1122 if (!ret) { 1123 WRITE_ONCE(ndev->mtu, new_mtu); 1124 dev->rx_skb_size = emac_rx_skb_size(new_mtu); 1125 dev->rx_sync_size = emac_rx_sync_size(new_mtu); 1126 } 1127 1128 return ret; 1129 } 1130 1131 static void emac_clean_tx_ring(struct emac_instance *dev) 1132 { 1133 int i; 1134 1135 for (i = 0; i < NUM_TX_BUFF; ++i) { 1136 if (dev->tx_skb[i]) { 1137 dev_kfree_skb(dev->tx_skb[i]); 1138 dev->tx_skb[i] = NULL; 1139 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY) 1140 ++dev->estats.tx_dropped; 1141 } 1142 dev->tx_desc[i].ctrl = 0; 1143 dev->tx_desc[i].data_ptr = 0; 1144 } 1145 } 1146 1147 static void emac_clean_rx_ring(struct emac_instance *dev) 1148 { 1149 int i; 1150 1151 for (i = 0; i < NUM_RX_BUFF; ++i) 1152 if (dev->rx_skb[i]) { 1153 dev->rx_desc[i].ctrl = 0; 1154 dev_kfree_skb(dev->rx_skb[i]); 1155 dev->rx_skb[i] = NULL; 1156 dev->rx_desc[i].data_ptr = 0; 1157 } 1158 1159 if (dev->rx_sg_skb) { 1160 dev_kfree_skb(dev->rx_sg_skb); 1161 dev->rx_sg_skb = NULL; 1162 } 1163 } 1164 1165 static int 1166 __emac_prepare_rx_skb(struct sk_buff *skb, struct emac_instance *dev, int slot) 1167 { 1168 if (unlikely(!skb)) 1169 return -ENOMEM; 1170 1171 dev->rx_skb[slot] = skb; 1172 dev->rx_desc[slot].data_len = 0; 1173 1174 dev->rx_desc[slot].data_ptr = 1175 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN, 1176 dev->rx_sync_size, DMA_FROM_DEVICE) + NET_IP_ALIGN; 1177 wmb(); 1178 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY | 1179 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1180 1181 return 0; 1182 } 1183 1184 static int 1185 emac_alloc_rx_skb(struct emac_instance *dev, int slot) 1186 { 1187 struct sk_buff *skb; 1188 1189 skb = __netdev_alloc_skb_ip_align(dev->ndev, dev->rx_skb_size, 1190 GFP_KERNEL); 1191 1192 return __emac_prepare_rx_skb(skb, dev, slot); 1193 } 1194 1195 static int 1196 emac_alloc_rx_skb_napi(struct emac_instance *dev, int slot) 1197 { 1198 struct sk_buff *skb; 1199 1200 skb = napi_alloc_skb(&dev->mal->napi, dev->rx_skb_size); 1201 1202 return __emac_prepare_rx_skb(skb, dev, slot); 1203 } 1204 1205 static void emac_print_link_status(struct emac_instance *dev) 1206 { 1207 if (netif_carrier_ok(dev->ndev)) 1208 printk(KERN_INFO "%s: link is up, %d %s%s\n", 1209 dev->ndev->name, dev->phy.speed, 1210 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX", 1211 dev->phy.pause ? ", pause enabled" : 1212 dev->phy.asym_pause ? ", asymmetric pause enabled" : ""); 1213 else 1214 printk(KERN_INFO "%s: link is down\n", dev->ndev->name); 1215 } 1216 1217 /* Process ctx, rtnl_lock semaphore */ 1218 static int emac_open(struct net_device *ndev) 1219 { 1220 struct emac_instance *dev = netdev_priv(ndev); 1221 int i; 1222 1223 DBG(dev, "open" NL); 1224 1225 /* Allocate RX ring */ 1226 for (i = 0; i < NUM_RX_BUFF; ++i) 1227 if (emac_alloc_rx_skb(dev, i)) { 1228 printk(KERN_ERR "%s: failed to allocate RX ring\n", 1229 ndev->name); 1230 goto oom; 1231 } 1232 1233 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0; 1234 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1235 dev->rx_sg_skb = NULL; 1236 1237 mutex_lock(&dev->link_lock); 1238 dev->opened = 1; 1239 1240 /* Start PHY polling now. 1241 */ 1242 if (dev->phy.address >= 0) { 1243 int link_poll_interval; 1244 if (dev->phy.def->ops->poll_link(&dev->phy)) { 1245 dev->phy.def->ops->read_link(&dev->phy); 1246 emac_rx_clk_default(dev); 1247 netif_carrier_on(dev->ndev); 1248 link_poll_interval = PHY_POLL_LINK_ON; 1249 } else { 1250 emac_rx_clk_tx(dev); 1251 netif_carrier_off(dev->ndev); 1252 link_poll_interval = PHY_POLL_LINK_OFF; 1253 } 1254 dev->link_polling = 1; 1255 wmb(); 1256 schedule_delayed_work(&dev->link_work, link_poll_interval); 1257 emac_print_link_status(dev); 1258 } else 1259 netif_carrier_on(dev->ndev); 1260 1261 /* Required for Pause packet support in EMAC */ 1262 dev_mc_add_global(ndev, default_mcast_addr); 1263 1264 emac_configure(dev); 1265 mal_poll_add(dev->mal, &dev->commac); 1266 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan); 1267 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu)); 1268 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1269 emac_tx_enable(dev); 1270 emac_rx_enable(dev); 1271 emac_netif_start(dev); 1272 1273 mutex_unlock(&dev->link_lock); 1274 1275 return 0; 1276 oom: 1277 emac_clean_rx_ring(dev); 1278 return -ENOMEM; 1279 } 1280 1281 /* BHs disabled */ 1282 #if 0 1283 static int emac_link_differs(struct emac_instance *dev) 1284 { 1285 u32 r = in_be32(&dev->emacp->mr1); 1286 1287 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF; 1288 int speed, pause, asym_pause; 1289 1290 if (r & EMAC_MR1_MF_1000) 1291 speed = SPEED_1000; 1292 else if (r & EMAC_MR1_MF_100) 1293 speed = SPEED_100; 1294 else 1295 speed = SPEED_10; 1296 1297 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) { 1298 case (EMAC_MR1_EIFC | EMAC_MR1_APP): 1299 pause = 1; 1300 asym_pause = 0; 1301 break; 1302 case EMAC_MR1_APP: 1303 pause = 0; 1304 asym_pause = 1; 1305 break; 1306 default: 1307 pause = asym_pause = 0; 1308 } 1309 return speed != dev->phy.speed || duplex != dev->phy.duplex || 1310 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause; 1311 } 1312 #endif 1313 1314 static void emac_link_timer(struct work_struct *work) 1315 { 1316 struct emac_instance *dev = 1317 container_of(to_delayed_work(work), 1318 struct emac_instance, link_work); 1319 int link_poll_interval; 1320 1321 mutex_lock(&dev->link_lock); 1322 DBG2(dev, "link timer" NL); 1323 1324 if (!dev->opened) 1325 goto bail; 1326 1327 if (dev->phy.def->ops->poll_link(&dev->phy)) { 1328 if (!netif_carrier_ok(dev->ndev)) { 1329 emac_rx_clk_default(dev); 1330 /* Get new link parameters */ 1331 dev->phy.def->ops->read_link(&dev->phy); 1332 1333 netif_carrier_on(dev->ndev); 1334 emac_netif_stop(dev); 1335 emac_full_tx_reset(dev); 1336 emac_netif_start(dev); 1337 emac_print_link_status(dev); 1338 } 1339 link_poll_interval = PHY_POLL_LINK_ON; 1340 } else { 1341 if (netif_carrier_ok(dev->ndev)) { 1342 emac_rx_clk_tx(dev); 1343 netif_carrier_off(dev->ndev); 1344 netif_tx_disable(dev->ndev); 1345 emac_reinitialize(dev); 1346 emac_print_link_status(dev); 1347 } 1348 link_poll_interval = PHY_POLL_LINK_OFF; 1349 } 1350 schedule_delayed_work(&dev->link_work, link_poll_interval); 1351 bail: 1352 mutex_unlock(&dev->link_lock); 1353 } 1354 1355 static void emac_force_link_update(struct emac_instance *dev) 1356 { 1357 netif_carrier_off(dev->ndev); 1358 smp_rmb(); 1359 if (dev->link_polling) { 1360 cancel_delayed_work_sync(&dev->link_work); 1361 if (dev->link_polling) 1362 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF); 1363 } 1364 } 1365 1366 /* Process ctx, rtnl_lock semaphore */ 1367 static int emac_close(struct net_device *ndev) 1368 { 1369 struct emac_instance *dev = netdev_priv(ndev); 1370 1371 DBG(dev, "close" NL); 1372 1373 if (dev->phy.address >= 0) { 1374 dev->link_polling = 0; 1375 cancel_delayed_work_sync(&dev->link_work); 1376 } 1377 mutex_lock(&dev->link_lock); 1378 emac_netif_stop(dev); 1379 dev->opened = 0; 1380 mutex_unlock(&dev->link_lock); 1381 1382 emac_rx_disable(dev); 1383 emac_tx_disable(dev); 1384 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan); 1385 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan); 1386 mal_poll_del(dev->mal, &dev->commac); 1387 1388 emac_clean_tx_ring(dev); 1389 emac_clean_rx_ring(dev); 1390 1391 netif_carrier_off(ndev); 1392 1393 return 0; 1394 } 1395 1396 static inline u16 emac_tx_csum(struct emac_instance *dev, 1397 struct sk_buff *skb) 1398 { 1399 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) && 1400 (skb->ip_summed == CHECKSUM_PARTIAL)) { 1401 ++dev->stats.tx_packets_csum; 1402 return EMAC_TX_CTRL_TAH_CSUM; 1403 } 1404 return 0; 1405 } 1406 1407 static inline netdev_tx_t emac_xmit_finish(struct emac_instance *dev, int len) 1408 { 1409 struct emac_regs __iomem *p = dev->emacp; 1410 struct net_device *ndev = dev->ndev; 1411 1412 /* Send the packet out. If the if makes a significant perf 1413 * difference, then we can store the TMR0 value in "dev" 1414 * instead 1415 */ 1416 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 1417 out_be32(&p->tmr0, EMAC4_TMR0_XMIT); 1418 else 1419 out_be32(&p->tmr0, EMAC_TMR0_XMIT); 1420 1421 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) { 1422 netif_stop_queue(ndev); 1423 DBG2(dev, "stopped TX queue" NL); 1424 } 1425 1426 netif_trans_update(ndev); 1427 ++dev->stats.tx_packets; 1428 dev->stats.tx_bytes += len; 1429 1430 return NETDEV_TX_OK; 1431 } 1432 1433 /* Tx lock BH */ 1434 static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1435 { 1436 struct emac_instance *dev = netdev_priv(ndev); 1437 unsigned int len = skb->len; 1438 int slot; 1439 1440 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY | 1441 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb); 1442 1443 slot = dev->tx_slot++; 1444 if (dev->tx_slot == NUM_TX_BUFF) { 1445 dev->tx_slot = 0; 1446 ctrl |= MAL_TX_CTRL_WRAP; 1447 } 1448 1449 DBG2(dev, "xmit(%u) %d" NL, len, slot); 1450 1451 dev->tx_skb[slot] = skb; 1452 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev, 1453 skb->data, len, 1454 DMA_TO_DEVICE); 1455 dev->tx_desc[slot].data_len = (u16) len; 1456 wmb(); 1457 dev->tx_desc[slot].ctrl = ctrl; 1458 1459 return emac_xmit_finish(dev, len); 1460 } 1461 1462 static inline int emac_xmit_split(struct emac_instance *dev, int slot, 1463 u32 pd, int len, int last, u16 base_ctrl) 1464 { 1465 while (1) { 1466 u16 ctrl = base_ctrl; 1467 int chunk = min(len, MAL_MAX_TX_SIZE); 1468 len -= chunk; 1469 1470 slot = (slot + 1) % NUM_TX_BUFF; 1471 1472 if (last && !len) 1473 ctrl |= MAL_TX_CTRL_LAST; 1474 if (slot == NUM_TX_BUFF - 1) 1475 ctrl |= MAL_TX_CTRL_WRAP; 1476 1477 dev->tx_skb[slot] = NULL; 1478 dev->tx_desc[slot].data_ptr = pd; 1479 dev->tx_desc[slot].data_len = (u16) chunk; 1480 dev->tx_desc[slot].ctrl = ctrl; 1481 ++dev->tx_cnt; 1482 1483 if (!len) 1484 break; 1485 1486 pd += chunk; 1487 } 1488 return slot; 1489 } 1490 1491 /* Tx lock BH disabled (SG version for TAH equipped EMACs) */ 1492 static netdev_tx_t 1493 emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev) 1494 { 1495 struct emac_instance *dev = netdev_priv(ndev); 1496 int nr_frags = skb_shinfo(skb)->nr_frags; 1497 int len = skb->len, chunk; 1498 int slot, i; 1499 u16 ctrl; 1500 u32 pd; 1501 1502 /* This is common "fast" path */ 1503 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE)) 1504 return emac_start_xmit(skb, ndev); 1505 1506 len -= skb->data_len; 1507 1508 /* Note, this is only an *estimation*, we can still run out of empty 1509 * slots because of the additional fragmentation into 1510 * MAL_MAX_TX_SIZE-sized chunks 1511 */ 1512 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF)) 1513 goto stop_queue; 1514 1515 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY | 1516 emac_tx_csum(dev, skb); 1517 slot = dev->tx_slot; 1518 1519 /* skb data */ 1520 dev->tx_skb[slot] = NULL; 1521 chunk = min(len, MAL_MAX_TX_SIZE); 1522 dev->tx_desc[slot].data_ptr = pd = 1523 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE); 1524 dev->tx_desc[slot].data_len = (u16) chunk; 1525 len -= chunk; 1526 if (unlikely(len)) 1527 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags, 1528 ctrl); 1529 /* skb fragments */ 1530 for (i = 0; i < nr_frags; ++i) { 1531 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1532 len = skb_frag_size(frag); 1533 1534 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF)) 1535 goto undo_frame; 1536 1537 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len, 1538 DMA_TO_DEVICE); 1539 1540 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1, 1541 ctrl); 1542 } 1543 1544 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot); 1545 1546 /* Attach skb to the last slot so we don't release it too early */ 1547 dev->tx_skb[slot] = skb; 1548 1549 /* Send the packet out */ 1550 if (dev->tx_slot == NUM_TX_BUFF - 1) 1551 ctrl |= MAL_TX_CTRL_WRAP; 1552 wmb(); 1553 dev->tx_desc[dev->tx_slot].ctrl = ctrl; 1554 dev->tx_slot = (slot + 1) % NUM_TX_BUFF; 1555 1556 return emac_xmit_finish(dev, skb->len); 1557 1558 undo_frame: 1559 /* Well, too bad. Our previous estimation was overly optimistic. 1560 * Undo everything. 1561 */ 1562 while (slot != dev->tx_slot) { 1563 dev->tx_desc[slot].ctrl = 0; 1564 --dev->tx_cnt; 1565 if (--slot < 0) 1566 slot = NUM_TX_BUFF - 1; 1567 } 1568 ++dev->estats.tx_undo; 1569 1570 stop_queue: 1571 netif_stop_queue(ndev); 1572 DBG2(dev, "stopped TX queue" NL); 1573 return NETDEV_TX_BUSY; 1574 } 1575 1576 /* Tx lock BHs */ 1577 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl) 1578 { 1579 struct emac_error_stats *st = &dev->estats; 1580 1581 DBG(dev, "BD TX error %04x" NL, ctrl); 1582 1583 ++st->tx_bd_errors; 1584 if (ctrl & EMAC_TX_ST_BFCS) 1585 ++st->tx_bd_bad_fcs; 1586 if (ctrl & EMAC_TX_ST_LCS) 1587 ++st->tx_bd_carrier_loss; 1588 if (ctrl & EMAC_TX_ST_ED) 1589 ++st->tx_bd_excessive_deferral; 1590 if (ctrl & EMAC_TX_ST_EC) 1591 ++st->tx_bd_excessive_collisions; 1592 if (ctrl & EMAC_TX_ST_LC) 1593 ++st->tx_bd_late_collision; 1594 if (ctrl & EMAC_TX_ST_MC) 1595 ++st->tx_bd_multple_collisions; 1596 if (ctrl & EMAC_TX_ST_SC) 1597 ++st->tx_bd_single_collision; 1598 if (ctrl & EMAC_TX_ST_UR) 1599 ++st->tx_bd_underrun; 1600 if (ctrl & EMAC_TX_ST_SQE) 1601 ++st->tx_bd_sqe; 1602 } 1603 1604 static void emac_poll_tx(void *param) 1605 { 1606 struct emac_instance *dev = param; 1607 u32 bad_mask; 1608 1609 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot); 1610 1611 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 1612 bad_mask = EMAC_IS_BAD_TX_TAH; 1613 else 1614 bad_mask = EMAC_IS_BAD_TX; 1615 1616 netif_tx_lock_bh(dev->ndev); 1617 if (dev->tx_cnt) { 1618 u16 ctrl; 1619 int slot = dev->ack_slot, n = 0; 1620 again: 1621 ctrl = dev->tx_desc[slot].ctrl; 1622 if (!(ctrl & MAL_TX_CTRL_READY)) { 1623 struct sk_buff *skb = dev->tx_skb[slot]; 1624 ++n; 1625 1626 if (skb) { 1627 dev_kfree_skb(skb); 1628 dev->tx_skb[slot] = NULL; 1629 } 1630 slot = (slot + 1) % NUM_TX_BUFF; 1631 1632 if (unlikely(ctrl & bad_mask)) 1633 emac_parse_tx_error(dev, ctrl); 1634 1635 if (--dev->tx_cnt) 1636 goto again; 1637 } 1638 if (n) { 1639 dev->ack_slot = slot; 1640 if (netif_queue_stopped(dev->ndev) && 1641 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH) 1642 netif_wake_queue(dev->ndev); 1643 1644 DBG2(dev, "tx %d pkts" NL, n); 1645 } 1646 } 1647 netif_tx_unlock_bh(dev->ndev); 1648 } 1649 1650 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot, 1651 int len) 1652 { 1653 struct sk_buff *skb = dev->rx_skb[slot]; 1654 1655 DBG2(dev, "recycle %d %d" NL, slot, len); 1656 1657 if (len) 1658 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN, 1659 SKB_DATA_ALIGN(len + NET_IP_ALIGN), 1660 DMA_FROM_DEVICE); 1661 1662 dev->rx_desc[slot].data_len = 0; 1663 wmb(); 1664 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY | 1665 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1666 } 1667 1668 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl) 1669 { 1670 struct emac_error_stats *st = &dev->estats; 1671 1672 DBG(dev, "BD RX error %04x" NL, ctrl); 1673 1674 ++st->rx_bd_errors; 1675 if (ctrl & EMAC_RX_ST_OE) 1676 ++st->rx_bd_overrun; 1677 if (ctrl & EMAC_RX_ST_BP) 1678 ++st->rx_bd_bad_packet; 1679 if (ctrl & EMAC_RX_ST_RP) 1680 ++st->rx_bd_runt_packet; 1681 if (ctrl & EMAC_RX_ST_SE) 1682 ++st->rx_bd_short_event; 1683 if (ctrl & EMAC_RX_ST_AE) 1684 ++st->rx_bd_alignment_error; 1685 if (ctrl & EMAC_RX_ST_BFCS) 1686 ++st->rx_bd_bad_fcs; 1687 if (ctrl & EMAC_RX_ST_PTL) 1688 ++st->rx_bd_packet_too_long; 1689 if (ctrl & EMAC_RX_ST_ORE) 1690 ++st->rx_bd_out_of_range; 1691 if (ctrl & EMAC_RX_ST_IRE) 1692 ++st->rx_bd_in_range; 1693 } 1694 1695 static inline void emac_rx_csum(struct emac_instance *dev, 1696 struct sk_buff *skb, u16 ctrl) 1697 { 1698 #ifdef CONFIG_IBM_EMAC_TAH 1699 if (!ctrl && dev->tah_dev) { 1700 skb->ip_summed = CHECKSUM_UNNECESSARY; 1701 ++dev->stats.rx_packets_csum; 1702 } 1703 #endif 1704 } 1705 1706 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot) 1707 { 1708 if (likely(dev->rx_sg_skb != NULL)) { 1709 int len = dev->rx_desc[slot].data_len; 1710 int tot_len = dev->rx_sg_skb->len + len; 1711 1712 if (unlikely(tot_len + NET_IP_ALIGN > dev->rx_skb_size)) { 1713 ++dev->estats.rx_dropped_mtu; 1714 dev_kfree_skb(dev->rx_sg_skb); 1715 dev->rx_sg_skb = NULL; 1716 } else { 1717 memcpy(skb_tail_pointer(dev->rx_sg_skb), 1718 dev->rx_skb[slot]->data, len); 1719 skb_put(dev->rx_sg_skb, len); 1720 emac_recycle_rx_skb(dev, slot, len); 1721 return 0; 1722 } 1723 } 1724 emac_recycle_rx_skb(dev, slot, 0); 1725 return -1; 1726 } 1727 1728 /* NAPI poll context */ 1729 static int emac_poll_rx(void *param, int budget) 1730 { 1731 struct emac_instance *dev = param; 1732 int slot = dev->rx_slot, received = 0; 1733 1734 DBG2(dev, "poll_rx(%d)" NL, budget); 1735 1736 again: 1737 while (budget > 0) { 1738 int len; 1739 struct sk_buff *skb; 1740 u16 ctrl = dev->rx_desc[slot].ctrl; 1741 1742 if (ctrl & MAL_RX_CTRL_EMPTY) 1743 break; 1744 1745 skb = dev->rx_skb[slot]; 1746 mb(); 1747 len = dev->rx_desc[slot].data_len; 1748 1749 if (unlikely(!MAL_IS_SINGLE_RX(ctrl))) 1750 goto sg; 1751 1752 ctrl &= EMAC_BAD_RX_MASK; 1753 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) { 1754 emac_parse_rx_error(dev, ctrl); 1755 ++dev->estats.rx_dropped_error; 1756 emac_recycle_rx_skb(dev, slot, 0); 1757 len = 0; 1758 goto next; 1759 } 1760 1761 if (len < ETH_HLEN) { 1762 ++dev->estats.rx_dropped_stack; 1763 emac_recycle_rx_skb(dev, slot, len); 1764 goto next; 1765 } 1766 1767 if (len && len < EMAC_RX_COPY_THRESH) { 1768 struct sk_buff *copy_skb; 1769 1770 copy_skb = napi_alloc_skb(&dev->mal->napi, len); 1771 if (unlikely(!copy_skb)) 1772 goto oom; 1773 1774 memcpy(copy_skb->data - NET_IP_ALIGN, 1775 skb->data - NET_IP_ALIGN, 1776 len + NET_IP_ALIGN); 1777 emac_recycle_rx_skb(dev, slot, len); 1778 skb = copy_skb; 1779 } else if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) 1780 goto oom; 1781 1782 skb_put(skb, len); 1783 push_packet: 1784 skb->protocol = eth_type_trans(skb, dev->ndev); 1785 emac_rx_csum(dev, skb, ctrl); 1786 1787 napi_gro_receive(&dev->mal->napi, skb); 1788 next: 1789 ++dev->stats.rx_packets; 1790 skip: 1791 dev->stats.rx_bytes += len; 1792 slot = (slot + 1) % NUM_RX_BUFF; 1793 --budget; 1794 ++received; 1795 continue; 1796 sg: 1797 if (ctrl & MAL_RX_CTRL_FIRST) { 1798 BUG_ON(dev->rx_sg_skb); 1799 if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) { 1800 DBG(dev, "rx OOM %d" NL, slot); 1801 ++dev->estats.rx_dropped_oom; 1802 emac_recycle_rx_skb(dev, slot, 0); 1803 } else { 1804 dev->rx_sg_skb = skb; 1805 skb_put(skb, len); 1806 } 1807 } else if (!emac_rx_sg_append(dev, slot) && 1808 (ctrl & MAL_RX_CTRL_LAST)) { 1809 1810 skb = dev->rx_sg_skb; 1811 dev->rx_sg_skb = NULL; 1812 1813 ctrl &= EMAC_BAD_RX_MASK; 1814 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) { 1815 emac_parse_rx_error(dev, ctrl); 1816 ++dev->estats.rx_dropped_error; 1817 dev_kfree_skb(skb); 1818 len = 0; 1819 } else 1820 goto push_packet; 1821 } 1822 goto skip; 1823 oom: 1824 DBG(dev, "rx OOM %d" NL, slot); 1825 /* Drop the packet and recycle skb */ 1826 ++dev->estats.rx_dropped_oom; 1827 emac_recycle_rx_skb(dev, slot, 0); 1828 goto next; 1829 } 1830 1831 if (received) { 1832 DBG2(dev, "rx %d BDs" NL, received); 1833 dev->rx_slot = slot; 1834 } 1835 1836 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) { 1837 mb(); 1838 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) { 1839 DBG2(dev, "rx restart" NL); 1840 received = 0; 1841 goto again; 1842 } 1843 1844 if (dev->rx_sg_skb) { 1845 DBG2(dev, "dropping partial rx packet" NL); 1846 ++dev->estats.rx_dropped_error; 1847 dev_kfree_skb(dev->rx_sg_skb); 1848 dev->rx_sg_skb = NULL; 1849 } 1850 1851 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1852 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1853 emac_rx_enable(dev); 1854 dev->rx_slot = 0; 1855 } 1856 return received; 1857 } 1858 1859 /* NAPI poll context */ 1860 static int emac_peek_rx(void *param) 1861 { 1862 struct emac_instance *dev = param; 1863 1864 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY); 1865 } 1866 1867 /* NAPI poll context */ 1868 static int emac_peek_rx_sg(void *param) 1869 { 1870 struct emac_instance *dev = param; 1871 1872 int slot = dev->rx_slot; 1873 while (1) { 1874 u16 ctrl = dev->rx_desc[slot].ctrl; 1875 if (ctrl & MAL_RX_CTRL_EMPTY) 1876 return 0; 1877 else if (ctrl & MAL_RX_CTRL_LAST) 1878 return 1; 1879 1880 slot = (slot + 1) % NUM_RX_BUFF; 1881 1882 /* I'm just being paranoid here :) */ 1883 if (unlikely(slot == dev->rx_slot)) 1884 return 0; 1885 } 1886 } 1887 1888 /* Hard IRQ */ 1889 static void emac_rxde(void *param) 1890 { 1891 struct emac_instance *dev = param; 1892 1893 ++dev->estats.rx_stopped; 1894 emac_rx_disable_async(dev); 1895 } 1896 1897 /* Hard IRQ */ 1898 static irqreturn_t emac_irq(int irq, void *dev_instance) 1899 { 1900 struct emac_instance *dev = dev_instance; 1901 struct emac_regs __iomem *p = dev->emacp; 1902 struct emac_error_stats *st = &dev->estats; 1903 u32 isr; 1904 1905 spin_lock(&dev->lock); 1906 1907 isr = in_be32(&p->isr); 1908 out_be32(&p->isr, isr); 1909 1910 DBG(dev, "isr = %08x" NL, isr); 1911 1912 if (isr & EMAC4_ISR_TXPE) 1913 ++st->tx_parity; 1914 if (isr & EMAC4_ISR_RXPE) 1915 ++st->rx_parity; 1916 if (isr & EMAC4_ISR_TXUE) 1917 ++st->tx_underrun; 1918 if (isr & EMAC4_ISR_RXOE) 1919 ++st->rx_fifo_overrun; 1920 if (isr & EMAC_ISR_OVR) 1921 ++st->rx_overrun; 1922 if (isr & EMAC_ISR_BP) 1923 ++st->rx_bad_packet; 1924 if (isr & EMAC_ISR_RP) 1925 ++st->rx_runt_packet; 1926 if (isr & EMAC_ISR_SE) 1927 ++st->rx_short_event; 1928 if (isr & EMAC_ISR_ALE) 1929 ++st->rx_alignment_error; 1930 if (isr & EMAC_ISR_BFCS) 1931 ++st->rx_bad_fcs; 1932 if (isr & EMAC_ISR_PTLE) 1933 ++st->rx_packet_too_long; 1934 if (isr & EMAC_ISR_ORE) 1935 ++st->rx_out_of_range; 1936 if (isr & EMAC_ISR_IRE) 1937 ++st->rx_in_range; 1938 if (isr & EMAC_ISR_SQE) 1939 ++st->tx_sqe; 1940 if (isr & EMAC_ISR_TE) 1941 ++st->tx_errors; 1942 1943 spin_unlock(&dev->lock); 1944 1945 return IRQ_HANDLED; 1946 } 1947 1948 static struct net_device_stats *emac_stats(struct net_device *ndev) 1949 { 1950 struct emac_instance *dev = netdev_priv(ndev); 1951 struct emac_stats *st = &dev->stats; 1952 struct emac_error_stats *est = &dev->estats; 1953 struct net_device_stats *nst = &ndev->stats; 1954 unsigned long flags; 1955 1956 DBG2(dev, "stats" NL); 1957 1958 /* Compute "legacy" statistics */ 1959 spin_lock_irqsave(&dev->lock, flags); 1960 nst->rx_packets = (unsigned long)st->rx_packets; 1961 nst->rx_bytes = (unsigned long)st->rx_bytes; 1962 nst->tx_packets = (unsigned long)st->tx_packets; 1963 nst->tx_bytes = (unsigned long)st->tx_bytes; 1964 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom + 1965 est->rx_dropped_error + 1966 est->rx_dropped_resize + 1967 est->rx_dropped_mtu); 1968 nst->tx_dropped = (unsigned long)est->tx_dropped; 1969 1970 nst->rx_errors = (unsigned long)est->rx_bd_errors; 1971 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun + 1972 est->rx_fifo_overrun + 1973 est->rx_overrun); 1974 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error + 1975 est->rx_alignment_error); 1976 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs + 1977 est->rx_bad_fcs); 1978 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet + 1979 est->rx_bd_short_event + 1980 est->rx_bd_packet_too_long + 1981 est->rx_bd_out_of_range + 1982 est->rx_bd_in_range + 1983 est->rx_runt_packet + 1984 est->rx_short_event + 1985 est->rx_packet_too_long + 1986 est->rx_out_of_range + 1987 est->rx_in_range); 1988 1989 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors); 1990 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun + 1991 est->tx_underrun); 1992 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss; 1993 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral + 1994 est->tx_bd_excessive_collisions + 1995 est->tx_bd_late_collision + 1996 est->tx_bd_multple_collisions); 1997 spin_unlock_irqrestore(&dev->lock, flags); 1998 return nst; 1999 } 2000 2001 static struct mal_commac_ops emac_commac_ops = { 2002 .poll_tx = &emac_poll_tx, 2003 .poll_rx = &emac_poll_rx, 2004 .peek_rx = &emac_peek_rx, 2005 .rxde = &emac_rxde, 2006 }; 2007 2008 static struct mal_commac_ops emac_commac_sg_ops = { 2009 .poll_tx = &emac_poll_tx, 2010 .poll_rx = &emac_poll_rx, 2011 .peek_rx = &emac_peek_rx_sg, 2012 .rxde = &emac_rxde, 2013 }; 2014 2015 /* Ethtool support */ 2016 static int emac_ethtool_get_link_ksettings(struct net_device *ndev, 2017 struct ethtool_link_ksettings *cmd) 2018 { 2019 struct emac_instance *dev = netdev_priv(ndev); 2020 u32 supported, advertising; 2021 2022 supported = dev->phy.features; 2023 cmd->base.port = PORT_MII; 2024 cmd->base.phy_address = dev->phy.address; 2025 2026 mutex_lock(&dev->link_lock); 2027 advertising = dev->phy.advertising; 2028 cmd->base.autoneg = dev->phy.autoneg; 2029 cmd->base.speed = dev->phy.speed; 2030 cmd->base.duplex = dev->phy.duplex; 2031 mutex_unlock(&dev->link_lock); 2032 2033 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 2034 supported); 2035 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 2036 advertising); 2037 2038 return 0; 2039 } 2040 2041 static int 2042 emac_ethtool_set_link_ksettings(struct net_device *ndev, 2043 const struct ethtool_link_ksettings *cmd) 2044 { 2045 struct emac_instance *dev = netdev_priv(ndev); 2046 u32 f = dev->phy.features; 2047 u32 advertising; 2048 2049 ethtool_convert_link_mode_to_legacy_u32(&advertising, 2050 cmd->link_modes.advertising); 2051 2052 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL, 2053 cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising); 2054 2055 /* Basic sanity checks */ 2056 if (dev->phy.address < 0) 2057 return -EOPNOTSUPP; 2058 if (cmd->base.autoneg != AUTONEG_ENABLE && 2059 cmd->base.autoneg != AUTONEG_DISABLE) 2060 return -EINVAL; 2061 if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0) 2062 return -EINVAL; 2063 if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL) 2064 return -EINVAL; 2065 2066 if (cmd->base.autoneg == AUTONEG_DISABLE) { 2067 switch (cmd->base.speed) { 2068 case SPEED_10: 2069 if (cmd->base.duplex == DUPLEX_HALF && 2070 !(f & SUPPORTED_10baseT_Half)) 2071 return -EINVAL; 2072 if (cmd->base.duplex == DUPLEX_FULL && 2073 !(f & SUPPORTED_10baseT_Full)) 2074 return -EINVAL; 2075 break; 2076 case SPEED_100: 2077 if (cmd->base.duplex == DUPLEX_HALF && 2078 !(f & SUPPORTED_100baseT_Half)) 2079 return -EINVAL; 2080 if (cmd->base.duplex == DUPLEX_FULL && 2081 !(f & SUPPORTED_100baseT_Full)) 2082 return -EINVAL; 2083 break; 2084 case SPEED_1000: 2085 if (cmd->base.duplex == DUPLEX_HALF && 2086 !(f & SUPPORTED_1000baseT_Half)) 2087 return -EINVAL; 2088 if (cmd->base.duplex == DUPLEX_FULL && 2089 !(f & SUPPORTED_1000baseT_Full)) 2090 return -EINVAL; 2091 break; 2092 default: 2093 return -EINVAL; 2094 } 2095 2096 mutex_lock(&dev->link_lock); 2097 dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed, 2098 cmd->base.duplex); 2099 mutex_unlock(&dev->link_lock); 2100 2101 } else { 2102 if (!(f & SUPPORTED_Autoneg)) 2103 return -EINVAL; 2104 2105 mutex_lock(&dev->link_lock); 2106 dev->phy.def->ops->setup_aneg(&dev->phy, 2107 (advertising & f) | 2108 (dev->phy.advertising & 2109 (ADVERTISED_Pause | 2110 ADVERTISED_Asym_Pause))); 2111 mutex_unlock(&dev->link_lock); 2112 } 2113 emac_force_link_update(dev); 2114 2115 return 0; 2116 } 2117 2118 static void 2119 emac_ethtool_get_ringparam(struct net_device *ndev, 2120 struct ethtool_ringparam *rp, 2121 struct kernel_ethtool_ringparam *kernel_rp, 2122 struct netlink_ext_ack *extack) 2123 { 2124 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF; 2125 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF; 2126 } 2127 2128 static void emac_ethtool_get_pauseparam(struct net_device *ndev, 2129 struct ethtool_pauseparam *pp) 2130 { 2131 struct emac_instance *dev = netdev_priv(ndev); 2132 2133 mutex_lock(&dev->link_lock); 2134 if ((dev->phy.features & SUPPORTED_Autoneg) && 2135 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause))) 2136 pp->autoneg = 1; 2137 2138 if (dev->phy.duplex == DUPLEX_FULL) { 2139 if (dev->phy.pause) 2140 pp->rx_pause = pp->tx_pause = 1; 2141 else if (dev->phy.asym_pause) 2142 pp->tx_pause = 1; 2143 } 2144 mutex_unlock(&dev->link_lock); 2145 } 2146 2147 static int emac_get_regs_len(struct emac_instance *dev) 2148 { 2149 return sizeof(struct emac_ethtool_regs_subhdr) + 2150 sizeof(struct emac_regs); 2151 } 2152 2153 static int emac_ethtool_get_regs_len(struct net_device *ndev) 2154 { 2155 struct emac_instance *dev = netdev_priv(ndev); 2156 int size; 2157 2158 size = sizeof(struct emac_ethtool_regs_hdr) + 2159 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal); 2160 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 2161 size += zmii_get_regs_len(dev->zmii_dev); 2162 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 2163 size += rgmii_get_regs_len(dev->rgmii_dev); 2164 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 2165 size += tah_get_regs_len(dev->tah_dev); 2166 2167 return size; 2168 } 2169 2170 static void *emac_dump_regs(struct emac_instance *dev, void *buf) 2171 { 2172 struct emac_ethtool_regs_subhdr *hdr = buf; 2173 2174 hdr->index = dev->cell_index; 2175 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) { 2176 hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER; 2177 } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) { 2178 hdr->version = EMAC4_ETHTOOL_REGS_VER; 2179 } else { 2180 hdr->version = EMAC_ETHTOOL_REGS_VER; 2181 } 2182 memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs)); 2183 return (void *)(hdr + 1) + sizeof(struct emac_regs); 2184 } 2185 2186 static void emac_ethtool_get_regs(struct net_device *ndev, 2187 struct ethtool_regs *regs, void *buf) 2188 { 2189 struct emac_instance *dev = netdev_priv(ndev); 2190 struct emac_ethtool_regs_hdr *hdr = buf; 2191 2192 hdr->components = 0; 2193 buf = hdr + 1; 2194 2195 buf = mal_dump_regs(dev->mal, buf); 2196 buf = emac_dump_regs(dev, buf); 2197 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) { 2198 hdr->components |= EMAC_ETHTOOL_REGS_ZMII; 2199 buf = zmii_dump_regs(dev->zmii_dev, buf); 2200 } 2201 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) { 2202 hdr->components |= EMAC_ETHTOOL_REGS_RGMII; 2203 buf = rgmii_dump_regs(dev->rgmii_dev, buf); 2204 } 2205 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) { 2206 hdr->components |= EMAC_ETHTOOL_REGS_TAH; 2207 buf = tah_dump_regs(dev->tah_dev, buf); 2208 } 2209 } 2210 2211 static int emac_ethtool_nway_reset(struct net_device *ndev) 2212 { 2213 struct emac_instance *dev = netdev_priv(ndev); 2214 int res = 0; 2215 2216 DBG(dev, "nway_reset" NL); 2217 2218 if (dev->phy.address < 0) 2219 return -EOPNOTSUPP; 2220 2221 mutex_lock(&dev->link_lock); 2222 if (!dev->phy.autoneg) { 2223 res = -EINVAL; 2224 goto out; 2225 } 2226 2227 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising); 2228 out: 2229 mutex_unlock(&dev->link_lock); 2230 emac_force_link_update(dev); 2231 return res; 2232 } 2233 2234 static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset) 2235 { 2236 if (stringset == ETH_SS_STATS) 2237 return EMAC_ETHTOOL_STATS_COUNT; 2238 else 2239 return -EINVAL; 2240 } 2241 2242 static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset, 2243 u8 * buf) 2244 { 2245 if (stringset == ETH_SS_STATS) 2246 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys)); 2247 } 2248 2249 static void emac_ethtool_get_ethtool_stats(struct net_device *ndev, 2250 struct ethtool_stats *estats, 2251 u64 * tmp_stats) 2252 { 2253 struct emac_instance *dev = netdev_priv(ndev); 2254 2255 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats)); 2256 tmp_stats += sizeof(dev->stats) / sizeof(u64); 2257 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats)); 2258 } 2259 2260 static void emac_ethtool_get_drvinfo(struct net_device *ndev, 2261 struct ethtool_drvinfo *info) 2262 { 2263 struct emac_instance *dev = netdev_priv(ndev); 2264 2265 strscpy(info->driver, "ibm_emac", sizeof(info->driver)); 2266 strscpy(info->version, DRV_VERSION, sizeof(info->version)); 2267 snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %pOF", 2268 dev->cell_index, dev->ofdev->dev.of_node); 2269 } 2270 2271 static const struct ethtool_ops emac_ethtool_ops = { 2272 .get_drvinfo = emac_ethtool_get_drvinfo, 2273 2274 .get_regs_len = emac_ethtool_get_regs_len, 2275 .get_regs = emac_ethtool_get_regs, 2276 2277 .nway_reset = emac_ethtool_nway_reset, 2278 2279 .get_ringparam = emac_ethtool_get_ringparam, 2280 .get_pauseparam = emac_ethtool_get_pauseparam, 2281 2282 .get_strings = emac_ethtool_get_strings, 2283 .get_sset_count = emac_ethtool_get_sset_count, 2284 .get_ethtool_stats = emac_ethtool_get_ethtool_stats, 2285 2286 .get_link = ethtool_op_get_link, 2287 .get_link_ksettings = emac_ethtool_get_link_ksettings, 2288 .set_link_ksettings = emac_ethtool_set_link_ksettings, 2289 }; 2290 2291 static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2292 { 2293 struct emac_instance *dev = netdev_priv(ndev); 2294 struct mii_ioctl_data *data = if_mii(rq); 2295 2296 DBG(dev, "ioctl %08x" NL, cmd); 2297 2298 if (dev->phy.address < 0) 2299 return -EOPNOTSUPP; 2300 2301 switch (cmd) { 2302 case SIOCGMIIPHY: 2303 data->phy_id = dev->phy.address; 2304 fallthrough; 2305 case SIOCGMIIREG: 2306 data->val_out = emac_mdio_read(ndev, dev->phy.address, 2307 data->reg_num); 2308 return 0; 2309 2310 case SIOCSMIIREG: 2311 emac_mdio_write(ndev, dev->phy.address, data->reg_num, 2312 data->val_in); 2313 return 0; 2314 default: 2315 return -EOPNOTSUPP; 2316 } 2317 } 2318 2319 struct emac_depentry { 2320 u32 phandle; 2321 struct device_node *node; 2322 struct platform_device *ofdev; 2323 void *drvdata; 2324 }; 2325 2326 #define EMAC_DEP_MAL_IDX 0 2327 #define EMAC_DEP_ZMII_IDX 1 2328 #define EMAC_DEP_RGMII_IDX 2 2329 #define EMAC_DEP_TAH_IDX 3 2330 #define EMAC_DEP_MDIO_IDX 4 2331 #define EMAC_DEP_PREV_IDX 5 2332 #define EMAC_DEP_COUNT 6 2333 2334 static int emac_check_deps(struct emac_instance *dev, 2335 struct emac_depentry *deps) 2336 { 2337 int i, there = 0; 2338 struct device_node *np; 2339 2340 for (i = 0; i < EMAC_DEP_COUNT; i++) { 2341 /* no dependency on that item, allright */ 2342 if (deps[i].phandle == 0) { 2343 there++; 2344 continue; 2345 } 2346 /* special case for blist as the dependency might go away */ 2347 if (i == EMAC_DEP_PREV_IDX) { 2348 np = *(dev->blist - 1); 2349 if (np == NULL) { 2350 deps[i].phandle = 0; 2351 there++; 2352 continue; 2353 } 2354 if (deps[i].node == NULL) 2355 deps[i].node = of_node_get(np); 2356 } 2357 if (deps[i].node == NULL) 2358 deps[i].node = of_find_node_by_phandle(deps[i].phandle); 2359 if (deps[i].node == NULL) 2360 continue; 2361 if (deps[i].ofdev == NULL) 2362 deps[i].ofdev = of_find_device_by_node(deps[i].node); 2363 if (deps[i].ofdev == NULL) 2364 continue; 2365 if (deps[i].drvdata == NULL) 2366 deps[i].drvdata = platform_get_drvdata(deps[i].ofdev); 2367 if (deps[i].drvdata != NULL) 2368 there++; 2369 } 2370 if (there != EMAC_DEP_COUNT) 2371 return -EPROBE_DEFER; 2372 return 0; 2373 } 2374 2375 static void emac_put_deps(struct emac_instance *dev) 2376 { 2377 platform_device_put(dev->mal_dev); 2378 platform_device_put(dev->zmii_dev); 2379 platform_device_put(dev->rgmii_dev); 2380 platform_device_put(dev->mdio_dev); 2381 platform_device_put(dev->tah_dev); 2382 } 2383 2384 static int emac_wait_deps(struct emac_instance *dev) 2385 { 2386 struct emac_depentry deps[EMAC_DEP_COUNT]; 2387 int i, err; 2388 2389 memset(&deps, 0, sizeof(deps)); 2390 2391 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph; 2392 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph; 2393 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph; 2394 if (dev->tah_ph) 2395 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph; 2396 if (dev->mdio_ph) 2397 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph; 2398 if (dev->blist && dev->blist > emac_boot_list) 2399 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu; 2400 err = emac_check_deps(dev, deps); 2401 for (i = 0; i < EMAC_DEP_COUNT; i++) { 2402 of_node_put(deps[i].node); 2403 if (err) 2404 platform_device_put(deps[i].ofdev); 2405 } 2406 if (!err) { 2407 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev; 2408 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev; 2409 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev; 2410 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev; 2411 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev; 2412 } 2413 platform_device_put(deps[EMAC_DEP_PREV_IDX].ofdev); 2414 return err; 2415 } 2416 2417 static int emac_read_uint_prop(struct device_node *np, const char *name, 2418 u32 *val, int fatal) 2419 { 2420 int err; 2421 2422 err = of_property_read_u32(np, name, val); 2423 if (err) { 2424 if (fatal) 2425 pr_err("%pOF: missing %s property", np, name); 2426 return err; 2427 } 2428 return 0; 2429 } 2430 2431 static void emac_adjust_link(struct net_device *ndev) 2432 { 2433 struct emac_instance *dev = netdev_priv(ndev); 2434 struct phy_device *phy = ndev->phydev; 2435 2436 dev->phy.autoneg = phy->autoneg; 2437 dev->phy.speed = phy->speed; 2438 dev->phy.duplex = phy->duplex; 2439 dev->phy.pause = phy->pause; 2440 dev->phy.asym_pause = phy->asym_pause; 2441 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.advertising, 2442 phy->advertising); 2443 } 2444 2445 static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum) 2446 { 2447 int ret = emac_mdio_read(bus->priv, addr, regnum); 2448 /* This is a workaround for powered down ports/phys. 2449 * In the wild, this was seen on the Cisco Meraki MX60(W). 2450 * This hardware disables ports as part of the handoff 2451 * procedure. Accessing the ports will lead to errors 2452 * (-ETIMEDOUT, -EREMOTEIO) that do more harm than good. 2453 */ 2454 return ret < 0 ? 0xffff : ret; 2455 } 2456 2457 static int emac_mii_bus_write(struct mii_bus *bus, int addr, 2458 int regnum, u16 val) 2459 { 2460 emac_mdio_write(bus->priv, addr, regnum, val); 2461 return 0; 2462 } 2463 2464 static int emac_mii_bus_reset(struct mii_bus *bus) 2465 { 2466 struct emac_instance *dev = netdev_priv(bus->priv); 2467 2468 return emac_reset(dev); 2469 } 2470 2471 static int emac_mdio_phy_start_aneg(struct mii_phy *phy, 2472 struct phy_device *phy_dev) 2473 { 2474 phy_dev->autoneg = phy->autoneg; 2475 phy_dev->speed = phy->speed; 2476 phy_dev->duplex = phy->duplex; 2477 ethtool_convert_legacy_u32_to_link_mode(phy_dev->advertising, 2478 phy->advertising); 2479 return phy_start_aneg(phy_dev); 2480 } 2481 2482 static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise) 2483 { 2484 struct net_device *ndev = phy->dev; 2485 2486 phy->autoneg = AUTONEG_ENABLE; 2487 phy->advertising = advertise; 2488 return emac_mdio_phy_start_aneg(phy, ndev->phydev); 2489 } 2490 2491 static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd) 2492 { 2493 struct net_device *ndev = phy->dev; 2494 2495 phy->autoneg = AUTONEG_DISABLE; 2496 phy->speed = speed; 2497 phy->duplex = fd; 2498 return emac_mdio_phy_start_aneg(phy, ndev->phydev); 2499 } 2500 2501 static int emac_mdio_poll_link(struct mii_phy *phy) 2502 { 2503 struct net_device *ndev = phy->dev; 2504 struct emac_instance *dev = netdev_priv(ndev); 2505 int res; 2506 2507 res = phy_read_status(ndev->phydev); 2508 if (res) { 2509 dev_err(&dev->ofdev->dev, "link update failed (%d).", res); 2510 return ethtool_op_get_link(ndev); 2511 } 2512 2513 return ndev->phydev->link; 2514 } 2515 2516 static int emac_mdio_read_link(struct mii_phy *phy) 2517 { 2518 struct net_device *ndev = phy->dev; 2519 struct phy_device *phy_dev = ndev->phydev; 2520 int res; 2521 2522 res = phy_read_status(phy_dev); 2523 if (res) 2524 return res; 2525 2526 phy->speed = phy_dev->speed; 2527 phy->duplex = phy_dev->duplex; 2528 phy->pause = phy_dev->pause; 2529 phy->asym_pause = phy_dev->asym_pause; 2530 return 0; 2531 } 2532 2533 static int emac_mdio_init_phy(struct mii_phy *phy) 2534 { 2535 struct net_device *ndev = phy->dev; 2536 2537 phy_start(ndev->phydev); 2538 return phy_init_hw(ndev->phydev); 2539 } 2540 2541 static const struct mii_phy_ops emac_dt_mdio_phy_ops = { 2542 .init = emac_mdio_init_phy, 2543 .setup_aneg = emac_mdio_setup_aneg, 2544 .setup_forced = emac_mdio_setup_forced, 2545 .poll_link = emac_mdio_poll_link, 2546 .read_link = emac_mdio_read_link, 2547 }; 2548 2549 static int emac_dt_mdio_probe(struct emac_instance *dev) 2550 { 2551 struct device_node *mii_np; 2552 struct mii_bus *bus; 2553 int res; 2554 2555 mii_np = of_get_available_child_by_name(dev->ofdev->dev.of_node, "mdio"); 2556 if (!mii_np) { 2557 dev_err(&dev->ofdev->dev, "no mdio definition found."); 2558 return -ENODEV; 2559 } 2560 2561 bus = devm_mdiobus_alloc(&dev->ofdev->dev); 2562 if (!bus) { 2563 res = -ENOMEM; 2564 goto put_node; 2565 } 2566 2567 bus->priv = dev->ndev; 2568 bus->parent = dev->ndev->dev.parent; 2569 bus->name = "emac_mdio"; 2570 bus->read = &emac_mii_bus_read; 2571 bus->write = &emac_mii_bus_write; 2572 bus->reset = &emac_mii_bus_reset; 2573 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name); 2574 res = devm_of_mdiobus_register(&dev->ofdev->dev, bus, mii_np); 2575 if (res) { 2576 dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)", 2577 bus->name, res); 2578 } 2579 2580 put_node: 2581 of_node_put(mii_np); 2582 return res; 2583 } 2584 2585 static int emac_dt_phy_connect(struct emac_instance *dev, 2586 struct device_node *phy_handle) 2587 { 2588 struct phy_device *phy_dev; 2589 2590 dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def), 2591 GFP_KERNEL); 2592 if (!dev->phy.def) 2593 return -ENOMEM; 2594 2595 phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link, 0, 2596 dev->phy_mode); 2597 if (!phy_dev) { 2598 dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n"); 2599 return -ENODEV; 2600 } 2601 2602 dev->phy.def->phy_id = phy_dev->drv->phy_id; 2603 dev->phy.def->phy_id_mask = phy_dev->drv->phy_id_mask; 2604 dev->phy.def->name = phy_dev->drv->name; 2605 dev->phy.def->ops = &emac_dt_mdio_phy_ops; 2606 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.features, 2607 phy_dev->supported); 2608 dev->phy.address = phy_dev->mdio.addr; 2609 dev->phy.mode = phy_dev->interface; 2610 return 0; 2611 } 2612 2613 static int emac_dt_phy_probe(struct emac_instance *dev) 2614 { 2615 struct device_node *np = dev->ofdev->dev.of_node; 2616 struct device_node *phy_handle; 2617 int res = 1; 2618 2619 phy_handle = of_parse_phandle(np, "phy-handle", 0); 2620 2621 if (phy_handle) { 2622 res = emac_dt_mdio_probe(dev); 2623 if (!res) { 2624 res = emac_dt_phy_connect(dev, phy_handle); 2625 } 2626 } 2627 2628 of_node_put(phy_handle); 2629 return res; 2630 } 2631 2632 static int emac_init_phy(struct emac_instance *dev) 2633 { 2634 struct device_node *np = dev->ofdev->dev.of_node; 2635 struct net_device *ndev = dev->ndev; 2636 u32 phy_map, adv; 2637 int i; 2638 2639 dev->phy.dev = ndev; 2640 dev->phy.mode = dev->phy_mode; 2641 2642 /* PHY-less configuration. */ 2643 if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) || 2644 of_phy_is_fixed_link(np)) { 2645 emac_reset(dev); 2646 2647 /* PHY-less configuration. */ 2648 dev->phy.address = -1; 2649 dev->phy.features = SUPPORTED_MII; 2650 if (emac_phy_supports_gige(dev->phy_mode)) 2651 dev->phy.features |= SUPPORTED_1000baseT_Full; 2652 else 2653 dev->phy.features |= SUPPORTED_100baseT_Full; 2654 dev->phy.pause = 1; 2655 2656 if (of_phy_is_fixed_link(np)) { 2657 int res = emac_dt_mdio_probe(dev); 2658 2659 if (res) 2660 return res; 2661 2662 res = of_phy_register_fixed_link(np); 2663 ndev->phydev = of_phy_find_device(np); 2664 if (res || !ndev->phydev) 2665 return res ? res : -EINVAL; 2666 emac_adjust_link(dev->ndev); 2667 put_device(&ndev->phydev->mdio.dev); 2668 } 2669 return 0; 2670 } 2671 2672 mutex_lock(&emac_phy_map_lock); 2673 phy_map = dev->phy_map | busy_phy_map; 2674 2675 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map); 2676 2677 dev->phy.mdio_read = emac_mdio_read; 2678 dev->phy.mdio_write = emac_mdio_write; 2679 2680 /* Enable internal clock source */ 2681 #ifdef CONFIG_PPC_DCR_NATIVE 2682 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2683 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); 2684 #endif 2685 /* PHY clock workaround */ 2686 emac_rx_clk_tx(dev); 2687 2688 /* Enable internal clock source on 440GX*/ 2689 #ifdef CONFIG_PPC_DCR_NATIVE 2690 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2691 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); 2692 #endif 2693 /* Configure EMAC with defaults so we can at least use MDIO 2694 * This is needed mostly for 440GX 2695 */ 2696 if (emac_phy_gpcs(dev->phy.mode)) { 2697 /* XXX 2698 * Make GPCS PHY address equal to EMAC index. 2699 * We probably should take into account busy_phy_map 2700 * and/or phy_map here. 2701 * 2702 * Note that the busy_phy_map is currently global 2703 * while it should probably be per-ASIC... 2704 */ 2705 dev->phy.gpcs_address = dev->gpcs_address; 2706 if (dev->phy.gpcs_address == 0xffffffff) 2707 dev->phy.address = dev->cell_index; 2708 } 2709 2710 emac_configure(dev); 2711 2712 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) { 2713 int res = emac_dt_phy_probe(dev); 2714 2715 switch (res) { 2716 case 1: 2717 /* No phy-handle property configured. 2718 * Continue with the existing phy probe 2719 * and setup code. 2720 */ 2721 break; 2722 2723 case 0: 2724 mutex_unlock(&emac_phy_map_lock); 2725 goto init_phy; 2726 2727 default: 2728 mutex_unlock(&emac_phy_map_lock); 2729 dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n", 2730 res); 2731 return res; 2732 } 2733 } 2734 2735 if (dev->phy_address != 0xffffffff) 2736 phy_map = ~(1 << dev->phy_address); 2737 2738 for (i = 0; i < 0x20; phy_map >>= 1, ++i) 2739 if (!(phy_map & 1)) { 2740 int r; 2741 busy_phy_map |= 1 << i; 2742 2743 /* Quick check if there is a PHY at the address */ 2744 r = emac_mdio_read(dev->ndev, i, MII_BMCR); 2745 if (r == 0xffff || r < 0) 2746 continue; 2747 if (!emac_mii_phy_probe(&dev->phy, i)) 2748 break; 2749 } 2750 2751 /* Enable external clock source */ 2752 #ifdef CONFIG_PPC_DCR_NATIVE 2753 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2754 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0); 2755 #endif 2756 mutex_unlock(&emac_phy_map_lock); 2757 if (i == 0x20) { 2758 printk(KERN_WARNING "%pOF: can't find PHY!\n", np); 2759 return -ENXIO; 2760 } 2761 2762 init_phy: 2763 /* Init PHY */ 2764 if (dev->phy.def->ops->init) 2765 dev->phy.def->ops->init(&dev->phy); 2766 2767 /* Disable any PHY features not supported by the platform */ 2768 dev->phy.def->features &= ~dev->phy_feat_exc; 2769 dev->phy.features &= ~dev->phy_feat_exc; 2770 2771 /* Setup initial link parameters */ 2772 if (dev->phy.features & SUPPORTED_Autoneg) { 2773 adv = dev->phy.features; 2774 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x)) 2775 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 2776 /* Restart autonegotiation */ 2777 dev->phy.def->ops->setup_aneg(&dev->phy, adv); 2778 } else { 2779 u32 f = dev->phy.def->features; 2780 int speed = SPEED_10, fd = DUPLEX_HALF; 2781 2782 /* Select highest supported speed/duplex */ 2783 if (f & SUPPORTED_1000baseT_Full) { 2784 speed = SPEED_1000; 2785 fd = DUPLEX_FULL; 2786 } else if (f & SUPPORTED_1000baseT_Half) 2787 speed = SPEED_1000; 2788 else if (f & SUPPORTED_100baseT_Full) { 2789 speed = SPEED_100; 2790 fd = DUPLEX_FULL; 2791 } else if (f & SUPPORTED_100baseT_Half) 2792 speed = SPEED_100; 2793 else if (f & SUPPORTED_10baseT_Full) 2794 fd = DUPLEX_FULL; 2795 2796 /* Force link parameters */ 2797 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd); 2798 } 2799 return 0; 2800 } 2801 2802 static int emac_init_config(struct emac_instance *dev) 2803 { 2804 struct device_node *np = dev->ofdev->dev.of_node; 2805 int err; 2806 2807 /* Read config from device-tree */ 2808 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1)) 2809 return -ENXIO; 2810 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1)) 2811 return -ENXIO; 2812 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1)) 2813 return -ENXIO; 2814 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1)) 2815 return -ENXIO; 2816 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0)) 2817 dev->max_mtu = ETH_DATA_LEN; 2818 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0)) 2819 dev->rx_fifo_size = 2048; 2820 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0)) 2821 dev->tx_fifo_size = 2048; 2822 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0)) 2823 dev->rx_fifo_size_gige = dev->rx_fifo_size; 2824 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0)) 2825 dev->tx_fifo_size_gige = dev->tx_fifo_size; 2826 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0)) 2827 dev->phy_address = 0xffffffff; 2828 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0)) 2829 dev->phy_map = 0xffffffff; 2830 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0)) 2831 dev->gpcs_address = 0xffffffff; 2832 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1)) 2833 return -ENXIO; 2834 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0)) 2835 dev->tah_ph = 0; 2836 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0)) 2837 dev->tah_port = 0; 2838 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0)) 2839 dev->mdio_ph = 0; 2840 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0)) 2841 dev->zmii_ph = 0; 2842 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0)) 2843 dev->zmii_port = 0xffffffff; 2844 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0)) 2845 dev->rgmii_ph = 0; 2846 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0)) 2847 dev->rgmii_port = 0xffffffff; 2848 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0)) 2849 dev->fifo_entry_size = 16; 2850 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0)) 2851 dev->mal_burst_size = 256; 2852 2853 /* PHY mode needs some decoding */ 2854 err = of_get_phy_mode(np, &dev->phy_mode); 2855 if (err) 2856 dev->phy_mode = PHY_INTERFACE_MODE_NA; 2857 2858 /* Check EMAC version */ 2859 if (of_device_is_compatible(np, "ibm,emac4sync")) { 2860 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC); 2861 if (of_device_is_compatible(np, "ibm,emac-460ex") || 2862 of_device_is_compatible(np, "ibm,emac-460gt")) 2863 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX; 2864 if (of_device_is_compatible(np, "ibm,emac-405ex") || 2865 of_device_is_compatible(np, "ibm,emac-405exr")) 2866 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; 2867 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) { 2868 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE | 2869 EMAC_FTR_APM821XX_NO_HALF_DUPLEX | 2870 EMAC_FTR_460EX_PHY_CLK_FIX); 2871 } 2872 } else if (of_device_is_compatible(np, "ibm,emac4")) { 2873 dev->features |= EMAC_FTR_EMAC4; 2874 if (of_device_is_compatible(np, "ibm,emac-440gx")) 2875 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX; 2876 } else { 2877 if (of_device_is_compatible(np, "ibm,emac-440ep") || 2878 of_device_is_compatible(np, "ibm,emac-440gr")) 2879 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; 2880 if (of_device_is_compatible(np, "ibm,emac-405ez")) { 2881 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL 2882 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x; 2883 #else 2884 printk(KERN_ERR "%pOF: Flow control not disabled!\n", 2885 np); 2886 return -ENXIO; 2887 #endif 2888 } 2889 2890 } 2891 2892 /* Fixup some feature bits based on the device tree */ 2893 if (of_property_read_bool(np, "has-inverted-stacr-oc")) 2894 dev->features |= EMAC_FTR_STACR_OC_INVERT; 2895 if (of_property_read_bool(np, "has-new-stacr-staopc")) 2896 dev->features |= EMAC_FTR_HAS_NEW_STACR; 2897 2898 /* CAB lacks the appropriate properties */ 2899 if (of_device_is_compatible(np, "ibm,emac-axon")) 2900 dev->features |= EMAC_FTR_HAS_NEW_STACR | 2901 EMAC_FTR_STACR_OC_INVERT; 2902 2903 /* Enable TAH/ZMII/RGMII features as found */ 2904 if (dev->tah_ph != 0) { 2905 #ifdef CONFIG_IBM_EMAC_TAH 2906 dev->features |= EMAC_FTR_HAS_TAH; 2907 #else 2908 printk(KERN_ERR "%pOF: TAH support not enabled !\n", np); 2909 return -ENXIO; 2910 #endif 2911 } 2912 2913 if (dev->zmii_ph != 0) { 2914 #ifdef CONFIG_IBM_EMAC_ZMII 2915 dev->features |= EMAC_FTR_HAS_ZMII; 2916 #else 2917 printk(KERN_ERR "%pOF: ZMII support not enabled !\n", np); 2918 return -ENXIO; 2919 #endif 2920 } 2921 2922 if (dev->rgmii_ph != 0) { 2923 #ifdef CONFIG_IBM_EMAC_RGMII 2924 dev->features |= EMAC_FTR_HAS_RGMII; 2925 #else 2926 printk(KERN_ERR "%pOF: RGMII support not enabled !\n", np); 2927 return -ENXIO; 2928 #endif 2929 } 2930 2931 /* Read MAC-address */ 2932 err = of_get_ethdev_address(np, dev->ndev); 2933 if (err == -EPROBE_DEFER) 2934 return err; 2935 if (err) { 2936 dev_warn(&dev->ofdev->dev, "Can't get valid mac-address. Generating random."); 2937 eth_hw_addr_random(dev->ndev); 2938 } 2939 2940 /* IAHT and GAHT filter parameterization */ 2941 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) { 2942 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT; 2943 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT; 2944 } else { 2945 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT; 2946 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT; 2947 } 2948 2949 /* This should never happen */ 2950 if (WARN_ON(EMAC_XAHT_REGS(dev) > EMAC_XAHT_MAX_REGS)) 2951 return -ENXIO; 2952 2953 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE); 2954 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige); 2955 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige); 2956 DBG(dev, "max_mtu : %d\n", dev->max_mtu); 2957 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq); 2958 2959 return 0; 2960 } 2961 2962 static const struct net_device_ops emac_netdev_ops = { 2963 .ndo_open = emac_open, 2964 .ndo_stop = emac_close, 2965 .ndo_get_stats = emac_stats, 2966 .ndo_set_rx_mode = emac_set_multicast_list, 2967 .ndo_eth_ioctl = emac_ioctl, 2968 .ndo_tx_timeout = emac_tx_timeout, 2969 .ndo_validate_addr = eth_validate_addr, 2970 .ndo_set_mac_address = emac_set_mac_address, 2971 .ndo_start_xmit = emac_start_xmit, 2972 }; 2973 2974 static const struct net_device_ops emac_gige_netdev_ops = { 2975 .ndo_open = emac_open, 2976 .ndo_stop = emac_close, 2977 .ndo_get_stats = emac_stats, 2978 .ndo_set_rx_mode = emac_set_multicast_list, 2979 .ndo_eth_ioctl = emac_ioctl, 2980 .ndo_tx_timeout = emac_tx_timeout, 2981 .ndo_validate_addr = eth_validate_addr, 2982 .ndo_set_mac_address = emac_set_mac_address, 2983 .ndo_start_xmit = emac_start_xmit_sg, 2984 .ndo_change_mtu = emac_change_mtu, 2985 }; 2986 2987 static int emac_probe(struct platform_device *ofdev) 2988 { 2989 struct net_device *ndev; 2990 struct emac_instance *dev; 2991 struct device_node *np = ofdev->dev.of_node; 2992 struct device_node **blist = NULL; 2993 int err, i; 2994 2995 /* Skip unused/unwired EMACS. We leave the check for an unused 2996 * property here for now, but new flat device trees should set a 2997 * status property to "disabled" instead. 2998 */ 2999 if (of_property_read_bool(np, "unused") || !of_device_is_available(np)) 3000 return -ENODEV; 3001 3002 /* Find ourselves in the bootlist if we are there */ 3003 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++) 3004 if (emac_boot_list[i] == np) 3005 blist = &emac_boot_list[i]; 3006 3007 /* Allocate our net_device structure */ 3008 err = -ENOMEM; 3009 ndev = devm_alloc_etherdev(&ofdev->dev, sizeof(struct emac_instance)); 3010 if (!ndev) 3011 goto err_gone; 3012 3013 dev = netdev_priv(ndev); 3014 dev->ndev = ndev; 3015 dev->ofdev = ofdev; 3016 dev->blist = blist; 3017 SET_NETDEV_DEV(ndev, &ofdev->dev); 3018 3019 /* Initialize some embedded data structures */ 3020 err = devm_mutex_init(&ofdev->dev, &dev->mdio_lock); 3021 if (err) 3022 goto err_gone; 3023 3024 err = devm_mutex_init(&ofdev->dev, &dev->link_lock); 3025 if (err) 3026 goto err_gone; 3027 3028 spin_lock_init(&dev->lock); 3029 INIT_WORK(&dev->reset_work, emac_reset_work); 3030 3031 /* Init various config data based on device-tree */ 3032 err = emac_init_config(dev); 3033 if (err) 3034 goto err_gone; 3035 3036 /* Setup error IRQ handler */ 3037 dev->emac_irq = platform_get_irq(ofdev, 0); 3038 if (dev->emac_irq < 0) { 3039 err = dev->emac_irq; 3040 goto err_gone; 3041 } 3042 3043 err = devm_request_irq(&ofdev->dev, dev->emac_irq, emac_irq, 0, "EMAC", 3044 dev); 3045 if (err) { 3046 dev_err_probe(&ofdev->dev, err, "failed to request IRQ %d", 3047 dev->emac_irq); 3048 goto err_gone; 3049 } 3050 3051 ndev->irq = dev->emac_irq; 3052 3053 dev->emacp = devm_platform_ioremap_resource(ofdev, 0); 3054 if (IS_ERR(dev->emacp)) { 3055 dev_err(&ofdev->dev, "can't map device registers"); 3056 err = PTR_ERR(dev->emacp); 3057 goto err_gone; 3058 } 3059 3060 /* Wait for dependent devices */ 3061 err = emac_wait_deps(dev); 3062 if (err) 3063 goto err_gone; 3064 dev->mal = platform_get_drvdata(dev->mal_dev); 3065 if (dev->mdio_dev != NULL) 3066 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev); 3067 3068 /* Register with MAL */ 3069 dev->commac.ops = &emac_commac_ops; 3070 dev->commac.dev = dev; 3071 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan); 3072 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan); 3073 err = mal_register_commac(dev->mal, &dev->commac); 3074 if (err) { 3075 printk(KERN_ERR "%pOF: failed to register with mal %pOF!\n", 3076 np, dev->mal_dev->dev.of_node); 3077 goto err_rel_deps; 3078 } 3079 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu); 3080 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu); 3081 3082 /* Get pointers to BD rings */ 3083 dev->tx_desc = 3084 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan); 3085 dev->rx_desc = 3086 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan); 3087 3088 DBG(dev, "tx_desc %p" NL, dev->tx_desc); 3089 DBG(dev, "rx_desc %p" NL, dev->rx_desc); 3090 3091 /* Clean rings */ 3092 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor)); 3093 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor)); 3094 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *)); 3095 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *)); 3096 3097 /* Attach to ZMII, if needed */ 3098 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) && 3099 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0) 3100 goto err_unreg_commac; 3101 3102 /* Attach to RGMII, if needed */ 3103 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) && 3104 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0) 3105 goto err_detach_zmii; 3106 3107 /* Attach to TAH, if needed */ 3108 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) && 3109 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0) 3110 goto err_detach_rgmii; 3111 3112 /* Set some link defaults before we can find out real parameters */ 3113 dev->phy.speed = SPEED_100; 3114 dev->phy.duplex = DUPLEX_FULL; 3115 dev->phy.autoneg = AUTONEG_DISABLE; 3116 dev->phy.pause = dev->phy.asym_pause = 0; 3117 dev->stop_timeout = STOP_TIMEOUT_100; 3118 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer); 3119 3120 /* Some SoCs like APM821xx does not support Half Duplex mode. */ 3121 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) { 3122 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half | 3123 SUPPORTED_100baseT_Half | 3124 SUPPORTED_10baseT_Half); 3125 } 3126 3127 /* Find PHY if any */ 3128 err = emac_init_phy(dev); 3129 if (err != 0) 3130 goto err_detach_tah; 3131 3132 if (dev->tah_dev) { 3133 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG; 3134 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM; 3135 } 3136 ndev->watchdog_timeo = 5 * HZ; 3137 if (emac_phy_supports_gige(dev->phy_mode)) { 3138 ndev->netdev_ops = &emac_gige_netdev_ops; 3139 dev->commac.ops = &emac_commac_sg_ops; 3140 } else 3141 ndev->netdev_ops = &emac_netdev_ops; 3142 ndev->ethtool_ops = &emac_ethtool_ops; 3143 3144 /* MTU range: 46 - 1500 or whatever is in OF */ 3145 ndev->min_mtu = EMAC_MIN_MTU; 3146 ndev->max_mtu = dev->max_mtu; 3147 3148 netif_carrier_off(ndev); 3149 3150 err = devm_register_netdev(&ofdev->dev, ndev); 3151 if (err) { 3152 printk(KERN_ERR "%pOF: failed to register net device (%d)!\n", 3153 np, err); 3154 goto err_detach_tah; 3155 } 3156 3157 /* Set our drvdata last as we don't want them visible until we are 3158 * fully initialized 3159 */ 3160 wmb(); 3161 platform_set_drvdata(ofdev, dev); 3162 3163 printk(KERN_INFO "%s: EMAC-%d %pOF, MAC %pM\n", 3164 ndev->name, dev->cell_index, np, ndev->dev_addr); 3165 3166 if (dev->phy_mode == PHY_INTERFACE_MODE_SGMII) 3167 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name); 3168 3169 if (dev->phy.address >= 0) 3170 printk("%s: found %s PHY (0x%02x)\n", ndev->name, 3171 dev->phy.def->name, dev->phy.address); 3172 3173 /* Life is good */ 3174 return 0; 3175 3176 /* I have a bad feeling about this ... */ 3177 3178 err_detach_tah: 3179 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 3180 tah_detach(dev->tah_dev, dev->tah_port); 3181 err_detach_rgmii: 3182 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 3183 rgmii_detach(dev->rgmii_dev, dev->rgmii_port); 3184 err_detach_zmii: 3185 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 3186 zmii_detach(dev->zmii_dev, dev->zmii_port); 3187 err_unreg_commac: 3188 mal_unregister_commac(dev->mal, &dev->commac); 3189 err_rel_deps: 3190 emac_put_deps(dev); 3191 err_gone: 3192 if (blist) 3193 *blist = NULL; 3194 return err; 3195 } 3196 3197 static void emac_remove(struct platform_device *ofdev) 3198 { 3199 struct emac_instance *dev = platform_get_drvdata(ofdev); 3200 3201 DBG(dev, "remove" NL); 3202 3203 cancel_work_sync(&dev->reset_work); 3204 3205 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 3206 tah_detach(dev->tah_dev, dev->tah_port); 3207 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 3208 rgmii_detach(dev->rgmii_dev, dev->rgmii_port); 3209 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 3210 zmii_detach(dev->zmii_dev, dev->zmii_port); 3211 3212 busy_phy_map &= ~(1 << dev->phy.address); 3213 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map); 3214 3215 mal_unregister_commac(dev->mal, &dev->commac); 3216 emac_put_deps(dev); 3217 } 3218 3219 /* XXX Features in here should be replaced by properties... */ 3220 static const struct of_device_id emac_match[] = 3221 { 3222 { 3223 .type = "network", 3224 .compatible = "ibm,emac", 3225 }, 3226 { 3227 .type = "network", 3228 .compatible = "ibm,emac4", 3229 }, 3230 { 3231 .type = "network", 3232 .compatible = "ibm,emac4sync", 3233 }, 3234 {}, 3235 }; 3236 MODULE_DEVICE_TABLE(of, emac_match); 3237 3238 static struct platform_driver emac_driver = { 3239 .driver = { 3240 .name = "emac", 3241 .of_match_table = emac_match, 3242 }, 3243 .probe = emac_probe, 3244 .remove = emac_remove, 3245 }; 3246 3247 static void __init emac_make_bootlist(void) 3248 { 3249 struct device_node *np = NULL; 3250 int j, max, i = 0; 3251 int cell_indices[EMAC_BOOT_LIST_SIZE]; 3252 3253 /* Collect EMACs */ 3254 while((np = of_find_all_nodes(np)) != NULL) { 3255 u32 idx; 3256 3257 if (of_match_node(emac_match, np) == NULL) 3258 continue; 3259 if (of_property_read_bool(np, "unused")) 3260 continue; 3261 if (of_property_read_u32(np, "cell-index", &idx)) 3262 continue; 3263 cell_indices[i] = idx; 3264 emac_boot_list[i++] = of_node_get(np); 3265 if (i >= EMAC_BOOT_LIST_SIZE) { 3266 of_node_put(np); 3267 break; 3268 } 3269 } 3270 max = i; 3271 3272 /* Bubble sort them (doh, what a creative algorithm :-) */ 3273 for (i = 0; max > 1 && (i < (max - 1)); i++) 3274 for (j = i; j < max; j++) { 3275 if (cell_indices[i] > cell_indices[j]) { 3276 swap(emac_boot_list[i], emac_boot_list[j]); 3277 swap(cell_indices[i], cell_indices[j]); 3278 } 3279 } 3280 } 3281 3282 static int __init emac_init(void) 3283 { 3284 int rc; 3285 3286 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n"); 3287 3288 /* Build EMAC boot list */ 3289 emac_make_bootlist(); 3290 3291 /* Init submodules */ 3292 rc = mal_init(); 3293 if (rc) 3294 goto err; 3295 rc = zmii_init(); 3296 if (rc) 3297 goto err_mal; 3298 rc = rgmii_init(); 3299 if (rc) 3300 goto err_zmii; 3301 rc = tah_init(); 3302 if (rc) 3303 goto err_rgmii; 3304 rc = platform_driver_register(&emac_driver); 3305 if (rc) 3306 goto err_tah; 3307 3308 return 0; 3309 3310 err_tah: 3311 tah_exit(); 3312 err_rgmii: 3313 rgmii_exit(); 3314 err_zmii: 3315 zmii_exit(); 3316 err_mal: 3317 mal_exit(); 3318 err: 3319 return rc; 3320 } 3321 3322 static void __exit emac_exit(void) 3323 { 3324 int i; 3325 3326 platform_driver_unregister(&emac_driver); 3327 3328 tah_exit(); 3329 rgmii_exit(); 3330 zmii_exit(); 3331 mal_exit(); 3332 3333 /* Destroy EMAC boot list */ 3334 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++) 3335 of_node_put(emac_boot_list[i]); 3336 } 3337 3338 module_init(emac_init); 3339 module_exit(emac_exit); 3340