1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/net/ethernet/ibm/emac/core.c 4 * 5 * Driver for PowerPC 4xx on-chip ethernet controller. 6 * 7 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 8 * <benh@kernel.crashing.org> 9 * 10 * Based on the arch/ppc version of the driver: 11 * 12 * Copyright (c) 2004, 2005 Zultys Technologies. 13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 14 * 15 * Based on original work by 16 * Matt Porter <mporter@kernel.crashing.org> 17 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> 18 * Armin Kuster <akuster@mvista.com> 19 * Johnnie Peters <jpeters@mvista.com> 20 */ 21 22 #include <linux/module.h> 23 #include <linux/sched.h> 24 #include <linux/string.h> 25 #include <linux/errno.h> 26 #include <linux/delay.h> 27 #include <linux/types.h> 28 #include <linux/pci.h> 29 #include <linux/etherdevice.h> 30 #include <linux/skbuff.h> 31 #include <linux/crc32.h> 32 #include <linux/ethtool.h> 33 #include <linux/if_vlan.h> 34 #include <linux/mii.h> 35 #include <linux/bitops.h> 36 #include <linux/of.h> 37 #include <linux/of_address.h> 38 #include <linux/of_irq.h> 39 #include <linux/of_net.h> 40 #include <linux/of_mdio.h> 41 #include <linux/of_platform.h> 42 #include <linux/platform_device.h> 43 #include <linux/slab.h> 44 45 #include <asm/processor.h> 46 #include <asm/io.h> 47 #include <asm/dma.h> 48 #include <linux/uaccess.h> 49 #include <asm/dcr.h> 50 #include <asm/dcr-regs.h> 51 52 #include "core.h" 53 54 /* 55 * Lack of dma_unmap_???? calls is intentional. 56 * 57 * API-correct usage requires additional support state information to be 58 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to 59 * EMAC design (e.g. TX buffer passed from network stack can be split into 60 * several BDs, dma_map_single/dma_map_page can be used to map particular BD), 61 * maintaining such information will add additional overhead. 62 * Current DMA API implementation for 4xx processors only ensures cache coherency 63 * and dma_unmap_???? routines are empty and are likely to stay this way. 64 * I decided to omit dma_unmap_??? calls because I don't want to add additional 65 * complexity just for the sake of following some abstract API, when it doesn't 66 * add any real benefit to the driver. I understand that this decision maybe 67 * controversial, but I really tried to make code API-correct and efficient 68 * at the same time and didn't come up with code I liked :(. --ebs 69 */ 70 71 #define DRV_NAME "emac" 72 #define DRV_VERSION "3.54" 73 #define DRV_DESC "PPC 4xx OCP EMAC driver" 74 75 MODULE_DESCRIPTION(DRV_DESC); 76 MODULE_AUTHOR 77 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>"); 78 MODULE_LICENSE("GPL"); 79 80 /* minimum number of free TX descriptors required to wake up TX process */ 81 #define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4) 82 83 /* If packet size is less than this number, we allocate small skb and copy packet 84 * contents into it instead of just sending original big skb up 85 */ 86 #define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD 87 88 /* Since multiple EMACs share MDIO lines in various ways, we need 89 * to avoid re-using the same PHY ID in cases where the arch didn't 90 * setup precise phy_map entries 91 * 92 * XXX This is something that needs to be reworked as we can have multiple 93 * EMAC "sets" (multiple ASICs containing several EMACs) though we can 94 * probably require in that case to have explicit PHY IDs in the device-tree 95 */ 96 static u32 busy_phy_map; 97 static DEFINE_MUTEX(emac_phy_map_lock); 98 99 /* Having stable interface names is a doomed idea. However, it would be nice 100 * if we didn't have completely random interface names at boot too :-) It's 101 * just a matter of making everybody's life easier. Since we are doing 102 * threaded probing, it's a bit harder though. The base idea here is that 103 * we make up a list of all emacs in the device-tree before we register the 104 * driver. Every emac will then wait for the previous one in the list to 105 * initialize before itself. We should also keep that list ordered by 106 * cell_index. 107 * That list is only 4 entries long, meaning that additional EMACs don't 108 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased. 109 */ 110 111 #define EMAC_BOOT_LIST_SIZE 4 112 static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE]; 113 114 /* I don't want to litter system log with timeout errors 115 * when we have brain-damaged PHY. 116 */ 117 static inline void emac_report_timeout_error(struct emac_instance *dev, 118 const char *error) 119 { 120 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX | 121 EMAC_FTR_460EX_PHY_CLK_FIX | 122 EMAC_FTR_440EP_PHY_CLK_FIX)) 123 DBG(dev, "%s" NL, error); 124 else if (net_ratelimit()) 125 printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error); 126 } 127 128 /* EMAC PHY clock workaround: 129 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, 130 * which allows controlling each EMAC clock 131 */ 132 static inline void emac_rx_clk_tx(struct emac_instance *dev) 133 { 134 #ifdef CONFIG_PPC_DCR_NATIVE 135 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX)) 136 dcri_clrset(SDR0, SDR0_MFR, 137 0, SDR0_MFR_ECS >> dev->cell_index); 138 #endif 139 } 140 141 static inline void emac_rx_clk_default(struct emac_instance *dev) 142 { 143 #ifdef CONFIG_PPC_DCR_NATIVE 144 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX)) 145 dcri_clrset(SDR0, SDR0_MFR, 146 SDR0_MFR_ECS >> dev->cell_index, 0); 147 #endif 148 } 149 150 /* PHY polling intervals */ 151 #define PHY_POLL_LINK_ON HZ 152 #define PHY_POLL_LINK_OFF (HZ / 5) 153 154 /* Graceful stop timeouts in us. 155 * We should allow up to 1 frame time (full-duplex, ignoring collisions) 156 */ 157 #define STOP_TIMEOUT_10 1230 158 #define STOP_TIMEOUT_100 124 159 #define STOP_TIMEOUT_1000 13 160 #define STOP_TIMEOUT_1000_JUMBO 73 161 162 static unsigned char default_mcast_addr[] = { 163 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01 164 }; 165 166 /* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */ 167 static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = { 168 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum", 169 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom", 170 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu", 171 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet", 172 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error", 173 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range", 174 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun", 175 "rx_bad_packet", "rx_runt_packet", "rx_short_event", 176 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long", 177 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors", 178 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral", 179 "tx_bd_excessive_collisions", "tx_bd_late_collision", 180 "tx_bd_multple_collisions", "tx_bd_single_collision", 181 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe", 182 "tx_errors" 183 }; 184 185 static irqreturn_t emac_irq(int irq, void *dev_instance); 186 static void emac_clean_tx_ring(struct emac_instance *dev); 187 static void __emac_set_multicast_list(struct emac_instance *dev); 188 189 static inline int emac_phy_supports_gige(int phy_mode) 190 { 191 return phy_interface_mode_is_rgmii(phy_mode) || 192 phy_mode == PHY_INTERFACE_MODE_GMII || 193 phy_mode == PHY_INTERFACE_MODE_SGMII || 194 phy_mode == PHY_INTERFACE_MODE_TBI || 195 phy_mode == PHY_INTERFACE_MODE_RTBI; 196 } 197 198 static inline int emac_phy_gpcs(int phy_mode) 199 { 200 return phy_mode == PHY_INTERFACE_MODE_SGMII || 201 phy_mode == PHY_INTERFACE_MODE_TBI || 202 phy_mode == PHY_INTERFACE_MODE_RTBI; 203 } 204 205 static inline void emac_tx_enable(struct emac_instance *dev) 206 { 207 struct emac_regs __iomem *p = dev->emacp; 208 u32 r; 209 210 DBG(dev, "tx_enable" NL); 211 212 r = in_be32(&p->mr0); 213 if (!(r & EMAC_MR0_TXE)) 214 out_be32(&p->mr0, r | EMAC_MR0_TXE); 215 } 216 217 static void emac_tx_disable(struct emac_instance *dev) 218 { 219 struct emac_regs __iomem *p = dev->emacp; 220 u32 r; 221 222 DBG(dev, "tx_disable" NL); 223 224 r = in_be32(&p->mr0); 225 if (r & EMAC_MR0_TXE) { 226 int n = dev->stop_timeout; 227 out_be32(&p->mr0, r & ~EMAC_MR0_TXE); 228 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) { 229 udelay(1); 230 --n; 231 } 232 if (unlikely(!n)) 233 emac_report_timeout_error(dev, "TX disable timeout"); 234 } 235 } 236 237 static void emac_rx_enable(struct emac_instance *dev) 238 { 239 struct emac_regs __iomem *p = dev->emacp; 240 u32 r; 241 242 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) 243 goto out; 244 245 DBG(dev, "rx_enable" NL); 246 247 r = in_be32(&p->mr0); 248 if (!(r & EMAC_MR0_RXE)) { 249 if (unlikely(!(r & EMAC_MR0_RXI))) { 250 /* Wait if previous async disable is still in progress */ 251 int n = dev->stop_timeout; 252 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) { 253 udelay(1); 254 --n; 255 } 256 if (unlikely(!n)) 257 emac_report_timeout_error(dev, 258 "RX disable timeout"); 259 } 260 out_be32(&p->mr0, r | EMAC_MR0_RXE); 261 } 262 out: 263 ; 264 } 265 266 static void emac_rx_disable(struct emac_instance *dev) 267 { 268 struct emac_regs __iomem *p = dev->emacp; 269 u32 r; 270 271 DBG(dev, "rx_disable" NL); 272 273 r = in_be32(&p->mr0); 274 if (r & EMAC_MR0_RXE) { 275 int n = dev->stop_timeout; 276 out_be32(&p->mr0, r & ~EMAC_MR0_RXE); 277 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) { 278 udelay(1); 279 --n; 280 } 281 if (unlikely(!n)) 282 emac_report_timeout_error(dev, "RX disable timeout"); 283 } 284 } 285 286 static inline void emac_netif_stop(struct emac_instance *dev) 287 { 288 netif_tx_lock_bh(dev->ndev); 289 netif_addr_lock(dev->ndev); 290 dev->no_mcast = 1; 291 netif_addr_unlock(dev->ndev); 292 netif_tx_unlock_bh(dev->ndev); 293 netif_trans_update(dev->ndev); /* prevent tx timeout */ 294 mal_poll_disable(dev->mal, &dev->commac); 295 netif_tx_disable(dev->ndev); 296 } 297 298 static inline void emac_netif_start(struct emac_instance *dev) 299 { 300 netif_tx_lock_bh(dev->ndev); 301 netif_addr_lock(dev->ndev); 302 dev->no_mcast = 0; 303 if (dev->mcast_pending && netif_running(dev->ndev)) 304 __emac_set_multicast_list(dev); 305 netif_addr_unlock(dev->ndev); 306 netif_tx_unlock_bh(dev->ndev); 307 308 netif_wake_queue(dev->ndev); 309 310 /* NOTE: unconditional netif_wake_queue is only appropriate 311 * so long as all callers are assured to have free tx slots 312 * (taken from tg3... though the case where that is wrong is 313 * not terribly harmful) 314 */ 315 mal_poll_enable(dev->mal, &dev->commac); 316 } 317 318 static inline void emac_rx_disable_async(struct emac_instance *dev) 319 { 320 struct emac_regs __iomem *p = dev->emacp; 321 u32 r; 322 323 DBG(dev, "rx_disable_async" NL); 324 325 r = in_be32(&p->mr0); 326 if (r & EMAC_MR0_RXE) 327 out_be32(&p->mr0, r & ~EMAC_MR0_RXE); 328 } 329 330 static int emac_reset(struct emac_instance *dev) 331 { 332 struct emac_regs __iomem *p = dev->emacp; 333 int n = 20; 334 bool __maybe_unused try_internal_clock = false; 335 336 DBG(dev, "reset" NL); 337 338 if (!dev->reset_failed) { 339 /* 40x erratum suggests stopping RX channel before reset, 340 * we stop TX as well 341 */ 342 emac_rx_disable(dev); 343 emac_tx_disable(dev); 344 } 345 346 #ifdef CONFIG_PPC_DCR_NATIVE 347 do_retry: 348 /* 349 * PPC460EX/GT Embedded Processor Advanced User's Manual 350 * section 28.10.1 Mode Register 0 (EMACx_MR0) states: 351 * Note: The PHY must provide a TX Clk in order to perform a soft reset 352 * of the EMAC. If none is present, select the internal clock 353 * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1). 354 * After a soft reset, select the external clock. 355 * 356 * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the 357 * ethernet cable is not attached. This causes the reset to timeout 358 * and the PHY detection code in emac_init_phy() is unable to 359 * communicate and detect the AR8035-A PHY. As a result, the emac 360 * driver bails out early and the user has no ethernet. 361 * In order to stay compatible with existing configurations, the 362 * driver will temporarily switch to the internal clock, after 363 * the first reset fails. 364 */ 365 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { 366 if (try_internal_clock || (dev->phy_address == 0xffffffff && 367 dev->phy_map == 0xffffffff)) { 368 /* No PHY: select internal loop clock before reset */ 369 dcri_clrset(SDR0, SDR0_ETH_CFG, 370 0, SDR0_ETH_CFG_ECS << dev->cell_index); 371 } else { 372 /* PHY present: select external clock before reset */ 373 dcri_clrset(SDR0, SDR0_ETH_CFG, 374 SDR0_ETH_CFG_ECS << dev->cell_index, 0); 375 } 376 } 377 #endif 378 379 out_be32(&p->mr0, EMAC_MR0_SRST); 380 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n) 381 --n; 382 383 #ifdef CONFIG_PPC_DCR_NATIVE 384 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { 385 if (!n && !try_internal_clock) { 386 /* first attempt has timed out. */ 387 n = 20; 388 try_internal_clock = true; 389 goto do_retry; 390 } 391 392 if (try_internal_clock || (dev->phy_address == 0xffffffff && 393 dev->phy_map == 0xffffffff)) { 394 /* No PHY: restore external clock source after reset */ 395 dcri_clrset(SDR0, SDR0_ETH_CFG, 396 SDR0_ETH_CFG_ECS << dev->cell_index, 0); 397 } 398 } 399 #endif 400 401 if (n) { 402 dev->reset_failed = 0; 403 return 0; 404 } else { 405 emac_report_timeout_error(dev, "reset timeout"); 406 dev->reset_failed = 1; 407 return -ETIMEDOUT; 408 } 409 } 410 411 static void emac_hash_mc(struct emac_instance *dev) 412 { 413 u32 __iomem *gaht_base = emac_gaht_base(dev); 414 const int regs = EMAC_XAHT_REGS(dev); 415 u32 gaht_temp[EMAC_XAHT_MAX_REGS]; 416 struct netdev_hw_addr *ha; 417 int i; 418 419 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev)); 420 421 memset(gaht_temp, 0, sizeof (gaht_temp)); 422 423 netdev_for_each_mc_addr(ha, dev->ndev) { 424 int slot, reg, mask; 425 DBG2(dev, "mc %pM" NL, ha->addr); 426 427 slot = EMAC_XAHT_CRC_TO_SLOT(dev, 428 ether_crc(ETH_ALEN, ha->addr)); 429 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot); 430 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot); 431 432 gaht_temp[reg] |= mask; 433 } 434 435 for (i = 0; i < regs; i++) 436 out_be32(gaht_base + i, gaht_temp[i]); 437 } 438 439 static inline u32 emac_iff2rmr(struct net_device *ndev) 440 { 441 struct emac_instance *dev = netdev_priv(ndev); 442 u32 r; 443 444 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE; 445 446 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 447 r |= EMAC4_RMR_BASE; 448 else 449 r |= EMAC_RMR_BASE; 450 451 if (ndev->flags & IFF_PROMISC) 452 r |= EMAC_RMR_PME; 453 else if (ndev->flags & IFF_ALLMULTI || 454 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev))) 455 r |= EMAC_RMR_PMME; 456 else if (!netdev_mc_empty(ndev)) 457 r |= EMAC_RMR_MAE; 458 459 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) { 460 r &= ~EMAC4_RMR_MJS_MASK; 461 r |= EMAC4_RMR_MJS(ndev->mtu + VLAN_HLEN); 462 } 463 464 return r; 465 } 466 467 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 468 { 469 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT; 470 471 DBG2(dev, "__emac_calc_base_mr1" NL); 472 473 switch(tx_size) { 474 case 2048: 475 ret |= EMAC_MR1_TFS_2K; 476 break; 477 default: 478 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n", 479 dev->ndev->name, tx_size); 480 } 481 482 switch(rx_size) { 483 case 16384: 484 ret |= EMAC_MR1_RFS_16K; 485 break; 486 case 4096: 487 ret |= EMAC_MR1_RFS_4K; 488 break; 489 default: 490 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n", 491 dev->ndev->name, rx_size); 492 } 493 494 return ret; 495 } 496 497 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 498 { 499 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR | 500 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000); 501 502 DBG2(dev, "__emac4_calc_base_mr1" NL); 503 504 switch(tx_size) { 505 case 16384: 506 ret |= EMAC4_MR1_TFS_16K; 507 break; 508 case 8192: 509 ret |= EMAC4_MR1_TFS_8K; 510 break; 511 case 4096: 512 ret |= EMAC4_MR1_TFS_4K; 513 break; 514 case 2048: 515 ret |= EMAC4_MR1_TFS_2K; 516 break; 517 default: 518 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n", 519 dev->ndev->name, tx_size); 520 } 521 522 switch(rx_size) { 523 case 16384: 524 ret |= EMAC4_MR1_RFS_16K; 525 break; 526 case 8192: 527 ret |= EMAC4_MR1_RFS_8K; 528 break; 529 case 4096: 530 ret |= EMAC4_MR1_RFS_4K; 531 break; 532 case 2048: 533 ret |= EMAC4_MR1_RFS_2K; 534 break; 535 default: 536 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n", 537 dev->ndev->name, rx_size); 538 } 539 540 return ret; 541 } 542 543 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 544 { 545 return emac_has_feature(dev, EMAC_FTR_EMAC4) ? 546 __emac4_calc_base_mr1(dev, tx_size, rx_size) : 547 __emac_calc_base_mr1(dev, tx_size, rx_size); 548 } 549 550 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size) 551 { 552 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 553 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4; 554 else 555 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT; 556 } 557 558 static inline u32 emac_calc_rwmr(struct emac_instance *dev, 559 unsigned int low, unsigned int high) 560 { 561 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 562 return (low << 22) | ( (high & 0x3ff) << 6); 563 else 564 return (low << 23) | ( (high & 0x1ff) << 7); 565 } 566 567 static int emac_configure(struct emac_instance *dev) 568 { 569 struct emac_regs __iomem *p = dev->emacp; 570 struct net_device *ndev = dev->ndev; 571 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev); 572 u32 r, mr1 = 0; 573 574 DBG(dev, "configure" NL); 575 576 if (!link) { 577 out_be32(&p->mr1, in_be32(&p->mr1) 578 | EMAC_MR1_FDE | EMAC_MR1_ILE); 579 udelay(100); 580 } else if (emac_reset(dev) < 0) 581 return -ETIMEDOUT; 582 583 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 584 tah_reset(dev->tah_dev); 585 586 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n", 587 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause); 588 589 /* Default fifo sizes */ 590 tx_size = dev->tx_fifo_size; 591 rx_size = dev->rx_fifo_size; 592 593 /* No link, force loopback */ 594 if (!link) 595 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE; 596 597 /* Check for full duplex */ 598 else if (dev->phy.duplex == DUPLEX_FULL) 599 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001; 600 601 /* Adjust fifo sizes, mr1 and timeouts based on link speed */ 602 dev->stop_timeout = STOP_TIMEOUT_10; 603 switch (dev->phy.speed) { 604 case SPEED_1000: 605 if (emac_phy_gpcs(dev->phy.mode)) { 606 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA( 607 (dev->phy.gpcs_address != 0xffffffff) ? 608 dev->phy.gpcs_address : dev->phy.address); 609 610 /* Put some arbitrary OUI, Manuf & Rev IDs so we can 611 * identify this GPCS PHY later. 612 */ 613 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef); 614 } else 615 mr1 |= EMAC_MR1_MF_1000; 616 617 /* Extended fifo sizes */ 618 tx_size = dev->tx_fifo_size_gige; 619 rx_size = dev->rx_fifo_size_gige; 620 621 if (dev->ndev->mtu > ETH_DATA_LEN) { 622 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 623 mr1 |= EMAC4_MR1_JPSM; 624 else 625 mr1 |= EMAC_MR1_JPSM; 626 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO; 627 } else 628 dev->stop_timeout = STOP_TIMEOUT_1000; 629 break; 630 case SPEED_100: 631 mr1 |= EMAC_MR1_MF_100; 632 dev->stop_timeout = STOP_TIMEOUT_100; 633 break; 634 default: /* make gcc happy */ 635 break; 636 } 637 638 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 639 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port, 640 dev->phy.speed); 641 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 642 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed); 643 644 /* on 40x erratum forces us to NOT use integrated flow control, 645 * let's hope it works on 44x ;) 646 */ 647 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) && 648 dev->phy.duplex == DUPLEX_FULL) { 649 if (dev->phy.pause) 650 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP; 651 else if (dev->phy.asym_pause) 652 mr1 |= EMAC_MR1_APP; 653 } 654 655 /* Add base settings & fifo sizes & program MR1 */ 656 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size); 657 out_be32(&p->mr1, mr1); 658 659 /* Set individual MAC address */ 660 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]); 661 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) | 662 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) | 663 ndev->dev_addr[5]); 664 665 /* VLAN Tag Protocol ID */ 666 out_be32(&p->vtpid, 0x8100); 667 668 /* Receive mode register */ 669 r = emac_iff2rmr(ndev); 670 if (r & EMAC_RMR_MAE) 671 emac_hash_mc(dev); 672 out_be32(&p->rmr, r); 673 674 /* FIFOs thresholds */ 675 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 676 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1, 677 tx_size / 2 / dev->fifo_entry_size); 678 else 679 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1, 680 tx_size / 2 / dev->fifo_entry_size); 681 out_be32(&p->tmr1, r); 682 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2)); 683 684 /* PAUSE frame is sent when RX FIFO reaches its high-water mark, 685 there should be still enough space in FIFO to allow the our link 686 partner time to process this frame and also time to send PAUSE 687 frame itself. 688 689 Here is the worst case scenario for the RX FIFO "headroom" 690 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap): 691 692 1) One maximum-length frame on TX 1522 bytes 693 2) One PAUSE frame time 64 bytes 694 3) PAUSE frame decode time allowance 64 bytes 695 4) One maximum-length frame on RX 1522 bytes 696 5) Round-trip propagation delay of the link (100Mb) 15 bytes 697 ---------- 698 3187 bytes 699 700 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes) 701 low-water mark to RX_FIFO_SIZE / 8 (512 bytes) 702 */ 703 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size, 704 rx_size / 4 / dev->fifo_entry_size); 705 out_be32(&p->rwmr, r); 706 707 /* Set PAUSE timer to the maximum */ 708 out_be32(&p->ptr, 0xffff); 709 710 /* IRQ sources */ 711 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE | 712 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE | 713 EMAC_ISR_IRE | EMAC_ISR_TE; 714 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 715 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE | 716 EMAC4_ISR_RXOE | */; 717 out_be32(&p->iser, r); 718 719 /* We need to take GPCS PHY out of isolate mode after EMAC reset */ 720 if (emac_phy_gpcs(dev->phy.mode)) { 721 if (dev->phy.gpcs_address != 0xffffffff) 722 emac_mii_reset_gpcs(&dev->phy); 723 else 724 emac_mii_reset_phy(&dev->phy); 725 } 726 727 return 0; 728 } 729 730 static void emac_reinitialize(struct emac_instance *dev) 731 { 732 DBG(dev, "reinitialize" NL); 733 734 emac_netif_stop(dev); 735 if (!emac_configure(dev)) { 736 emac_tx_enable(dev); 737 emac_rx_enable(dev); 738 } 739 emac_netif_start(dev); 740 } 741 742 static void emac_full_tx_reset(struct emac_instance *dev) 743 { 744 DBG(dev, "full_tx_reset" NL); 745 746 emac_tx_disable(dev); 747 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan); 748 emac_clean_tx_ring(dev); 749 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0; 750 751 emac_configure(dev); 752 753 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan); 754 emac_tx_enable(dev); 755 emac_rx_enable(dev); 756 } 757 758 static void emac_reset_work(struct work_struct *work) 759 { 760 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work); 761 762 DBG(dev, "reset_work" NL); 763 764 mutex_lock(&dev->link_lock); 765 if (dev->opened) { 766 emac_netif_stop(dev); 767 emac_full_tx_reset(dev); 768 emac_netif_start(dev); 769 } 770 mutex_unlock(&dev->link_lock); 771 } 772 773 static void emac_tx_timeout(struct net_device *ndev, unsigned int txqueue) 774 { 775 struct emac_instance *dev = netdev_priv(ndev); 776 777 DBG(dev, "tx_timeout" NL); 778 779 schedule_work(&dev->reset_work); 780 } 781 782 783 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr) 784 { 785 int done = !!(stacr & EMAC_STACR_OC); 786 787 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 788 done = !done; 789 790 return done; 791 }; 792 793 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg) 794 { 795 struct emac_regs __iomem *p = dev->emacp; 796 u32 r = 0; 797 int n, err = -ETIMEDOUT; 798 799 mutex_lock(&dev->mdio_lock); 800 801 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg); 802 803 /* Enable proper MDIO port */ 804 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 805 zmii_get_mdio(dev->zmii_dev, dev->zmii_port); 806 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 807 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port); 808 809 /* Wait for management interface to become idle */ 810 n = 20; 811 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 812 udelay(1); 813 if (!--n) { 814 DBG2(dev, " -> timeout wait idle\n"); 815 goto bail; 816 } 817 } 818 819 /* Issue read command */ 820 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 821 r = EMAC4_STACR_BASE(dev->opb_bus_freq); 822 else 823 r = EMAC_STACR_BASE(dev->opb_bus_freq); 824 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 825 r |= EMAC_STACR_OC; 826 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR)) 827 r |= EMACX_STACR_STAC_READ; 828 else 829 r |= EMAC_STACR_STAC_READ; 830 r |= (reg & EMAC_STACR_PRA_MASK) 831 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT); 832 out_be32(&p->stacr, r); 833 834 /* Wait for read to complete */ 835 n = 200; 836 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) { 837 udelay(1); 838 if (!--n) { 839 DBG2(dev, " -> timeout wait complete\n"); 840 goto bail; 841 } 842 } 843 844 if (unlikely(r & EMAC_STACR_PHYE)) { 845 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg); 846 err = -EREMOTEIO; 847 goto bail; 848 } 849 850 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK); 851 852 DBG2(dev, "mdio_read -> %04x" NL, r); 853 err = 0; 854 bail: 855 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 856 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port); 857 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 858 zmii_put_mdio(dev->zmii_dev, dev->zmii_port); 859 mutex_unlock(&dev->mdio_lock); 860 861 return err == 0 ? r : err; 862 } 863 864 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg, 865 u16 val) 866 { 867 struct emac_regs __iomem *p = dev->emacp; 868 u32 r = 0; 869 int n; 870 871 mutex_lock(&dev->mdio_lock); 872 873 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val); 874 875 /* Enable proper MDIO port */ 876 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 877 zmii_get_mdio(dev->zmii_dev, dev->zmii_port); 878 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 879 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port); 880 881 /* Wait for management interface to be idle */ 882 n = 20; 883 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 884 udelay(1); 885 if (!--n) { 886 DBG2(dev, " -> timeout wait idle\n"); 887 goto bail; 888 } 889 } 890 891 /* Issue write command */ 892 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 893 r = EMAC4_STACR_BASE(dev->opb_bus_freq); 894 else 895 r = EMAC_STACR_BASE(dev->opb_bus_freq); 896 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 897 r |= EMAC_STACR_OC; 898 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR)) 899 r |= EMACX_STACR_STAC_WRITE; 900 else 901 r |= EMAC_STACR_STAC_WRITE; 902 r |= (reg & EMAC_STACR_PRA_MASK) | 903 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) | 904 (val << EMAC_STACR_PHYD_SHIFT); 905 out_be32(&p->stacr, r); 906 907 /* Wait for write to complete */ 908 n = 200; 909 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 910 udelay(1); 911 if (!--n) { 912 DBG2(dev, " -> timeout wait complete\n"); 913 goto bail; 914 } 915 } 916 bail: 917 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 918 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port); 919 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 920 zmii_put_mdio(dev->zmii_dev, dev->zmii_port); 921 mutex_unlock(&dev->mdio_lock); 922 } 923 924 static int emac_mdio_read(struct net_device *ndev, int id, int reg) 925 { 926 struct emac_instance *dev = netdev_priv(ndev); 927 int res; 928 929 res = __emac_mdio_read((dev->mdio_instance && 930 dev->phy.gpcs_address != id) ? 931 dev->mdio_instance : dev, 932 (u8) id, (u8) reg); 933 return res; 934 } 935 936 static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val) 937 { 938 struct emac_instance *dev = netdev_priv(ndev); 939 940 __emac_mdio_write((dev->mdio_instance && 941 dev->phy.gpcs_address != id) ? 942 dev->mdio_instance : dev, 943 (u8) id, (u8) reg, (u16) val); 944 } 945 946 /* Tx lock BH */ 947 static void __emac_set_multicast_list(struct emac_instance *dev) 948 { 949 struct emac_regs __iomem *p = dev->emacp; 950 u32 rmr = emac_iff2rmr(dev->ndev); 951 952 DBG(dev, "__multicast %08x" NL, rmr); 953 954 /* I decided to relax register access rules here to avoid 955 * full EMAC reset. 956 * 957 * There is a real problem with EMAC4 core if we use MWSW_001 bit 958 * in MR1 register and do a full EMAC reset. 959 * One TX BD status update is delayed and, after EMAC reset, it 960 * never happens, resulting in TX hung (it'll be recovered by TX 961 * timeout handler eventually, but this is just gross). 962 * So we either have to do full TX reset or try to cheat here :) 963 * 964 * The only required change is to RX mode register, so I *think* all 965 * we need is just to stop RX channel. This seems to work on all 966 * tested SoCs. --ebs 967 * 968 */ 969 dev->mcast_pending = 0; 970 emac_rx_disable(dev); 971 if (rmr & EMAC_RMR_MAE) 972 emac_hash_mc(dev); 973 out_be32(&p->rmr, rmr); 974 emac_rx_enable(dev); 975 } 976 977 /* Tx lock BH */ 978 static void emac_set_multicast_list(struct net_device *ndev) 979 { 980 struct emac_instance *dev = netdev_priv(ndev); 981 982 DBG(dev, "multicast" NL); 983 984 BUG_ON(!netif_running(dev->ndev)); 985 986 if (dev->no_mcast) { 987 dev->mcast_pending = 1; 988 return; 989 } 990 991 mutex_lock(&dev->link_lock); 992 __emac_set_multicast_list(dev); 993 mutex_unlock(&dev->link_lock); 994 } 995 996 static int emac_set_mac_address(struct net_device *ndev, void *sa) 997 { 998 struct emac_instance *dev = netdev_priv(ndev); 999 struct sockaddr *addr = sa; 1000 struct emac_regs __iomem *p = dev->emacp; 1001 1002 if (!is_valid_ether_addr(addr->sa_data)) 1003 return -EADDRNOTAVAIL; 1004 1005 mutex_lock(&dev->link_lock); 1006 1007 eth_hw_addr_set(ndev, addr->sa_data); 1008 1009 emac_rx_disable(dev); 1010 emac_tx_disable(dev); 1011 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]); 1012 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) | 1013 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) | 1014 ndev->dev_addr[5]); 1015 emac_tx_enable(dev); 1016 emac_rx_enable(dev); 1017 1018 mutex_unlock(&dev->link_lock); 1019 1020 return 0; 1021 } 1022 1023 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu) 1024 { 1025 int rx_sync_size = emac_rx_sync_size(new_mtu); 1026 int rx_skb_size = emac_rx_skb_size(new_mtu); 1027 int i, ret = 0; 1028 int mr1_jumbo_bit_change = 0; 1029 1030 mutex_lock(&dev->link_lock); 1031 emac_netif_stop(dev); 1032 emac_rx_disable(dev); 1033 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan); 1034 1035 if (dev->rx_sg_skb) { 1036 ++dev->estats.rx_dropped_resize; 1037 dev_kfree_skb(dev->rx_sg_skb); 1038 dev->rx_sg_skb = NULL; 1039 } 1040 1041 /* Make a first pass over RX ring and mark BDs ready, dropping 1042 * non-processed packets on the way. We need this as a separate pass 1043 * to simplify error recovery in the case of allocation failure later. 1044 */ 1045 for (i = 0; i < NUM_RX_BUFF; ++i) { 1046 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST) 1047 ++dev->estats.rx_dropped_resize; 1048 1049 dev->rx_desc[i].data_len = 0; 1050 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY | 1051 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1052 } 1053 1054 /* Reallocate RX ring only if bigger skb buffers are required */ 1055 if (rx_skb_size <= dev->rx_skb_size) 1056 goto skip; 1057 1058 /* Second pass, allocate new skbs */ 1059 for (i = 0; i < NUM_RX_BUFF; ++i) { 1060 struct sk_buff *skb; 1061 1062 skb = netdev_alloc_skb_ip_align(dev->ndev, rx_skb_size); 1063 if (!skb) { 1064 ret = -ENOMEM; 1065 goto oom; 1066 } 1067 1068 BUG_ON(!dev->rx_skb[i]); 1069 dev_kfree_skb(dev->rx_skb[i]); 1070 1071 dev->rx_desc[i].data_ptr = 1072 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN, 1073 rx_sync_size, DMA_FROM_DEVICE) 1074 + NET_IP_ALIGN; 1075 dev->rx_skb[i] = skb; 1076 } 1077 skip: 1078 /* Check if we need to change "Jumbo" bit in MR1 */ 1079 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) { 1080 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) || 1081 (dev->ndev->mtu > ETH_DATA_LEN); 1082 } else { 1083 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^ 1084 (dev->ndev->mtu > ETH_DATA_LEN); 1085 } 1086 1087 if (mr1_jumbo_bit_change) { 1088 /* This is to prevent starting RX channel in emac_rx_enable() */ 1089 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1090 1091 WRITE_ONCE(dev->ndev->mtu, new_mtu); 1092 emac_full_tx_reset(dev); 1093 } 1094 1095 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu)); 1096 oom: 1097 /* Restart RX */ 1098 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1099 dev->rx_slot = 0; 1100 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1101 emac_rx_enable(dev); 1102 emac_netif_start(dev); 1103 mutex_unlock(&dev->link_lock); 1104 1105 return ret; 1106 } 1107 1108 /* Process ctx, rtnl_lock semaphore */ 1109 static int emac_change_mtu(struct net_device *ndev, int new_mtu) 1110 { 1111 struct emac_instance *dev = netdev_priv(ndev); 1112 int ret = 0; 1113 1114 DBG(dev, "change_mtu(%d)" NL, new_mtu); 1115 1116 if (netif_running(ndev)) { 1117 /* Check if we really need to reinitialize RX ring. The 1118 * jumbo frame settings are only updated by a resize. 1119 */ 1120 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu) || 1121 ndev->mtu > ETH_DATA_LEN || new_mtu > ETH_DATA_LEN) 1122 ret = emac_resize_rx_ring(dev, new_mtu); 1123 } 1124 1125 if (!ret) { 1126 WRITE_ONCE(ndev->mtu, new_mtu); 1127 dev->rx_skb_size = emac_rx_skb_size(new_mtu); 1128 dev->rx_sync_size = emac_rx_sync_size(new_mtu); 1129 } 1130 1131 return ret; 1132 } 1133 1134 static void emac_clean_tx_ring(struct emac_instance *dev) 1135 { 1136 int i; 1137 1138 for (i = 0; i < NUM_TX_BUFF; ++i) { 1139 if (dev->tx_skb[i]) { 1140 dev_kfree_skb(dev->tx_skb[i]); 1141 dev->tx_skb[i] = NULL; 1142 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY) 1143 ++dev->estats.tx_dropped; 1144 } 1145 dev->tx_desc[i].ctrl = 0; 1146 dev->tx_desc[i].data_ptr = 0; 1147 } 1148 } 1149 1150 static void emac_clean_rx_ring(struct emac_instance *dev) 1151 { 1152 int i; 1153 1154 for (i = 0; i < NUM_RX_BUFF; ++i) 1155 if (dev->rx_skb[i]) { 1156 dev->rx_desc[i].ctrl = 0; 1157 dev_kfree_skb(dev->rx_skb[i]); 1158 dev->rx_skb[i] = NULL; 1159 dev->rx_desc[i].data_ptr = 0; 1160 } 1161 1162 if (dev->rx_sg_skb) { 1163 dev_kfree_skb(dev->rx_sg_skb); 1164 dev->rx_sg_skb = NULL; 1165 } 1166 } 1167 1168 static void emac_clear_mal_desc(struct mal_descriptor *desc, int count) 1169 { 1170 int i; 1171 1172 for (i = 0; i < count; i++) { 1173 WRITE_ONCE(desc[i].ctrl, 0); 1174 WRITE_ONCE(desc[i].data_len, 0); 1175 WRITE_ONCE(desc[i].data_ptr, 0); 1176 } 1177 } 1178 1179 static int 1180 __emac_prepare_rx_skb(struct sk_buff *skb, struct emac_instance *dev, int slot) 1181 { 1182 if (unlikely(!skb)) 1183 return -ENOMEM; 1184 1185 dev->rx_skb[slot] = skb; 1186 dev->rx_desc[slot].data_len = 0; 1187 1188 dev->rx_desc[slot].data_ptr = 1189 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN, 1190 dev->rx_sync_size, DMA_FROM_DEVICE) + NET_IP_ALIGN; 1191 wmb(); 1192 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY | 1193 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1194 1195 return 0; 1196 } 1197 1198 static int 1199 emac_alloc_rx_skb(struct emac_instance *dev, int slot) 1200 { 1201 struct sk_buff *skb; 1202 1203 skb = __netdev_alloc_skb_ip_align(dev->ndev, dev->rx_skb_size, 1204 GFP_KERNEL); 1205 1206 return __emac_prepare_rx_skb(skb, dev, slot); 1207 } 1208 1209 static int 1210 emac_alloc_rx_skb_napi(struct emac_instance *dev, int slot) 1211 { 1212 struct sk_buff *skb; 1213 1214 skb = napi_alloc_skb(&dev->mal->napi, dev->rx_skb_size); 1215 1216 return __emac_prepare_rx_skb(skb, dev, slot); 1217 } 1218 1219 static void emac_print_link_status(struct emac_instance *dev) 1220 { 1221 if (netif_carrier_ok(dev->ndev)) 1222 printk(KERN_INFO "%s: link is up, %d %s%s\n", 1223 dev->ndev->name, dev->phy.speed, 1224 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX", 1225 dev->phy.pause ? ", pause enabled" : 1226 dev->phy.asym_pause ? ", asymmetric pause enabled" : ""); 1227 else 1228 printk(KERN_INFO "%s: link is down\n", dev->ndev->name); 1229 } 1230 1231 /* Process ctx, rtnl_lock semaphore */ 1232 static int emac_open(struct net_device *ndev) 1233 { 1234 struct emac_instance *dev = netdev_priv(ndev); 1235 int i; 1236 1237 DBG(dev, "open" NL); 1238 1239 /* Allocate RX ring */ 1240 for (i = 0; i < NUM_RX_BUFF; ++i) 1241 if (emac_alloc_rx_skb(dev, i)) { 1242 printk(KERN_ERR "%s: failed to allocate RX ring\n", 1243 ndev->name); 1244 goto oom; 1245 } 1246 1247 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0; 1248 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1249 dev->rx_sg_skb = NULL; 1250 1251 mutex_lock(&dev->link_lock); 1252 dev->opened = 1; 1253 1254 /* Start PHY polling now. 1255 */ 1256 if (dev->phy.address >= 0) { 1257 int link_poll_interval; 1258 if (dev->phy.def->ops->poll_link(&dev->phy)) { 1259 dev->phy.def->ops->read_link(&dev->phy); 1260 emac_rx_clk_default(dev); 1261 netif_carrier_on(dev->ndev); 1262 link_poll_interval = PHY_POLL_LINK_ON; 1263 } else { 1264 emac_rx_clk_tx(dev); 1265 netif_carrier_off(dev->ndev); 1266 link_poll_interval = PHY_POLL_LINK_OFF; 1267 } 1268 dev->link_polling = 1; 1269 wmb(); 1270 schedule_delayed_work(&dev->link_work, link_poll_interval); 1271 emac_print_link_status(dev); 1272 } else 1273 netif_carrier_on(dev->ndev); 1274 1275 /* Required for Pause packet support in EMAC */ 1276 dev_mc_add_global(ndev, default_mcast_addr); 1277 1278 emac_configure(dev); 1279 mal_poll_add(dev->mal, &dev->commac); 1280 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan); 1281 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu)); 1282 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1283 emac_tx_enable(dev); 1284 emac_rx_enable(dev); 1285 emac_netif_start(dev); 1286 1287 mutex_unlock(&dev->link_lock); 1288 1289 return 0; 1290 oom: 1291 emac_clean_rx_ring(dev); 1292 return -ENOMEM; 1293 } 1294 1295 /* BHs disabled */ 1296 #if 0 1297 static int emac_link_differs(struct emac_instance *dev) 1298 { 1299 u32 r = in_be32(&dev->emacp->mr1); 1300 1301 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF; 1302 int speed, pause, asym_pause; 1303 1304 if (r & EMAC_MR1_MF_1000) 1305 speed = SPEED_1000; 1306 else if (r & EMAC_MR1_MF_100) 1307 speed = SPEED_100; 1308 else 1309 speed = SPEED_10; 1310 1311 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) { 1312 case (EMAC_MR1_EIFC | EMAC_MR1_APP): 1313 pause = 1; 1314 asym_pause = 0; 1315 break; 1316 case EMAC_MR1_APP: 1317 pause = 0; 1318 asym_pause = 1; 1319 break; 1320 default: 1321 pause = asym_pause = 0; 1322 } 1323 return speed != dev->phy.speed || duplex != dev->phy.duplex || 1324 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause; 1325 } 1326 #endif 1327 1328 static void emac_link_timer(struct work_struct *work) 1329 { 1330 struct emac_instance *dev = 1331 container_of(to_delayed_work(work), 1332 struct emac_instance, link_work); 1333 int link_poll_interval; 1334 1335 mutex_lock(&dev->link_lock); 1336 DBG2(dev, "link timer" NL); 1337 1338 if (!dev->opened) 1339 goto bail; 1340 1341 if (dev->phy.def->ops->poll_link(&dev->phy)) { 1342 if (!netif_carrier_ok(dev->ndev)) { 1343 emac_rx_clk_default(dev); 1344 /* Get new link parameters */ 1345 dev->phy.def->ops->read_link(&dev->phy); 1346 1347 netif_carrier_on(dev->ndev); 1348 emac_netif_stop(dev); 1349 emac_full_tx_reset(dev); 1350 emac_netif_start(dev); 1351 emac_print_link_status(dev); 1352 } 1353 link_poll_interval = PHY_POLL_LINK_ON; 1354 } else { 1355 if (netif_carrier_ok(dev->ndev)) { 1356 emac_rx_clk_tx(dev); 1357 netif_carrier_off(dev->ndev); 1358 netif_tx_disable(dev->ndev); 1359 emac_reinitialize(dev); 1360 emac_print_link_status(dev); 1361 } 1362 link_poll_interval = PHY_POLL_LINK_OFF; 1363 } 1364 schedule_delayed_work(&dev->link_work, link_poll_interval); 1365 bail: 1366 mutex_unlock(&dev->link_lock); 1367 } 1368 1369 static void emac_force_link_update(struct emac_instance *dev) 1370 { 1371 netif_carrier_off(dev->ndev); 1372 smp_rmb(); 1373 if (dev->link_polling) { 1374 cancel_delayed_work_sync(&dev->link_work); 1375 if (dev->link_polling) 1376 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF); 1377 } 1378 } 1379 1380 /* Process ctx, rtnl_lock semaphore */ 1381 static int emac_close(struct net_device *ndev) 1382 { 1383 struct emac_instance *dev = netdev_priv(ndev); 1384 1385 DBG(dev, "close" NL); 1386 1387 if (dev->phy.address >= 0) { 1388 dev->link_polling = 0; 1389 cancel_delayed_work_sync(&dev->link_work); 1390 } 1391 mutex_lock(&dev->link_lock); 1392 emac_netif_stop(dev); 1393 dev->opened = 0; 1394 mutex_unlock(&dev->link_lock); 1395 1396 emac_rx_disable(dev); 1397 emac_tx_disable(dev); 1398 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan); 1399 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan); 1400 mal_poll_del(dev->mal, &dev->commac); 1401 1402 emac_clean_tx_ring(dev); 1403 emac_clean_rx_ring(dev); 1404 1405 netif_carrier_off(ndev); 1406 1407 return 0; 1408 } 1409 1410 static inline u16 emac_tx_csum(struct emac_instance *dev, 1411 struct sk_buff *skb) 1412 { 1413 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) && 1414 (skb->ip_summed == CHECKSUM_PARTIAL)) { 1415 ++dev->stats.tx_packets_csum; 1416 return EMAC_TX_CTRL_TAH_CSUM; 1417 } 1418 return 0; 1419 } 1420 1421 static inline netdev_tx_t emac_xmit_finish(struct emac_instance *dev, int len) 1422 { 1423 struct emac_regs __iomem *p = dev->emacp; 1424 struct net_device *ndev = dev->ndev; 1425 1426 /* Send the packet out. If the if makes a significant perf 1427 * difference, then we can store the TMR0 value in "dev" 1428 * instead 1429 */ 1430 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 1431 out_be32(&p->tmr0, EMAC4_TMR0_XMIT); 1432 else 1433 out_be32(&p->tmr0, EMAC_TMR0_XMIT); 1434 1435 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) { 1436 netif_stop_queue(ndev); 1437 DBG2(dev, "stopped TX queue" NL); 1438 } 1439 1440 netif_trans_update(ndev); 1441 ++dev->stats.tx_packets; 1442 dev->stats.tx_bytes += len; 1443 1444 return NETDEV_TX_OK; 1445 } 1446 1447 /* Tx lock BH */ 1448 static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1449 { 1450 struct emac_instance *dev = netdev_priv(ndev); 1451 unsigned int len = skb->len; 1452 int slot; 1453 1454 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY | 1455 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb); 1456 1457 slot = dev->tx_slot++; 1458 if (dev->tx_slot == NUM_TX_BUFF) { 1459 dev->tx_slot = 0; 1460 ctrl |= MAL_TX_CTRL_WRAP; 1461 } 1462 1463 DBG2(dev, "xmit(%u) %d" NL, len, slot); 1464 1465 dev->tx_skb[slot] = skb; 1466 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev, 1467 skb->data, len, 1468 DMA_TO_DEVICE); 1469 dev->tx_desc[slot].data_len = (u16) len; 1470 wmb(); 1471 dev->tx_desc[slot].ctrl = ctrl; 1472 1473 return emac_xmit_finish(dev, len); 1474 } 1475 1476 static inline int emac_xmit_split(struct emac_instance *dev, int slot, 1477 u32 pd, int len, int last, u16 base_ctrl) 1478 { 1479 while (1) { 1480 u16 ctrl = base_ctrl; 1481 int chunk = min(len, MAL_MAX_TX_SIZE); 1482 len -= chunk; 1483 1484 slot = (slot + 1) % NUM_TX_BUFF; 1485 1486 if (last && !len) 1487 ctrl |= MAL_TX_CTRL_LAST; 1488 if (slot == NUM_TX_BUFF - 1) 1489 ctrl |= MAL_TX_CTRL_WRAP; 1490 1491 dev->tx_skb[slot] = NULL; 1492 dev->tx_desc[slot].data_ptr = pd; 1493 dev->tx_desc[slot].data_len = (u16) chunk; 1494 dev->tx_desc[slot].ctrl = ctrl; 1495 ++dev->tx_cnt; 1496 1497 if (!len) 1498 break; 1499 1500 pd += chunk; 1501 } 1502 return slot; 1503 } 1504 1505 /* Tx lock BH disabled (SG version for TAH equipped EMACs) */ 1506 static netdev_tx_t 1507 emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev) 1508 { 1509 struct emac_instance *dev = netdev_priv(ndev); 1510 int nr_frags = skb_shinfo(skb)->nr_frags; 1511 int len = skb->len, chunk; 1512 int slot, i; 1513 u16 ctrl; 1514 u32 pd; 1515 1516 /* This is common "fast" path */ 1517 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE)) 1518 return emac_start_xmit(skb, ndev); 1519 1520 len -= skb->data_len; 1521 1522 /* Note, this is only an *estimation*, we can still run out of empty 1523 * slots because of the additional fragmentation into 1524 * MAL_MAX_TX_SIZE-sized chunks 1525 */ 1526 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF)) 1527 goto stop_queue; 1528 1529 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY | 1530 emac_tx_csum(dev, skb); 1531 slot = dev->tx_slot; 1532 1533 /* skb data */ 1534 dev->tx_skb[slot] = NULL; 1535 chunk = min(len, MAL_MAX_TX_SIZE); 1536 dev->tx_desc[slot].data_ptr = pd = 1537 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE); 1538 dev->tx_desc[slot].data_len = (u16) chunk; 1539 len -= chunk; 1540 if (unlikely(len)) 1541 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags, 1542 ctrl); 1543 /* skb fragments */ 1544 for (i = 0; i < nr_frags; ++i) { 1545 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1546 len = skb_frag_size(frag); 1547 1548 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF)) 1549 goto undo_frame; 1550 1551 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len, 1552 DMA_TO_DEVICE); 1553 1554 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1, 1555 ctrl); 1556 } 1557 1558 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot); 1559 1560 /* Attach skb to the last slot so we don't release it too early */ 1561 dev->tx_skb[slot] = skb; 1562 1563 /* Send the packet out */ 1564 if (dev->tx_slot == NUM_TX_BUFF - 1) 1565 ctrl |= MAL_TX_CTRL_WRAP; 1566 wmb(); 1567 dev->tx_desc[dev->tx_slot].ctrl = ctrl; 1568 dev->tx_slot = (slot + 1) % NUM_TX_BUFF; 1569 1570 return emac_xmit_finish(dev, skb->len); 1571 1572 undo_frame: 1573 /* Well, too bad. Our previous estimation was overly optimistic. 1574 * Undo everything. 1575 */ 1576 while (slot != dev->tx_slot) { 1577 dev->tx_desc[slot].ctrl = 0; 1578 --dev->tx_cnt; 1579 if (--slot < 0) 1580 slot = NUM_TX_BUFF - 1; 1581 } 1582 ++dev->estats.tx_undo; 1583 1584 stop_queue: 1585 netif_stop_queue(ndev); 1586 DBG2(dev, "stopped TX queue" NL); 1587 return NETDEV_TX_BUSY; 1588 } 1589 1590 /* Tx lock BHs */ 1591 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl) 1592 { 1593 struct emac_error_stats *st = &dev->estats; 1594 1595 DBG(dev, "BD TX error %04x" NL, ctrl); 1596 1597 ++st->tx_bd_errors; 1598 if (ctrl & EMAC_TX_ST_BFCS) 1599 ++st->tx_bd_bad_fcs; 1600 if (ctrl & EMAC_TX_ST_LCS) 1601 ++st->tx_bd_carrier_loss; 1602 if (ctrl & EMAC_TX_ST_ED) 1603 ++st->tx_bd_excessive_deferral; 1604 if (ctrl & EMAC_TX_ST_EC) 1605 ++st->tx_bd_excessive_collisions; 1606 if (ctrl & EMAC_TX_ST_LC) 1607 ++st->tx_bd_late_collision; 1608 if (ctrl & EMAC_TX_ST_MC) 1609 ++st->tx_bd_multple_collisions; 1610 if (ctrl & EMAC_TX_ST_SC) 1611 ++st->tx_bd_single_collision; 1612 if (ctrl & EMAC_TX_ST_UR) 1613 ++st->tx_bd_underrun; 1614 if (ctrl & EMAC_TX_ST_SQE) 1615 ++st->tx_bd_sqe; 1616 } 1617 1618 static void emac_poll_tx(void *param) 1619 { 1620 struct emac_instance *dev = param; 1621 u32 bad_mask; 1622 1623 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot); 1624 1625 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 1626 bad_mask = EMAC_IS_BAD_TX_TAH; 1627 else 1628 bad_mask = EMAC_IS_BAD_TX; 1629 1630 netif_tx_lock_bh(dev->ndev); 1631 if (dev->tx_cnt) { 1632 u16 ctrl; 1633 int slot = dev->ack_slot, n = 0; 1634 again: 1635 ctrl = dev->tx_desc[slot].ctrl; 1636 if (!(ctrl & MAL_TX_CTRL_READY)) { 1637 struct sk_buff *skb = dev->tx_skb[slot]; 1638 ++n; 1639 1640 if (skb) { 1641 dev_kfree_skb(skb); 1642 dev->tx_skb[slot] = NULL; 1643 } 1644 slot = (slot + 1) % NUM_TX_BUFF; 1645 1646 if (unlikely(ctrl & bad_mask)) 1647 emac_parse_tx_error(dev, ctrl); 1648 1649 if (--dev->tx_cnt) 1650 goto again; 1651 } 1652 if (n) { 1653 dev->ack_slot = slot; 1654 if (netif_queue_stopped(dev->ndev) && 1655 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH) 1656 netif_wake_queue(dev->ndev); 1657 1658 DBG2(dev, "tx %d pkts" NL, n); 1659 } 1660 } 1661 netif_tx_unlock_bh(dev->ndev); 1662 } 1663 1664 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot, 1665 int len) 1666 { 1667 struct sk_buff *skb = dev->rx_skb[slot]; 1668 1669 DBG2(dev, "recycle %d %d" NL, slot, len); 1670 1671 if (len) 1672 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN, 1673 SKB_DATA_ALIGN(len + NET_IP_ALIGN), 1674 DMA_FROM_DEVICE); 1675 1676 dev->rx_desc[slot].data_len = 0; 1677 wmb(); 1678 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY | 1679 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1680 } 1681 1682 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl) 1683 { 1684 struct emac_error_stats *st = &dev->estats; 1685 1686 DBG(dev, "BD RX error %04x" NL, ctrl); 1687 1688 ++st->rx_bd_errors; 1689 if (ctrl & EMAC_RX_ST_OE) 1690 ++st->rx_bd_overrun; 1691 if (ctrl & EMAC_RX_ST_BP) 1692 ++st->rx_bd_bad_packet; 1693 if (ctrl & EMAC_RX_ST_RP) 1694 ++st->rx_bd_runt_packet; 1695 if (ctrl & EMAC_RX_ST_SE) 1696 ++st->rx_bd_short_event; 1697 if (ctrl & EMAC_RX_ST_AE) 1698 ++st->rx_bd_alignment_error; 1699 if (ctrl & EMAC_RX_ST_BFCS) 1700 ++st->rx_bd_bad_fcs; 1701 if (ctrl & EMAC_RX_ST_PTL) 1702 ++st->rx_bd_packet_too_long; 1703 if (ctrl & EMAC_RX_ST_ORE) 1704 ++st->rx_bd_out_of_range; 1705 if (ctrl & EMAC_RX_ST_IRE) 1706 ++st->rx_bd_in_range; 1707 } 1708 1709 static inline void emac_rx_csum(struct emac_instance *dev, 1710 struct sk_buff *skb, u16 ctrl) 1711 { 1712 #ifdef CONFIG_IBM_EMAC_TAH 1713 if (!ctrl && dev->tah_dev) { 1714 skb->ip_summed = CHECKSUM_UNNECESSARY; 1715 ++dev->stats.rx_packets_csum; 1716 } 1717 #endif 1718 } 1719 1720 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot) 1721 { 1722 if (likely(dev->rx_sg_skb != NULL)) { 1723 int len = dev->rx_desc[slot].data_len; 1724 int tot_len = dev->rx_sg_skb->len + len; 1725 1726 if (unlikely(tot_len + NET_IP_ALIGN > dev->rx_skb_size)) { 1727 ++dev->estats.rx_dropped_mtu; 1728 dev_kfree_skb(dev->rx_sg_skb); 1729 dev->rx_sg_skb = NULL; 1730 } else { 1731 memcpy(skb_tail_pointer(dev->rx_sg_skb), 1732 dev->rx_skb[slot]->data, len); 1733 skb_put(dev->rx_sg_skb, len); 1734 emac_recycle_rx_skb(dev, slot, len); 1735 return 0; 1736 } 1737 } 1738 emac_recycle_rx_skb(dev, slot, 0); 1739 return -1; 1740 } 1741 1742 /* NAPI poll context */ 1743 static int emac_poll_rx(void *param, int budget) 1744 { 1745 struct emac_instance *dev = param; 1746 int slot = dev->rx_slot, received = 0; 1747 1748 DBG2(dev, "poll_rx(%d)" NL, budget); 1749 1750 again: 1751 while (budget > 0) { 1752 int len; 1753 struct sk_buff *skb; 1754 u16 ctrl = dev->rx_desc[slot].ctrl; 1755 1756 if (ctrl & MAL_RX_CTRL_EMPTY) 1757 break; 1758 1759 skb = dev->rx_skb[slot]; 1760 mb(); 1761 len = dev->rx_desc[slot].data_len; 1762 1763 if (unlikely(!MAL_IS_SINGLE_RX(ctrl))) 1764 goto sg; 1765 1766 ctrl &= EMAC_BAD_RX_MASK; 1767 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) { 1768 emac_parse_rx_error(dev, ctrl); 1769 ++dev->estats.rx_dropped_error; 1770 emac_recycle_rx_skb(dev, slot, 0); 1771 len = 0; 1772 goto next; 1773 } 1774 1775 if (len < ETH_HLEN) { 1776 ++dev->estats.rx_dropped_stack; 1777 emac_recycle_rx_skb(dev, slot, len); 1778 goto next; 1779 } 1780 1781 if (len && len < EMAC_RX_COPY_THRESH) { 1782 struct sk_buff *copy_skb; 1783 1784 copy_skb = napi_alloc_skb(&dev->mal->napi, len); 1785 if (unlikely(!copy_skb)) 1786 goto oom; 1787 1788 memcpy(copy_skb->data - NET_IP_ALIGN, 1789 skb->data - NET_IP_ALIGN, 1790 len + NET_IP_ALIGN); 1791 emac_recycle_rx_skb(dev, slot, len); 1792 skb = copy_skb; 1793 } else if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) 1794 goto oom; 1795 1796 skb_put(skb, len); 1797 push_packet: 1798 skb->protocol = eth_type_trans(skb, dev->ndev); 1799 emac_rx_csum(dev, skb, ctrl); 1800 1801 napi_gro_receive(&dev->mal->napi, skb); 1802 next: 1803 ++dev->stats.rx_packets; 1804 skip: 1805 dev->stats.rx_bytes += len; 1806 slot = (slot + 1) % NUM_RX_BUFF; 1807 --budget; 1808 ++received; 1809 continue; 1810 sg: 1811 if (ctrl & MAL_RX_CTRL_FIRST) { 1812 BUG_ON(dev->rx_sg_skb); 1813 if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) { 1814 DBG(dev, "rx OOM %d" NL, slot); 1815 ++dev->estats.rx_dropped_oom; 1816 emac_recycle_rx_skb(dev, slot, 0); 1817 } else { 1818 dev->rx_sg_skb = skb; 1819 skb_put(skb, len); 1820 } 1821 } else if (!emac_rx_sg_append(dev, slot) && 1822 (ctrl & MAL_RX_CTRL_LAST)) { 1823 1824 skb = dev->rx_sg_skb; 1825 dev->rx_sg_skb = NULL; 1826 1827 ctrl &= EMAC_BAD_RX_MASK; 1828 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) { 1829 emac_parse_rx_error(dev, ctrl); 1830 ++dev->estats.rx_dropped_error; 1831 dev_kfree_skb(skb); 1832 len = 0; 1833 } else 1834 goto push_packet; 1835 } 1836 goto skip; 1837 oom: 1838 DBG(dev, "rx OOM %d" NL, slot); 1839 /* Drop the packet and recycle skb */ 1840 ++dev->estats.rx_dropped_oom; 1841 emac_recycle_rx_skb(dev, slot, 0); 1842 goto next; 1843 } 1844 1845 if (received) { 1846 DBG2(dev, "rx %d BDs" NL, received); 1847 dev->rx_slot = slot; 1848 } 1849 1850 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) { 1851 mb(); 1852 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) { 1853 DBG2(dev, "rx restart" NL); 1854 received = 0; 1855 goto again; 1856 } 1857 1858 if (dev->rx_sg_skb) { 1859 DBG2(dev, "dropping partial rx packet" NL); 1860 ++dev->estats.rx_dropped_error; 1861 dev_kfree_skb(dev->rx_sg_skb); 1862 dev->rx_sg_skb = NULL; 1863 } 1864 1865 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1866 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1867 emac_rx_enable(dev); 1868 dev->rx_slot = 0; 1869 } 1870 return received; 1871 } 1872 1873 /* NAPI poll context */ 1874 static int emac_peek_rx(void *param) 1875 { 1876 struct emac_instance *dev = param; 1877 1878 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY); 1879 } 1880 1881 /* NAPI poll context */ 1882 static int emac_peek_rx_sg(void *param) 1883 { 1884 struct emac_instance *dev = param; 1885 1886 int slot = dev->rx_slot; 1887 while (1) { 1888 u16 ctrl = dev->rx_desc[slot].ctrl; 1889 if (ctrl & MAL_RX_CTRL_EMPTY) 1890 return 0; 1891 else if (ctrl & MAL_RX_CTRL_LAST) 1892 return 1; 1893 1894 slot = (slot + 1) % NUM_RX_BUFF; 1895 1896 /* I'm just being paranoid here :) */ 1897 if (unlikely(slot == dev->rx_slot)) 1898 return 0; 1899 } 1900 } 1901 1902 /* Hard IRQ */ 1903 static void emac_rxde(void *param) 1904 { 1905 struct emac_instance *dev = param; 1906 1907 ++dev->estats.rx_stopped; 1908 emac_rx_disable_async(dev); 1909 } 1910 1911 /* Hard IRQ */ 1912 static irqreturn_t emac_irq(int irq, void *dev_instance) 1913 { 1914 struct emac_instance *dev = dev_instance; 1915 struct emac_regs __iomem *p = dev->emacp; 1916 struct emac_error_stats *st = &dev->estats; 1917 u32 isr; 1918 1919 spin_lock(&dev->lock); 1920 1921 isr = in_be32(&p->isr); 1922 out_be32(&p->isr, isr); 1923 1924 DBG(dev, "isr = %08x" NL, isr); 1925 1926 if (isr & EMAC4_ISR_TXPE) 1927 ++st->tx_parity; 1928 if (isr & EMAC4_ISR_RXPE) 1929 ++st->rx_parity; 1930 if (isr & EMAC4_ISR_TXUE) 1931 ++st->tx_underrun; 1932 if (isr & EMAC4_ISR_RXOE) 1933 ++st->rx_fifo_overrun; 1934 if (isr & EMAC_ISR_OVR) 1935 ++st->rx_overrun; 1936 if (isr & EMAC_ISR_BP) 1937 ++st->rx_bad_packet; 1938 if (isr & EMAC_ISR_RP) 1939 ++st->rx_runt_packet; 1940 if (isr & EMAC_ISR_SE) 1941 ++st->rx_short_event; 1942 if (isr & EMAC_ISR_ALE) 1943 ++st->rx_alignment_error; 1944 if (isr & EMAC_ISR_BFCS) 1945 ++st->rx_bad_fcs; 1946 if (isr & EMAC_ISR_PTLE) 1947 ++st->rx_packet_too_long; 1948 if (isr & EMAC_ISR_ORE) 1949 ++st->rx_out_of_range; 1950 if (isr & EMAC_ISR_IRE) 1951 ++st->rx_in_range; 1952 if (isr & EMAC_ISR_SQE) 1953 ++st->tx_sqe; 1954 if (isr & EMAC_ISR_TE) 1955 ++st->tx_errors; 1956 1957 spin_unlock(&dev->lock); 1958 1959 return IRQ_HANDLED; 1960 } 1961 1962 static struct net_device_stats *emac_stats(struct net_device *ndev) 1963 { 1964 struct emac_instance *dev = netdev_priv(ndev); 1965 struct emac_stats *st = &dev->stats; 1966 struct emac_error_stats *est = &dev->estats; 1967 struct net_device_stats *nst = &ndev->stats; 1968 unsigned long flags; 1969 1970 DBG2(dev, "stats" NL); 1971 1972 /* Compute "legacy" statistics */ 1973 spin_lock_irqsave(&dev->lock, flags); 1974 nst->rx_packets = (unsigned long)st->rx_packets; 1975 nst->rx_bytes = (unsigned long)st->rx_bytes; 1976 nst->tx_packets = (unsigned long)st->tx_packets; 1977 nst->tx_bytes = (unsigned long)st->tx_bytes; 1978 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom + 1979 est->rx_dropped_error + 1980 est->rx_dropped_resize + 1981 est->rx_dropped_mtu); 1982 nst->tx_dropped = (unsigned long)est->tx_dropped; 1983 1984 nst->rx_errors = (unsigned long)est->rx_bd_errors; 1985 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun + 1986 est->rx_fifo_overrun + 1987 est->rx_overrun); 1988 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error + 1989 est->rx_alignment_error); 1990 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs + 1991 est->rx_bad_fcs); 1992 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet + 1993 est->rx_bd_short_event + 1994 est->rx_bd_packet_too_long + 1995 est->rx_bd_out_of_range + 1996 est->rx_bd_in_range + 1997 est->rx_runt_packet + 1998 est->rx_short_event + 1999 est->rx_packet_too_long + 2000 est->rx_out_of_range + 2001 est->rx_in_range); 2002 2003 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors); 2004 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun + 2005 est->tx_underrun); 2006 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss; 2007 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral + 2008 est->tx_bd_excessive_collisions + 2009 est->tx_bd_late_collision + 2010 est->tx_bd_multple_collisions); 2011 spin_unlock_irqrestore(&dev->lock, flags); 2012 return nst; 2013 } 2014 2015 static struct mal_commac_ops emac_commac_ops = { 2016 .poll_tx = &emac_poll_tx, 2017 .poll_rx = &emac_poll_rx, 2018 .peek_rx = &emac_peek_rx, 2019 .rxde = &emac_rxde, 2020 }; 2021 2022 static struct mal_commac_ops emac_commac_sg_ops = { 2023 .poll_tx = &emac_poll_tx, 2024 .poll_rx = &emac_poll_rx, 2025 .peek_rx = &emac_peek_rx_sg, 2026 .rxde = &emac_rxde, 2027 }; 2028 2029 /* Ethtool support */ 2030 static int emac_ethtool_get_link_ksettings(struct net_device *ndev, 2031 struct ethtool_link_ksettings *cmd) 2032 { 2033 struct emac_instance *dev = netdev_priv(ndev); 2034 u32 supported, advertising; 2035 2036 supported = dev->phy.features; 2037 cmd->base.port = PORT_MII; 2038 cmd->base.phy_address = dev->phy.address; 2039 2040 mutex_lock(&dev->link_lock); 2041 advertising = dev->phy.advertising; 2042 cmd->base.autoneg = dev->phy.autoneg; 2043 cmd->base.speed = dev->phy.speed; 2044 cmd->base.duplex = dev->phy.duplex; 2045 mutex_unlock(&dev->link_lock); 2046 2047 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 2048 supported); 2049 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 2050 advertising); 2051 2052 return 0; 2053 } 2054 2055 static int 2056 emac_ethtool_set_link_ksettings(struct net_device *ndev, 2057 const struct ethtool_link_ksettings *cmd) 2058 { 2059 struct emac_instance *dev = netdev_priv(ndev); 2060 u32 f = dev->phy.features; 2061 u32 advertising; 2062 2063 ethtool_convert_link_mode_to_legacy_u32(&advertising, 2064 cmd->link_modes.advertising); 2065 2066 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL, 2067 cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising); 2068 2069 /* Basic sanity checks */ 2070 if (dev->phy.address < 0) 2071 return -EOPNOTSUPP; 2072 if (cmd->base.autoneg != AUTONEG_ENABLE && 2073 cmd->base.autoneg != AUTONEG_DISABLE) 2074 return -EINVAL; 2075 if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0) 2076 return -EINVAL; 2077 if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL) 2078 return -EINVAL; 2079 2080 if (cmd->base.autoneg == AUTONEG_DISABLE) { 2081 switch (cmd->base.speed) { 2082 case SPEED_10: 2083 if (cmd->base.duplex == DUPLEX_HALF && 2084 !(f & SUPPORTED_10baseT_Half)) 2085 return -EINVAL; 2086 if (cmd->base.duplex == DUPLEX_FULL && 2087 !(f & SUPPORTED_10baseT_Full)) 2088 return -EINVAL; 2089 break; 2090 case SPEED_100: 2091 if (cmd->base.duplex == DUPLEX_HALF && 2092 !(f & SUPPORTED_100baseT_Half)) 2093 return -EINVAL; 2094 if (cmd->base.duplex == DUPLEX_FULL && 2095 !(f & SUPPORTED_100baseT_Full)) 2096 return -EINVAL; 2097 break; 2098 case SPEED_1000: 2099 if (cmd->base.duplex == DUPLEX_HALF && 2100 !(f & SUPPORTED_1000baseT_Half)) 2101 return -EINVAL; 2102 if (cmd->base.duplex == DUPLEX_FULL && 2103 !(f & SUPPORTED_1000baseT_Full)) 2104 return -EINVAL; 2105 break; 2106 default: 2107 return -EINVAL; 2108 } 2109 2110 mutex_lock(&dev->link_lock); 2111 dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed, 2112 cmd->base.duplex); 2113 mutex_unlock(&dev->link_lock); 2114 2115 } else { 2116 if (!(f & SUPPORTED_Autoneg)) 2117 return -EINVAL; 2118 2119 mutex_lock(&dev->link_lock); 2120 dev->phy.def->ops->setup_aneg(&dev->phy, 2121 (advertising & f) | 2122 (dev->phy.advertising & 2123 (ADVERTISED_Pause | 2124 ADVERTISED_Asym_Pause))); 2125 mutex_unlock(&dev->link_lock); 2126 } 2127 emac_force_link_update(dev); 2128 2129 return 0; 2130 } 2131 2132 static void 2133 emac_ethtool_get_ringparam(struct net_device *ndev, 2134 struct ethtool_ringparam *rp, 2135 struct kernel_ethtool_ringparam *kernel_rp, 2136 struct netlink_ext_ack *extack) 2137 { 2138 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF; 2139 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF; 2140 } 2141 2142 static void emac_ethtool_get_pauseparam(struct net_device *ndev, 2143 struct ethtool_pauseparam *pp) 2144 { 2145 struct emac_instance *dev = netdev_priv(ndev); 2146 2147 mutex_lock(&dev->link_lock); 2148 if ((dev->phy.features & SUPPORTED_Autoneg) && 2149 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause))) 2150 pp->autoneg = 1; 2151 2152 if (dev->phy.duplex == DUPLEX_FULL) { 2153 if (dev->phy.pause) 2154 pp->rx_pause = pp->tx_pause = 1; 2155 else if (dev->phy.asym_pause) 2156 pp->tx_pause = 1; 2157 } 2158 mutex_unlock(&dev->link_lock); 2159 } 2160 2161 static int emac_get_regs_len(struct emac_instance *dev) 2162 { 2163 return sizeof(struct emac_ethtool_regs_subhdr) + 2164 sizeof(struct emac_regs); 2165 } 2166 2167 static int emac_ethtool_get_regs_len(struct net_device *ndev) 2168 { 2169 struct emac_instance *dev = netdev_priv(ndev); 2170 int size; 2171 2172 size = sizeof(struct emac_ethtool_regs_hdr) + 2173 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal); 2174 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 2175 size += zmii_get_regs_len(dev->zmii_dev); 2176 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 2177 size += rgmii_get_regs_len(dev->rgmii_dev); 2178 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 2179 size += tah_get_regs_len(dev->tah_dev); 2180 2181 return size; 2182 } 2183 2184 static void *emac_dump_regs(struct emac_instance *dev, void *buf) 2185 { 2186 struct emac_ethtool_regs_subhdr *hdr = buf; 2187 2188 hdr->index = dev->cell_index; 2189 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) { 2190 hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER; 2191 } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) { 2192 hdr->version = EMAC4_ETHTOOL_REGS_VER; 2193 } else { 2194 hdr->version = EMAC_ETHTOOL_REGS_VER; 2195 } 2196 memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs)); 2197 return (void *)(hdr + 1) + sizeof(struct emac_regs); 2198 } 2199 2200 static void emac_ethtool_get_regs(struct net_device *ndev, 2201 struct ethtool_regs *regs, void *buf) 2202 { 2203 struct emac_instance *dev = netdev_priv(ndev); 2204 struct emac_ethtool_regs_hdr *hdr = buf; 2205 2206 hdr->components = 0; 2207 buf = hdr + 1; 2208 2209 buf = mal_dump_regs(dev->mal, buf); 2210 buf = emac_dump_regs(dev, buf); 2211 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) { 2212 hdr->components |= EMAC_ETHTOOL_REGS_ZMII; 2213 buf = zmii_dump_regs(dev->zmii_dev, buf); 2214 } 2215 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) { 2216 hdr->components |= EMAC_ETHTOOL_REGS_RGMII; 2217 buf = rgmii_dump_regs(dev->rgmii_dev, buf); 2218 } 2219 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) { 2220 hdr->components |= EMAC_ETHTOOL_REGS_TAH; 2221 buf = tah_dump_regs(dev->tah_dev, buf); 2222 } 2223 } 2224 2225 static int emac_ethtool_nway_reset(struct net_device *ndev) 2226 { 2227 struct emac_instance *dev = netdev_priv(ndev); 2228 int res = 0; 2229 2230 DBG(dev, "nway_reset" NL); 2231 2232 if (dev->phy.address < 0) 2233 return -EOPNOTSUPP; 2234 2235 mutex_lock(&dev->link_lock); 2236 if (!dev->phy.autoneg) { 2237 res = -EINVAL; 2238 goto out; 2239 } 2240 2241 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising); 2242 out: 2243 mutex_unlock(&dev->link_lock); 2244 emac_force_link_update(dev); 2245 return res; 2246 } 2247 2248 static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset) 2249 { 2250 if (stringset == ETH_SS_STATS) 2251 return EMAC_ETHTOOL_STATS_COUNT; 2252 else 2253 return -EINVAL; 2254 } 2255 2256 static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset, 2257 u8 * buf) 2258 { 2259 if (stringset == ETH_SS_STATS) 2260 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys)); 2261 } 2262 2263 static void emac_ethtool_get_ethtool_stats(struct net_device *ndev, 2264 struct ethtool_stats *estats, 2265 u64 * tmp_stats) 2266 { 2267 struct emac_instance *dev = netdev_priv(ndev); 2268 2269 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats)); 2270 tmp_stats += sizeof(dev->stats) / sizeof(u64); 2271 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats)); 2272 } 2273 2274 static void emac_ethtool_get_drvinfo(struct net_device *ndev, 2275 struct ethtool_drvinfo *info) 2276 { 2277 struct emac_instance *dev = netdev_priv(ndev); 2278 2279 strscpy(info->driver, "ibm_emac", sizeof(info->driver)); 2280 strscpy(info->version, DRV_VERSION, sizeof(info->version)); 2281 snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %pOF", 2282 dev->cell_index, dev->ofdev->dev.of_node); 2283 } 2284 2285 static const struct ethtool_ops emac_ethtool_ops = { 2286 .get_drvinfo = emac_ethtool_get_drvinfo, 2287 2288 .get_regs_len = emac_ethtool_get_regs_len, 2289 .get_regs = emac_ethtool_get_regs, 2290 2291 .nway_reset = emac_ethtool_nway_reset, 2292 2293 .get_ringparam = emac_ethtool_get_ringparam, 2294 .get_pauseparam = emac_ethtool_get_pauseparam, 2295 2296 .get_strings = emac_ethtool_get_strings, 2297 .get_sset_count = emac_ethtool_get_sset_count, 2298 .get_ethtool_stats = emac_ethtool_get_ethtool_stats, 2299 2300 .get_link = ethtool_op_get_link, 2301 .get_link_ksettings = emac_ethtool_get_link_ksettings, 2302 .set_link_ksettings = emac_ethtool_set_link_ksettings, 2303 }; 2304 2305 static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2306 { 2307 struct emac_instance *dev = netdev_priv(ndev); 2308 struct mii_ioctl_data *data = if_mii(rq); 2309 2310 DBG(dev, "ioctl %08x" NL, cmd); 2311 2312 if (dev->phy.address < 0) 2313 return -EOPNOTSUPP; 2314 2315 switch (cmd) { 2316 case SIOCGMIIPHY: 2317 data->phy_id = dev->phy.address; 2318 fallthrough; 2319 case SIOCGMIIREG: 2320 data->val_out = emac_mdio_read(ndev, dev->phy.address, 2321 data->reg_num); 2322 return 0; 2323 2324 case SIOCSMIIREG: 2325 emac_mdio_write(ndev, dev->phy.address, data->reg_num, 2326 data->val_in); 2327 return 0; 2328 default: 2329 return -EOPNOTSUPP; 2330 } 2331 } 2332 2333 struct emac_depentry { 2334 u32 phandle; 2335 struct device_node *node; 2336 struct platform_device *ofdev; 2337 void *drvdata; 2338 }; 2339 2340 #define EMAC_DEP_MAL_IDX 0 2341 #define EMAC_DEP_ZMII_IDX 1 2342 #define EMAC_DEP_RGMII_IDX 2 2343 #define EMAC_DEP_TAH_IDX 3 2344 #define EMAC_DEP_MDIO_IDX 4 2345 #define EMAC_DEP_PREV_IDX 5 2346 #define EMAC_DEP_COUNT 6 2347 2348 static int emac_check_deps(struct emac_instance *dev, 2349 struct emac_depentry *deps) 2350 { 2351 int i, there = 0; 2352 struct device_node *np; 2353 2354 for (i = 0; i < EMAC_DEP_COUNT; i++) { 2355 /* no dependency on that item, allright */ 2356 if (deps[i].phandle == 0) { 2357 there++; 2358 continue; 2359 } 2360 /* special case for blist as the dependency might go away */ 2361 if (i == EMAC_DEP_PREV_IDX) { 2362 np = *(dev->blist - 1); 2363 if (np == NULL) { 2364 deps[i].phandle = 0; 2365 there++; 2366 continue; 2367 } 2368 if (deps[i].node == NULL) 2369 deps[i].node = of_node_get(np); 2370 } 2371 if (deps[i].node == NULL) 2372 deps[i].node = of_find_node_by_phandle(deps[i].phandle); 2373 if (deps[i].node == NULL) 2374 continue; 2375 if (deps[i].ofdev == NULL) 2376 deps[i].ofdev = of_find_device_by_node(deps[i].node); 2377 if (deps[i].ofdev == NULL) 2378 continue; 2379 if (deps[i].drvdata == NULL) 2380 deps[i].drvdata = platform_get_drvdata(deps[i].ofdev); 2381 if (deps[i].drvdata != NULL) 2382 there++; 2383 } 2384 if (there != EMAC_DEP_COUNT) 2385 return -EPROBE_DEFER; 2386 return 0; 2387 } 2388 2389 static void emac_put_deps(struct emac_instance *dev) 2390 { 2391 platform_device_put(dev->mal_dev); 2392 platform_device_put(dev->zmii_dev); 2393 platform_device_put(dev->rgmii_dev); 2394 platform_device_put(dev->mdio_dev); 2395 platform_device_put(dev->tah_dev); 2396 } 2397 2398 static int emac_wait_deps(struct emac_instance *dev) 2399 { 2400 struct emac_depentry deps[EMAC_DEP_COUNT]; 2401 int i, err; 2402 2403 memset(&deps, 0, sizeof(deps)); 2404 2405 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph; 2406 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph; 2407 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph; 2408 if (dev->tah_ph) 2409 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph; 2410 if (dev->mdio_ph) 2411 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph; 2412 if (dev->blist && dev->blist > emac_boot_list) 2413 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu; 2414 err = emac_check_deps(dev, deps); 2415 for (i = 0; i < EMAC_DEP_COUNT; i++) { 2416 of_node_put(deps[i].node); 2417 if (err) 2418 platform_device_put(deps[i].ofdev); 2419 } 2420 if (!err) { 2421 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev; 2422 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev; 2423 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev; 2424 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev; 2425 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev; 2426 } 2427 platform_device_put(deps[EMAC_DEP_PREV_IDX].ofdev); 2428 return err; 2429 } 2430 2431 static int emac_read_uint_prop(struct device_node *np, const char *name, 2432 u32 *val, int fatal) 2433 { 2434 int err; 2435 2436 err = of_property_read_u32(np, name, val); 2437 if (err) { 2438 if (fatal) 2439 pr_err("%pOF: missing %s property", np, name); 2440 return err; 2441 } 2442 return 0; 2443 } 2444 2445 static void emac_adjust_link(struct net_device *ndev) 2446 { 2447 struct emac_instance *dev = netdev_priv(ndev); 2448 struct phy_device *phy = ndev->phydev; 2449 2450 dev->phy.autoneg = phy->autoneg; 2451 dev->phy.speed = phy->speed; 2452 dev->phy.duplex = phy->duplex; 2453 dev->phy.pause = phy->pause; 2454 dev->phy.asym_pause = phy->asym_pause; 2455 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.advertising, 2456 phy->advertising); 2457 } 2458 2459 static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum) 2460 { 2461 int ret = emac_mdio_read(bus->priv, addr, regnum); 2462 /* This is a workaround for powered down ports/phys. 2463 * In the wild, this was seen on the Cisco Meraki MX60(W). 2464 * This hardware disables ports as part of the handoff 2465 * procedure. Accessing the ports will lead to errors 2466 * (-ETIMEDOUT, -EREMOTEIO) that do more harm than good. 2467 */ 2468 return ret < 0 ? 0xffff : ret; 2469 } 2470 2471 static int emac_mii_bus_write(struct mii_bus *bus, int addr, 2472 int regnum, u16 val) 2473 { 2474 emac_mdio_write(bus->priv, addr, regnum, val); 2475 return 0; 2476 } 2477 2478 static int emac_mii_bus_reset(struct mii_bus *bus) 2479 { 2480 struct emac_instance *dev = netdev_priv(bus->priv); 2481 2482 return emac_reset(dev); 2483 } 2484 2485 static int emac_mdio_phy_start_aneg(struct mii_phy *phy, 2486 struct phy_device *phy_dev) 2487 { 2488 phy_dev->autoneg = phy->autoneg; 2489 phy_dev->speed = phy->speed; 2490 phy_dev->duplex = phy->duplex; 2491 ethtool_convert_legacy_u32_to_link_mode(phy_dev->advertising, 2492 phy->advertising); 2493 return phy_start_aneg(phy_dev); 2494 } 2495 2496 static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise) 2497 { 2498 struct net_device *ndev = phy->dev; 2499 2500 phy->autoneg = AUTONEG_ENABLE; 2501 phy->advertising = advertise; 2502 return emac_mdio_phy_start_aneg(phy, ndev->phydev); 2503 } 2504 2505 static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd) 2506 { 2507 struct net_device *ndev = phy->dev; 2508 2509 phy->autoneg = AUTONEG_DISABLE; 2510 phy->speed = speed; 2511 phy->duplex = fd; 2512 return emac_mdio_phy_start_aneg(phy, ndev->phydev); 2513 } 2514 2515 static int emac_mdio_poll_link(struct mii_phy *phy) 2516 { 2517 struct net_device *ndev = phy->dev; 2518 struct emac_instance *dev = netdev_priv(ndev); 2519 int res; 2520 2521 res = phy_read_status(ndev->phydev); 2522 if (res) { 2523 dev_err(&dev->ofdev->dev, "link update failed (%d).", res); 2524 return ethtool_op_get_link(ndev); 2525 } 2526 2527 return ndev->phydev->link; 2528 } 2529 2530 static int emac_mdio_read_link(struct mii_phy *phy) 2531 { 2532 struct net_device *ndev = phy->dev; 2533 struct phy_device *phy_dev = ndev->phydev; 2534 int res; 2535 2536 res = phy_read_status(phy_dev); 2537 if (res) 2538 return res; 2539 2540 phy->speed = phy_dev->speed; 2541 phy->duplex = phy_dev->duplex; 2542 phy->pause = phy_dev->pause; 2543 phy->asym_pause = phy_dev->asym_pause; 2544 return 0; 2545 } 2546 2547 static int emac_mdio_init_phy(struct mii_phy *phy) 2548 { 2549 struct net_device *ndev = phy->dev; 2550 2551 phy_start(ndev->phydev); 2552 return phy_init_hw(ndev->phydev); 2553 } 2554 2555 static const struct mii_phy_ops emac_dt_mdio_phy_ops = { 2556 .init = emac_mdio_init_phy, 2557 .setup_aneg = emac_mdio_setup_aneg, 2558 .setup_forced = emac_mdio_setup_forced, 2559 .poll_link = emac_mdio_poll_link, 2560 .read_link = emac_mdio_read_link, 2561 }; 2562 2563 static int emac_dt_mdio_probe(struct emac_instance *dev) 2564 { 2565 struct device_node *mii_np; 2566 struct mii_bus *bus; 2567 int res; 2568 2569 mii_np = of_get_available_child_by_name(dev->ofdev->dev.of_node, "mdio"); 2570 if (!mii_np) { 2571 dev_err(&dev->ofdev->dev, "no mdio definition found."); 2572 return -ENODEV; 2573 } 2574 2575 bus = devm_mdiobus_alloc(&dev->ofdev->dev); 2576 if (!bus) { 2577 res = -ENOMEM; 2578 goto put_node; 2579 } 2580 2581 bus->priv = dev->ndev; 2582 bus->parent = dev->ndev->dev.parent; 2583 bus->name = "emac_mdio"; 2584 bus->read = &emac_mii_bus_read; 2585 bus->write = &emac_mii_bus_write; 2586 bus->reset = &emac_mii_bus_reset; 2587 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name); 2588 res = devm_of_mdiobus_register(&dev->ofdev->dev, bus, mii_np); 2589 if (res) { 2590 dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)", 2591 bus->name, res); 2592 } 2593 2594 put_node: 2595 of_node_put(mii_np); 2596 return res; 2597 } 2598 2599 static int emac_dt_phy_connect(struct emac_instance *dev, 2600 struct device_node *phy_handle) 2601 { 2602 struct phy_device *phy_dev; 2603 2604 dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def), 2605 GFP_KERNEL); 2606 if (!dev->phy.def) 2607 return -ENOMEM; 2608 2609 phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link, 0, 2610 dev->phy_mode); 2611 if (!phy_dev) { 2612 dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n"); 2613 return -ENODEV; 2614 } 2615 2616 dev->phy.def->phy_id = phy_dev->drv->phy_id; 2617 dev->phy.def->phy_id_mask = phy_dev->drv->phy_id_mask; 2618 dev->phy.def->name = phy_dev->drv->name; 2619 dev->phy.def->ops = &emac_dt_mdio_phy_ops; 2620 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.features, 2621 phy_dev->supported); 2622 dev->phy.address = phy_dev->mdio.addr; 2623 dev->phy.mode = phy_dev->interface; 2624 return 0; 2625 } 2626 2627 static int emac_dt_phy_probe(struct emac_instance *dev) 2628 { 2629 struct device_node *np = dev->ofdev->dev.of_node; 2630 struct device_node *phy_handle; 2631 int res = 1; 2632 2633 phy_handle = of_parse_phandle(np, "phy-handle", 0); 2634 2635 if (phy_handle) { 2636 res = emac_dt_mdio_probe(dev); 2637 if (!res) { 2638 res = emac_dt_phy_connect(dev, phy_handle); 2639 } 2640 } 2641 2642 of_node_put(phy_handle); 2643 return res; 2644 } 2645 2646 static int emac_init_phy(struct emac_instance *dev) 2647 { 2648 struct device_node *np = dev->ofdev->dev.of_node; 2649 struct net_device *ndev = dev->ndev; 2650 u32 phy_map, adv; 2651 int i; 2652 2653 dev->phy.dev = ndev; 2654 dev->phy.mode = dev->phy_mode; 2655 2656 /* PHY-less configuration. */ 2657 if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) || 2658 of_phy_is_fixed_link(np)) { 2659 emac_reset(dev); 2660 2661 /* PHY-less configuration. */ 2662 dev->phy.address = -1; 2663 dev->phy.features = SUPPORTED_MII; 2664 if (emac_phy_supports_gige(dev->phy_mode)) 2665 dev->phy.features |= SUPPORTED_1000baseT_Full; 2666 else 2667 dev->phy.features |= SUPPORTED_100baseT_Full; 2668 dev->phy.pause = 1; 2669 2670 if (of_phy_is_fixed_link(np)) { 2671 int res = emac_dt_mdio_probe(dev); 2672 2673 if (res) 2674 return res; 2675 2676 res = of_phy_register_fixed_link(np); 2677 ndev->phydev = of_phy_find_device(np); 2678 if (res || !ndev->phydev) 2679 return res ? res : -EINVAL; 2680 emac_adjust_link(dev->ndev); 2681 put_device(&ndev->phydev->mdio.dev); 2682 } 2683 return 0; 2684 } 2685 2686 mutex_lock(&emac_phy_map_lock); 2687 phy_map = dev->phy_map | busy_phy_map; 2688 2689 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map); 2690 2691 dev->phy.mdio_read = emac_mdio_read; 2692 dev->phy.mdio_write = emac_mdio_write; 2693 2694 /* Enable internal clock source */ 2695 #ifdef CONFIG_PPC_DCR_NATIVE 2696 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2697 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); 2698 #endif 2699 /* PHY clock workaround */ 2700 emac_rx_clk_tx(dev); 2701 2702 /* Enable internal clock source on 440GX*/ 2703 #ifdef CONFIG_PPC_DCR_NATIVE 2704 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2705 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); 2706 #endif 2707 /* Configure EMAC with defaults so we can at least use MDIO 2708 * This is needed mostly for 440GX 2709 */ 2710 if (emac_phy_gpcs(dev->phy.mode)) { 2711 /* XXX 2712 * Make GPCS PHY address equal to EMAC index. 2713 * We probably should take into account busy_phy_map 2714 * and/or phy_map here. 2715 * 2716 * Note that the busy_phy_map is currently global 2717 * while it should probably be per-ASIC... 2718 */ 2719 dev->phy.gpcs_address = dev->gpcs_address; 2720 if (dev->phy.gpcs_address == 0xffffffff) 2721 dev->phy.address = dev->cell_index; 2722 } 2723 2724 emac_configure(dev); 2725 2726 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) { 2727 int res = emac_dt_phy_probe(dev); 2728 2729 switch (res) { 2730 case 1: 2731 /* No phy-handle property configured. 2732 * Continue with the existing phy probe 2733 * and setup code. 2734 */ 2735 break; 2736 2737 case 0: 2738 mutex_unlock(&emac_phy_map_lock); 2739 goto init_phy; 2740 2741 default: 2742 mutex_unlock(&emac_phy_map_lock); 2743 dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n", 2744 res); 2745 return res; 2746 } 2747 } 2748 2749 if (dev->phy_address != 0xffffffff) 2750 phy_map = ~(1 << dev->phy_address); 2751 2752 for (i = 0; i < 0x20; phy_map >>= 1, ++i) 2753 if (!(phy_map & 1)) { 2754 int r; 2755 busy_phy_map |= 1 << i; 2756 2757 /* Quick check if there is a PHY at the address */ 2758 r = emac_mdio_read(dev->ndev, i, MII_BMCR); 2759 if (r == 0xffff || r < 0) 2760 continue; 2761 if (!emac_mii_phy_probe(&dev->phy, i)) 2762 break; 2763 } 2764 2765 /* Enable external clock source */ 2766 #ifdef CONFIG_PPC_DCR_NATIVE 2767 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2768 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0); 2769 #endif 2770 mutex_unlock(&emac_phy_map_lock); 2771 if (i == 0x20) { 2772 printk(KERN_WARNING "%pOF: can't find PHY!\n", np); 2773 return -ENXIO; 2774 } 2775 2776 init_phy: 2777 /* Init PHY */ 2778 if (dev->phy.def->ops->init) 2779 dev->phy.def->ops->init(&dev->phy); 2780 2781 /* Disable any PHY features not supported by the platform */ 2782 dev->phy.def->features &= ~dev->phy_feat_exc; 2783 dev->phy.features &= ~dev->phy_feat_exc; 2784 2785 /* Setup initial link parameters */ 2786 if (dev->phy.features & SUPPORTED_Autoneg) { 2787 adv = dev->phy.features; 2788 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x)) 2789 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 2790 /* Restart autonegotiation */ 2791 dev->phy.def->ops->setup_aneg(&dev->phy, adv); 2792 } else { 2793 u32 f = dev->phy.def->features; 2794 int speed = SPEED_10, fd = DUPLEX_HALF; 2795 2796 /* Select highest supported speed/duplex */ 2797 if (f & SUPPORTED_1000baseT_Full) { 2798 speed = SPEED_1000; 2799 fd = DUPLEX_FULL; 2800 } else if (f & SUPPORTED_1000baseT_Half) 2801 speed = SPEED_1000; 2802 else if (f & SUPPORTED_100baseT_Full) { 2803 speed = SPEED_100; 2804 fd = DUPLEX_FULL; 2805 } else if (f & SUPPORTED_100baseT_Half) 2806 speed = SPEED_100; 2807 else if (f & SUPPORTED_10baseT_Full) 2808 fd = DUPLEX_FULL; 2809 2810 /* Force link parameters */ 2811 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd); 2812 } 2813 return 0; 2814 } 2815 2816 static int emac_init_config(struct emac_instance *dev) 2817 { 2818 struct device_node *np = dev->ofdev->dev.of_node; 2819 int err; 2820 2821 /* Read config from device-tree */ 2822 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1)) 2823 return -ENXIO; 2824 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1)) 2825 return -ENXIO; 2826 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1)) 2827 return -ENXIO; 2828 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1)) 2829 return -ENXIO; 2830 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0)) 2831 dev->max_mtu = ETH_DATA_LEN; 2832 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0)) 2833 dev->rx_fifo_size = 2048; 2834 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0)) 2835 dev->tx_fifo_size = 2048; 2836 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0)) 2837 dev->rx_fifo_size_gige = dev->rx_fifo_size; 2838 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0)) 2839 dev->tx_fifo_size_gige = dev->tx_fifo_size; 2840 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0)) 2841 dev->phy_address = 0xffffffff; 2842 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0)) 2843 dev->phy_map = 0xffffffff; 2844 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0)) 2845 dev->gpcs_address = 0xffffffff; 2846 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1)) 2847 return -ENXIO; 2848 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0)) 2849 dev->tah_ph = 0; 2850 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0)) 2851 dev->tah_port = 0; 2852 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0)) 2853 dev->mdio_ph = 0; 2854 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0)) 2855 dev->zmii_ph = 0; 2856 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0)) 2857 dev->zmii_port = 0xffffffff; 2858 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0)) 2859 dev->rgmii_ph = 0; 2860 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0)) 2861 dev->rgmii_port = 0xffffffff; 2862 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0)) 2863 dev->fifo_entry_size = 16; 2864 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0)) 2865 dev->mal_burst_size = 256; 2866 2867 /* PHY mode needs some decoding */ 2868 err = of_get_phy_mode(np, &dev->phy_mode); 2869 if (err) 2870 dev->phy_mode = PHY_INTERFACE_MODE_NA; 2871 2872 /* Check EMAC version */ 2873 if (of_device_is_compatible(np, "ibm,emac4sync")) { 2874 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC); 2875 if (of_device_is_compatible(np, "ibm,emac-460ex") || 2876 of_device_is_compatible(np, "ibm,emac-460gt")) 2877 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX; 2878 if (of_device_is_compatible(np, "ibm,emac-405ex") || 2879 of_device_is_compatible(np, "ibm,emac-405exr")) 2880 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; 2881 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) { 2882 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE | 2883 EMAC_FTR_APM821XX_NO_HALF_DUPLEX | 2884 EMAC_FTR_460EX_PHY_CLK_FIX); 2885 } 2886 } else if (of_device_is_compatible(np, "ibm,emac4")) { 2887 dev->features |= EMAC_FTR_EMAC4; 2888 if (of_device_is_compatible(np, "ibm,emac-440gx")) 2889 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX; 2890 } else { 2891 if (of_device_is_compatible(np, "ibm,emac-440ep") || 2892 of_device_is_compatible(np, "ibm,emac-440gr")) 2893 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; 2894 if (of_device_is_compatible(np, "ibm,emac-405ez")) { 2895 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL 2896 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x; 2897 #else 2898 printk(KERN_ERR "%pOF: Flow control not disabled!\n", 2899 np); 2900 return -ENXIO; 2901 #endif 2902 } 2903 2904 } 2905 2906 /* Fixup some feature bits based on the device tree */ 2907 if (of_property_read_bool(np, "has-inverted-stacr-oc")) 2908 dev->features |= EMAC_FTR_STACR_OC_INVERT; 2909 if (of_property_read_bool(np, "has-new-stacr-staopc")) 2910 dev->features |= EMAC_FTR_HAS_NEW_STACR; 2911 2912 /* CAB lacks the appropriate properties */ 2913 if (of_device_is_compatible(np, "ibm,emac-axon")) 2914 dev->features |= EMAC_FTR_HAS_NEW_STACR | 2915 EMAC_FTR_STACR_OC_INVERT; 2916 2917 /* Enable TAH/ZMII/RGMII features as found */ 2918 if (dev->tah_ph != 0) { 2919 #ifdef CONFIG_IBM_EMAC_TAH 2920 dev->features |= EMAC_FTR_HAS_TAH; 2921 #else 2922 printk(KERN_ERR "%pOF: TAH support not enabled !\n", np); 2923 return -ENXIO; 2924 #endif 2925 } 2926 2927 if (dev->zmii_ph != 0) { 2928 #ifdef CONFIG_IBM_EMAC_ZMII 2929 dev->features |= EMAC_FTR_HAS_ZMII; 2930 #else 2931 printk(KERN_ERR "%pOF: ZMII support not enabled !\n", np); 2932 return -ENXIO; 2933 #endif 2934 } 2935 2936 if (dev->rgmii_ph != 0) { 2937 #ifdef CONFIG_IBM_EMAC_RGMII 2938 dev->features |= EMAC_FTR_HAS_RGMII; 2939 #else 2940 printk(KERN_ERR "%pOF: RGMII support not enabled !\n", np); 2941 return -ENXIO; 2942 #endif 2943 } 2944 2945 /* Read MAC-address */ 2946 err = of_get_ethdev_address(np, dev->ndev); 2947 if (err == -EPROBE_DEFER) 2948 return err; 2949 if (err) { 2950 dev_warn(&dev->ofdev->dev, "Can't get valid mac-address. Generating random."); 2951 eth_hw_addr_random(dev->ndev); 2952 } 2953 2954 /* IAHT and GAHT filter parameterization */ 2955 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) { 2956 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT; 2957 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT; 2958 } else { 2959 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT; 2960 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT; 2961 } 2962 2963 /* This should never happen */ 2964 if (WARN_ON(EMAC_XAHT_REGS(dev) > EMAC_XAHT_MAX_REGS)) 2965 return -ENXIO; 2966 2967 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE); 2968 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige); 2969 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige); 2970 DBG(dev, "max_mtu : %d\n", dev->max_mtu); 2971 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq); 2972 2973 return 0; 2974 } 2975 2976 static const struct net_device_ops emac_netdev_ops = { 2977 .ndo_open = emac_open, 2978 .ndo_stop = emac_close, 2979 .ndo_get_stats = emac_stats, 2980 .ndo_set_rx_mode = emac_set_multicast_list, 2981 .ndo_eth_ioctl = emac_ioctl, 2982 .ndo_tx_timeout = emac_tx_timeout, 2983 .ndo_validate_addr = eth_validate_addr, 2984 .ndo_set_mac_address = emac_set_mac_address, 2985 .ndo_start_xmit = emac_start_xmit, 2986 }; 2987 2988 static const struct net_device_ops emac_gige_netdev_ops = { 2989 .ndo_open = emac_open, 2990 .ndo_stop = emac_close, 2991 .ndo_get_stats = emac_stats, 2992 .ndo_set_rx_mode = emac_set_multicast_list, 2993 .ndo_eth_ioctl = emac_ioctl, 2994 .ndo_tx_timeout = emac_tx_timeout, 2995 .ndo_validate_addr = eth_validate_addr, 2996 .ndo_set_mac_address = emac_set_mac_address, 2997 .ndo_start_xmit = emac_start_xmit_sg, 2998 .ndo_change_mtu = emac_change_mtu, 2999 }; 3000 3001 static int emac_probe(struct platform_device *ofdev) 3002 { 3003 struct net_device *ndev; 3004 struct emac_instance *dev; 3005 struct device_node *np = ofdev->dev.of_node; 3006 struct device_node **blist = NULL; 3007 int err, i; 3008 3009 /* Skip unused/unwired EMACS. We leave the check for an unused 3010 * property here for now, but new flat device trees should set a 3011 * status property to "disabled" instead. 3012 */ 3013 if (of_property_read_bool(np, "unused") || !of_device_is_available(np)) 3014 return -ENODEV; 3015 3016 /* Find ourselves in the bootlist if we are there */ 3017 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++) 3018 if (emac_boot_list[i] == np) 3019 blist = &emac_boot_list[i]; 3020 3021 /* Allocate our net_device structure */ 3022 err = -ENOMEM; 3023 ndev = devm_alloc_etherdev(&ofdev->dev, sizeof(struct emac_instance)); 3024 if (!ndev) 3025 goto err_gone; 3026 3027 dev = netdev_priv(ndev); 3028 dev->ndev = ndev; 3029 dev->ofdev = ofdev; 3030 dev->blist = blist; 3031 SET_NETDEV_DEV(ndev, &ofdev->dev); 3032 3033 /* Initialize some embedded data structures */ 3034 err = devm_mutex_init(&ofdev->dev, &dev->mdio_lock); 3035 if (err) 3036 goto err_gone; 3037 3038 err = devm_mutex_init(&ofdev->dev, &dev->link_lock); 3039 if (err) 3040 goto err_gone; 3041 3042 spin_lock_init(&dev->lock); 3043 INIT_WORK(&dev->reset_work, emac_reset_work); 3044 3045 /* Init various config data based on device-tree */ 3046 err = emac_init_config(dev); 3047 if (err) 3048 goto err_gone; 3049 3050 if (emac_phy_supports_gige(dev->phy_mode)) { 3051 ndev->netdev_ops = &emac_gige_netdev_ops; 3052 dev->commac.ops = &emac_commac_sg_ops; 3053 } else { 3054 ndev->netdev_ops = &emac_netdev_ops; 3055 dev->commac.ops = &emac_commac_ops; 3056 } 3057 ndev->ethtool_ops = &emac_ethtool_ops; 3058 3059 dev->emacp = devm_platform_ioremap_resource(ofdev, 0); 3060 if (IS_ERR(dev->emacp)) { 3061 err = PTR_ERR(dev->emacp); 3062 goto err_gone; 3063 } 3064 3065 /* Setup error IRQ handler */ 3066 dev->emac_irq = platform_get_irq(ofdev, 0); 3067 if (dev->emac_irq < 0) { 3068 err = dev->emac_irq; 3069 goto err_gone; 3070 } 3071 3072 err = devm_request_irq(&ofdev->dev, dev->emac_irq, emac_irq, 0, "EMAC", 3073 dev); 3074 if (err) { 3075 dev_err_probe(&ofdev->dev, err, "failed to request IRQ %d", 3076 dev->emac_irq); 3077 goto err_gone; 3078 } 3079 3080 ndev->irq = dev->emac_irq; 3081 3082 /* Wait for dependent devices */ 3083 err = emac_wait_deps(dev); 3084 if (err) 3085 goto err_gone; 3086 dev->mal = platform_get_drvdata(dev->mal_dev); 3087 if (dev->mdio_dev != NULL) 3088 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev); 3089 3090 /* Register with MAL */ 3091 dev->commac.dev = dev; 3092 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan); 3093 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan); 3094 err = mal_register_commac(dev->mal, &dev->commac); 3095 if (err) { 3096 printk(KERN_ERR "%pOF: failed to register with mal %pOF!\n", 3097 np, dev->mal_dev->dev.of_node); 3098 goto err_rel_deps; 3099 } 3100 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu); 3101 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu); 3102 3103 /* Get pointers to BD rings */ 3104 dev->tx_desc = 3105 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan); 3106 dev->rx_desc = 3107 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan); 3108 3109 DBG(dev, "tx_desc %p" NL, dev->tx_desc); 3110 DBG(dev, "rx_desc %p" NL, dev->rx_desc); 3111 3112 /* Clean rings */ 3113 emac_clear_mal_desc(dev->tx_desc, NUM_TX_BUFF); 3114 emac_clear_mal_desc(dev->rx_desc, NUM_RX_BUFF); 3115 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *)); 3116 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *)); 3117 3118 /* Attach to ZMII, if needed */ 3119 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) && 3120 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0) 3121 goto err_unreg_commac; 3122 3123 /* Attach to RGMII, if needed */ 3124 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) && 3125 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0) 3126 goto err_detach_zmii; 3127 3128 /* Attach to TAH, if needed */ 3129 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) && 3130 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0) 3131 goto err_detach_rgmii; 3132 3133 /* Set some link defaults before we can find out real parameters */ 3134 dev->phy.speed = SPEED_100; 3135 dev->phy.duplex = DUPLEX_FULL; 3136 dev->phy.autoneg = AUTONEG_DISABLE; 3137 dev->phy.pause = dev->phy.asym_pause = 0; 3138 dev->stop_timeout = STOP_TIMEOUT_100; 3139 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer); 3140 3141 /* Some SoCs like APM821xx does not support Half Duplex mode. */ 3142 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) { 3143 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half | 3144 SUPPORTED_100baseT_Half | 3145 SUPPORTED_10baseT_Half); 3146 } 3147 3148 /* Find PHY if any */ 3149 err = emac_init_phy(dev); 3150 if (err != 0) 3151 goto err_detach_tah; 3152 3153 if (dev->tah_dev) { 3154 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG; 3155 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM; 3156 } 3157 ndev->watchdog_timeo = 5 * HZ; 3158 3159 /* MTU range: 46 - 1500 or whatever is in OF */ 3160 ndev->min_mtu = EMAC_MIN_MTU; 3161 ndev->max_mtu = dev->max_mtu; 3162 3163 netif_carrier_off(ndev); 3164 3165 err = register_netdev(ndev); 3166 if (err) { 3167 printk(KERN_ERR "%pOF: failed to register net device (%d)!\n", 3168 np, err); 3169 goto err_detach_tah; 3170 } 3171 3172 /* Set our drvdata last as we don't want them visible until we are 3173 * fully initialized 3174 */ 3175 wmb(); 3176 platform_set_drvdata(ofdev, dev); 3177 3178 printk(KERN_INFO "%s: EMAC-%d %pOF, MAC %pM\n", 3179 ndev->name, dev->cell_index, np, ndev->dev_addr); 3180 3181 if (dev->phy_mode == PHY_INTERFACE_MODE_SGMII) 3182 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name); 3183 3184 if (dev->phy.address >= 0) 3185 printk("%s: found %s PHY (0x%02x)\n", ndev->name, 3186 dev->phy.def->name, dev->phy.address); 3187 3188 /* Life is good */ 3189 return 0; 3190 3191 /* I have a bad feeling about this ... */ 3192 3193 err_detach_tah: 3194 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 3195 tah_detach(dev->tah_dev, dev->tah_port); 3196 err_detach_rgmii: 3197 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 3198 rgmii_detach(dev->rgmii_dev, dev->rgmii_port); 3199 err_detach_zmii: 3200 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 3201 zmii_detach(dev->zmii_dev, dev->zmii_port); 3202 err_unreg_commac: 3203 mal_unregister_commac(dev->mal, &dev->commac); 3204 err_rel_deps: 3205 emac_put_deps(dev); 3206 err_gone: 3207 if (blist) 3208 *blist = NULL; 3209 return err; 3210 } 3211 3212 static void emac_remove(struct platform_device *ofdev) 3213 { 3214 struct emac_instance *dev = platform_get_drvdata(ofdev); 3215 3216 DBG(dev, "remove" NL); 3217 3218 /* Unregister network device before tearing down hardware 3219 * to prevent use-after-free during deferred cleanup. This ensures 3220 * the network stack stops all operations before hardware resources 3221 * are released. 3222 */ 3223 unregister_netdev(dev->ndev); 3224 3225 cancel_work_sync(&dev->reset_work); 3226 3227 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 3228 tah_detach(dev->tah_dev, dev->tah_port); 3229 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 3230 rgmii_detach(dev->rgmii_dev, dev->rgmii_port); 3231 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 3232 zmii_detach(dev->zmii_dev, dev->zmii_port); 3233 3234 busy_phy_map &= ~(1 << dev->phy.address); 3235 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map); 3236 3237 mal_unregister_commac(dev->mal, &dev->commac); 3238 emac_put_deps(dev); 3239 } 3240 3241 /* XXX Features in here should be replaced by properties... */ 3242 static const struct of_device_id emac_match[] = 3243 { 3244 { 3245 .type = "network", 3246 .compatible = "ibm,emac", 3247 }, 3248 { 3249 .type = "network", 3250 .compatible = "ibm,emac4", 3251 }, 3252 { 3253 .type = "network", 3254 .compatible = "ibm,emac4sync", 3255 }, 3256 {}, 3257 }; 3258 MODULE_DEVICE_TABLE(of, emac_match); 3259 3260 static struct platform_driver emac_driver = { 3261 .driver = { 3262 .name = "emac", 3263 .of_match_table = emac_match, 3264 }, 3265 .probe = emac_probe, 3266 .remove = emac_remove, 3267 }; 3268 3269 static void __init emac_make_bootlist(void) 3270 { 3271 struct device_node *np = NULL; 3272 int j, max, i = 0; 3273 int cell_indices[EMAC_BOOT_LIST_SIZE]; 3274 3275 /* Collect EMACs */ 3276 while((np = of_find_all_nodes(np)) != NULL) { 3277 u32 idx; 3278 3279 if (of_match_node(emac_match, np) == NULL) 3280 continue; 3281 if (of_property_read_bool(np, "unused")) 3282 continue; 3283 if (of_property_read_u32(np, "cell-index", &idx)) 3284 continue; 3285 cell_indices[i] = idx; 3286 emac_boot_list[i++] = of_node_get(np); 3287 if (i >= EMAC_BOOT_LIST_SIZE) { 3288 of_node_put(np); 3289 break; 3290 } 3291 } 3292 max = i; 3293 3294 /* Bubble sort them (doh, what a creative algorithm :-) */ 3295 for (i = 0; max > 1 && (i < (max - 1)); i++) 3296 for (j = i; j < max; j++) { 3297 if (cell_indices[i] > cell_indices[j]) { 3298 swap(emac_boot_list[i], emac_boot_list[j]); 3299 swap(cell_indices[i], cell_indices[j]); 3300 } 3301 } 3302 } 3303 3304 static int __init emac_init(void) 3305 { 3306 int rc; 3307 3308 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n"); 3309 3310 /* Build EMAC boot list */ 3311 emac_make_bootlist(); 3312 3313 /* Init submodules */ 3314 rc = mal_init(); 3315 if (rc) 3316 goto err; 3317 rc = zmii_init(); 3318 if (rc) 3319 goto err_mal; 3320 rc = rgmii_init(); 3321 if (rc) 3322 goto err_zmii; 3323 rc = tah_init(); 3324 if (rc) 3325 goto err_rgmii; 3326 rc = platform_driver_register(&emac_driver); 3327 if (rc) 3328 goto err_tah; 3329 3330 return 0; 3331 3332 err_tah: 3333 tah_exit(); 3334 err_rgmii: 3335 rgmii_exit(); 3336 err_zmii: 3337 zmii_exit(); 3338 err_mal: 3339 mal_exit(); 3340 err: 3341 return rc; 3342 } 3343 3344 static void __exit emac_exit(void) 3345 { 3346 int i; 3347 3348 platform_driver_unregister(&emac_driver); 3349 3350 tah_exit(); 3351 rgmii_exit(); 3352 zmii_exit(); 3353 mal_exit(); 3354 3355 /* Destroy EMAC boot list */ 3356 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++) 3357 of_node_put(emac_boot_list[i]); 3358 } 3359 3360 module_init(emac_init); 3361 module_exit(emac_exit); 3362