1*17fcb3dcSFan Gong /* SPDX-License-Identifier: GPL-2.0 */ 2*17fcb3dcSFan Gong /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */ 3*17fcb3dcSFan Gong 4*17fcb3dcSFan Gong #ifndef _HINIC3_RX_H_ 5*17fcb3dcSFan Gong #define _HINIC3_RX_H_ 6*17fcb3dcSFan Gong 7*17fcb3dcSFan Gong #include <linux/bitfield.h> 8*17fcb3dcSFan Gong #include <linux/netdevice.h> 9*17fcb3dcSFan Gong 10*17fcb3dcSFan Gong #define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK GENMASK(4, 0) 11*17fcb3dcSFan Gong #define RQ_CQE_OFFOLAD_TYPE_IP_TYPE_MASK GENMASK(6, 5) 12*17fcb3dcSFan Gong #define RQ_CQE_OFFOLAD_TYPE_TUNNEL_PKT_FORMAT_MASK GENMASK(11, 8) 13*17fcb3dcSFan Gong #define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK BIT(21) 14*17fcb3dcSFan Gong #define RQ_CQE_OFFOLAD_TYPE_GET(val, member) \ 15*17fcb3dcSFan Gong FIELD_GET(RQ_CQE_OFFOLAD_TYPE_##member##_MASK, val) 16*17fcb3dcSFan Gong 17*17fcb3dcSFan Gong #define RQ_CQE_SGE_VLAN_MASK GENMASK(15, 0) 18*17fcb3dcSFan Gong #define RQ_CQE_SGE_LEN_MASK GENMASK(31, 16) 19*17fcb3dcSFan Gong #define RQ_CQE_SGE_GET(val, member) \ 20*17fcb3dcSFan Gong FIELD_GET(RQ_CQE_SGE_##member##_MASK, val) 21*17fcb3dcSFan Gong 22*17fcb3dcSFan Gong #define RQ_CQE_STATUS_CSUM_ERR_MASK GENMASK(15, 0) 23*17fcb3dcSFan Gong #define RQ_CQE_STATUS_NUM_LRO_MASK GENMASK(23, 16) 24*17fcb3dcSFan Gong #define RQ_CQE_STATUS_RXDONE_MASK BIT(31) 25*17fcb3dcSFan Gong #define RQ_CQE_STATUS_GET(val, member) \ 26*17fcb3dcSFan Gong FIELD_GET(RQ_CQE_STATUS_##member##_MASK, val) 27*17fcb3dcSFan Gong 28*17fcb3dcSFan Gong /* RX Completion information that is provided by HW for a specific RX WQE */ 29*17fcb3dcSFan Gong struct hinic3_rq_cqe { 30*17fcb3dcSFan Gong u32 status; 31*17fcb3dcSFan Gong u32 vlan_len; 32*17fcb3dcSFan Gong u32 offload_type; 33*17fcb3dcSFan Gong u32 rsvd3; 34*17fcb3dcSFan Gong u32 rsvd4; 35*17fcb3dcSFan Gong u32 rsvd5; 36*17fcb3dcSFan Gong u32 rsvd6; 37*17fcb3dcSFan Gong u32 pkt_info; 38*17fcb3dcSFan Gong }; 39*17fcb3dcSFan Gong 40*17fcb3dcSFan Gong struct hinic3_rq_wqe { 41*17fcb3dcSFan Gong u32 buf_hi_addr; 42*17fcb3dcSFan Gong u32 buf_lo_addr; 43*17fcb3dcSFan Gong u32 cqe_hi_addr; 44*17fcb3dcSFan Gong u32 cqe_lo_addr; 45*17fcb3dcSFan Gong }; 46*17fcb3dcSFan Gong 47*17fcb3dcSFan Gong struct hinic3_rx_info { 48*17fcb3dcSFan Gong struct page *page; 49*17fcb3dcSFan Gong u32 page_offset; 50*17fcb3dcSFan Gong }; 51*17fcb3dcSFan Gong 52*17fcb3dcSFan Gong struct hinic3_rxq { 53*17fcb3dcSFan Gong struct net_device *netdev; 54*17fcb3dcSFan Gong 55*17fcb3dcSFan Gong u16 q_id; 56*17fcb3dcSFan Gong u32 q_depth; 57*17fcb3dcSFan Gong u32 q_mask; 58*17fcb3dcSFan Gong 59*17fcb3dcSFan Gong u16 buf_len; 60*17fcb3dcSFan Gong u32 buf_len_shift; 61*17fcb3dcSFan Gong 62*17fcb3dcSFan Gong u32 cons_idx; 63*17fcb3dcSFan Gong u32 delta; 64*17fcb3dcSFan Gong 65*17fcb3dcSFan Gong u32 irq_id; 66*17fcb3dcSFan Gong u16 msix_entry_idx; 67*17fcb3dcSFan Gong 68*17fcb3dcSFan Gong /* cqe_arr and rx_info are arrays of rq_depth elements. Each element is 69*17fcb3dcSFan Gong * statically associated (by index) to a specific rq_wqe. 70*17fcb3dcSFan Gong */ 71*17fcb3dcSFan Gong struct hinic3_rq_cqe *cqe_arr; 72*17fcb3dcSFan Gong struct hinic3_rx_info *rx_info; 73*17fcb3dcSFan Gong struct page_pool *page_pool; 74*17fcb3dcSFan Gong 75*17fcb3dcSFan Gong struct hinic3_io_queue *rq; 76*17fcb3dcSFan Gong 77*17fcb3dcSFan Gong struct hinic3_irq_cfg *irq_cfg; 78*17fcb3dcSFan Gong u16 next_to_alloc; 79*17fcb3dcSFan Gong u16 next_to_update; 80*17fcb3dcSFan Gong struct device *dev; /* device for DMA mapping */ 81*17fcb3dcSFan Gong 82*17fcb3dcSFan Gong dma_addr_t cqe_start_paddr; 83*17fcb3dcSFan Gong } ____cacheline_aligned; 84*17fcb3dcSFan Gong 85*17fcb3dcSFan Gong int hinic3_alloc_rxqs(struct net_device *netdev); 86*17fcb3dcSFan Gong void hinic3_free_rxqs(struct net_device *netdev); 87*17fcb3dcSFan Gong 88*17fcb3dcSFan Gong int hinic3_rx_poll(struct hinic3_rxq *rxq, int budget); 89*17fcb3dcSFan Gong 90*17fcb3dcSFan Gong #endif 91