xref: /linux/drivers/net/ethernet/huawei/hinic3/hinic3_mgmt_interface.h (revision 8a5f956a9fb7d74fff681145082acfad5afa6bb8)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
3 
4 #ifndef _HINIC3_MGMT_INTERFACE_H_
5 #define _HINIC3_MGMT_INTERFACE_H_
6 
7 #include <linux/bitfield.h>
8 #include <linux/bits.h>
9 #include <linux/if_ether.h>
10 
11 #include "hinic3_hw_intf.h"
12 
13 struct l2nic_cmd_feature_nego {
14 	struct mgmt_msg_head msg_head;
15 	u16                  func_id;
16 	u8                   opcode;
17 	u8                   rsvd;
18 	u64                  s_feature[4];
19 };
20 
21 enum l2nic_func_tbl_cfg_bitmap {
22 	L2NIC_FUNC_TBL_CFG_INIT        = 0,
23 	L2NIC_FUNC_TBL_CFG_RX_BUF_SIZE = 1,
24 	L2NIC_FUNC_TBL_CFG_MTU         = 2,
25 };
26 
27 struct l2nic_func_tbl_cfg {
28 	u16 rx_wqe_buf_size;
29 	u16 mtu;
30 	u32 rsvd[9];
31 };
32 
33 struct l2nic_cmd_set_func_tbl {
34 	struct mgmt_msg_head      msg_head;
35 	u16                       func_id;
36 	u16                       rsvd;
37 	u32                       cfg_bitmap;
38 	struct l2nic_func_tbl_cfg tbl_cfg;
39 };
40 
41 struct l2nic_cmd_set_mac {
42 	struct mgmt_msg_head msg_head;
43 	u16                  func_id;
44 	u16                  vlan_id;
45 	u16                  rsvd1;
46 	u8                   mac[ETH_ALEN];
47 };
48 
49 struct l2nic_cmd_update_mac {
50 	struct mgmt_msg_head msg_head;
51 	u16                  func_id;
52 	u16                  vlan_id;
53 	u16                  rsvd1;
54 	u8                   old_mac[ETH_ALEN];
55 	u16                  rsvd2;
56 	u8                   new_mac[ETH_ALEN];
57 };
58 
59 struct l2nic_cmd_set_ci_attr {
60 	struct mgmt_msg_head msg_head;
61 	u16                  func_idx;
62 	u8                   dma_attr_off;
63 	u8                   pending_limit;
64 	u8                   coalescing_time;
65 	u8                   intr_en;
66 	u16                  intr_idx;
67 	u32                  l2nic_sqn;
68 	u32                  rsvd;
69 	u64                  ci_addr;
70 };
71 
72 struct l2nic_cmd_clear_qp_resource {
73 	struct mgmt_msg_head msg_head;
74 	u16                  func_id;
75 	u16                  rsvd1;
76 };
77 
78 struct l2nic_cmd_force_pkt_drop {
79 	struct mgmt_msg_head msg_head;
80 	u8                   port;
81 	u8                   rsvd1[3];
82 };
83 
84 struct l2nic_cmd_set_vport_state {
85 	struct mgmt_msg_head msg_head;
86 	u16                  func_id;
87 	u16                  rsvd1;
88 	/* 0--disable, 1--enable */
89 	u8                   state;
90 	u8                   rsvd2[3];
91 };
92 
93 struct l2nic_cmd_set_dcb_state {
94 	struct mgmt_msg_head head;
95 	u16                  func_id;
96 	/* 0 - get dcb state, 1 - set dcb state */
97 	u8                   op_code;
98 	/* 0 - disable, 1 - enable dcb */
99 	u8                   state;
100 	/* 0 - disable, 1 - enable dcb */
101 	u8                   port_state;
102 	u8                   rsvd[7];
103 };
104 
105 #define L2NIC_RSS_TYPE_VALID_MASK         BIT(23)
106 #define L2NIC_RSS_TYPE_TCP_IPV6_EXT_MASK  BIT(24)
107 #define L2NIC_RSS_TYPE_IPV6_EXT_MASK      BIT(25)
108 #define L2NIC_RSS_TYPE_TCP_IPV6_MASK      BIT(26)
109 #define L2NIC_RSS_TYPE_IPV6_MASK          BIT(27)
110 #define L2NIC_RSS_TYPE_TCP_IPV4_MASK      BIT(28)
111 #define L2NIC_RSS_TYPE_IPV4_MASK          BIT(29)
112 #define L2NIC_RSS_TYPE_UDP_IPV6_MASK      BIT(30)
113 #define L2NIC_RSS_TYPE_UDP_IPV4_MASK      BIT(31)
114 #define L2NIC_RSS_TYPE_SET(val, member)  \
115 	FIELD_PREP(L2NIC_RSS_TYPE_##member##_MASK, val)
116 #define L2NIC_RSS_TYPE_GET(val, member)  \
117 	FIELD_GET(L2NIC_RSS_TYPE_##member##_MASK, val)
118 
119 #define L2NIC_RSS_INDIR_SIZE  256
120 #define L2NIC_RSS_KEY_SIZE    40
121 
122 /* IEEE 802.1Qaz std */
123 #define L2NIC_DCB_COS_MAX     0x8
124 
125 struct l2nic_cmd_set_rss_ctx_tbl {
126 	struct mgmt_msg_head msg_head;
127 	u16                  func_id;
128 	u16                  rsvd1;
129 	u32                  context;
130 };
131 
132 struct l2nic_cmd_cfg_rss_engine {
133 	struct mgmt_msg_head msg_head;
134 	u16                  func_id;
135 	u8                   opcode;
136 	u8                   hash_engine;
137 	u8                   rsvd1[4];
138 };
139 
140 struct l2nic_cmd_cfg_rss_hash_key {
141 	struct mgmt_msg_head msg_head;
142 	u16                  func_id;
143 	u8                   opcode;
144 	u8                   rsvd1;
145 	u8                   key[L2NIC_RSS_KEY_SIZE];
146 };
147 
148 struct l2nic_cmd_cfg_rss {
149 	struct mgmt_msg_head msg_head;
150 	u16                  func_id;
151 	u8                   rss_en;
152 	u8                   rq_priority_number;
153 	u8                   prio_tc[L2NIC_DCB_COS_MAX];
154 	u16                  num_qps;
155 	u16                  rsvd1;
156 };
157 
158 /* Commands between NIC to fw */
159 enum l2nic_cmd {
160 	/* FUNC CFG */
161 	L2NIC_CMD_SET_FUNC_TBL        = 5,
162 	L2NIC_CMD_SET_VPORT_ENABLE    = 6,
163 	L2NIC_CMD_SET_SQ_CI_ATTR      = 8,
164 	L2NIC_CMD_CLEAR_QP_RESOURCE   = 11,
165 	L2NIC_CMD_FEATURE_NEGO        = 15,
166 	L2NIC_CMD_SET_MAC             = 21,
167 	L2NIC_CMD_DEL_MAC             = 22,
168 	L2NIC_CMD_UPDATE_MAC          = 23,
169 	L2NIC_CMD_CFG_RSS             = 60,
170 	L2NIC_CMD_CFG_RSS_HASH_KEY    = 63,
171 	L2NIC_CMD_CFG_RSS_HASH_ENGINE = 64,
172 	L2NIC_CMD_SET_RSS_CTX_TBL     = 65,
173 	L2NIC_CMD_QOS_DCB_STATE       = 110,
174 	L2NIC_CMD_FORCE_PKT_DROP      = 113,
175 	L2NIC_CMD_MAX                 = 256,
176 };
177 
178 struct l2nic_cmd_rss_set_indir_tbl {
179 	__le32 rsvd[4];
180 	__le16 entry[L2NIC_RSS_INDIR_SIZE];
181 };
182 
183 /* NIC CMDQ MODE */
184 enum l2nic_ucode_cmd {
185 	L2NIC_UCODE_CMD_MODIFY_QUEUE_CTX  = 0,
186 	L2NIC_UCODE_CMD_CLEAN_QUEUE_CTX   = 1,
187 	L2NIC_UCODE_CMD_SET_RSS_INDIR_TBL = 4,
188 };
189 
190 /* hilink mac group command */
191 enum mag_cmd {
192 	MAG_CMD_GET_LINK_STATUS = 7,
193 };
194 
195 /* firmware also use this cmd report link event to driver */
196 struct mag_cmd_get_link_status {
197 	struct mgmt_msg_head head;
198 	u8                   port_id;
199 	/* 0:link down  1:link up */
200 	u8                   status;
201 	u8                   rsvd0[2];
202 };
203 
204 enum hinic3_nic_feature_cap {
205 	HINIC3_NIC_F_CSUM           = BIT(0),
206 	HINIC3_NIC_F_SCTP_CRC       = BIT(1),
207 	HINIC3_NIC_F_TSO            = BIT(2),
208 	HINIC3_NIC_F_LRO            = BIT(3),
209 	HINIC3_NIC_F_UFO            = BIT(4),
210 	HINIC3_NIC_F_RSS            = BIT(5),
211 	HINIC3_NIC_F_RX_VLAN_FILTER = BIT(6),
212 	HINIC3_NIC_F_RX_VLAN_STRIP  = BIT(7),
213 	HINIC3_NIC_F_TX_VLAN_INSERT = BIT(8),
214 	HINIC3_NIC_F_VXLAN_OFFLOAD  = BIT(9),
215 	HINIC3_NIC_F_FDIR           = BIT(11),
216 	HINIC3_NIC_F_PROMISC        = BIT(12),
217 	HINIC3_NIC_F_ALLMULTI       = BIT(13),
218 	HINIC3_NIC_F_RATE_LIMIT     = BIT(16),
219 };
220 
221 #define HINIC3_NIC_F_ALL_MASK           0x33bff
222 #define HINIC3_NIC_DRV_DEFAULT_FEATURE  0x3f03f
223 
224 #endif
225