1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */ 3 4 #ifndef _HINIC3_MBOX_H_ 5 #define _HINIC3_MBOX_H_ 6 7 #include <linux/bitfield.h> 8 #include <linux/mutex.h> 9 10 struct hinic3_hwdev; 11 struct mgmt_msg_params; 12 13 #define MBOX_MSG_HEADER_SRC_GLB_FUNC_IDX_MASK GENMASK_ULL(12, 0) 14 #define MBOX_MSG_HEADER_STATUS_MASK BIT_ULL(13) 15 #define MBOX_MSG_HEADER_SOURCE_MASK BIT_ULL(15) 16 #define MBOX_MSG_HEADER_AEQ_ID_MASK GENMASK_ULL(17, 16) 17 #define MBOX_MSG_HEADER_MSG_ID_MASK GENMASK_ULL(21, 18) 18 #define MBOX_MSG_HEADER_CMD_MASK GENMASK_ULL(31, 22) 19 #define MBOX_MSG_HEADER_MSG_LEN_MASK GENMASK_ULL(42, 32) 20 #define MBOX_MSG_HEADER_MODULE_MASK GENMASK_ULL(47, 43) 21 #define MBOX_MSG_HEADER_SEG_LEN_MASK GENMASK_ULL(53, 48) 22 #define MBOX_MSG_HEADER_NO_ACK_MASK BIT_ULL(54) 23 #define MBOX_MSG_HEADER_DATA_TYPE_MASK BIT_ULL(55) 24 #define MBOX_MSG_HEADER_SEQID_MASK GENMASK_ULL(61, 56) 25 #define MBOX_MSG_HEADER_LAST_MASK BIT_ULL(62) 26 #define MBOX_MSG_HEADER_DIRECTION_MASK BIT_ULL(63) 27 28 #define MBOX_MSG_HEADER_SET(val, member) \ 29 FIELD_PREP(MBOX_MSG_HEADER_##member##_MASK, val) 30 #define MBOX_MSG_HEADER_GET(val, member) \ 31 FIELD_GET(MBOX_MSG_HEADER_##member##_MASK, le64_to_cpu(val)) 32 33 /* identifies if a segment belongs to a message or to a response. A VF is only 34 * expected to send messages and receive responses. PF driver could receive 35 * messages and send responses. 36 */ 37 enum mbox_msg_direction_type { 38 MBOX_MSG_SEND = 0, 39 MBOX_MSG_RESP = 1, 40 }; 41 42 /* Indicates if mbox message expects a response (ack) or not */ 43 enum mbox_msg_ack_type { 44 MBOX_MSG_ACK = 0, 45 MBOX_MSG_NO_ACK = 1, 46 }; 47 48 enum mbox_msg_data_type { 49 MBOX_MSG_DATA_INLINE = 0, 50 MBOX_MSG_DATA_DMA = 1, 51 }; 52 53 enum mbox_msg_src_type { 54 MBOX_MSG_FROM_MBOX = 1, 55 }; 56 57 enum mbox_msg_aeq_type { 58 MBOX_MSG_AEQ_FOR_EVENT = 0, 59 MBOX_MSG_AEQ_FOR_MBOX = 1, 60 }; 61 62 #define HINIC3_MBOX_WQ_NAME "hinic3_mbox" 63 64 struct mbox_msg_info { 65 u8 msg_id; 66 u8 status; 67 }; 68 69 struct hinic3_msg_desc { 70 u8 *msg; 71 __le16 msg_len; 72 u8 seq_id; 73 u8 mod; 74 __le16 cmd; 75 struct mbox_msg_info msg_info; 76 }; 77 78 struct hinic3_msg_channel { 79 struct hinic3_msg_desc resp_msg; 80 struct hinic3_msg_desc recv_msg; 81 }; 82 83 struct hinic3_send_mbox { 84 u8 __iomem *data; 85 void *wb_vaddr; 86 dma_addr_t wb_paddr; 87 }; 88 89 enum mbox_event_state { 90 MBOX_EVENT_START = 0, 91 MBOX_EVENT_FAIL = 1, 92 MBOX_EVENT_SUCCESS = 2, 93 MBOX_EVENT_TIMEOUT = 3, 94 MBOX_EVENT_END = 4, 95 }; 96 97 struct mbox_dma_msg { 98 __le32 xor; 99 __le32 dma_addr_high; 100 __le32 dma_addr_low; 101 __le32 msg_len; 102 __le64 rsvd; 103 }; 104 105 struct mbox_dma_queue { 106 void *dma_buf_vaddr; 107 dma_addr_t dma_buf_paddr; 108 u16 depth; 109 u16 prod_idx; 110 u16 cons_idx; 111 }; 112 113 struct hinic3_mbox { 114 struct hinic3_hwdev *hwdev; 115 /* lock for send mbox message and ack message */ 116 struct mutex mbox_send_lock; 117 struct hinic3_send_mbox send_mbox; 118 struct mbox_dma_queue sync_msg_queue; 119 struct mbox_dma_queue async_msg_queue; 120 struct workqueue_struct *workq; 121 /* driver and MGMT CPU */ 122 struct hinic3_msg_channel mgmt_msg; 123 /* VF to PF */ 124 struct hinic3_msg_channel *func_msg; 125 u8 send_msg_id; 126 enum mbox_event_state event_flag; 127 /* lock for mbox event flag */ 128 spinlock_t mbox_lock; 129 }; 130 131 void hinic3_mbox_func_aeqe_handler(struct hinic3_hwdev *hwdev, u8 *header, 132 u8 size); 133 int hinic3_init_mbox(struct hinic3_hwdev *hwdev); 134 void hinic3_free_mbox(struct hinic3_hwdev *hwdev); 135 136 int hinic3_send_mbox_to_mgmt(struct hinic3_hwdev *hwdev, u8 mod, u16 cmd, 137 const struct mgmt_msg_params *msg_params); 138 int hinic3_send_mbox_to_mgmt_no_ack(struct hinic3_hwdev *hwdev, u8 mod, u16 cmd, 139 const struct mgmt_msg_params *msg_params); 140 141 #endif 142