1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */ 3 4 #ifndef _HINIC3_HW_INTF_H_ 5 #define _HINIC3_HW_INTF_H_ 6 7 #include <linux/bits.h> 8 #include <linux/types.h> 9 10 #define MGMT_MSG_CMD_OP_SET 1 11 #define MGMT_MSG_CMD_OP_GET 0 12 13 #define MGMT_STATUS_PF_SET_VF_ALREADY 0x4 14 #define MGMT_STATUS_EXIST 0x6 15 #define MGMT_STATUS_CMD_UNSUPPORTED 0xFF 16 17 #define MGMT_MSG_POLLING_TIMEOUT 0 18 19 struct mgmt_msg_head { 20 u8 status; 21 u8 version; 22 u8 rsvd0[6]; 23 }; 24 25 struct mgmt_msg_params { 26 const void *buf_in; 27 u32 in_size; 28 void *buf_out; 29 u32 expected_out_size; 30 u32 timeout_ms; 31 }; 32 33 /* CMDQ MODULE_TYPE */ 34 enum mgmt_mod_type { 35 /* HW communication module */ 36 MGMT_MOD_COMM = 0, 37 /* L2NIC module */ 38 MGMT_MOD_L2NIC = 1, 39 /* Configuration module */ 40 MGMT_MOD_CFGM = 7, 41 MGMT_MOD_HILINK = 14, 42 }; 43 44 static inline void mgmt_msg_params_init_default(struct mgmt_msg_params *msg_params, 45 void *inout_buf, u32 buf_size) 46 { 47 msg_params->buf_in = inout_buf; 48 msg_params->buf_out = inout_buf; 49 msg_params->in_size = buf_size; 50 msg_params->expected_out_size = buf_size; 51 msg_params->timeout_ms = 0; 52 } 53 54 /* COMM Commands between Driver to fw */ 55 enum comm_cmd { 56 /* Commands for clearing FLR and resources */ 57 COMM_CMD_FUNC_RESET = 0, 58 COMM_CMD_FEATURE_NEGO = 1, 59 COMM_CMD_FLUSH_DOORBELL = 2, 60 COMM_CMD_START_FLUSH = 3, 61 COMM_CMD_GET_GLOBAL_ATTR = 5, 62 COMM_CMD_SET_FUNC_SVC_USED_STATE = 7, 63 64 /* Driver Configuration Commands */ 65 COMM_CMD_SET_CMDQ_CTXT = 20, 66 COMM_CMD_SET_VAT = 21, 67 COMM_CMD_CFG_PAGESIZE = 22, 68 COMM_CMD_CFG_MSIX_CTRL_REG = 23, 69 COMM_CMD_SET_CEQ_CTRL_REG = 24, 70 COMM_CMD_SET_DMA_ATTR = 25, 71 }; 72 73 struct comm_cmd_cfg_msix_ctrl_reg { 74 struct mgmt_msg_head head; 75 u16 func_id; 76 u8 opcode; 77 u8 rsvd1; 78 u16 msix_index; 79 u8 pending_cnt; 80 u8 coalesce_timer_cnt; 81 u8 resend_timer_cnt; 82 u8 lli_timer_cnt; 83 u8 lli_credit_cnt; 84 u8 rsvd2[5]; 85 }; 86 87 enum comm_func_reset_bits { 88 COMM_FUNC_RESET_BIT_FLUSH = BIT(0), 89 COMM_FUNC_RESET_BIT_MQM = BIT(1), 90 COMM_FUNC_RESET_BIT_SMF = BIT(2), 91 COMM_FUNC_RESET_BIT_PF_BW_CFG = BIT(3), 92 93 COMM_FUNC_RESET_BIT_COMM = BIT(10), 94 /* clear mbox and aeq, The COMM_FUNC_RESET_BIT_COMM bit must be set */ 95 COMM_FUNC_RESET_BIT_COMM_MGMT_CH = BIT(11), 96 /* clear cmdq and ceq, The COMM_FUNC_RESET_BIT_COMM bit must be set */ 97 COMM_FUNC_RESET_BIT_COMM_CMD_CH = BIT(12), 98 COMM_FUNC_RESET_BIT_NIC = BIT(13), 99 }; 100 101 struct comm_cmd_func_reset { 102 struct mgmt_msg_head head; 103 u16 func_id; 104 u16 rsvd1[3]; 105 u64 reset_flag; 106 }; 107 108 #define COMM_MAX_FEATURE_QWORD 4 109 struct comm_cmd_feature_nego { 110 struct mgmt_msg_head head; 111 u16 func_id; 112 u8 opcode; 113 u8 rsvd; 114 u64 s_feature[COMM_MAX_FEATURE_QWORD]; 115 }; 116 117 struct comm_cmd_set_ceq_ctrl_reg { 118 struct mgmt_msg_head head; 119 u16 func_id; 120 u16 q_id; 121 u32 ctrl0; 122 u32 ctrl1; 123 u32 rsvd1; 124 }; 125 126 struct comm_cmdq_ctxt_info { 127 __le64 curr_wqe_page_pfn; 128 __le64 wq_block_pfn; 129 }; 130 131 struct comm_cmd_set_cmdq_ctxt { 132 struct mgmt_msg_head head; 133 u16 func_id; 134 u8 cmdq_id; 135 u8 rsvd1[5]; 136 struct comm_cmdq_ctxt_info ctxt; 137 }; 138 139 /* Services supported by HW. HW uses these values when delivering events. 140 * HW supports multiple services that are not yet supported by driver 141 * (e.g. RoCE). 142 */ 143 enum hinic3_service_type { 144 HINIC3_SERVICE_T_NIC = 0, 145 /* MAX is only used by SW for array sizes. */ 146 HINIC3_SERVICE_T_MAX = 1, 147 }; 148 149 #endif 150