1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */ 3 4 #ifndef _HINIC3_EQS_H_ 5 #define _HINIC3_EQS_H_ 6 7 #include <linux/interrupt.h> 8 9 #include "hinic3_hw_cfg.h" 10 #include "hinic3_queue_common.h" 11 12 #define HINIC3_MAX_AEQS 4 13 #define HINIC3_MAX_CEQS 32 14 15 #define HINIC3_AEQ_MAX_PAGES 4 16 #define HINIC3_CEQ_MAX_PAGES 8 17 18 #define HINIC3_AEQE_SIZE 64 19 #define HINIC3_CEQE_SIZE 4 20 21 #define HINIC3_AEQE_DESC_SIZE 4 22 #define HINIC3_AEQE_DATA_SIZE (HINIC3_AEQE_SIZE - HINIC3_AEQE_DESC_SIZE) 23 24 #define HINIC3_DEFAULT_AEQ_LEN 0x10000 25 #define HINIC3_DEFAULT_CEQ_LEN 0x10000 26 27 #define HINIC3_EQ_IRQ_NAME_LEN 64 28 29 #define HINIC3_EQ_USLEEP_LOW_BOUND 900 30 #define HINIC3_EQ_USLEEP_HIGH_BOUND 1000 31 32 enum hinic3_eq_type { 33 HINIC3_AEQ = 0, 34 HINIC3_CEQ = 1, 35 }; 36 37 enum hinic3_eq_intr_mode { 38 HINIC3_INTR_MODE_ARMED = 0, 39 HINIC3_INTR_MODE_ALWAYS = 1, 40 }; 41 42 enum hinic3_eq_ci_arm_state { 43 HINIC3_EQ_NOT_ARMED = 0, 44 HINIC3_EQ_ARMED = 1, 45 }; 46 47 struct hinic3_eq { 48 struct hinic3_hwdev *hwdev; 49 struct hinic3_queue_pages qpages; 50 u16 q_id; 51 enum hinic3_eq_type type; 52 u32 eq_len; 53 u32 cons_idx; 54 u8 wrapped; 55 u32 irq_id; 56 u16 msix_entry_idx; 57 char irq_name[HINIC3_EQ_IRQ_NAME_LEN]; 58 struct work_struct aeq_work; 59 }; 60 61 struct hinic3_aeq_elem { 62 u8 aeqe_data[HINIC3_AEQE_DATA_SIZE]; 63 __be32 desc; 64 }; 65 66 enum hinic3_aeq_type { 67 HINIC3_HW_INTER_INT = 0, 68 HINIC3_MBX_FROM_FUNC = 1, 69 HINIC3_MSG_FROM_FW = 2, 70 HINIC3_MAX_AEQ_EVENTS = 6, 71 }; 72 73 typedef void (*hinic3_aeq_event_cb)(struct hinic3_hwdev *hwdev, u8 *data, 74 u8 size); 75 76 struct hinic3_aeqs { 77 struct hinic3_hwdev *hwdev; 78 hinic3_aeq_event_cb aeq_cb[HINIC3_MAX_AEQ_EVENTS]; 79 struct hinic3_eq aeq[HINIC3_MAX_AEQS]; 80 u16 num_aeqs; 81 struct workqueue_struct *workq; 82 /* lock for aeq event flag */ 83 spinlock_t aeq_lock; 84 }; 85 86 enum hinic3_ceq_event { 87 HINIC3_CMDQ = 3, 88 HINIC3_MAX_CEQ_EVENTS = 6, 89 }; 90 91 typedef void (*hinic3_ceq_event_cb)(struct hinic3_hwdev *hwdev, 92 __le32 ceqe_data); 93 94 struct hinic3_ceqs { 95 struct hinic3_hwdev *hwdev; 96 97 hinic3_ceq_event_cb ceq_cb[HINIC3_MAX_CEQ_EVENTS]; 98 99 struct hinic3_eq ceq[HINIC3_MAX_CEQS]; 100 u16 num_ceqs; 101 /* lock for ceq event flag */ 102 spinlock_t ceq_lock; 103 }; 104 105 int hinic3_aeqs_init(struct hinic3_hwdev *hwdev, u16 num_aeqs, 106 struct msix_entry *msix_entries); 107 void hinic3_aeqs_free(struct hinic3_hwdev *hwdev); 108 int hinic3_aeq_register_cb(struct hinic3_hwdev *hwdev, 109 enum hinic3_aeq_type event, 110 hinic3_aeq_event_cb hwe_cb); 111 void hinic3_aeq_unregister_cb(struct hinic3_hwdev *hwdev, 112 enum hinic3_aeq_type event); 113 int hinic3_ceqs_init(struct hinic3_hwdev *hwdev, u16 num_ceqs, 114 struct msix_entry *msix_entries); 115 void hinic3_ceqs_free(struct hinic3_hwdev *hwdev); 116 int hinic3_ceq_register_cb(struct hinic3_hwdev *hwdev, 117 enum hinic3_ceq_event event, 118 hinic3_ceq_event_cb callback); 119 void hinic3_ceq_unregister_cb(struct hinic3_hwdev *hwdev, 120 enum hinic3_ceq_event event); 121 122 #endif 123