1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_HW_WQE_H 8 #define HINIC_HW_WQE_H 9 10 #include "hinic_common.h" 11 12 #define HINIC_CMDQ_CTRL_PI_SHIFT 0 13 #define HINIC_CMDQ_CTRL_CMD_SHIFT 16 14 #define HINIC_CMDQ_CTRL_MOD_SHIFT 24 15 #define HINIC_CMDQ_CTRL_ACK_TYPE_SHIFT 29 16 #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_SHIFT 31 17 18 #define HINIC_CMDQ_CTRL_PI_MASK 0xFFFF 19 #define HINIC_CMDQ_CTRL_CMD_MASK 0xFF 20 #define HINIC_CMDQ_CTRL_MOD_MASK 0x1F 21 #define HINIC_CMDQ_CTRL_ACK_TYPE_MASK 0x3 22 #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK 0x1 23 24 #define HINIC_CMDQ_CTRL_SET(val, member) \ 25 (((u32)(val) & HINIC_CMDQ_CTRL_##member##_MASK) \ 26 << HINIC_CMDQ_CTRL_##member##_SHIFT) 27 28 #define HINIC_CMDQ_CTRL_GET(val, member) \ 29 (((val) >> HINIC_CMDQ_CTRL_##member##_SHIFT) \ 30 & HINIC_CMDQ_CTRL_##member##_MASK) 31 32 #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT 0 33 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_SHIFT 15 34 #define HINIC_CMDQ_WQE_HEADER_DATA_FMT_SHIFT 22 35 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_SHIFT 23 36 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_SHIFT 27 37 #define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_SHIFT 29 38 #define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_SHIFT 31 39 40 #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_MASK 0xFF 41 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_MASK 0x1 42 #define HINIC_CMDQ_WQE_HEADER_DATA_FMT_MASK 0x1 43 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_MASK 0x1 44 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_MASK 0x3 45 #define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_MASK 0x3 46 #define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_MASK 0x1 47 48 #define HINIC_CMDQ_WQE_HEADER_SET(val, member) \ 49 (((u32)(val) & HINIC_CMDQ_WQE_HEADER_##member##_MASK) \ 50 << HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) 51 52 #define HINIC_CMDQ_WQE_HEADER_GET(val, member) \ 53 (((val) >> HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) \ 54 & HINIC_CMDQ_WQE_HEADER_##member##_MASK) 55 56 #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0 57 #define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT 16 58 #define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT 22 59 #define HINIC_SQ_CTRL_LEN_SHIFT 29 60 61 #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF 62 #define HINIC_SQ_CTRL_TASKSECT_LEN_MASK 0x1F 63 #define HINIC_SQ_CTRL_DATA_FORMAT_MASK 0x1 64 #define HINIC_SQ_CTRL_LEN_MASK 0x3 65 66 #define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT 2 67 #define HINIC_SQ_CTRL_QUEUE_INFO_UFO_SHIFT 10 68 #define HINIC_SQ_CTRL_QUEUE_INFO_TSO_SHIFT 11 69 #define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT 12 70 #define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT 13 71 #define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_SHIFT 27 72 #define HINIC_SQ_CTRL_QUEUE_INFO_UC_SHIFT 28 73 #define HINIC_SQ_CTRL_QUEUE_INFO_PRI_SHIFT 29 74 75 #define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_MASK 0xFF 76 #define HINIC_SQ_CTRL_QUEUE_INFO_UFO_MASK 0x1 77 #define HINIC_SQ_CTRL_QUEUE_INFO_TSO_MASK 0x1 78 #define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK 0x1 79 #define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFF 80 #define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_MASK 0x1 81 #define HINIC_SQ_CTRL_QUEUE_INFO_UC_MASK 0x1 82 #define HINIC_SQ_CTRL_QUEUE_INFO_PRI_MASK 0x7 83 84 #define HINIC_SQ_CTRL_SET(val, member) \ 85 (((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \ 86 << HINIC_SQ_CTRL_##member##_SHIFT) 87 88 #define HINIC_SQ_CTRL_GET(val, member) \ 89 (((val) >> HINIC_SQ_CTRL_##member##_SHIFT) \ 90 & HINIC_SQ_CTRL_##member##_MASK) 91 92 #define HINIC_SQ_CTRL_CLEAR(val, member) \ 93 ((u32)(val) & (~(HINIC_SQ_CTRL_##member##_MASK \ 94 << HINIC_SQ_CTRL_##member##_SHIFT))) 95 96 #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0 97 #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT 8 98 #define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_SHIFT 10 99 #define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT 12 100 #define HINIC_SQ_TASK_INFO0_PARSE_FLAG_SHIFT 13 101 /* 1 bit reserved */ 102 #define HINIC_SQ_TASK_INFO0_TSO_FLAG_SHIFT 15 103 #define HINIC_SQ_TASK_INFO0_VLAN_TAG_SHIFT 16 104 105 #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK 0xFF 106 #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK 0x3 107 #define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK 0x3 108 #define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK 0x1 109 #define HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK 0x1 110 /* 1 bit reserved */ 111 #define HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK 0x1 112 #define HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK 0xFFFF 113 114 #define HINIC_SQ_TASK_INFO0_SET(val, member) \ 115 (((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \ 116 HINIC_SQ_TASK_INFO0_##member##_SHIFT) 117 118 /* 8 bits reserved */ 119 #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT 8 120 #define HINIC_SQ_TASK_INFO1_INNER_L4LEN_SHIFT 16 121 #define HINIC_SQ_TASK_INFO1_INNER_L3LEN_SHIFT 24 122 123 /* 8 bits reserved */ 124 #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK 0xFF 125 #define HINIC_SQ_TASK_INFO1_INNER_L4LEN_MASK 0xFF 126 #define HINIC_SQ_TASK_INFO1_INNER_L3LEN_MASK 0xFF 127 128 #define HINIC_SQ_TASK_INFO1_SET(val, member) \ 129 (((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \ 130 HINIC_SQ_TASK_INFO1_##member##_SHIFT) 131 132 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT 0 133 #define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_SHIFT 8 134 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 16 135 /* 1 bit reserved */ 136 #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT 24 137 /* 8 bits reserved */ 138 139 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_MASK 0xFF 140 #define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_MASK 0xFF 141 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK 0x7 142 /* 1 bit reserved */ 143 #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK 0x3 144 /* 8 bits reserved */ 145 146 #define HINIC_SQ_TASK_INFO2_SET(val, member) \ 147 (((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \ 148 HINIC_SQ_TASK_INFO2_##member##_SHIFT) 149 150 /* 31 bits reserved */ 151 #define HINIC_SQ_TASK_INFO4_L2TYPE_SHIFT 31 152 153 /* 31 bits reserved */ 154 #define HINIC_SQ_TASK_INFO4_L2TYPE_MASK 0x1 155 156 #define HINIC_SQ_TASK_INFO4_SET(val, member) \ 157 (((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \ 158 HINIC_SQ_TASK_INFO4_##member##_SHIFT) 159 160 #define HINIC_RQ_CQE_STATUS_RXDONE_SHIFT 31 161 162 #define HINIC_RQ_CQE_STATUS_RXDONE_MASK 0x1 163 164 #define HINIC_RQ_CQE_STATUS_CSUM_ERR_SHIFT 0 165 166 #define HINIC_RQ_CQE_STATUS_CSUM_ERR_MASK 0xFFFFU 167 168 #define HINIC_RQ_CQE_STATUS_GET(val, member) \ 169 (((val) >> HINIC_RQ_CQE_STATUS_##member##_SHIFT) & \ 170 HINIC_RQ_CQE_STATUS_##member##_MASK) 171 172 #define HINIC_RQ_CQE_STATUS_CLEAR(val, member) \ 173 ((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \ 174 HINIC_RQ_CQE_STATUS_##member##_SHIFT))) 175 176 #define HINIC_RQ_CQE_SGE_LEN_SHIFT 16 177 178 #define HINIC_RQ_CQE_SGE_LEN_MASK 0xFFFF 179 180 #define HINIC_RQ_CQE_SGE_GET(val, member) \ 181 (((val) >> HINIC_RQ_CQE_SGE_##member##_SHIFT) & \ 182 HINIC_RQ_CQE_SGE_##member##_MASK) 183 184 #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0 185 #define HINIC_RQ_CTRL_COMPLETE_FORMAT_SHIFT 15 186 #define HINIC_RQ_CTRL_COMPLETE_LEN_SHIFT 27 187 #define HINIC_RQ_CTRL_LEN_SHIFT 29 188 189 #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF 190 #define HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK 0x1 191 #define HINIC_RQ_CTRL_COMPLETE_LEN_MASK 0x3 192 #define HINIC_RQ_CTRL_LEN_MASK 0x3 193 194 #define HINIC_RQ_CTRL_SET(val, member) \ 195 (((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \ 196 HINIC_RQ_CTRL_##member##_SHIFT) 197 198 #define HINIC_SQ_WQE_SIZE(nr_sges) \ 199 (sizeof(struct hinic_sq_ctrl) + \ 200 sizeof(struct hinic_sq_task) + \ 201 (nr_sges) * sizeof(struct hinic_sq_bufdesc)) 202 203 #define HINIC_SCMD_DATA_LEN 16 204 205 #define HINIC_MAX_SQ_BUFDESCS 17 206 207 #define HINIC_SQ_WQE_MAX_SIZE 320 208 #define HINIC_RQ_WQE_SIZE 32 209 210 #define HINIC_MSS_DEFAULT 0x3E00 211 #define HINIC_MSS_MIN 0x50 212 213 enum hinic_l4offload_type { 214 HINIC_L4_OFF_DISABLE = 0, 215 HINIC_TCP_OFFLOAD_ENABLE = 1, 216 HINIC_SCTP_OFFLOAD_ENABLE = 2, 217 HINIC_UDP_OFFLOAD_ENABLE = 3, 218 }; 219 220 enum hinic_vlan_offload { 221 HINIC_VLAN_OFF_DISABLE = 0, 222 HINIC_VLAN_OFF_ENABLE = 1, 223 }; 224 225 enum hinic_pkt_parsed { 226 HINIC_PKT_NOT_PARSED = 0, 227 HINIC_PKT_PARSED = 1, 228 }; 229 230 enum hinic_l3_offload_type { 231 L3TYPE_UNKNOWN = 0, 232 IPV6_PKT = 1, 233 IPV4_PKT_NO_CHKSUM_OFFLOAD = 2, 234 IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3, 235 }; 236 237 enum hinic_l4_offload_type { 238 OFFLOAD_DISABLE = 0, 239 TCP_OFFLOAD_ENABLE = 1, 240 SCTP_OFFLOAD_ENABLE = 2, 241 UDP_OFFLOAD_ENABLE = 3, 242 }; 243 244 enum hinic_l4_tunnel_type { 245 NOT_TUNNEL, 246 TUNNEL_UDP_NO_CSUM, 247 TUNNEL_UDP_CSUM, 248 }; 249 250 enum hinic_outer_l3type { 251 HINIC_OUTER_L3TYPE_UNKNOWN = 0, 252 HINIC_OUTER_L3TYPE_IPV6 = 1, 253 HINIC_OUTER_L3TYPE_IPV4_NO_CHKSUM = 2, 254 HINIC_OUTER_L3TYPE_IPV4_CHKSUM = 3, 255 }; 256 257 enum hinic_media_type { 258 HINIC_MEDIA_UNKNOWN = 0, 259 }; 260 261 enum hinic_l2type { 262 HINIC_L2TYPE_ETH = 0, 263 }; 264 265 enum hinc_tunnel_l4type { 266 HINIC_TUNNEL_L4TYPE_UNKNOWN = 0, 267 }; 268 269 struct hinic_cmdq_header { 270 u32 header_info; 271 u32 saved_data; 272 }; 273 274 struct hinic_status { 275 u32 status_info; 276 }; 277 278 struct hinic_ctrl { 279 u32 ctrl_info; 280 }; 281 282 struct hinic_sge_resp { 283 struct hinic_sge sge; 284 u32 rsvd; 285 }; 286 287 struct hinic_cmdq_completion { 288 /* HW Format */ 289 union { 290 struct hinic_sge_resp sge_resp; 291 u64 direct_resp; 292 }; 293 }; 294 295 struct hinic_scmd_bufdesc { 296 u32 buf_len; 297 u32 rsvd; 298 u8 data[HINIC_SCMD_DATA_LEN]; 299 }; 300 301 struct hinic_lcmd_bufdesc { 302 struct hinic_sge sge; 303 u32 rsvd1; 304 u64 rsvd2; 305 u64 rsvd3; 306 }; 307 308 struct hinic_cmdq_wqe_scmd { 309 struct hinic_cmdq_header header; 310 u64 rsvd; 311 struct hinic_status status; 312 struct hinic_ctrl ctrl; 313 struct hinic_cmdq_completion completion; 314 struct hinic_scmd_bufdesc buf_desc; 315 }; 316 317 struct hinic_cmdq_wqe_lcmd { 318 struct hinic_cmdq_header header; 319 struct hinic_status status; 320 struct hinic_ctrl ctrl; 321 struct hinic_cmdq_completion completion; 322 struct hinic_lcmd_bufdesc buf_desc; 323 }; 324 325 struct hinic_cmdq_direct_wqe { 326 struct hinic_cmdq_wqe_scmd wqe_scmd; 327 }; 328 329 struct hinic_cmdq_wqe { 330 /* HW Format */ 331 union { 332 struct hinic_cmdq_direct_wqe direct_wqe; 333 struct hinic_cmdq_wqe_lcmd wqe_lcmd; 334 }; 335 }; 336 337 struct hinic_sq_ctrl { 338 u32 ctrl_info; 339 u32 queue_info; 340 }; 341 342 struct hinic_sq_task { 343 u32 pkt_info0; 344 u32 pkt_info1; 345 u32 pkt_info2; 346 u32 ufo_v6_identify; 347 u32 pkt_info4; 348 u32 zero_pad; 349 }; 350 351 struct hinic_sq_bufdesc { 352 struct hinic_sge sge; 353 u32 rsvd; 354 }; 355 356 struct hinic_sq_wqe { 357 struct hinic_sq_ctrl ctrl; 358 struct hinic_sq_task task; 359 struct hinic_sq_bufdesc buf_descs[HINIC_MAX_SQ_BUFDESCS]; 360 }; 361 362 struct hinic_rq_cqe { 363 u32 status; 364 u32 len; 365 366 u32 rsvd2; 367 u32 rsvd3; 368 u32 rsvd4; 369 u32 rsvd5; 370 u32 rsvd6; 371 u32 rsvd7; 372 }; 373 374 struct hinic_rq_ctrl { 375 u32 ctrl_info; 376 }; 377 378 struct hinic_rq_cqe_sect { 379 struct hinic_sge sge; 380 u32 rsvd; 381 }; 382 383 struct hinic_rq_bufdesc { 384 u32 hi_addr; 385 u32 lo_addr; 386 }; 387 388 struct hinic_rq_wqe { 389 struct hinic_rq_ctrl ctrl; 390 u32 rsvd; 391 struct hinic_rq_cqe_sect cqe_sect; 392 struct hinic_rq_bufdesc buf_desc; 393 }; 394 395 struct hinic_hw_wqe { 396 /* HW Format */ 397 union { 398 struct hinic_cmdq_wqe cmdq_wqe; 399 struct hinic_sq_wqe sq_wqe; 400 struct hinic_rq_wqe rq_wqe; 401 }; 402 }; 403 404 #endif 405