1a425b6e1SLuo bin /* SPDX-License-Identifier: GPL-2.0-only */ 2a425b6e1SLuo bin /* Huawei HiNIC PCI Express Linux driver 3a425b6e1SLuo bin * Copyright(c) 2017 Huawei Technologies Co., Ltd 4a425b6e1SLuo bin */ 5a425b6e1SLuo bin 6a425b6e1SLuo bin #ifndef HINIC_MBOX_H_ 7a425b6e1SLuo bin #define HINIC_MBOX_H_ 8a425b6e1SLuo bin 9a425b6e1SLuo bin #define HINIC_MBOX_PF_SEND_ERR 0x1 10a425b6e1SLuo bin #define HINIC_MBOX_PF_BUSY_ACTIVE_FW 0x2 11a425b6e1SLuo bin #define HINIC_MBOX_VF_CMD_ERROR 0x3 12a425b6e1SLuo bin 13a425b6e1SLuo bin #define HINIC_MAX_FUNCTIONS 512 14a425b6e1SLuo bin 15a425b6e1SLuo bin #define HINIC_MAX_PF_FUNCS 16 16a425b6e1SLuo bin 17a425b6e1SLuo bin #define HINIC_MBOX_WQ_NAME "hinic_mbox" 18a425b6e1SLuo bin 19a425b6e1SLuo bin #define HINIC_FUNC_CSR_MAILBOX_DATA_OFF 0x80 20a425b6e1SLuo bin #define HINIC_FUNC_CSR_MAILBOX_CONTROL_OFF 0x0100 21a425b6e1SLuo bin #define HINIC_FUNC_CSR_MAILBOX_INT_OFFSET_OFF 0x0104 22a425b6e1SLuo bin #define HINIC_FUNC_CSR_MAILBOX_RESULT_H_OFF 0x0108 23a425b6e1SLuo bin #define HINIC_FUNC_CSR_MAILBOX_RESULT_L_OFF 0x010C 24a425b6e1SLuo bin 25088c5f0dSLuo bin #define MAX_FUNCTION_NUM 512 26088c5f0dSLuo bin 27*c8c29ec3SLuo bin struct vf_cmd_check_handle { 28*c8c29ec3SLuo bin u8 cmd; 29*c8c29ec3SLuo bin bool (*check_cmd)(struct hinic_hwdev *hwdev, u16 src_func_idx, 30*c8c29ec3SLuo bin void *buf_in, u16 in_size); 31*c8c29ec3SLuo bin }; 32*c8c29ec3SLuo bin 33a425b6e1SLuo bin enum hinic_mbox_ack_type { 34a425b6e1SLuo bin MBOX_ACK, 35a425b6e1SLuo bin MBOX_NO_ACK, 36a425b6e1SLuo bin }; 37a425b6e1SLuo bin 38a425b6e1SLuo bin struct mbox_msg_info { 39a425b6e1SLuo bin u8 msg_id; 40a425b6e1SLuo bin u8 status; 41a425b6e1SLuo bin }; 42a425b6e1SLuo bin 43a425b6e1SLuo bin struct hinic_recv_mbox { 44a425b6e1SLuo bin struct completion recv_done; 45a425b6e1SLuo bin void *mbox; 46a425b6e1SLuo bin u8 cmd; 47a425b6e1SLuo bin enum hinic_mod_type mod; 48a425b6e1SLuo bin u16 mbox_len; 49a425b6e1SLuo bin void *buf_out; 50a425b6e1SLuo bin enum hinic_mbox_ack_type ack_type; 51a425b6e1SLuo bin struct mbox_msg_info msg_info; 52a425b6e1SLuo bin u8 seq_id; 53a425b6e1SLuo bin atomic_t msg_cnt; 54a425b6e1SLuo bin }; 55a425b6e1SLuo bin 56a425b6e1SLuo bin struct hinic_send_mbox { 57a425b6e1SLuo bin struct completion send_done; 58a425b6e1SLuo bin u8 *data; 59a425b6e1SLuo bin 60a425b6e1SLuo bin u64 *wb_status; 61a425b6e1SLuo bin void *wb_vaddr; 62a425b6e1SLuo bin dma_addr_t wb_paddr; 63a425b6e1SLuo bin }; 64a425b6e1SLuo bin 65a425b6e1SLuo bin typedef void (*hinic_vf_mbox_cb)(void *handle, u8 cmd, void *buf_in, 66a425b6e1SLuo bin u16 in_size, void *buf_out, u16 *out_size); 67a425b6e1SLuo bin typedef int (*hinic_pf_mbox_cb)(void *handle, u16 vf_id, u8 cmd, void *buf_in, 68a425b6e1SLuo bin u16 in_size, void *buf_out, u16 *out_size); 69a425b6e1SLuo bin 70a425b6e1SLuo bin enum mbox_event_state { 71a425b6e1SLuo bin EVENT_START = 0, 72a425b6e1SLuo bin EVENT_FAIL, 73a425b6e1SLuo bin EVENT_TIMEOUT, 74a425b6e1SLuo bin EVENT_END, 75a425b6e1SLuo bin }; 76a425b6e1SLuo bin 77a425b6e1SLuo bin enum hinic_mbox_cb_state { 78a425b6e1SLuo bin HINIC_VF_MBOX_CB_REG = 0, 79a425b6e1SLuo bin HINIC_VF_MBOX_CB_RUNNING, 80a425b6e1SLuo bin HINIC_PF_MBOX_CB_REG, 81a425b6e1SLuo bin HINIC_PF_MBOX_CB_RUNNING, 82a425b6e1SLuo bin HINIC_PPF_MBOX_CB_REG, 83a425b6e1SLuo bin HINIC_PPF_MBOX_CB_RUNNING, 84a425b6e1SLuo bin HINIC_PPF_TO_PF_MBOX_CB_REG, 85a425b6e1SLuo bin HINIC_PPF_TO_PF_MBOX_CB_RUNNIG, 86a425b6e1SLuo bin }; 87a425b6e1SLuo bin 88a425b6e1SLuo bin struct hinic_mbox_func_to_func { 89a425b6e1SLuo bin struct hinic_hwdev *hwdev; 90a425b6e1SLuo bin struct hinic_hwif *hwif; 91a425b6e1SLuo bin 92a425b6e1SLuo bin struct semaphore mbox_send_sem; 93a425b6e1SLuo bin struct semaphore msg_send_sem; 94a425b6e1SLuo bin struct hinic_send_mbox send_mbox; 95a425b6e1SLuo bin 96a425b6e1SLuo bin struct workqueue_struct *workq; 97a425b6e1SLuo bin 98a425b6e1SLuo bin struct hinic_recv_mbox mbox_resp[HINIC_MAX_FUNCTIONS]; 99a425b6e1SLuo bin struct hinic_recv_mbox mbox_send[HINIC_MAX_FUNCTIONS]; 100a425b6e1SLuo bin 101a425b6e1SLuo bin hinic_vf_mbox_cb vf_mbox_cb[HINIC_MOD_MAX]; 102a425b6e1SLuo bin hinic_pf_mbox_cb pf_mbox_cb[HINIC_MOD_MAX]; 103a425b6e1SLuo bin unsigned long pf_mbox_cb_state[HINIC_MOD_MAX]; 104a425b6e1SLuo bin unsigned long vf_mbox_cb_state[HINIC_MOD_MAX]; 105a425b6e1SLuo bin 106a425b6e1SLuo bin u8 send_msg_id; 107a425b6e1SLuo bin enum mbox_event_state event_flag; 108a425b6e1SLuo bin 109a425b6e1SLuo bin /* lock for mbox event flag */ 110a425b6e1SLuo bin spinlock_t mbox_lock; 111088c5f0dSLuo bin 112088c5f0dSLuo bin u32 vf_mbx_old_rand_id[MAX_FUNCTION_NUM]; 113088c5f0dSLuo bin u32 vf_mbx_rand_id[MAX_FUNCTION_NUM]; 114088c5f0dSLuo bin bool support_vf_random; 115a425b6e1SLuo bin }; 116a425b6e1SLuo bin 117a425b6e1SLuo bin struct hinic_mbox_work { 118a425b6e1SLuo bin struct work_struct work; 119a425b6e1SLuo bin u16 src_func_idx; 120a425b6e1SLuo bin struct hinic_mbox_func_to_func *func_to_func; 121a425b6e1SLuo bin struct hinic_recv_mbox *recv_mbox; 122a425b6e1SLuo bin }; 123a425b6e1SLuo bin 124a425b6e1SLuo bin struct vf_cmd_msg_handle { 125a425b6e1SLuo bin u8 cmd; 126a425b6e1SLuo bin int (*cmd_msg_handler)(void *hwdev, u16 vf_id, 127a425b6e1SLuo bin void *buf_in, u16 in_size, 128a425b6e1SLuo bin void *buf_out, u16 *out_size); 129a425b6e1SLuo bin }; 130a425b6e1SLuo bin 131*c8c29ec3SLuo bin bool hinic_mbox_check_func_id_8B(struct hinic_hwdev *hwdev, u16 func_idx, 132*c8c29ec3SLuo bin void *buf_in, u16 in_size); 133*c8c29ec3SLuo bin 134*c8c29ec3SLuo bin bool hinic_mbox_check_cmd_valid(struct hinic_hwdev *hwdev, 135*c8c29ec3SLuo bin struct vf_cmd_check_handle *cmd_handle, 136*c8c29ec3SLuo bin u16 vf_id, u8 cmd, void *buf_in, 137*c8c29ec3SLuo bin u16 in_size, u8 size); 138*c8c29ec3SLuo bin 139a425b6e1SLuo bin int hinic_register_pf_mbox_cb(struct hinic_hwdev *hwdev, 140a425b6e1SLuo bin enum hinic_mod_type mod, 141a425b6e1SLuo bin hinic_pf_mbox_cb callback); 142a425b6e1SLuo bin 143a425b6e1SLuo bin int hinic_register_vf_mbox_cb(struct hinic_hwdev *hwdev, 144a425b6e1SLuo bin enum hinic_mod_type mod, 145a425b6e1SLuo bin hinic_vf_mbox_cb callback); 146a425b6e1SLuo bin 147a425b6e1SLuo bin void hinic_unregister_pf_mbox_cb(struct hinic_hwdev *hwdev, 148a425b6e1SLuo bin enum hinic_mod_type mod); 149a425b6e1SLuo bin 150a425b6e1SLuo bin void hinic_unregister_vf_mbox_cb(struct hinic_hwdev *hwdev, 151a425b6e1SLuo bin enum hinic_mod_type mod); 152a425b6e1SLuo bin 153a425b6e1SLuo bin int hinic_func_to_func_init(struct hinic_hwdev *hwdev); 154a425b6e1SLuo bin 155a425b6e1SLuo bin void hinic_func_to_func_free(struct hinic_hwdev *hwdev); 156a425b6e1SLuo bin 157a425b6e1SLuo bin int hinic_mbox_to_pf(struct hinic_hwdev *hwdev, enum hinic_mod_type mod, 158a425b6e1SLuo bin u8 cmd, void *buf_in, u16 in_size, void *buf_out, 159a425b6e1SLuo bin u16 *out_size, u32 timeout); 160a425b6e1SLuo bin 161a425b6e1SLuo bin int hinic_mbox_to_func(struct hinic_mbox_func_to_func *func_to_func, 162a425b6e1SLuo bin enum hinic_mod_type mod, u16 cmd, u16 dst_func, 163a425b6e1SLuo bin void *buf_in, u16 in_size, void *buf_out, 164a425b6e1SLuo bin u16 *out_size, u32 timeout); 165a425b6e1SLuo bin 166a425b6e1SLuo bin int hinic_mbox_to_vf(struct hinic_hwdev *hwdev, 167a425b6e1SLuo bin enum hinic_mod_type mod, u16 vf_id, u8 cmd, void *buf_in, 168a425b6e1SLuo bin u16 in_size, void *buf_out, u16 *out_size, u32 timeout); 169a425b6e1SLuo bin 170088c5f0dSLuo bin int hinic_vf_mbox_random_id_init(struct hinic_hwdev *hwdev); 171088c5f0dSLuo bin 172a425b6e1SLuo bin #endif 173