1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #include <linux/pci.h> 8 #include <linux/device.h> 9 #include <linux/errno.h> 10 #include <linux/io.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 14 #include "hinic_hw_csr.h" 15 #include "hinic_hw_if.h" 16 17 #define PCIE_ATTR_ENTRY 0 18 19 #define VALID_MSIX_IDX(attr, msix_index) ((msix_index) < (attr)->num_irqs) 20 21 /** 22 * hinic_msix_attr_set - set message attribute for msix entry 23 * @hwif: the HW interface of a pci function device 24 * @msix_index: msix_index 25 * @pending_limit: the maximum pending interrupt events (unit 8) 26 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 27 * @lli_timer: replenishing period for low latency credit (unit 8 us) 28 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 29 * @resend_timer: maximum wait for resending msix (unit coalesc period) 30 * 31 * Return 0 - Success, negative - Failure 32 **/ 33 int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, 34 u8 pending_limit, u8 coalesc_timer, 35 u8 lli_timer, u8 lli_credit_limit, 36 u8 resend_timer) 37 { 38 u32 msix_ctrl, addr; 39 40 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 41 return -EINVAL; 42 43 msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | 44 HINIC_MSIX_ATTR_SET(coalesc_timer, COALESC_TIMER) | 45 HINIC_MSIX_ATTR_SET(lli_timer, LLI_TIMER) | 46 HINIC_MSIX_ATTR_SET(lli_credit_limit, LLI_CREDIT) | 47 HINIC_MSIX_ATTR_SET(resend_timer, RESEND_TIMER); 48 49 addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); 50 51 hinic_hwif_write_reg(hwif, addr, msix_ctrl); 52 return 0; 53 } 54 55 /** 56 * hinic_msix_attr_get - get message attribute of msix entry 57 * @hwif: the HW interface of a pci function device 58 * @msix_index: msix_index 59 * @pending_limit: the maximum pending interrupt events (unit 8) 60 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 61 * @lli_timer: replenishing period for low latency credit (unit 8 us) 62 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 63 * @resend_timer: maximum wait for resending msix (unit coalesc period) 64 * 65 * Return 0 - Success, negative - Failure 66 **/ 67 int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index, 68 u8 *pending_limit, u8 *coalesc_timer, 69 u8 *lli_timer, u8 *lli_credit_limit, 70 u8 *resend_timer) 71 { 72 u32 addr, val; 73 74 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 75 return -EINVAL; 76 77 addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); 78 val = hinic_hwif_read_reg(hwif, addr); 79 80 *pending_limit = HINIC_MSIX_ATTR_GET(val, PENDING_LIMIT); 81 *coalesc_timer = HINIC_MSIX_ATTR_GET(val, COALESC_TIMER); 82 *lli_timer = HINIC_MSIX_ATTR_GET(val, LLI_TIMER); 83 *lli_credit_limit = HINIC_MSIX_ATTR_GET(val, LLI_CREDIT); 84 *resend_timer = HINIC_MSIX_ATTR_GET(val, RESEND_TIMER); 85 return 0; 86 } 87 88 /** 89 * hinic_msix_attr_cnt_clear - clear message attribute counters for msix entry 90 * @hwif: the HW interface of a pci function device 91 * @msix_index: msix_index 92 * 93 * Return 0 - Success, negative - Failure 94 **/ 95 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index) 96 { 97 u32 msix_ctrl, addr; 98 99 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 100 return -EINVAL; 101 102 msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER); 103 addr = HINIC_CSR_MSIX_CNT_ADDR(msix_index); 104 105 hinic_hwif_write_reg(hwif, addr, msix_ctrl); 106 return 0; 107 } 108 109 /** 110 * hinic_set_pf_action - set action on pf channel 111 * @hwif: the HW interface of a pci function device 112 * @action: action on pf channel 113 * 114 * Return 0 - Success, negative - Failure 115 **/ 116 void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action) 117 { 118 u32 attr5; 119 120 if (HINIC_IS_VF(hwif)) 121 return; 122 123 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR); 124 attr5 = HINIC_FA5_CLEAR(attr5, PF_ACTION); 125 attr5 |= HINIC_FA5_SET(action, PF_ACTION); 126 127 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR, attr5); 128 } 129 130 enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif) 131 { 132 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 133 134 return HINIC_FA4_GET(attr4, OUTBOUND_STATE); 135 } 136 137 void hinic_outbound_state_set(struct hinic_hwif *hwif, 138 enum hinic_outbound_state outbound_state) 139 { 140 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 141 142 attr4 = HINIC_FA4_CLEAR(attr4, OUTBOUND_STATE); 143 attr4 |= HINIC_FA4_SET(outbound_state, OUTBOUND_STATE); 144 145 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); 146 } 147 148 enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif) 149 { 150 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 151 152 return HINIC_FA4_GET(attr4, DB_STATE); 153 } 154 155 void hinic_db_state_set(struct hinic_hwif *hwif, 156 enum hinic_db_state db_state) 157 { 158 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 159 160 attr4 = HINIC_FA4_CLEAR(attr4, DB_STATE); 161 attr4 |= HINIC_FA4_SET(db_state, DB_STATE); 162 163 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); 164 } 165 166 void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx, 167 enum hinic_msix_state flag) 168 { 169 u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE + 170 HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL; 171 u32 mask_bits; 172 173 mask_bits = readl(hwif->intr_regs_base + offset); 174 mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; 175 176 if (flag) 177 mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; 178 179 writel(mask_bits, hwif->intr_regs_base + offset); 180 } 181 182 /** 183 * hwif_ready - test if the HW is ready for use 184 * @hwif: the HW interface of a pci function device 185 * 186 * Return 0 - Success, negative - Failure 187 **/ 188 static int hwif_ready(struct hinic_hwif *hwif) 189 { 190 struct pci_dev *pdev = hwif->pdev; 191 u32 addr, attr1; 192 193 addr = HINIC_CSR_FUNC_ATTR1_ADDR; 194 attr1 = hinic_hwif_read_reg(hwif, addr); 195 196 if (!HINIC_FA1_GET(attr1, INIT_STATUS)) { 197 dev_err(&pdev->dev, "hwif status is not ready\n"); 198 return -EFAULT; 199 } 200 201 return 0; 202 } 203 204 /** 205 * set_hwif_attr - set the attributes in the relevant members in hwif 206 * @hwif: the HW interface of a pci function device 207 * @attr0: the first attribute that was read from the hw 208 * @attr1: the second attribute that was read from the hw 209 **/ 210 static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1, 211 u32 attr2) 212 { 213 hwif->attr.func_idx = HINIC_FA0_GET(attr0, FUNC_IDX); 214 hwif->attr.pf_idx = HINIC_FA0_GET(attr0, PF_IDX); 215 hwif->attr.pci_intf_idx = HINIC_FA0_GET(attr0, PCI_INTF_IDX); 216 hwif->attr.func_type = HINIC_FA0_GET(attr0, FUNC_TYPE); 217 218 hwif->attr.num_aeqs = BIT(HINIC_FA1_GET(attr1, AEQS_PER_FUNC)); 219 hwif->attr.num_ceqs = BIT(HINIC_FA1_GET(attr1, CEQS_PER_FUNC)); 220 hwif->attr.num_irqs = BIT(HINIC_FA1_GET(attr1, IRQS_PER_FUNC)); 221 hwif->attr.num_dma_attr = BIT(HINIC_FA1_GET(attr1, DMA_ATTR_PER_FUNC)); 222 hwif->attr.global_vf_id_of_pf = HINIC_FA2_GET(attr2, 223 GLOBAL_VF_ID_OF_PF); 224 } 225 226 /** 227 * read_hwif_attr - read the attributes and set members in hwif 228 * @hwif: the HW interface of a pci function device 229 **/ 230 static void read_hwif_attr(struct hinic_hwif *hwif) 231 { 232 u32 addr, attr0, attr1, attr2; 233 234 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 235 attr0 = hinic_hwif_read_reg(hwif, addr); 236 237 addr = HINIC_CSR_FUNC_ATTR1_ADDR; 238 attr1 = hinic_hwif_read_reg(hwif, addr); 239 240 addr = HINIC_CSR_FUNC_ATTR2_ADDR; 241 attr2 = hinic_hwif_read_reg(hwif, addr); 242 243 set_hwif_attr(hwif, attr0, attr1, attr2); 244 } 245 246 /** 247 * set_ppf - try to set hwif as ppf and set the type of hwif in this case 248 * @hwif: the HW interface of a pci function device 249 **/ 250 static void set_ppf(struct hinic_hwif *hwif) 251 { 252 struct hinic_func_attr *attr = &hwif->attr; 253 u32 addr, val, ppf_election; 254 255 /* Read Modify Write */ 256 addr = HINIC_CSR_PPF_ELECTION_ADDR(HINIC_HWIF_PCI_INTF(hwif)); 257 258 val = hinic_hwif_read_reg(hwif, addr); 259 val = HINIC_PPF_ELECTION_CLEAR(val, IDX); 260 261 ppf_election = HINIC_PPF_ELECTION_SET(HINIC_HWIF_FUNC_IDX(hwif), IDX); 262 263 val |= ppf_election; 264 hinic_hwif_write_reg(hwif, addr, val); 265 266 /* check PPF */ 267 val = hinic_hwif_read_reg(hwif, addr); 268 269 attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX); 270 if (attr->ppf_idx == HINIC_HWIF_FUNC_IDX(hwif)) 271 attr->func_type = HINIC_PPF; 272 } 273 274 /** 275 * set_dma_attr - set the dma attributes in the HW 276 * @hwif: the HW interface of a pci function device 277 * @entry_idx: the entry index in the dma table 278 * @st: PCIE TLP steering tag 279 * @at: PCIE TLP AT field 280 * @ph: PCIE TLP Processing Hint field 281 * @no_snooping: PCIE TLP No snooping 282 * @tph_en: PCIE TLP Processing Hint Enable 283 **/ 284 static void set_dma_attr(struct hinic_hwif *hwif, u32 entry_idx, 285 u8 st, u8 at, u8 ph, 286 enum hinic_pcie_nosnoop no_snooping, 287 enum hinic_pcie_tph tph_en) 288 { 289 u32 addr, val, dma_attr_entry; 290 291 /* Read Modify Write */ 292 addr = HINIC_CSR_DMA_ATTR_ADDR(entry_idx); 293 294 val = hinic_hwif_read_reg(hwif, addr); 295 val = HINIC_DMA_ATTR_CLEAR(val, ST) & 296 HINIC_DMA_ATTR_CLEAR(val, AT) & 297 HINIC_DMA_ATTR_CLEAR(val, PH) & 298 HINIC_DMA_ATTR_CLEAR(val, NO_SNOOPING) & 299 HINIC_DMA_ATTR_CLEAR(val, TPH_EN); 300 301 dma_attr_entry = HINIC_DMA_ATTR_SET(st, ST) | 302 HINIC_DMA_ATTR_SET(at, AT) | 303 HINIC_DMA_ATTR_SET(ph, PH) | 304 HINIC_DMA_ATTR_SET(no_snooping, NO_SNOOPING) | 305 HINIC_DMA_ATTR_SET(tph_en, TPH_EN); 306 307 val |= dma_attr_entry; 308 hinic_hwif_write_reg(hwif, addr, val); 309 } 310 311 /** 312 * dma_attr_table_init - initialize the the default dma attributes 313 * @hwif: the HW interface of a pci function device 314 **/ 315 static void dma_attr_init(struct hinic_hwif *hwif) 316 { 317 set_dma_attr(hwif, PCIE_ATTR_ENTRY, HINIC_PCIE_ST_DISABLE, 318 HINIC_PCIE_AT_DISABLE, HINIC_PCIE_PH_DISABLE, 319 HINIC_PCIE_SNOOP, HINIC_PCIE_TPH_DISABLE); 320 } 321 322 u16 hinic_glb_pf_vf_offset(struct hinic_hwif *hwif) 323 { 324 if (!hwif) 325 return 0; 326 327 return hwif->attr.global_vf_id_of_pf; 328 } 329 330 u16 hinic_global_func_id_hw(struct hinic_hwif *hwif) 331 { 332 u32 addr, attr0; 333 334 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 335 attr0 = hinic_hwif_read_reg(hwif, addr); 336 337 return HINIC_FA0_GET(attr0, FUNC_IDX); 338 } 339 340 u16 hinic_pf_id_of_vf_hw(struct hinic_hwif *hwif) 341 { 342 u32 addr, attr0; 343 344 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 345 attr0 = hinic_hwif_read_reg(hwif, addr); 346 347 return HINIC_FA0_GET(attr0, PF_IDX); 348 } 349 350 /** 351 * hinic_init_hwif - initialize the hw interface 352 * @hwif: the HW interface of a pci function device 353 * @pdev: the pci device for acessing PCI resources 354 * 355 * Return 0 - Success, negative - Failure 356 **/ 357 int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev) 358 { 359 int err; 360 361 hwif->pdev = pdev; 362 363 hwif->cfg_regs_bar = pci_ioremap_bar(pdev, HINIC_PCI_CFG_REGS_BAR); 364 if (!hwif->cfg_regs_bar) { 365 dev_err(&pdev->dev, "Failed to map configuration regs\n"); 366 return -ENOMEM; 367 } 368 369 hwif->intr_regs_base = pci_ioremap_bar(pdev, HINIC_PCI_INTR_REGS_BAR); 370 if (!hwif->intr_regs_base) { 371 dev_err(&pdev->dev, "Failed to map configuration regs\n"); 372 err = -ENOMEM; 373 goto err_map_intr_bar; 374 } 375 376 err = hwif_ready(hwif); 377 if (err) { 378 dev_err(&pdev->dev, "HW interface is not ready\n"); 379 goto err_hwif_ready; 380 } 381 382 read_hwif_attr(hwif); 383 384 if (HINIC_IS_PF(hwif)) 385 set_ppf(hwif); 386 387 /* No transactionss before DMA is initialized */ 388 dma_attr_init(hwif); 389 return 0; 390 391 err_hwif_ready: 392 iounmap(hwif->intr_regs_base); 393 394 err_map_intr_bar: 395 iounmap(hwif->cfg_regs_bar); 396 397 return err; 398 } 399 400 /** 401 * hinic_free_hwif - free the HW interface 402 * @hwif: the HW interface of a pci function device 403 **/ 404 void hinic_free_hwif(struct hinic_hwif *hwif) 405 { 406 iounmap(hwif->intr_regs_base); 407 iounmap(hwif->cfg_regs_bar); 408 } 409