1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_HW_DEV_H 8 #define HINIC_HW_DEV_H 9 10 #include <linux/pci.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 14 #include "hinic_hw_if.h" 15 #include "hinic_hw_eqs.h" 16 #include "hinic_hw_mgmt.h" 17 #include "hinic_hw_qp.h" 18 #include "hinic_hw_io.h" 19 20 #define HINIC_MAX_QPS 32 21 22 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ 23 HINIC_MGMT_MSG_CMD_BASE) 24 25 struct hinic_cap { 26 u16 max_qps; 27 u16 num_qps; 28 }; 29 30 enum hinic_port_cmd { 31 HINIC_PORT_CMD_CHANGE_MTU = 2, 32 33 HINIC_PORT_CMD_ADD_VLAN = 3, 34 HINIC_PORT_CMD_DEL_VLAN = 4, 35 36 HINIC_PORT_CMD_SET_MAC = 9, 37 HINIC_PORT_CMD_GET_MAC = 10, 38 HINIC_PORT_CMD_DEL_MAC = 11, 39 40 HINIC_PORT_CMD_SET_RX_MODE = 12, 41 42 HINIC_PORT_CMD_GET_LINK_STATE = 24, 43 44 HINIC_PORT_CMD_SET_LRO = 25, 45 46 HINIC_PORT_CMD_SET_RX_CSUM = 26, 47 48 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37, 49 50 HINIC_PORT_CMD_SET_PORT_STATE = 41, 51 52 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43, 53 54 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44, 55 56 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45, 57 58 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46, 59 60 HINIC_PORT_CMD_GET_RSS_CTX_TBL = 47, 61 62 HINIC_PORT_CMD_SET_RSS_CTX_TBL = 48, 63 64 HINIC_PORT_CMD_RSS_TEMP_MGR = 49, 65 66 HINIC_PORT_CMD_RSS_CFG = 66, 67 68 HINIC_PORT_CMD_FWCTXT_INIT = 69, 69 70 HINIC_PORT_CMD_SET_FUNC_STATE = 93, 71 72 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, 73 74 HINIC_PORT_CMD_SET_TSO = 112, 75 76 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115, 77 78 HINIC_PORT_CMD_GET_CAP = 170, 79 80 HINIC_PORT_CMD_SET_LRO_TIMER = 244, 81 }; 82 83 enum hinic_ucode_cmd { 84 HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0, 85 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, 86 HINIC_UCODE_CMD_ARM_SQ, 87 HINIC_UCODE_CMD_ARM_RQ, 88 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, 89 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, 90 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, 91 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, 92 HINIC_UCODE_CMD_SET_IQ_ENABLE, 93 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 94 }; 95 96 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 97 #define NIC_RSS_CMD_TEMP_FREE 0x02 98 99 enum hinic_mgmt_msg_cmd { 100 HINIC_MGMT_MSG_CMD_BASE = 160, 101 102 HINIC_MGMT_MSG_CMD_LINK_STATUS = 160, 103 104 HINIC_MGMT_MSG_CMD_MAX, 105 }; 106 107 enum hinic_cb_state { 108 HINIC_CB_ENABLED = BIT(0), 109 HINIC_CB_RUNNING = BIT(1), 110 }; 111 112 enum hinic_res_state { 113 HINIC_RES_CLEAN = 0, 114 HINIC_RES_ACTIVE = 1, 115 }; 116 117 struct hinic_cmd_fw_ctxt { 118 u8 status; 119 u8 version; 120 u8 rsvd0[6]; 121 122 u16 func_idx; 123 u16 rx_buf_sz; 124 125 u32 rsvd1; 126 }; 127 128 struct hinic_cmd_hw_ioctxt { 129 u8 status; 130 u8 version; 131 u8 rsvd0[6]; 132 133 u16 func_idx; 134 135 u16 rsvd1; 136 137 u8 set_cmdq_depth; 138 u8 cmdq_depth; 139 140 u8 lro_en; 141 u8 rsvd3; 142 u8 rsvd4; 143 u8 rsvd5; 144 145 u16 rq_depth; 146 u16 rx_buf_sz_idx; 147 u16 sq_depth; 148 }; 149 150 struct hinic_cmd_io_status { 151 u8 status; 152 u8 version; 153 u8 rsvd0[6]; 154 155 u16 func_idx; 156 u8 rsvd1; 157 u8 rsvd2; 158 u32 io_status; 159 }; 160 161 struct hinic_cmd_clear_io_res { 162 u8 status; 163 u8 version; 164 u8 rsvd0[6]; 165 166 u16 func_idx; 167 u8 rsvd1; 168 u8 rsvd2; 169 }; 170 171 struct hinic_cmd_set_res_state { 172 u8 status; 173 u8 version; 174 u8 rsvd0[6]; 175 176 u16 func_idx; 177 u8 state; 178 u8 rsvd1; 179 u32 rsvd2; 180 }; 181 182 struct hinic_cmd_base_qpn { 183 u8 status; 184 u8 version; 185 u8 rsvd0[6]; 186 187 u16 func_idx; 188 u16 qpn; 189 }; 190 191 struct hinic_cmd_hw_ci { 192 u8 status; 193 u8 version; 194 u8 rsvd0[6]; 195 196 u16 func_idx; 197 198 u8 dma_attr_off; 199 u8 pending_limit; 200 u8 coalesc_timer; 201 202 u8 msix_en; 203 u16 msix_entry_idx; 204 205 u32 sq_id; 206 u32 rsvd1; 207 u64 ci_addr; 208 }; 209 210 struct hinic_hwdev { 211 struct hinic_hwif *hwif; 212 struct msix_entry *msix_entries; 213 214 struct hinic_aeqs aeqs; 215 struct hinic_func_to_io func_to_io; 216 217 struct hinic_cap nic_cap; 218 }; 219 220 struct hinic_nic_cb { 221 void (*handler)(void *handle, void *buf_in, 222 u16 in_size, void *buf_out, 223 u16 *out_size); 224 225 void *handle; 226 unsigned long cb_state; 227 }; 228 229 struct hinic_pfhwdev { 230 struct hinic_hwdev hwdev; 231 232 struct hinic_pf_to_mgmt pf_to_mgmt; 233 234 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; 235 }; 236 237 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 238 enum hinic_mgmt_msg_cmd cmd, void *handle, 239 void (*handler)(void *handle, void *buf_in, 240 u16 in_size, void *buf_out, 241 u16 *out_size)); 242 243 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 244 enum hinic_mgmt_msg_cmd cmd); 245 246 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 247 void *buf_in, u16 in_size, void *buf_out, 248 u16 *out_size); 249 250 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev); 251 252 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); 253 254 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev); 255 256 void hinic_free_hwdev(struct hinic_hwdev *hwdev); 257 258 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev); 259 260 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); 261 262 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); 263 264 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); 265 266 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); 267 268 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 269 u8 pending_limit, u8 coalesc_timer, 270 u8 lli_timer_cfg, u8 lli_credit_limit, 271 u8 resend_timer); 272 273 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 274 u8 pending_limit, u8 coalesc_timer); 275 276 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 277 enum hinic_msix_state flag); 278 279 #endif 280