1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_HW_DEV_H 8 #define HINIC_HW_DEV_H 9 10 #include <linux/pci.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 14 #include "hinic_hw_if.h" 15 #include "hinic_hw_eqs.h" 16 #include "hinic_hw_mgmt.h" 17 #include "hinic_hw_qp.h" 18 #include "hinic_hw_io.h" 19 #include "hinic_hw_mbox.h" 20 21 #define HINIC_MAX_QPS 32 22 23 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ 24 HINIC_MGMT_MSG_CMD_BASE) 25 26 #define HINIC_PF_SET_VF_ALREADY 0x4 27 #define HINIC_MGMT_STATUS_EXIST 0x6 28 #define HINIC_MGMT_CMD_UNSUPPORTED 0xFF 29 30 struct hinic_cap { 31 u16 max_qps; 32 u16 num_qps; 33 u8 max_vf; 34 u16 max_vf_qps; 35 }; 36 37 enum hw_ioctxt_set_cmdq_depth { 38 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT, 39 HW_IOCTXT_SET_CMDQ_DEPTH_ENABLE, 40 }; 41 42 enum hinic_port_cmd { 43 HINIC_PORT_CMD_VF_REGISTER = 0x0, 44 HINIC_PORT_CMD_VF_UNREGISTER = 0x1, 45 46 HINIC_PORT_CMD_CHANGE_MTU = 2, 47 48 HINIC_PORT_CMD_ADD_VLAN = 3, 49 HINIC_PORT_CMD_DEL_VLAN = 4, 50 51 HINIC_PORT_CMD_SET_PFC = 5, 52 53 HINIC_PORT_CMD_SET_MAC = 9, 54 HINIC_PORT_CMD_GET_MAC = 10, 55 HINIC_PORT_CMD_DEL_MAC = 11, 56 57 HINIC_PORT_CMD_SET_RX_MODE = 12, 58 59 HINIC_PORT_CMD_GET_PAUSE_INFO = 20, 60 HINIC_PORT_CMD_SET_PAUSE_INFO = 21, 61 62 HINIC_PORT_CMD_GET_LINK_STATE = 24, 63 64 HINIC_PORT_CMD_SET_LRO = 25, 65 66 HINIC_PORT_CMD_SET_RX_CSUM = 26, 67 68 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27, 69 70 HINIC_PORT_CMD_GET_PORT_STATISTICS = 28, 71 72 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29, 73 74 HINIC_PORT_CMD_GET_VPORT_STAT = 30, 75 76 HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31, 77 78 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37, 79 80 HINIC_PORT_CMD_SET_PORT_STATE = 41, 81 82 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43, 83 84 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44, 85 86 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45, 87 88 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46, 89 90 HINIC_PORT_CMD_GET_RSS_CTX_TBL = 47, 91 92 HINIC_PORT_CMD_SET_RSS_CTX_TBL = 48, 93 94 HINIC_PORT_CMD_RSS_TEMP_MGR = 49, 95 96 HINIC_PORT_CMD_RSS_CFG = 66, 97 98 HINIC_PORT_CMD_FWCTXT_INIT = 69, 99 100 HINIC_PORT_CMD_GET_LOOPBACK_MODE = 72, 101 HINIC_PORT_CMD_SET_LOOPBACK_MODE, 102 103 HINIC_PORT_CMD_ENABLE_SPOOFCHK = 78, 104 105 HINIC_PORT_CMD_GET_MGMT_VERSION = 88, 106 107 HINIC_PORT_CMD_SET_FUNC_STATE = 93, 108 109 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, 110 111 HINIC_PORT_CMD_SET_VF_RATE = 105, 112 113 HINIC_PORT_CMD_SET_VF_VLAN = 106, 114 115 HINIC_PORT_CMD_CLR_VF_VLAN, 116 117 HINIC_PORT_CMD_SET_TSO = 112, 118 119 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115, 120 121 HINIC_PORT_CMD_LINK_STATUS_REPORT = 160, 122 123 HINIC_PORT_CMD_UPDATE_MAC = 164, 124 125 HINIC_PORT_CMD_GET_CAP = 170, 126 127 HINIC_PORT_CMD_GET_LINK_MODE = 217, 128 129 HINIC_PORT_CMD_SET_SPEED = 218, 130 131 HINIC_PORT_CMD_SET_AUTONEG = 219, 132 133 HINIC_PORT_CMD_GET_STD_SFP_INFO = 240, 134 135 HINIC_PORT_CMD_SET_LRO_TIMER = 244, 136 137 HINIC_PORT_CMD_SET_VF_MAX_MIN_RATE = 249, 138 139 HINIC_PORT_CMD_GET_SFP_ABS = 251, 140 }; 141 142 /* cmd of mgmt CPU message for HILINK module */ 143 enum hinic_hilink_cmd { 144 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3, 145 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8, 146 }; 147 148 enum hinic_ucode_cmd { 149 HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0, 150 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, 151 HINIC_UCODE_CMD_ARM_SQ, 152 HINIC_UCODE_CMD_ARM_RQ, 153 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, 154 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, 155 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, 156 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, 157 HINIC_UCODE_CMD_SET_IQ_ENABLE, 158 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 159 }; 160 161 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 162 #define NIC_RSS_CMD_TEMP_FREE 0x02 163 164 enum hinic_mgmt_msg_cmd { 165 HINIC_MGMT_MSG_CMD_BASE = 160, 166 167 HINIC_MGMT_MSG_CMD_LINK_STATUS = 160, 168 169 HINIC_MGMT_MSG_CMD_MAX, 170 }; 171 172 enum hinic_cb_state { 173 HINIC_CB_ENABLED = BIT(0), 174 HINIC_CB_RUNNING = BIT(1), 175 }; 176 177 enum hinic_res_state { 178 HINIC_RES_CLEAN = 0, 179 HINIC_RES_ACTIVE = 1, 180 }; 181 182 struct hinic_cmd_fw_ctxt { 183 u8 status; 184 u8 version; 185 u8 rsvd0[6]; 186 187 u16 func_idx; 188 u16 rx_buf_sz; 189 190 u32 rsvd1; 191 }; 192 193 struct hinic_cmd_hw_ioctxt { 194 u8 status; 195 u8 version; 196 u8 rsvd0[6]; 197 198 u16 func_idx; 199 200 u16 rsvd1; 201 202 u8 set_cmdq_depth; 203 u8 cmdq_depth; 204 205 u8 lro_en; 206 u8 rsvd3; 207 u8 ppf_idx; 208 u8 rsvd4; 209 210 u16 rq_depth; 211 u16 rx_buf_sz_idx; 212 u16 sq_depth; 213 }; 214 215 struct hinic_cmd_io_status { 216 u8 status; 217 u8 version; 218 u8 rsvd0[6]; 219 220 u16 func_idx; 221 u8 rsvd1; 222 u8 rsvd2; 223 u32 io_status; 224 }; 225 226 struct hinic_cmd_clear_io_res { 227 u8 status; 228 u8 version; 229 u8 rsvd0[6]; 230 231 u16 func_idx; 232 u8 rsvd1; 233 u8 rsvd2; 234 }; 235 236 struct hinic_cmd_set_res_state { 237 u8 status; 238 u8 version; 239 u8 rsvd0[6]; 240 241 u16 func_idx; 242 u8 state; 243 u8 rsvd1; 244 u32 rsvd2; 245 }; 246 247 struct hinic_ceq_ctrl_reg { 248 u8 status; 249 u8 version; 250 u8 rsvd0[6]; 251 252 u16 func_id; 253 u16 q_id; 254 u32 ctrl0; 255 u32 ctrl1; 256 }; 257 258 struct hinic_cmd_base_qpn { 259 u8 status; 260 u8 version; 261 u8 rsvd0[6]; 262 263 u16 func_idx; 264 u16 qpn; 265 }; 266 267 struct hinic_cmd_hw_ci { 268 u8 status; 269 u8 version; 270 u8 rsvd0[6]; 271 272 u16 func_idx; 273 274 u8 dma_attr_off; 275 u8 pending_limit; 276 u8 coalesc_timer; 277 278 u8 msix_en; 279 u16 msix_entry_idx; 280 281 u32 sq_id; 282 u32 rsvd1; 283 u64 ci_addr; 284 }; 285 286 struct hinic_cmd_l2nic_reset { 287 u8 status; 288 u8 version; 289 u8 rsvd0[6]; 290 291 u16 func_id; 292 u16 reset_flag; 293 }; 294 295 struct hinic_msix_config { 296 u8 status; 297 u8 version; 298 u8 rsvd0[6]; 299 300 u16 func_id; 301 u16 msix_index; 302 u8 pending_cnt; 303 u8 coalesce_timer_cnt; 304 u8 lli_timer_cnt; 305 u8 lli_credit_cnt; 306 u8 resend_timer_cnt; 307 u8 rsvd1[3]; 308 }; 309 310 struct hinic_hwdev { 311 struct hinic_hwif *hwif; 312 struct msix_entry *msix_entries; 313 314 struct hinic_aeqs aeqs; 315 struct hinic_func_to_io func_to_io; 316 struct hinic_mbox_func_to_func *func_to_func; 317 318 struct hinic_cap nic_cap; 319 u8 port_id; 320 }; 321 322 struct hinic_nic_cb { 323 void (*handler)(void *handle, void *buf_in, 324 u16 in_size, void *buf_out, 325 u16 *out_size); 326 327 void *handle; 328 unsigned long cb_state; 329 }; 330 331 struct hinic_pfhwdev { 332 struct hinic_hwdev hwdev; 333 334 struct hinic_pf_to_mgmt pf_to_mgmt; 335 336 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; 337 }; 338 339 struct hinic_dev_cap { 340 u8 status; 341 u8 version; 342 u8 rsvd0[6]; 343 344 u8 rsvd1[5]; 345 u8 intr_type; 346 u8 max_cos_id; 347 u8 er_id; 348 u8 port_id; 349 u8 max_vf; 350 u8 rsvd2[62]; 351 u16 max_sqs; 352 u16 max_rqs; 353 u16 max_vf_sqs; 354 u16 max_vf_rqs; 355 u8 rsvd3[204]; 356 }; 357 358 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 359 enum hinic_mgmt_msg_cmd cmd, void *handle, 360 void (*handler)(void *handle, void *buf_in, 361 u16 in_size, void *buf_out, 362 u16 *out_size)); 363 364 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 365 enum hinic_mgmt_msg_cmd cmd); 366 367 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 368 void *buf_in, u16 in_size, void *buf_out, 369 u16 *out_size); 370 371 int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd, 372 void *buf_in, u16 in_size, void *buf_out, 373 u16 *out_size); 374 375 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth); 376 377 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); 378 379 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev); 380 381 void hinic_free_hwdev(struct hinic_hwdev *hwdev); 382 383 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev); 384 385 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); 386 387 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); 388 389 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); 390 391 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); 392 393 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 394 u8 pending_limit, u8 coalesc_timer, 395 u8 lli_timer_cfg, u8 lli_credit_limit, 396 u8 resend_timer); 397 398 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 399 u8 pending_limit, u8 coalesc_timer); 400 401 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 402 enum hinic_msix_state flag); 403 404 int hinic_get_interrupt_cfg(struct hinic_hwdev *hwdev, 405 struct hinic_msix_config *interrupt_info); 406 407 int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev, 408 struct hinic_msix_config *interrupt_info); 409 410 #endif 411