1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_HW_DEV_H 8 #define HINIC_HW_DEV_H 9 10 #include <linux/pci.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 14 #include "hinic_hw_if.h" 15 #include "hinic_hw_eqs.h" 16 #include "hinic_hw_mgmt.h" 17 #include "hinic_hw_qp.h" 18 #include "hinic_hw_io.h" 19 #include "hinic_hw_mbox.h" 20 21 #define HINIC_MAX_QPS 32 22 23 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ 24 HINIC_MGMT_MSG_CMD_BASE) 25 26 #define HINIC_PF_SET_VF_ALREADY 0x4 27 #define HINIC_MGMT_STATUS_EXIST 0x6 28 29 struct hinic_cap { 30 u16 max_qps; 31 u16 num_qps; 32 u8 max_vf; 33 u16 max_vf_qps; 34 }; 35 36 enum hinic_port_cmd { 37 HINIC_PORT_CMD_VF_REGISTER = 0x0, 38 HINIC_PORT_CMD_VF_UNREGISTER = 0x1, 39 40 HINIC_PORT_CMD_CHANGE_MTU = 2, 41 42 HINIC_PORT_CMD_ADD_VLAN = 3, 43 HINIC_PORT_CMD_DEL_VLAN = 4, 44 45 HINIC_PORT_CMD_SET_MAC = 9, 46 HINIC_PORT_CMD_GET_MAC = 10, 47 HINIC_PORT_CMD_DEL_MAC = 11, 48 49 HINIC_PORT_CMD_SET_RX_MODE = 12, 50 51 HINIC_PORT_CMD_GET_LINK_STATE = 24, 52 53 HINIC_PORT_CMD_SET_LRO = 25, 54 55 HINIC_PORT_CMD_SET_RX_CSUM = 26, 56 57 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27, 58 59 HINIC_PORT_CMD_GET_PORT_STATISTICS = 28, 60 61 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29, 62 63 HINIC_PORT_CMD_GET_VPORT_STAT = 30, 64 65 HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31, 66 67 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37, 68 69 HINIC_PORT_CMD_SET_PORT_STATE = 41, 70 71 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43, 72 73 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44, 74 75 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45, 76 77 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46, 78 79 HINIC_PORT_CMD_GET_RSS_CTX_TBL = 47, 80 81 HINIC_PORT_CMD_SET_RSS_CTX_TBL = 48, 82 83 HINIC_PORT_CMD_RSS_TEMP_MGR = 49, 84 85 HINIC_PORT_CMD_RSS_CFG = 66, 86 87 HINIC_PORT_CMD_FWCTXT_INIT = 69, 88 89 HINIC_PORT_CMD_GET_MGMT_VERSION = 88, 90 91 HINIC_PORT_CMD_SET_FUNC_STATE = 93, 92 93 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, 94 95 HINIC_PORT_CMD_SET_VF_VLAN = 106, 96 97 HINIC_PORT_CMD_CLR_VF_VLAN, 98 99 HINIC_PORT_CMD_SET_TSO = 112, 100 101 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115, 102 103 HINIC_PORT_CMD_LINK_STATUS_REPORT = 160, 104 105 HINIC_PORT_CMD_UPDATE_MAC = 164, 106 107 HINIC_PORT_CMD_GET_CAP = 170, 108 109 HINIC_PORT_CMD_SET_LRO_TIMER = 244, 110 }; 111 112 enum hinic_ucode_cmd { 113 HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0, 114 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, 115 HINIC_UCODE_CMD_ARM_SQ, 116 HINIC_UCODE_CMD_ARM_RQ, 117 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, 118 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, 119 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, 120 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, 121 HINIC_UCODE_CMD_SET_IQ_ENABLE, 122 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 123 }; 124 125 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 126 #define NIC_RSS_CMD_TEMP_FREE 0x02 127 128 enum hinic_mgmt_msg_cmd { 129 HINIC_MGMT_MSG_CMD_BASE = 160, 130 131 HINIC_MGMT_MSG_CMD_LINK_STATUS = 160, 132 133 HINIC_MGMT_MSG_CMD_MAX, 134 }; 135 136 enum hinic_cb_state { 137 HINIC_CB_ENABLED = BIT(0), 138 HINIC_CB_RUNNING = BIT(1), 139 }; 140 141 enum hinic_res_state { 142 HINIC_RES_CLEAN = 0, 143 HINIC_RES_ACTIVE = 1, 144 }; 145 146 struct hinic_cmd_fw_ctxt { 147 u8 status; 148 u8 version; 149 u8 rsvd0[6]; 150 151 u16 func_idx; 152 u16 rx_buf_sz; 153 154 u32 rsvd1; 155 }; 156 157 struct hinic_cmd_hw_ioctxt { 158 u8 status; 159 u8 version; 160 u8 rsvd0[6]; 161 162 u16 func_idx; 163 164 u16 rsvd1; 165 166 u8 set_cmdq_depth; 167 u8 cmdq_depth; 168 169 u8 lro_en; 170 u8 rsvd3; 171 u8 ppf_idx; 172 u8 rsvd4; 173 174 u16 rq_depth; 175 u16 rx_buf_sz_idx; 176 u16 sq_depth; 177 }; 178 179 struct hinic_cmd_io_status { 180 u8 status; 181 u8 version; 182 u8 rsvd0[6]; 183 184 u16 func_idx; 185 u8 rsvd1; 186 u8 rsvd2; 187 u32 io_status; 188 }; 189 190 struct hinic_cmd_clear_io_res { 191 u8 status; 192 u8 version; 193 u8 rsvd0[6]; 194 195 u16 func_idx; 196 u8 rsvd1; 197 u8 rsvd2; 198 }; 199 200 struct hinic_cmd_set_res_state { 201 u8 status; 202 u8 version; 203 u8 rsvd0[6]; 204 205 u16 func_idx; 206 u8 state; 207 u8 rsvd1; 208 u32 rsvd2; 209 }; 210 211 struct hinic_ceq_ctrl_reg { 212 u8 status; 213 u8 version; 214 u8 rsvd0[6]; 215 216 u16 func_id; 217 u16 q_id; 218 u32 ctrl0; 219 u32 ctrl1; 220 }; 221 222 struct hinic_cmd_base_qpn { 223 u8 status; 224 u8 version; 225 u8 rsvd0[6]; 226 227 u16 func_idx; 228 u16 qpn; 229 }; 230 231 struct hinic_cmd_hw_ci { 232 u8 status; 233 u8 version; 234 u8 rsvd0[6]; 235 236 u16 func_idx; 237 238 u8 dma_attr_off; 239 u8 pending_limit; 240 u8 coalesc_timer; 241 242 u8 msix_en; 243 u16 msix_entry_idx; 244 245 u32 sq_id; 246 u32 rsvd1; 247 u64 ci_addr; 248 }; 249 250 struct hinic_hwdev { 251 struct hinic_hwif *hwif; 252 struct msix_entry *msix_entries; 253 254 struct hinic_aeqs aeqs; 255 struct hinic_func_to_io func_to_io; 256 struct hinic_mbox_func_to_func *func_to_func; 257 258 struct hinic_cap nic_cap; 259 }; 260 261 struct hinic_nic_cb { 262 void (*handler)(void *handle, void *buf_in, 263 u16 in_size, void *buf_out, 264 u16 *out_size); 265 266 void *handle; 267 unsigned long cb_state; 268 }; 269 270 struct hinic_pfhwdev { 271 struct hinic_hwdev hwdev; 272 273 struct hinic_pf_to_mgmt pf_to_mgmt; 274 275 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; 276 }; 277 278 struct hinic_dev_cap { 279 u8 status; 280 u8 version; 281 u8 rsvd0[6]; 282 283 u8 rsvd1[5]; 284 u8 intr_type; 285 u8 max_cos_id; 286 u8 er_id; 287 u8 port_id; 288 u8 max_vf; 289 u8 rsvd2[62]; 290 u16 max_sqs; 291 u16 max_rqs; 292 u16 max_vf_sqs; 293 u16 max_vf_rqs; 294 u8 rsvd3[204]; 295 }; 296 297 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 298 enum hinic_mgmt_msg_cmd cmd, void *handle, 299 void (*handler)(void *handle, void *buf_in, 300 u16 in_size, void *buf_out, 301 u16 *out_size)); 302 303 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 304 enum hinic_mgmt_msg_cmd cmd); 305 306 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 307 void *buf_in, u16 in_size, void *buf_out, 308 u16 *out_size); 309 310 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev); 311 312 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); 313 314 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev); 315 316 void hinic_free_hwdev(struct hinic_hwdev *hwdev); 317 318 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev); 319 320 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); 321 322 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); 323 324 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); 325 326 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); 327 328 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 329 u8 pending_limit, u8 coalesc_timer, 330 u8 lli_timer_cfg, u8 lli_credit_limit, 331 u8 resend_timer); 332 333 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 334 u8 pending_limit, u8 coalesc_timer); 335 336 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 337 enum hinic_msix_state flag); 338 339 #endif 340