1 /* 2 * Huawei HiNIC PCI Express Linux driver 3 * Copyright(c) 2017 Huawei Technologies Co., Ltd 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 */ 15 16 #ifndef HINIC_HW_DEV_H 17 #define HINIC_HW_DEV_H 18 19 #include <linux/pci.h> 20 #include <linux/types.h> 21 #include <linux/bitops.h> 22 23 #include "hinic_hw_if.h" 24 #include "hinic_hw_eqs.h" 25 #include "hinic_hw_mgmt.h" 26 #include "hinic_hw_qp.h" 27 #include "hinic_hw_io.h" 28 29 #define HINIC_MAX_QPS 32 30 31 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ 32 HINIC_MGMT_MSG_CMD_BASE) 33 34 struct hinic_cap { 35 u16 max_qps; 36 u16 num_qps; 37 }; 38 39 enum hinic_port_cmd { 40 HINIC_PORT_CMD_CHANGE_MTU = 2, 41 42 HINIC_PORT_CMD_ADD_VLAN = 3, 43 HINIC_PORT_CMD_DEL_VLAN = 4, 44 45 HINIC_PORT_CMD_SET_MAC = 9, 46 HINIC_PORT_CMD_GET_MAC = 10, 47 HINIC_PORT_CMD_DEL_MAC = 11, 48 49 HINIC_PORT_CMD_SET_RX_MODE = 12, 50 51 HINIC_PORT_CMD_GET_LINK_STATE = 24, 52 53 HINIC_PORT_CMD_SET_LRO = 25, 54 55 HINIC_PORT_CMD_SET_RX_CSUM = 26, 56 57 HINIC_PORT_CMD_SET_PORT_STATE = 41, 58 59 HINIC_PORT_CMD_FWCTXT_INIT = 69, 60 61 HINIC_PORT_CMD_SET_FUNC_STATE = 93, 62 63 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, 64 65 HINIC_PORT_CMD_SET_TSO = 112, 66 67 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115, 68 69 HINIC_PORT_CMD_GET_CAP = 170, 70 71 HINIC_PORT_CMD_SET_LRO_TIMER = 244, 72 }; 73 74 enum hinic_mgmt_msg_cmd { 75 HINIC_MGMT_MSG_CMD_BASE = 160, 76 77 HINIC_MGMT_MSG_CMD_LINK_STATUS = 160, 78 79 HINIC_MGMT_MSG_CMD_MAX, 80 }; 81 82 enum hinic_cb_state { 83 HINIC_CB_ENABLED = BIT(0), 84 HINIC_CB_RUNNING = BIT(1), 85 }; 86 87 enum hinic_res_state { 88 HINIC_RES_CLEAN = 0, 89 HINIC_RES_ACTIVE = 1, 90 }; 91 92 struct hinic_cmd_fw_ctxt { 93 u8 status; 94 u8 version; 95 u8 rsvd0[6]; 96 97 u16 func_idx; 98 u16 rx_buf_sz; 99 100 u32 rsvd1; 101 }; 102 103 struct hinic_cmd_hw_ioctxt { 104 u8 status; 105 u8 version; 106 u8 rsvd0[6]; 107 108 u16 func_idx; 109 110 u16 rsvd1; 111 112 u8 set_cmdq_depth; 113 u8 cmdq_depth; 114 115 u8 lro_en; 116 u8 rsvd3; 117 u8 rsvd4; 118 u8 rsvd5; 119 120 u16 rq_depth; 121 u16 rx_buf_sz_idx; 122 u16 sq_depth; 123 }; 124 125 struct hinic_cmd_io_status { 126 u8 status; 127 u8 version; 128 u8 rsvd0[6]; 129 130 u16 func_idx; 131 u8 rsvd1; 132 u8 rsvd2; 133 u32 io_status; 134 }; 135 136 struct hinic_cmd_clear_io_res { 137 u8 status; 138 u8 version; 139 u8 rsvd0[6]; 140 141 u16 func_idx; 142 u8 rsvd1; 143 u8 rsvd2; 144 }; 145 146 struct hinic_cmd_set_res_state { 147 u8 status; 148 u8 version; 149 u8 rsvd0[6]; 150 151 u16 func_idx; 152 u8 state; 153 u8 rsvd1; 154 u32 rsvd2; 155 }; 156 157 struct hinic_cmd_base_qpn { 158 u8 status; 159 u8 version; 160 u8 rsvd0[6]; 161 162 u16 func_idx; 163 u16 qpn; 164 }; 165 166 struct hinic_cmd_hw_ci { 167 u8 status; 168 u8 version; 169 u8 rsvd0[6]; 170 171 u16 func_idx; 172 173 u8 dma_attr_off; 174 u8 pending_limit; 175 u8 coalesc_timer; 176 177 u8 msix_en; 178 u16 msix_entry_idx; 179 180 u32 sq_id; 181 u32 rsvd1; 182 u64 ci_addr; 183 }; 184 185 struct hinic_hwdev { 186 struct hinic_hwif *hwif; 187 struct msix_entry *msix_entries; 188 189 struct hinic_aeqs aeqs; 190 struct hinic_func_to_io func_to_io; 191 192 struct hinic_cap nic_cap; 193 }; 194 195 struct hinic_nic_cb { 196 void (*handler)(void *handle, void *buf_in, 197 u16 in_size, void *buf_out, 198 u16 *out_size); 199 200 void *handle; 201 unsigned long cb_state; 202 }; 203 204 struct hinic_pfhwdev { 205 struct hinic_hwdev hwdev; 206 207 struct hinic_pf_to_mgmt pf_to_mgmt; 208 209 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; 210 }; 211 212 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 213 enum hinic_mgmt_msg_cmd cmd, void *handle, 214 void (*handler)(void *handle, void *buf_in, 215 u16 in_size, void *buf_out, 216 u16 *out_size)); 217 218 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 219 enum hinic_mgmt_msg_cmd cmd); 220 221 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 222 void *buf_in, u16 in_size, void *buf_out, 223 u16 *out_size); 224 225 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev); 226 227 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); 228 229 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev); 230 231 void hinic_free_hwdev(struct hinic_hwdev *hwdev); 232 233 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); 234 235 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); 236 237 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); 238 239 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); 240 241 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 242 u8 pending_limit, u8 coalesc_timer, 243 u8 lli_timer_cfg, u8 lli_credit_limit, 244 u8 resend_timer); 245 246 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 247 u8 pending_limit, u8 coalesc_timer); 248 249 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 250 enum hinic_msix_state flag); 251 252 #endif 253