1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_HW_DEV_H 8 #define HINIC_HW_DEV_H 9 10 #include <linux/pci.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 #include <net/devlink.h> 14 15 #include "hinic_hw_if.h" 16 #include "hinic_hw_eqs.h" 17 #include "hinic_hw_mgmt.h" 18 #include "hinic_hw_qp.h" 19 #include "hinic_hw_io.h" 20 #include "hinic_hw_mbox.h" 21 22 #define HINIC_MAX_QPS 32 23 24 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ 25 HINIC_MGMT_MSG_CMD_BASE) 26 27 #define HINIC_PF_SET_VF_ALREADY 0x4 28 #define HINIC_MGMT_STATUS_EXIST 0x6 29 #define HINIC_MGMT_CMD_UNSUPPORTED 0xFF 30 31 #define HINIC_CMD_VER_FUNC_ID 2 32 33 struct hinic_cap { 34 u16 max_qps; 35 u16 num_qps; 36 u8 max_vf; 37 u16 max_vf_qps; 38 }; 39 40 enum hw_ioctxt_set_cmdq_depth { 41 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT, 42 HW_IOCTXT_SET_CMDQ_DEPTH_ENABLE, 43 }; 44 45 enum hinic_port_cmd { 46 HINIC_PORT_CMD_VF_REGISTER = 0x0, 47 HINIC_PORT_CMD_VF_UNREGISTER = 0x1, 48 49 HINIC_PORT_CMD_CHANGE_MTU = 2, 50 51 HINIC_PORT_CMD_ADD_VLAN = 3, 52 HINIC_PORT_CMD_DEL_VLAN = 4, 53 54 HINIC_PORT_CMD_SET_PFC = 5, 55 56 HINIC_PORT_CMD_SET_MAC = 9, 57 HINIC_PORT_CMD_GET_MAC = 10, 58 HINIC_PORT_CMD_DEL_MAC = 11, 59 60 HINIC_PORT_CMD_SET_RX_MODE = 12, 61 62 HINIC_PORT_CMD_GET_PAUSE_INFO = 20, 63 HINIC_PORT_CMD_SET_PAUSE_INFO = 21, 64 65 HINIC_PORT_CMD_GET_LINK_STATE = 24, 66 67 HINIC_PORT_CMD_SET_LRO = 25, 68 69 HINIC_PORT_CMD_SET_RX_CSUM = 26, 70 71 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27, 72 73 HINIC_PORT_CMD_GET_PORT_STATISTICS = 28, 74 75 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29, 76 77 HINIC_PORT_CMD_GET_VPORT_STAT = 30, 78 79 HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31, 80 81 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37, 82 83 HINIC_PORT_CMD_SET_PORT_STATE = 41, 84 85 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43, 86 87 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44, 88 89 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45, 90 91 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46, 92 93 HINIC_PORT_CMD_GET_RSS_CTX_TBL = 47, 94 95 HINIC_PORT_CMD_SET_RSS_CTX_TBL = 48, 96 97 HINIC_PORT_CMD_RSS_TEMP_MGR = 49, 98 99 HINIC_PORT_CMD_RD_LINE_TBL = 57, 100 101 HINIC_PORT_CMD_RSS_CFG = 66, 102 103 HINIC_PORT_CMD_FWCTXT_INIT = 69, 104 105 HINIC_PORT_CMD_GET_LOOPBACK_MODE = 72, 106 HINIC_PORT_CMD_SET_LOOPBACK_MODE, 107 108 HINIC_PORT_CMD_ENABLE_SPOOFCHK = 78, 109 110 HINIC_PORT_CMD_GET_MGMT_VERSION = 88, 111 112 HINIC_PORT_CMD_SET_FUNC_STATE = 93, 113 114 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, 115 116 HINIC_PORT_CMD_SET_VF_RATE = 105, 117 118 HINIC_PORT_CMD_SET_VF_VLAN = 106, 119 120 HINIC_PORT_CMD_CLR_VF_VLAN, 121 122 HINIC_PORT_CMD_SET_TSO = 112, 123 124 HINIC_PORT_CMD_UPDATE_FW = 114, 125 126 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115, 127 128 HINIC_PORT_CMD_LINK_STATUS_REPORT = 160, 129 130 HINIC_PORT_CMD_UPDATE_MAC = 164, 131 132 HINIC_PORT_CMD_GET_CAP = 170, 133 134 HINIC_PORT_CMD_GET_LINK_MODE = 217, 135 136 HINIC_PORT_CMD_SET_SPEED = 218, 137 138 HINIC_PORT_CMD_SET_AUTONEG = 219, 139 140 HINIC_PORT_CMD_GET_STD_SFP_INFO = 240, 141 142 HINIC_PORT_CMD_SET_LRO_TIMER = 244, 143 144 HINIC_PORT_CMD_SET_VF_MAX_MIN_RATE = 249, 145 146 HINIC_PORT_CMD_GET_SFP_ABS = 251, 147 }; 148 149 /* cmd of mgmt CPU message for HILINK module */ 150 enum hinic_hilink_cmd { 151 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3, 152 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8, 153 }; 154 155 enum hinic_ucode_cmd { 156 HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0, 157 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, 158 HINIC_UCODE_CMD_ARM_SQ, 159 HINIC_UCODE_CMD_ARM_RQ, 160 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, 161 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, 162 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, 163 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, 164 HINIC_UCODE_CMD_SET_IQ_ENABLE, 165 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 166 }; 167 168 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 169 #define NIC_RSS_CMD_TEMP_FREE 0x02 170 171 enum hinic_mgmt_msg_cmd { 172 HINIC_MGMT_MSG_CMD_BASE = 0xA0, 173 174 HINIC_MGMT_MSG_CMD_LINK_STATUS = 0xA0, 175 176 HINIC_MGMT_MSG_CMD_CABLE_PLUG_EVENT = 0xE5, 177 HINIC_MGMT_MSG_CMD_LINK_ERR_EVENT = 0xE6, 178 179 HINIC_MGMT_MSG_CMD_MAX, 180 }; 181 182 enum hinic_cb_state { 183 HINIC_CB_ENABLED = BIT(0), 184 HINIC_CB_RUNNING = BIT(1), 185 }; 186 187 enum hinic_res_state { 188 HINIC_RES_CLEAN = 0, 189 HINIC_RES_ACTIVE = 1, 190 }; 191 192 struct hinic_cmd_fw_ctxt { 193 u8 status; 194 u8 version; 195 u8 rsvd0[6]; 196 197 u16 func_idx; 198 u16 rx_buf_sz; 199 200 u32 rsvd1; 201 }; 202 203 struct hinic_cmd_hw_ioctxt { 204 u8 status; 205 u8 version; 206 u8 rsvd0[6]; 207 208 u16 func_idx; 209 210 u16 rsvd1; 211 212 u8 set_cmdq_depth; 213 u8 cmdq_depth; 214 215 u8 lro_en; 216 u8 rsvd3; 217 u8 ppf_idx; 218 u8 rsvd4; 219 220 u16 rq_depth; 221 u16 rx_buf_sz_idx; 222 u16 sq_depth; 223 }; 224 225 struct hinic_cmd_io_status { 226 u8 status; 227 u8 version; 228 u8 rsvd0[6]; 229 230 u16 func_idx; 231 u8 rsvd1; 232 u8 rsvd2; 233 u32 io_status; 234 }; 235 236 struct hinic_cmd_clear_io_res { 237 u8 status; 238 u8 version; 239 u8 rsvd0[6]; 240 241 u16 func_idx; 242 u8 rsvd1; 243 u8 rsvd2; 244 }; 245 246 struct hinic_cmd_set_res_state { 247 u8 status; 248 u8 version; 249 u8 rsvd0[6]; 250 251 u16 func_idx; 252 u8 state; 253 u8 rsvd1; 254 u32 rsvd2; 255 }; 256 257 struct hinic_ceq_ctrl_reg { 258 u8 status; 259 u8 version; 260 u8 rsvd0[6]; 261 262 u16 func_id; 263 u16 q_id; 264 u32 ctrl0; 265 u32 ctrl1; 266 }; 267 268 struct hinic_cmd_base_qpn { 269 u8 status; 270 u8 version; 271 u8 rsvd0[6]; 272 273 u16 func_idx; 274 u16 qpn; 275 }; 276 277 struct hinic_cmd_hw_ci { 278 u8 status; 279 u8 version; 280 u8 rsvd0[6]; 281 282 u16 func_idx; 283 284 u8 dma_attr_off; 285 u8 pending_limit; 286 u8 coalesc_timer; 287 288 u8 msix_en; 289 u16 msix_entry_idx; 290 291 u32 sq_id; 292 u32 rsvd1; 293 u64 ci_addr; 294 }; 295 296 struct hinic_cmd_l2nic_reset { 297 u8 status; 298 u8 version; 299 u8 rsvd0[6]; 300 301 u16 func_id; 302 u16 reset_flag; 303 }; 304 305 struct hinic_msix_config { 306 u8 status; 307 u8 version; 308 u8 rsvd0[6]; 309 310 u16 func_id; 311 u16 msix_index; 312 u8 pending_cnt; 313 u8 coalesce_timer_cnt; 314 u8 lli_timer_cnt; 315 u8 lli_credit_cnt; 316 u8 resend_timer_cnt; 317 u8 rsvd1[3]; 318 }; 319 320 struct hinic_set_random_id { 321 u8 status; 322 u8 version; 323 u8 rsvd0[6]; 324 325 u8 vf_in_pf; 326 u8 rsvd1; 327 u16 func_idx; 328 u32 random_id; 329 }; 330 331 struct hinic_board_info { 332 u32 board_type; 333 u32 port_num; 334 u32 port_speed; 335 u32 pcie_width; 336 u32 host_num; 337 u32 pf_num; 338 u32 vf_total_num; 339 u32 tile_num; 340 u32 qcm_num; 341 u32 core_num; 342 u32 work_mode; 343 u32 service_mode; 344 u32 pcie_mode; 345 u32 cfg_addr; 346 u32 boot_sel; 347 u32 board_id; 348 }; 349 350 struct hinic_comm_board_info { 351 u8 status; 352 u8 version; 353 u8 rsvd0[6]; 354 355 struct hinic_board_info info; 356 357 u32 rsvd1[4]; 358 }; 359 360 struct hinic_hwdev { 361 struct hinic_hwif *hwif; 362 struct msix_entry *msix_entries; 363 364 struct hinic_aeqs aeqs; 365 struct hinic_func_to_io func_to_io; 366 struct hinic_mbox_func_to_func *func_to_func; 367 368 struct hinic_cap nic_cap; 369 u8 port_id; 370 struct hinic_devlink_priv *devlink_dev; 371 }; 372 373 struct hinic_nic_cb { 374 void (*handler)(void *handle, void *buf_in, 375 u16 in_size, void *buf_out, 376 u16 *out_size); 377 378 void *handle; 379 unsigned long cb_state; 380 }; 381 382 #define HINIC_COMM_SELF_CMD_MAX 4 383 384 typedef void (*comm_mgmt_self_msg_proc)(void *handle, void *buf_in, u16 in_size, 385 void *buf_out, u16 *out_size); 386 387 struct comm_mgmt_self_msg_sub_info { 388 u8 cmd; 389 comm_mgmt_self_msg_proc proc; 390 }; 391 392 struct comm_mgmt_self_msg_info { 393 u8 cmd_num; 394 struct comm_mgmt_self_msg_sub_info info[HINIC_COMM_SELF_CMD_MAX]; 395 }; 396 397 struct hinic_pfhwdev { 398 struct hinic_hwdev hwdev; 399 400 struct hinic_pf_to_mgmt pf_to_mgmt; 401 402 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; 403 404 struct comm_mgmt_self_msg_info proc; 405 }; 406 407 struct hinic_dev_cap { 408 u8 status; 409 u8 version; 410 u8 rsvd0[6]; 411 412 u8 rsvd1[5]; 413 u8 intr_type; 414 u8 max_cos_id; 415 u8 er_id; 416 u8 port_id; 417 u8 max_vf; 418 u8 rsvd2[62]; 419 u16 max_sqs; 420 u16 max_rqs; 421 u16 max_vf_sqs; 422 u16 max_vf_rqs; 423 u8 rsvd3[204]; 424 }; 425 426 union hinic_fault_hw_mgmt { 427 u32 val[4]; 428 /* valid only type == FAULT_TYPE_CHIP */ 429 struct { 430 u8 node_id; 431 u8 err_level; 432 u16 err_type; 433 u32 err_csr_addr; 434 u32 err_csr_value; 435 /* func_id valid only if err_level == FAULT_LEVEL_SERIOUS_FLR */ 436 u16 func_id; 437 u16 rsvd2; 438 } chip; 439 440 /* valid only if type == FAULT_TYPE_UCODE */ 441 struct { 442 u8 cause_id; 443 u8 core_id; 444 u8 c_id; 445 u8 rsvd3; 446 u32 epc; 447 u32 rsvd4; 448 u32 rsvd5; 449 } ucode; 450 451 /* valid only if type == FAULT_TYPE_MEM_RD_TIMEOUT || 452 * FAULT_TYPE_MEM_WR_TIMEOUT 453 */ 454 struct { 455 u32 err_csr_ctrl; 456 u32 err_csr_data; 457 u32 ctrl_tab; 458 u32 mem_index; 459 } mem_timeout; 460 461 /* valid only if type == FAULT_TYPE_REG_RD_TIMEOUT || 462 * FAULT_TYPE_REG_WR_TIMEOUT 463 */ 464 struct { 465 u32 err_csr; 466 u32 rsvd6; 467 u32 rsvd7; 468 u32 rsvd8; 469 } reg_timeout; 470 471 struct { 472 /* 0: read; 1: write */ 473 u8 op_type; 474 u8 port_id; 475 u8 dev_ad; 476 u8 rsvd9; 477 u32 csr_addr; 478 u32 op_data; 479 u32 rsvd10; 480 } phy_fault; 481 }; 482 483 struct hinic_fault_event { 484 u8 type; 485 u8 fault_level; 486 u8 rsvd0[2]; 487 union hinic_fault_hw_mgmt event; 488 }; 489 490 struct hinic_cmd_fault_event { 491 u8 status; 492 u8 version; 493 u8 rsvd0[6]; 494 495 struct hinic_fault_event event; 496 }; 497 498 enum hinic_fault_type { 499 FAULT_TYPE_CHIP, 500 FAULT_TYPE_UCODE, 501 FAULT_TYPE_MEM_RD_TIMEOUT, 502 FAULT_TYPE_MEM_WR_TIMEOUT, 503 FAULT_TYPE_REG_RD_TIMEOUT, 504 FAULT_TYPE_REG_WR_TIMEOUT, 505 FAULT_TYPE_PHY_FAULT, 506 FAULT_TYPE_MAX, 507 }; 508 509 enum hinic_fault_err_level { 510 FAULT_LEVEL_FATAL, 511 FAULT_LEVEL_SERIOUS_RESET, 512 FAULT_LEVEL_SERIOUS_FLR, 513 FAULT_LEVEL_GENERAL, 514 FAULT_LEVEL_SUGGESTION, 515 FAULT_LEVEL_MAX 516 }; 517 518 struct hinic_mgmt_watchdog_info { 519 u8 status; 520 u8 version; 521 u8 rsvd0[6]; 522 523 u32 curr_time_h; 524 u32 curr_time_l; 525 u32 task_id; 526 u32 rsv; 527 528 u32 reg[13]; 529 u32 pc; 530 u32 lr; 531 u32 cpsr; 532 533 u32 stack_top; 534 u32 stack_bottom; 535 u32 sp; 536 u32 curr_used; 537 u32 peak_used; 538 u32 is_overflow; 539 540 u32 stack_actlen; 541 u8 data[1024]; 542 }; 543 544 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 545 enum hinic_mgmt_msg_cmd cmd, void *handle, 546 void (*handler)(void *handle, void *buf_in, 547 u16 in_size, void *buf_out, 548 u16 *out_size)); 549 550 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 551 enum hinic_mgmt_msg_cmd cmd); 552 553 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 554 void *buf_in, u16 in_size, void *buf_out, 555 u16 *out_size); 556 557 int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd, 558 void *buf_in, u16 in_size, void *buf_out, 559 u16 *out_size); 560 561 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth); 562 563 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); 564 565 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev, struct devlink *devlink); 566 567 void hinic_free_hwdev(struct hinic_hwdev *hwdev); 568 569 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev); 570 571 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); 572 573 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); 574 575 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); 576 577 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); 578 579 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 580 u8 pending_limit, u8 coalesc_timer, 581 u8 lli_timer_cfg, u8 lli_credit_limit, 582 u8 resend_timer); 583 584 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 585 u8 pending_limit, u8 coalesc_timer); 586 587 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 588 enum hinic_msix_state flag); 589 590 int hinic_get_interrupt_cfg(struct hinic_hwdev *hwdev, 591 struct hinic_msix_config *interrupt_info); 592 593 int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev, 594 struct hinic_msix_config *interrupt_info); 595 596 int hinic_get_board_info(struct hinic_hwdev *hwdev, 597 struct hinic_comm_board_info *board_info); 598 599 #endif 600