1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_MAIN_H 5 #define __HCLGEVF_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include "hclge_mbx.h" 9 #include "hclgevf_cmd.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_MOD_VERSION "1.0" 13 #define HCLGEVF_DRIVER_NAME "hclgevf" 14 15 #define HCLGEVF_MISC_VECTOR_NUM 0 16 17 #define HCLGEVF_INVALID_VPORT 0xffff 18 19 /* This number in actual depends upon the total number of VFs 20 * created by physical function. But the maximum number of 21 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 22 */ 23 #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 24 25 #define HCLGEVF_VECTOR_REG_BASE 0x20000 26 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 27 #define HCLGEVF_VECTOR_REG_OFFSET 0x4 28 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 29 30 /* Vector0 interrupt CMDQ event source register(RW) */ 31 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 32 /* CMDQ register bits for RX event(=MBX event) */ 33 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 34 /* RST register bits for RESET event */ 35 #define HCLGEVF_VECTOR0_RST_INT_B 2 36 37 #define HCLGEVF_TQP_RESET_TRY_TIMES 10 38 /* Reset related Registers */ 39 #define HCLGEVF_RST_ING 0x20C00 40 #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 41 #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 42 #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 43 #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 44 #define HCLGEVF_RST_ING_BITS \ 45 (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 46 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 47 48 #define HCLGEVF_RSS_IND_TBL_SIZE 512 49 #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 50 #define HCLGEVF_RSS_KEY_SIZE 40 51 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 52 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 53 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 54 #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 55 #define HCLGEVF_RSS_CFG_TBL_NUM \ 56 (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 57 #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 58 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 59 #define HCLGEVF_D_PORT_BIT BIT(0) 60 #define HCLGEVF_S_PORT_BIT BIT(1) 61 #define HCLGEVF_D_IP_BIT BIT(2) 62 #define HCLGEVF_S_IP_BIT BIT(3) 63 #define HCLGEVF_V_TAG_BIT BIT(4) 64 65 enum hclgevf_evt_cause { 66 HCLGEVF_VECTOR0_EVENT_RST, 67 HCLGEVF_VECTOR0_EVENT_MBX, 68 HCLGEVF_VECTOR0_EVENT_OTHER, 69 }; 70 71 /* states of hclgevf device & tasks */ 72 enum hclgevf_states { 73 /* device states */ 74 HCLGEVF_STATE_DOWN, 75 HCLGEVF_STATE_DISABLED, 76 HCLGEVF_STATE_IRQ_INITED, 77 /* task states */ 78 HCLGEVF_STATE_SERVICE_SCHED, 79 HCLGEVF_STATE_RST_SERVICE_SCHED, 80 HCLGEVF_STATE_RST_HANDLING, 81 HCLGEVF_STATE_MBX_SERVICE_SCHED, 82 HCLGEVF_STATE_MBX_HANDLING, 83 HCLGEVF_STATE_CMD_DISABLE, 84 }; 85 86 #define HCLGEVF_MPF_ENBALE 1 87 88 struct hclgevf_mac { 89 u8 media_type; 90 u8 mac_addr[ETH_ALEN]; 91 int link; 92 u8 duplex; 93 u32 speed; 94 }; 95 96 struct hclgevf_hw { 97 void __iomem *io_base; 98 int num_vec; 99 struct hclgevf_cmq cmq; 100 struct hclgevf_mac mac; 101 void *hdev; /* hchgevf device it is part of */ 102 }; 103 104 /* TQP stats */ 105 struct hlcgevf_tqp_stats { 106 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 107 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 108 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 109 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 110 }; 111 112 struct hclgevf_tqp { 113 struct device *dev; /* device for DMA mapping */ 114 struct hnae3_queue q; 115 struct hlcgevf_tqp_stats tqp_stats; 116 u16 index; /* global index in a NIC controller */ 117 118 bool alloced; 119 }; 120 121 struct hclgevf_cfg { 122 u8 vmdq_vport_num; 123 u8 tc_num; 124 u16 tqp_desc_num; 125 u16 rx_buf_len; 126 u8 phy_addr; 127 u8 media_type; 128 u8 mac_addr[ETH_ALEN]; 129 u32 numa_node_map; 130 }; 131 132 struct hclgevf_rss_tuple_cfg { 133 u8 ipv4_tcp_en; 134 u8 ipv4_udp_en; 135 u8 ipv4_sctp_en; 136 u8 ipv4_fragment_en; 137 u8 ipv6_tcp_en; 138 u8 ipv6_udp_en; 139 u8 ipv6_sctp_en; 140 u8 ipv6_fragment_en; 141 }; 142 143 struct hclgevf_rss_cfg { 144 u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 145 u32 hash_algo; 146 u32 rss_size; 147 u8 hw_tc_map; 148 u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 149 struct hclgevf_rss_tuple_cfg rss_tuple_sets; 150 }; 151 152 struct hclgevf_misc_vector { 153 u8 __iomem *addr; 154 int vector_irq; 155 }; 156 157 struct hclgevf_dev { 158 struct pci_dev *pdev; 159 struct hnae3_ae_dev *ae_dev; 160 struct hclgevf_hw hw; 161 struct hclgevf_misc_vector misc_vector; 162 struct hclgevf_rss_cfg rss_cfg; 163 unsigned long state; 164 unsigned long flr_state; 165 unsigned long default_reset_request; 166 unsigned long last_reset_time; 167 enum hnae3_reset_type reset_level; 168 unsigned long reset_pending; 169 enum hnae3_reset_type reset_type; 170 171 #define HCLGEVF_RESET_REQUESTED 0 172 #define HCLGEVF_RESET_PENDING 1 173 unsigned long reset_state; /* requested, pending */ 174 unsigned long reset_count; /* the number of reset has been done */ 175 u32 reset_attempts; 176 177 u32 fw_version; 178 u16 num_tqps; /* num task queue pairs of this PF */ 179 180 u16 alloc_rss_size; /* allocated RSS task queue */ 181 u16 rss_size_max; /* HW defined max RSS task queue */ 182 183 u16 num_alloc_vport; /* num vports this driver supports */ 184 u32 numa_node_mask; 185 u16 rx_buf_len; 186 u16 num_desc; 187 u8 hw_tc_map; 188 189 u16 num_msi; 190 u16 num_msi_left; 191 u16 num_msi_used; 192 u16 num_roce_msix; /* Num of roce vectors for this VF */ 193 u16 roce_base_msix_offset; 194 int roce_base_vector; 195 u32 base_msi_vector; 196 u16 *vector_status; 197 int *vector_irq; 198 199 bool mbx_event_pending; 200 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 201 struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 202 203 struct timer_list service_timer; 204 struct timer_list keep_alive_timer; 205 struct work_struct service_task; 206 struct work_struct keep_alive_task; 207 struct work_struct rst_service_task; 208 struct work_struct mbx_service_task; 209 210 struct hclgevf_tqp *htqp; 211 212 struct hnae3_handle nic; 213 struct hnae3_handle roce; 214 215 struct hnae3_client *nic_client; 216 struct hnae3_client *roce_client; 217 u32 flag; 218 }; 219 220 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 221 { 222 return !!hdev->reset_pending; 223 } 224 225 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 226 const u8 *msg_data, u8 msg_len, bool need_resp, 227 u8 *resp_data, u16 resp_len); 228 void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 229 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 230 231 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 232 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 233 u8 duplex); 234 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 235 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 236 #endif 237