1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_MAIN_H 5 #define __HCLGEVF_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include "hclge_mbx.h" 9 #include "hclgevf_cmd.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_MOD_VERSION "1.0" 13 #define HCLGEVF_DRIVER_NAME "hclgevf" 14 15 #define HCLGEVF_MISC_VECTOR_NUM 0 16 17 #define HCLGEVF_INVALID_VPORT 0xffff 18 19 /* This number in actual depends upon the total number of VFs 20 * created by physical function. But the maximum number of 21 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 22 */ 23 #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 24 25 #define HCLGEVF_VECTOR_REG_BASE 0x20000 26 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 27 #define HCLGEVF_VECTOR_REG_OFFSET 0x4 28 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 29 30 /* Vector0 interrupt CMDQ event source register(RW) */ 31 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 32 /* CMDQ register bits for RX event(=MBX event) */ 33 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 34 35 #define HCLGEVF_TQP_RESET_TRY_TIMES 10 36 /* Reset related Registers */ 37 #define HCLGEVF_FUN_RST_ING 0x20C00 38 #define HCLGEVF_FUN_RST_ING_B 0 39 40 #define HCLGEVF_RSS_IND_TBL_SIZE 512 41 #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 42 #define HCLGEVF_RSS_KEY_SIZE 40 43 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 44 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 45 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 46 #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 47 #define HCLGEVF_RSS_CFG_TBL_NUM \ 48 (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 49 50 /* states of hclgevf device & tasks */ 51 enum hclgevf_states { 52 /* device states */ 53 HCLGEVF_STATE_DOWN, 54 HCLGEVF_STATE_DISABLED, 55 /* task states */ 56 HCLGEVF_STATE_SERVICE_SCHED, 57 HCLGEVF_STATE_RST_SERVICE_SCHED, 58 HCLGEVF_STATE_RST_HANDLING, 59 HCLGEVF_STATE_MBX_SERVICE_SCHED, 60 HCLGEVF_STATE_MBX_HANDLING, 61 }; 62 63 #define HCLGEVF_MPF_ENBALE 1 64 65 struct hclgevf_mac { 66 u8 media_type; 67 u8 mac_addr[ETH_ALEN]; 68 int link; 69 u8 duplex; 70 u32 speed; 71 }; 72 73 struct hclgevf_hw { 74 void __iomem *io_base; 75 int num_vec; 76 struct hclgevf_cmq cmq; 77 struct hclgevf_mac mac; 78 void *hdev; /* hchgevf device it is part of */ 79 }; 80 81 /* TQP stats */ 82 struct hlcgevf_tqp_stats { 83 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 84 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 85 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 86 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 87 }; 88 89 struct hclgevf_tqp { 90 struct device *dev; /* device for DMA mapping */ 91 struct hnae3_queue q; 92 struct hlcgevf_tqp_stats tqp_stats; 93 u16 index; /* global index in a NIC controller */ 94 95 bool alloced; 96 }; 97 98 struct hclgevf_cfg { 99 u8 vmdq_vport_num; 100 u8 tc_num; 101 u16 tqp_desc_num; 102 u16 rx_buf_len; 103 u8 phy_addr; 104 u8 media_type; 105 u8 mac_addr[ETH_ALEN]; 106 u32 numa_node_map; 107 }; 108 109 struct hclgevf_rss_cfg { 110 u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 111 u32 hash_algo; 112 u32 rss_size; 113 u8 hw_tc_map; 114 u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 115 }; 116 117 struct hclgevf_misc_vector { 118 u8 __iomem *addr; 119 int vector_irq; 120 }; 121 122 struct hclgevf_dev { 123 struct pci_dev *pdev; 124 struct hnae3_ae_dev *ae_dev; 125 struct hclgevf_hw hw; 126 struct hclgevf_misc_vector misc_vector; 127 struct hclgevf_rss_cfg rss_cfg; 128 unsigned long state; 129 130 #define HCLGEVF_RESET_REQUESTED 0 131 #define HCLGEVF_RESET_PENDING 1 132 unsigned long reset_state; /* requested, pending */ 133 u32 reset_attempts; 134 135 u32 fw_version; 136 u16 num_tqps; /* num task queue pairs of this PF */ 137 138 u16 alloc_rss_size; /* allocated RSS task queue */ 139 u16 rss_size_max; /* HW defined max RSS task queue */ 140 141 u16 num_alloc_vport; /* num vports this driver supports */ 142 u32 numa_node_mask; 143 u16 rx_buf_len; 144 u16 num_desc; 145 u8 hw_tc_map; 146 147 u16 num_msi; 148 u16 num_msi_left; 149 u16 num_msi_used; 150 u16 num_roce_msix; /* Num of roce vectors for this VF */ 151 u16 roce_base_msix_offset; 152 int roce_base_vector; 153 u32 base_msi_vector; 154 u16 *vector_status; 155 int *vector_irq; 156 157 bool mbx_event_pending; 158 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 159 struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 160 161 struct timer_list service_timer; 162 struct work_struct service_task; 163 struct work_struct rst_service_task; 164 struct work_struct mbx_service_task; 165 166 struct hclgevf_tqp *htqp; 167 168 struct hnae3_handle nic; 169 struct hnae3_handle roce; 170 171 struct hnae3_client *nic_client; 172 struct hnae3_client *roce_client; 173 u32 flag; 174 }; 175 176 static inline bool hclgevf_dev_ongoing_reset(struct hclgevf_dev *hdev) 177 { 178 return (hdev && 179 (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) && 180 (hdev->nic.reset_level == HNAE3_VF_RESET)); 181 } 182 183 static inline bool hclgevf_dev_ongoing_full_reset(struct hclgevf_dev *hdev) 184 { 185 return (hdev && 186 (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) && 187 (hdev->nic.reset_level == HNAE3_VF_FULL_RESET)); 188 } 189 190 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 191 const u8 *msg_data, u8 msg_len, bool need_resp, 192 u8 *resp_data, u16 resp_len); 193 void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 194 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 195 196 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 197 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 198 u8 duplex); 199 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 200 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 201 #endif 202