1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_MAIN_H 5 #define __HCLGEVF_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include "hclge_mbx.h" 9 #include "hclgevf_cmd.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_MOD_VERSION "1.0" 13 #define HCLGEVF_DRIVER_NAME "hclgevf" 14 15 #define HCLGEVF_MAX_VLAN_ID 4095 16 #define HCLGEVF_MISC_VECTOR_NUM 0 17 18 #define HCLGEVF_INVALID_VPORT 0xffff 19 #define HCLGEVF_GENERAL_TASK_INTERVAL 5 20 #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2 21 22 /* This number in actual depends upon the total number of VFs 23 * created by physical function. But the maximum number of 24 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 25 */ 26 #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 27 28 #define HCLGEVF_VECTOR_REG_BASE 0x20000 29 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 30 #define HCLGEVF_VECTOR_REG_OFFSET 0x4 31 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 32 33 /* bar registers for cmdq */ 34 #define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000 35 #define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004 36 #define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008 37 #define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010 38 #define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014 39 #define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018 40 #define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C 41 #define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020 42 #define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024 43 #define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028 44 #define HCLGEVF_CMDQ_INTR_SRC_REG 0x27100 45 #define HCLGEVF_CMDQ_INTR_STS_REG 0x27104 46 #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 47 #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C 48 49 /* bar registers for common func */ 50 #define HCLGEVF_GRO_EN_REG 0x28000 51 52 /* bar registers for rcb */ 53 #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000 54 #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004 55 #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008 56 #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C 57 #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014 58 #define HCLGEVF_RING_RX_TAIL_REG 0x80018 59 #define HCLGEVF_RING_RX_HEAD_REG 0x8001C 60 #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020 61 #define HCLGEVF_RING_RX_OFFSET_REG 0x80024 62 #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028 63 #define HCLGEVF_RING_RX_STASH_REG 0x80030 64 #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034 65 #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040 66 #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044 67 #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048 68 #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C 69 #define HCLGEVF_RING_TX_TC_REG 0x80050 70 #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054 71 #define HCLGEVF_RING_TX_TAIL_REG 0x80058 72 #define HCLGEVF_RING_TX_HEAD_REG 0x8005C 73 #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060 74 #define HCLGEVF_RING_TX_OFFSET_REG 0x80064 75 #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068 76 #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070 77 #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074 78 #define HCLGEVF_RING_EN_REG 0x80090 79 80 /* bar registers for tqp interrupt */ 81 #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000 82 #define HCLGEVF_TQP_INTR_GL0_REG 0x20100 83 #define HCLGEVF_TQP_INTR_GL1_REG 0x20200 84 #define HCLGEVF_TQP_INTR_GL2_REG 0x20300 85 #define HCLGEVF_TQP_INTR_RL_REG 0x20900 86 87 /* Vector0 interrupt CMDQ event source register(RW) */ 88 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 89 /* CMDQ register bits for RX event(=MBX event) */ 90 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 91 /* RST register bits for RESET event */ 92 #define HCLGEVF_VECTOR0_RST_INT_B 2 93 94 #define HCLGEVF_TQP_RESET_TRY_TIMES 10 95 /* Reset related Registers */ 96 #define HCLGEVF_RST_ING 0x20C00 97 #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 98 #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 99 #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 100 #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 101 #define HCLGEVF_RST_ING_BITS \ 102 (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 103 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 104 105 #define HCLGEVF_RSS_IND_TBL_SIZE 512 106 #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 107 #define HCLGEVF_RSS_KEY_SIZE 40 108 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 109 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 110 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 111 #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 112 #define HCLGEVF_RSS_CFG_TBL_NUM \ 113 (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 114 #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 115 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 116 #define HCLGEVF_D_PORT_BIT BIT(0) 117 #define HCLGEVF_S_PORT_BIT BIT(1) 118 #define HCLGEVF_D_IP_BIT BIT(2) 119 #define HCLGEVF_S_IP_BIT BIT(3) 120 #define HCLGEVF_V_TAG_BIT BIT(4) 121 122 #define HCLGEVF_STATS_TIMER_INTERVAL (36) 123 124 enum hclgevf_evt_cause { 125 HCLGEVF_VECTOR0_EVENT_RST, 126 HCLGEVF_VECTOR0_EVENT_MBX, 127 HCLGEVF_VECTOR0_EVENT_OTHER, 128 }; 129 130 /* states of hclgevf device & tasks */ 131 enum hclgevf_states { 132 /* device states */ 133 HCLGEVF_STATE_DOWN, 134 HCLGEVF_STATE_DISABLED, 135 HCLGEVF_STATE_IRQ_INITED, 136 HCLGEVF_STATE_REMOVING, 137 HCLGEVF_STATE_NIC_REGISTERED, 138 /* task states */ 139 HCLGEVF_STATE_SERVICE_SCHED, 140 HCLGEVF_STATE_RST_SERVICE_SCHED, 141 HCLGEVF_STATE_RST_HANDLING, 142 HCLGEVF_STATE_MBX_SERVICE_SCHED, 143 HCLGEVF_STATE_MBX_HANDLING, 144 HCLGEVF_STATE_CMD_DISABLE, 145 }; 146 147 #define HCLGEVF_MPF_ENBALE 1 148 149 struct hclgevf_mac { 150 u8 media_type; 151 u8 module_type; 152 u8 mac_addr[ETH_ALEN]; 153 int link; 154 u8 duplex; 155 u32 speed; 156 u64 supported; 157 u64 advertising; 158 }; 159 160 struct hclgevf_hw { 161 void __iomem *io_base; 162 int num_vec; 163 struct hclgevf_cmq cmq; 164 struct hclgevf_mac mac; 165 void *hdev; /* hchgevf device it is part of */ 166 }; 167 168 /* TQP stats */ 169 struct hlcgevf_tqp_stats { 170 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 171 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 172 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 173 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 174 }; 175 176 struct hclgevf_tqp { 177 struct device *dev; /* device for DMA mapping */ 178 struct hnae3_queue q; 179 struct hlcgevf_tqp_stats tqp_stats; 180 u16 index; /* global index in a NIC controller */ 181 182 bool alloced; 183 }; 184 185 struct hclgevf_cfg { 186 u8 vmdq_vport_num; 187 u8 tc_num; 188 u16 tqp_desc_num; 189 u16 rx_buf_len; 190 u8 phy_addr; 191 u8 media_type; 192 u8 mac_addr[ETH_ALEN]; 193 u32 numa_node_map; 194 }; 195 196 struct hclgevf_rss_tuple_cfg { 197 u8 ipv4_tcp_en; 198 u8 ipv4_udp_en; 199 u8 ipv4_sctp_en; 200 u8 ipv4_fragment_en; 201 u8 ipv6_tcp_en; 202 u8 ipv6_udp_en; 203 u8 ipv6_sctp_en; 204 u8 ipv6_fragment_en; 205 }; 206 207 struct hclgevf_rss_cfg { 208 u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 209 u32 hash_algo; 210 u32 rss_size; 211 u8 hw_tc_map; 212 u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 213 struct hclgevf_rss_tuple_cfg rss_tuple_sets; 214 }; 215 216 struct hclgevf_misc_vector { 217 u8 __iomem *addr; 218 int vector_irq; 219 }; 220 221 struct hclgevf_rst_stats { 222 u32 rst_cnt; /* the number of reset */ 223 u32 vf_func_rst_cnt; /* the number of VF function reset */ 224 u32 flr_rst_cnt; /* the number of FLR */ 225 u32 vf_rst_cnt; /* the number of VF reset */ 226 u32 rst_done_cnt; /* the number of reset completed */ 227 u32 hw_rst_done_cnt; /* the number of HW reset completed */ 228 }; 229 230 struct hclgevf_dev { 231 struct pci_dev *pdev; 232 struct hnae3_ae_dev *ae_dev; 233 struct hclgevf_hw hw; 234 struct hclgevf_misc_vector misc_vector; 235 struct hclgevf_rss_cfg rss_cfg; 236 unsigned long state; 237 unsigned long flr_state; 238 unsigned long default_reset_request; 239 unsigned long last_reset_time; 240 enum hnae3_reset_type reset_level; 241 unsigned long reset_pending; 242 enum hnae3_reset_type reset_type; 243 244 #define HCLGEVF_RESET_REQUESTED 0 245 #define HCLGEVF_RESET_PENDING 1 246 unsigned long reset_state; /* requested, pending */ 247 struct hclgevf_rst_stats rst_stats; 248 u32 reset_attempts; 249 250 u32 fw_version; 251 u16 num_tqps; /* num task queue pairs of this PF */ 252 253 u16 alloc_rss_size; /* allocated RSS task queue */ 254 u16 rss_size_max; /* HW defined max RSS task queue */ 255 256 u16 num_alloc_vport; /* num vports this driver supports */ 257 u32 numa_node_mask; 258 u16 rx_buf_len; 259 u16 num_tx_desc; /* desc num of per tx queue */ 260 u16 num_rx_desc; /* desc num of per rx queue */ 261 u8 hw_tc_map; 262 263 u16 num_msi; 264 u16 num_msi_left; 265 u16 num_msi_used; 266 u16 num_roce_msix; /* Num of roce vectors for this VF */ 267 u16 roce_base_msix_offset; 268 int roce_base_vector; 269 u32 base_msi_vector; 270 u16 *vector_status; 271 int *vector_irq; 272 273 bool mbx_event_pending; 274 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 275 struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 276 277 struct timer_list service_timer; 278 struct timer_list keep_alive_timer; 279 struct work_struct service_task; 280 struct work_struct keep_alive_task; 281 struct work_struct rst_service_task; 282 struct work_struct mbx_service_task; 283 284 struct hclgevf_tqp *htqp; 285 286 struct hnae3_handle nic; 287 struct hnae3_handle roce; 288 289 struct hnae3_client *nic_client; 290 struct hnae3_client *roce_client; 291 u32 flag; 292 u32 stats_timer; 293 }; 294 295 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 296 { 297 return !!hdev->reset_pending; 298 } 299 300 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 301 const u8 *msg_data, u8 msg_len, bool need_resp, 302 u8 *resp_data, u16 resp_len); 303 void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 304 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 305 306 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 307 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 308 u8 duplex); 309 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 310 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 311 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 312 u8 *port_base_vlan_info, u8 data_size); 313 #endif 314