1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclgevf_regs.h" 10 #include "hclge_mbx.h" 11 #include "hnae3.h" 12 #include "hclgevf_devlink.h" 13 #include "hclge_comm_rss.h" 14 #include "hclgevf_trace.h" 15 16 #define HCLGEVF_NAME "hclgevf" 17 18 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 19 20 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 21 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 22 unsigned long delay); 23 24 static struct hnae3_ae_algo ae_algovf; 25 26 static struct workqueue_struct *hclgevf_wq; 27 28 static const struct pci_device_id ae_algovf_pci_tbl[] = { 29 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 30 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 31 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 32 /* required last entry */ 33 {0, } 34 }; 35 36 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 37 38 /* hclgevf_cmd_send - send command to command queue 39 * @hw: pointer to the hw struct 40 * @desc: prefilled descriptor for describing the command 41 * @num : the number of descriptors to be sent 42 * 43 * This is the main send command for command queue, it 44 * sends the queue, cleans the queue, etc 45 */ 46 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 47 { 48 return hclge_comm_cmd_send(&hw->hw, desc, num); 49 } 50 51 static void hclgevf_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 52 int num, bool is_special) 53 { 54 int i; 55 56 trace_hclge_vf_cmd_send(hw, desc, 0, num); 57 58 if (is_special) 59 return; 60 61 for (i = 1; i < num; i++) 62 trace_hclge_vf_cmd_send(hw, &desc[i], i, num); 63 } 64 65 static void hclgevf_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, 66 int num, bool is_special) 67 { 68 int i; 69 70 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 71 return; 72 73 trace_hclge_vf_cmd_get(hw, desc, 0, num); 74 75 if (is_special) 76 return; 77 78 for (i = 1; i < num; i++) 79 trace_hclge_vf_cmd_get(hw, &desc[i], i, num); 80 } 81 82 static const struct hclge_comm_cmq_ops hclgevf_cmq_ops = { 83 .trace_cmd_send = hclgevf_trace_cmd_send, 84 .trace_cmd_get = hclgevf_trace_cmd_get, 85 }; 86 87 void hclgevf_arq_init(struct hclgevf_dev *hdev) 88 { 89 struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 90 91 spin_lock(&cmdq->crq.lock); 92 /* initialize the pointers of async rx queue of mailbox */ 93 hdev->arq.hdev = hdev; 94 hdev->arq.head = 0; 95 hdev->arq.tail = 0; 96 atomic_set(&hdev->arq.count, 0); 97 spin_unlock(&cmdq->crq.lock); 98 } 99 100 struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 101 { 102 if (!handle->client) 103 return container_of(handle, struct hclgevf_dev, nic); 104 else if (handle->client->type == HNAE3_CLIENT_ROCE) 105 return container_of(handle, struct hclgevf_dev, roce); 106 else 107 return container_of(handle, struct hclgevf_dev, nic); 108 } 109 110 static void hclgevf_update_stats(struct hnae3_handle *handle) 111 { 112 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 113 int status; 114 115 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 116 if (status) 117 dev_err(&hdev->pdev->dev, 118 "VF update of TQPS stats fail, status = %d.\n", 119 status); 120 } 121 122 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 123 { 124 if (strset == ETH_SS_TEST) 125 return -EOPNOTSUPP; 126 else if (strset == ETH_SS_STATS) 127 return hclge_comm_tqps_get_sset_count(handle); 128 129 return 0; 130 } 131 132 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 133 u8 *data) 134 { 135 u8 *p = (char *)data; 136 137 if (strset == ETH_SS_STATS) 138 p = hclge_comm_tqps_get_strings(handle, p); 139 } 140 141 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 142 { 143 hclge_comm_tqps_get_stats(handle, data); 144 } 145 146 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 147 u8 subcode) 148 { 149 if (msg) { 150 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 151 msg->code = code; 152 msg->subcode = subcode; 153 } 154 } 155 156 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 157 { 158 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 159 u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 160 struct hclge_basic_info *basic_info; 161 struct hclge_vf_to_pf_msg send_msg; 162 unsigned long caps; 163 int status; 164 165 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 166 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 167 sizeof(resp_msg)); 168 if (status) { 169 dev_err(&hdev->pdev->dev, 170 "failed to get basic info from pf, ret = %d", status); 171 return status; 172 } 173 174 basic_info = (struct hclge_basic_info *)resp_msg; 175 176 hdev->hw_tc_map = basic_info->hw_tc_map; 177 hdev->mbx_api_version = le16_to_cpu(basic_info->mbx_api_version); 178 caps = le32_to_cpu(basic_info->pf_caps); 179 if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 180 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 181 182 return 0; 183 } 184 185 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 186 { 187 struct hnae3_handle *nic = &hdev->nic; 188 struct hclge_vf_to_pf_msg send_msg; 189 u8 resp_msg; 190 int ret; 191 192 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 193 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 194 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 195 sizeof(u8)); 196 if (ret) { 197 dev_err(&hdev->pdev->dev, 198 "VF request to get port based vlan state failed %d", 199 ret); 200 return ret; 201 } 202 203 nic->port_base_vlan_state = resp_msg; 204 205 return 0; 206 } 207 208 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 209 { 210 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 211 212 struct hclge_mbx_vf_queue_info *queue_info; 213 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 214 struct hclge_vf_to_pf_msg send_msg; 215 int status; 216 217 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 218 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 219 HCLGEVF_TQPS_RSS_INFO_LEN); 220 if (status) { 221 dev_err(&hdev->pdev->dev, 222 "VF request to get tqp info from PF failed %d", 223 status); 224 return status; 225 } 226 227 queue_info = (struct hclge_mbx_vf_queue_info *)resp_msg; 228 hdev->num_tqps = le16_to_cpu(queue_info->num_tqps); 229 hdev->rss_size_max = le16_to_cpu(queue_info->rss_size); 230 hdev->rx_buf_len = le16_to_cpu(queue_info->rx_buf_len); 231 232 return 0; 233 } 234 235 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 236 { 237 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 238 239 struct hclge_mbx_vf_queue_depth *queue_depth; 240 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 241 struct hclge_vf_to_pf_msg send_msg; 242 int ret; 243 244 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 245 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 246 HCLGEVF_TQPS_DEPTH_INFO_LEN); 247 if (ret) { 248 dev_err(&hdev->pdev->dev, 249 "VF request to get tqp depth info from PF failed %d", 250 ret); 251 return ret; 252 } 253 254 queue_depth = (struct hclge_mbx_vf_queue_depth *)resp_msg; 255 hdev->num_tx_desc = le16_to_cpu(queue_depth->num_tx_desc); 256 hdev->num_rx_desc = le16_to_cpu(queue_depth->num_rx_desc); 257 258 return 0; 259 } 260 261 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 262 { 263 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 264 struct hclge_vf_to_pf_msg send_msg; 265 u16 qid_in_pf = 0; 266 u8 resp_data[2]; 267 int ret; 268 269 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 270 *(__le16 *)send_msg.data = cpu_to_le16(queue_id); 271 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 272 sizeof(resp_data)); 273 if (!ret) 274 qid_in_pf = le16_to_cpu(*(__le16 *)resp_data); 275 276 return qid_in_pf; 277 } 278 279 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 280 { 281 struct hclge_vf_to_pf_msg send_msg; 282 u8 resp_msg[2]; 283 int ret; 284 285 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 286 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 287 sizeof(resp_msg)); 288 if (ret) { 289 dev_err(&hdev->pdev->dev, 290 "VF request to get the pf port media type failed %d", 291 ret); 292 return ret; 293 } 294 295 hdev->hw.mac.media_type = resp_msg[0]; 296 hdev->hw.mac.module_type = resp_msg[1]; 297 298 return 0; 299 } 300 301 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 302 { 303 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 304 struct hclge_comm_tqp *tqp; 305 int i; 306 307 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 308 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 309 if (!hdev->htqp) 310 return -ENOMEM; 311 312 tqp = hdev->htqp; 313 314 for (i = 0; i < hdev->num_tqps; i++) { 315 tqp->dev = &hdev->pdev->dev; 316 tqp->index = i; 317 318 tqp->q.ae_algo = &ae_algovf; 319 tqp->q.buf_size = hdev->rx_buf_len; 320 tqp->q.tx_desc_num = hdev->num_tx_desc; 321 tqp->q.rx_desc_num = hdev->num_rx_desc; 322 323 /* need an extended offset to configure queues >= 324 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 325 */ 326 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 327 tqp->q.io_base = hdev->hw.hw.io_base + 328 HCLGEVF_TQP_REG_OFFSET + 329 i * HCLGEVF_TQP_REG_SIZE; 330 else 331 tqp->q.io_base = hdev->hw.hw.io_base + 332 HCLGEVF_TQP_REG_OFFSET + 333 HCLGEVF_TQP_EXT_REG_OFFSET + 334 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 335 HCLGEVF_TQP_REG_SIZE; 336 337 /* when device supports tx push and has device memory, 338 * the queue can execute push mode or doorbell mode on 339 * device memory. 340 */ 341 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 342 tqp->q.mem_base = hdev->hw.hw.mem_base + 343 HCLGEVF_TQP_MEM_OFFSET(hdev, i); 344 345 tqp++; 346 } 347 348 return 0; 349 } 350 351 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 352 { 353 struct hnae3_handle *nic = &hdev->nic; 354 struct hnae3_knic_private_info *kinfo; 355 u16 new_tqps = hdev->num_tqps; 356 unsigned int i; 357 u8 num_tc = 0; 358 359 kinfo = &nic->kinfo; 360 kinfo->num_tx_desc = hdev->num_tx_desc; 361 kinfo->num_rx_desc = hdev->num_rx_desc; 362 kinfo->rx_buf_len = hdev->rx_buf_len; 363 for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++) 364 if (hdev->hw_tc_map & BIT(i)) 365 num_tc++; 366 367 num_tc = num_tc ? num_tc : 1; 368 kinfo->tc_info.num_tc = num_tc; 369 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 370 new_tqps = kinfo->rss_size * num_tc; 371 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 372 373 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 374 sizeof(struct hnae3_queue *), GFP_KERNEL); 375 if (!kinfo->tqp) 376 return -ENOMEM; 377 378 for (i = 0; i < kinfo->num_tqps; i++) { 379 hdev->htqp[i].q.handle = &hdev->nic; 380 hdev->htqp[i].q.tqp_index = i; 381 kinfo->tqp[i] = &hdev->htqp[i].q; 382 } 383 384 /* after init the max rss_size and tqps, adjust the default tqp numbers 385 * and rss size with the actual vector numbers 386 */ 387 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 388 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 389 kinfo->rss_size); 390 391 return 0; 392 } 393 394 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 395 { 396 struct hclge_vf_to_pf_msg send_msg; 397 int status; 398 399 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 400 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 401 if (status) 402 dev_err(&hdev->pdev->dev, 403 "VF failed to fetch link status(%d) from PF", status); 404 } 405 406 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 407 { 408 struct hnae3_handle *rhandle = &hdev->roce; 409 struct hnae3_handle *handle = &hdev->nic; 410 struct hnae3_client *rclient; 411 struct hnae3_client *client; 412 413 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 414 return; 415 416 client = handle->client; 417 rclient = hdev->roce_client; 418 419 link_state = 420 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 421 if (link_state != hdev->hw.mac.link) { 422 hdev->hw.mac.link = link_state; 423 client->ops->link_status_change(handle, !!link_state); 424 if (rclient && rclient->ops->link_status_change) 425 rclient->ops->link_status_change(rhandle, !!link_state); 426 } 427 428 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 429 } 430 431 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 432 { 433 #define HCLGEVF_ADVERTISING 0 434 #define HCLGEVF_SUPPORTED 1 435 436 struct hclge_vf_to_pf_msg send_msg; 437 438 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 439 send_msg.data[0] = HCLGEVF_ADVERTISING; 440 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 441 send_msg.data[0] = HCLGEVF_SUPPORTED; 442 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 443 } 444 445 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 446 { 447 struct hnae3_handle *nic = &hdev->nic; 448 int ret; 449 450 nic->ae_algo = &ae_algovf; 451 nic->pdev = hdev->pdev; 452 nic->numa_node_mask = hdev->numa_node_mask; 453 nic->flags |= HNAE3_SUPPORT_VF; 454 nic->kinfo.io_base = hdev->hw.hw.io_base; 455 456 ret = hclgevf_knic_setup(hdev); 457 if (ret) 458 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 459 ret); 460 return ret; 461 } 462 463 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 464 { 465 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 466 dev_warn(&hdev->pdev->dev, 467 "vector(vector_id %d) has been freed.\n", vector_id); 468 return; 469 } 470 471 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 472 hdev->num_msi_left += 1; 473 hdev->num_msi_used -= 1; 474 } 475 476 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 477 struct hnae3_vector_info *vector_info) 478 { 479 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 480 struct hnae3_vector_info *vector = vector_info; 481 int alloc = 0; 482 int i, j; 483 484 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 485 vector_num = min(hdev->num_msi_left, vector_num); 486 487 for (j = 0; j < vector_num; j++) { 488 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 489 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 490 vector->vector = pci_irq_vector(hdev->pdev, i); 491 vector->io_addr = hdev->hw.hw.io_base + 492 HCLGEVF_VECTOR_REG_BASE + 493 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 494 hdev->vector_status[i] = 0; 495 hdev->vector_irq[i] = vector->vector; 496 497 vector++; 498 alloc++; 499 500 break; 501 } 502 } 503 } 504 hdev->num_msi_left -= alloc; 505 hdev->num_msi_used += alloc; 506 507 return alloc; 508 } 509 510 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 511 { 512 int i; 513 514 for (i = 0; i < hdev->num_msi; i++) 515 if (vector == hdev->vector_irq[i]) 516 return i; 517 518 return -EINVAL; 519 } 520 521 /* for revision 0x20, vf shared the same rss config with pf */ 522 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 523 { 524 #define HCLGEVF_RSS_MBX_RESP_LEN 8 525 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 526 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 527 struct hclge_vf_to_pf_msg send_msg; 528 u16 msg_num, hash_key_index; 529 u8 index; 530 int ret; 531 532 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 533 msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 534 HCLGEVF_RSS_MBX_RESP_LEN; 535 for (index = 0; index < msg_num; index++) { 536 send_msg.data[0] = index; 537 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 538 HCLGEVF_RSS_MBX_RESP_LEN); 539 if (ret) { 540 dev_err(&hdev->pdev->dev, 541 "VF get rss hash key from PF failed, ret=%d", 542 ret); 543 return ret; 544 } 545 546 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 547 if (index == msg_num - 1) 548 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 549 &resp_msg[0], 550 HCLGE_COMM_RSS_KEY_SIZE - hash_key_index); 551 else 552 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 553 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 554 } 555 556 return 0; 557 } 558 559 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 560 u8 *hfunc) 561 { 562 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 563 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 564 int ret; 565 566 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 567 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 568 } else { 569 if (hfunc) 570 *hfunc = ETH_RSS_HASH_TOP; 571 if (key) { 572 ret = hclgevf_get_rss_hash_key(hdev); 573 if (ret) 574 return ret; 575 memcpy(key, rss_cfg->rss_hash_key, 576 HCLGE_COMM_RSS_KEY_SIZE); 577 } 578 } 579 580 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 581 hdev->ae_dev->dev_specs.rss_ind_tbl_size); 582 583 return 0; 584 } 585 586 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 587 const u8 *key, const u8 hfunc) 588 { 589 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 590 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 591 int ret, i; 592 593 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 594 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, 595 hfunc); 596 if (ret) 597 return ret; 598 } 599 600 /* update the shadow RSS table with user specified qids */ 601 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 602 rss_cfg->rss_indirection_tbl[i] = indir[i]; 603 604 /* update the hardware */ 605 return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 606 rss_cfg->rss_indirection_tbl); 607 } 608 609 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 610 struct ethtool_rxnfc *nfc) 611 { 612 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 613 int ret; 614 615 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 616 return -EOPNOTSUPP; 617 618 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 619 &hdev->rss_cfg, nfc); 620 if (ret) 621 dev_err(&hdev->pdev->dev, 622 "failed to set rss tuple, ret = %d.\n", ret); 623 624 return ret; 625 } 626 627 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 628 struct ethtool_rxnfc *nfc) 629 { 630 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 631 u8 tuple_sets; 632 int ret; 633 634 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 635 return -EOPNOTSUPP; 636 637 nfc->data = 0; 638 639 ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type, 640 &tuple_sets); 641 if (ret || !tuple_sets) 642 return ret; 643 644 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 645 646 return 0; 647 } 648 649 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 650 { 651 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 652 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 653 654 return rss_cfg->rss_size; 655 } 656 657 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 658 int vector_id, 659 struct hnae3_ring_chain_node *ring_chain) 660 { 661 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 662 struct hclge_vf_to_pf_msg send_msg; 663 struct hnae3_ring_chain_node *node; 664 int status; 665 int i = 0; 666 667 memset(&send_msg, 0, sizeof(send_msg)); 668 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 669 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 670 send_msg.vector_id = vector_id; 671 672 for (node = ring_chain; node; node = node->next) { 673 send_msg.param[i].ring_type = 674 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 675 676 send_msg.param[i].tqp_index = node->tqp_index; 677 send_msg.param[i].int_gl_index = 678 hnae3_get_field(node->int_gl_idx, 679 HNAE3_RING_GL_IDX_M, 680 HNAE3_RING_GL_IDX_S); 681 682 i++; 683 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 684 send_msg.ring_num = i; 685 686 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 687 NULL, 0); 688 if (status) { 689 dev_err(&hdev->pdev->dev, 690 "Map TQP fail, status is %d.\n", 691 status); 692 return status; 693 } 694 i = 0; 695 } 696 } 697 698 return 0; 699 } 700 701 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 702 struct hnae3_ring_chain_node *ring_chain) 703 { 704 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 705 int vector_id; 706 707 vector_id = hclgevf_get_vector_index(hdev, vector); 708 if (vector_id < 0) { 709 dev_err(&handle->pdev->dev, 710 "Get vector index fail. ret =%d\n", vector_id); 711 return vector_id; 712 } 713 714 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 715 } 716 717 static int hclgevf_unmap_ring_from_vector( 718 struct hnae3_handle *handle, 719 int vector, 720 struct hnae3_ring_chain_node *ring_chain) 721 { 722 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 723 int ret, vector_id; 724 725 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 726 return 0; 727 728 vector_id = hclgevf_get_vector_index(hdev, vector); 729 if (vector_id < 0) { 730 dev_err(&handle->pdev->dev, 731 "Get vector index fail. ret =%d\n", vector_id); 732 return vector_id; 733 } 734 735 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 736 if (ret) 737 dev_err(&handle->pdev->dev, 738 "Unmap ring from vector fail. vector=%d, ret =%d\n", 739 vector_id, 740 ret); 741 742 return ret; 743 } 744 745 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 746 { 747 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 748 int vector_id; 749 750 vector_id = hclgevf_get_vector_index(hdev, vector); 751 if (vector_id < 0) { 752 dev_err(&handle->pdev->dev, 753 "hclgevf_put_vector get vector index fail. ret =%d\n", 754 vector_id); 755 return vector_id; 756 } 757 758 hclgevf_free_vector(hdev, vector_id); 759 760 return 0; 761 } 762 763 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 764 bool en_uc_pmc, bool en_mc_pmc, 765 bool en_bc_pmc) 766 { 767 struct hnae3_handle *handle = &hdev->nic; 768 struct hclge_vf_to_pf_msg send_msg; 769 int ret; 770 771 memset(&send_msg, 0, sizeof(send_msg)); 772 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 773 send_msg.en_bc = en_bc_pmc ? 1 : 0; 774 send_msg.en_uc = en_uc_pmc ? 1 : 0; 775 send_msg.en_mc = en_mc_pmc ? 1 : 0; 776 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 777 &handle->priv_flags) ? 1 : 0; 778 779 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 780 if (ret) 781 dev_err(&hdev->pdev->dev, 782 "Set promisc mode fail, status is %d.\n", ret); 783 784 return ret; 785 } 786 787 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 788 bool en_mc_pmc) 789 { 790 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 791 bool en_bc_pmc; 792 793 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 794 795 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 796 en_bc_pmc); 797 } 798 799 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 800 { 801 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 802 803 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 804 hclgevf_task_schedule(hdev, 0); 805 } 806 807 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 808 { 809 struct hnae3_handle *handle = &hdev->nic; 810 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 811 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 812 int ret; 813 814 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 815 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 816 if (!ret) 817 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 818 } 819 } 820 821 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 822 u16 stream_id, bool enable) 823 { 824 struct hclgevf_cfg_com_tqp_queue_cmd *req; 825 struct hclge_desc desc; 826 827 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 828 829 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 830 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 831 req->stream_id = cpu_to_le16(stream_id); 832 if (enable) 833 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 834 835 return hclgevf_cmd_send(&hdev->hw, &desc, 1); 836 } 837 838 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 839 { 840 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 841 int ret; 842 u16 i; 843 844 for (i = 0; i < handle->kinfo.num_tqps; i++) { 845 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 846 if (ret) 847 return ret; 848 } 849 850 return 0; 851 } 852 853 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 854 { 855 struct hclge_vf_to_pf_msg send_msg; 856 u8 host_mac[ETH_ALEN]; 857 int status; 858 859 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 860 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 861 ETH_ALEN); 862 if (status) { 863 dev_err(&hdev->pdev->dev, 864 "fail to get VF MAC from host %d", status); 865 return status; 866 } 867 868 ether_addr_copy(p, host_mac); 869 870 return 0; 871 } 872 873 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 874 { 875 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 876 u8 host_mac_addr[ETH_ALEN]; 877 878 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 879 return; 880 881 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 882 if (hdev->has_pf_mac) 883 ether_addr_copy(p, host_mac_addr); 884 else 885 ether_addr_copy(p, hdev->hw.mac.mac_addr); 886 } 887 888 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 889 bool is_first) 890 { 891 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 892 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 893 struct hclge_vf_to_pf_msg send_msg; 894 u8 *new_mac_addr = (u8 *)p; 895 int status; 896 897 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 898 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 899 ether_addr_copy(send_msg.data, new_mac_addr); 900 if (is_first && !hdev->has_pf_mac) 901 eth_zero_addr(&send_msg.data[ETH_ALEN]); 902 else 903 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 904 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 905 if (!status) 906 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 907 908 return status; 909 } 910 911 static struct hclgevf_mac_addr_node * 912 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 913 { 914 struct hclgevf_mac_addr_node *mac_node, *tmp; 915 916 list_for_each_entry_safe(mac_node, tmp, list, node) 917 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 918 return mac_node; 919 920 return NULL; 921 } 922 923 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 924 enum HCLGEVF_MAC_NODE_STATE state) 925 { 926 switch (state) { 927 /* from set_rx_mode or tmp_add_list */ 928 case HCLGEVF_MAC_TO_ADD: 929 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 930 mac_node->state = HCLGEVF_MAC_ACTIVE; 931 break; 932 /* only from set_rx_mode */ 933 case HCLGEVF_MAC_TO_DEL: 934 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 935 list_del(&mac_node->node); 936 kfree(mac_node); 937 } else { 938 mac_node->state = HCLGEVF_MAC_TO_DEL; 939 } 940 break; 941 /* only from tmp_add_list, the mac_node->state won't be 942 * HCLGEVF_MAC_ACTIVE 943 */ 944 case HCLGEVF_MAC_ACTIVE: 945 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 946 mac_node->state = HCLGEVF_MAC_ACTIVE; 947 break; 948 } 949 } 950 951 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 952 enum HCLGEVF_MAC_NODE_STATE state, 953 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 954 const unsigned char *addr) 955 { 956 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 957 struct hclgevf_mac_addr_node *mac_node; 958 struct list_head *list; 959 960 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 961 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 962 963 spin_lock_bh(&hdev->mac_table.mac_list_lock); 964 965 /* if the mac addr is already in the mac list, no need to add a new 966 * one into it, just check the mac addr state, convert it to a new 967 * state, or just remove it, or do nothing. 968 */ 969 mac_node = hclgevf_find_mac_node(list, addr); 970 if (mac_node) { 971 hclgevf_update_mac_node(mac_node, state); 972 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 973 return 0; 974 } 975 /* if this address is never added, unnecessary to delete */ 976 if (state == HCLGEVF_MAC_TO_DEL) { 977 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 978 return -ENOENT; 979 } 980 981 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 982 if (!mac_node) { 983 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 984 return -ENOMEM; 985 } 986 987 mac_node->state = state; 988 ether_addr_copy(mac_node->mac_addr, addr); 989 list_add_tail(&mac_node->node, list); 990 991 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 992 return 0; 993 } 994 995 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 996 const unsigned char *addr) 997 { 998 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 999 HCLGEVF_MAC_ADDR_UC, addr); 1000 } 1001 1002 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1003 const unsigned char *addr) 1004 { 1005 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1006 HCLGEVF_MAC_ADDR_UC, addr); 1007 } 1008 1009 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1010 const unsigned char *addr) 1011 { 1012 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1013 HCLGEVF_MAC_ADDR_MC, addr); 1014 } 1015 1016 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1017 const unsigned char *addr) 1018 { 1019 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1020 HCLGEVF_MAC_ADDR_MC, addr); 1021 } 1022 1023 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1024 struct hclgevf_mac_addr_node *mac_node, 1025 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1026 { 1027 struct hclge_vf_to_pf_msg send_msg; 1028 u8 code, subcode; 1029 1030 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1031 code = HCLGE_MBX_SET_UNICAST; 1032 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1033 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1034 else 1035 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1036 } else { 1037 code = HCLGE_MBX_SET_MULTICAST; 1038 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1039 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1040 else 1041 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1042 } 1043 1044 hclgevf_build_send_msg(&send_msg, code, subcode); 1045 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1046 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1047 } 1048 1049 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1050 struct list_head *list, 1051 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1052 { 1053 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1054 struct hclgevf_mac_addr_node *mac_node, *tmp; 1055 int ret; 1056 1057 list_for_each_entry_safe(mac_node, tmp, list, node) { 1058 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1059 if (ret) { 1060 hnae3_format_mac_addr(format_mac_addr, 1061 mac_node->mac_addr); 1062 dev_err(&hdev->pdev->dev, 1063 "failed to configure mac %s, state = %d, ret = %d\n", 1064 format_mac_addr, mac_node->state, ret); 1065 return; 1066 } 1067 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1068 mac_node->state = HCLGEVF_MAC_ACTIVE; 1069 } else { 1070 list_del(&mac_node->node); 1071 kfree(mac_node); 1072 } 1073 } 1074 } 1075 1076 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1077 struct list_head *mac_list) 1078 { 1079 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1080 1081 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1082 /* if the mac address from tmp_add_list is not in the 1083 * uc/mc_mac_list, it means have received a TO_DEL request 1084 * during the time window of sending mac config request to PF 1085 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1086 * then it will be removed at next time. If is TO_ADD, it means 1087 * send TO_ADD request failed, so just remove the mac node. 1088 */ 1089 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1090 if (new_node) { 1091 hclgevf_update_mac_node(new_node, mac_node->state); 1092 list_del(&mac_node->node); 1093 kfree(mac_node); 1094 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1095 mac_node->state = HCLGEVF_MAC_TO_DEL; 1096 list_move_tail(&mac_node->node, mac_list); 1097 } else { 1098 list_del(&mac_node->node); 1099 kfree(mac_node); 1100 } 1101 } 1102 } 1103 1104 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1105 struct list_head *mac_list) 1106 { 1107 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1108 1109 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1110 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1111 if (new_node) { 1112 /* If the mac addr is exist in the mac list, it means 1113 * received a new request TO_ADD during the time window 1114 * of sending mac addr configurrequest to PF, so just 1115 * change the mac state to ACTIVE. 1116 */ 1117 new_node->state = HCLGEVF_MAC_ACTIVE; 1118 list_del(&mac_node->node); 1119 kfree(mac_node); 1120 } else { 1121 list_move_tail(&mac_node->node, mac_list); 1122 } 1123 } 1124 } 1125 1126 static void hclgevf_clear_list(struct list_head *list) 1127 { 1128 struct hclgevf_mac_addr_node *mac_node, *tmp; 1129 1130 list_for_each_entry_safe(mac_node, tmp, list, node) { 1131 list_del(&mac_node->node); 1132 kfree(mac_node); 1133 } 1134 } 1135 1136 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1137 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1138 { 1139 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1140 struct list_head tmp_add_list, tmp_del_list; 1141 struct list_head *list; 1142 1143 INIT_LIST_HEAD(&tmp_add_list); 1144 INIT_LIST_HEAD(&tmp_del_list); 1145 1146 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1147 * we can add/delete these mac addr outside the spin lock 1148 */ 1149 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1150 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1151 1152 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1153 1154 list_for_each_entry_safe(mac_node, tmp, list, node) { 1155 switch (mac_node->state) { 1156 case HCLGEVF_MAC_TO_DEL: 1157 list_move_tail(&mac_node->node, &tmp_del_list); 1158 break; 1159 case HCLGEVF_MAC_TO_ADD: 1160 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1161 if (!new_node) 1162 goto stop_traverse; 1163 1164 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1165 new_node->state = mac_node->state; 1166 list_add_tail(&new_node->node, &tmp_add_list); 1167 break; 1168 default: 1169 break; 1170 } 1171 } 1172 1173 stop_traverse: 1174 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1175 1176 /* delete first, in order to get max mac table space for adding */ 1177 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1178 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1179 1180 /* if some mac addresses were added/deleted fail, move back to the 1181 * mac_list, and retry at next time. 1182 */ 1183 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1184 1185 hclgevf_sync_from_del_list(&tmp_del_list, list); 1186 hclgevf_sync_from_add_list(&tmp_add_list, list); 1187 1188 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1189 } 1190 1191 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1192 { 1193 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1194 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1195 } 1196 1197 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1198 { 1199 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1200 1201 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1202 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1203 1204 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1205 } 1206 1207 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1208 { 1209 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1210 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1211 struct hclge_vf_to_pf_msg send_msg; 1212 1213 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1214 return -EOPNOTSUPP; 1215 1216 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1217 HCLGE_MBX_ENABLE_VLAN_FILTER); 1218 send_msg.data[0] = enable ? 1 : 0; 1219 1220 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1221 } 1222 1223 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1224 __be16 proto, u16 vlan_id, 1225 bool is_kill) 1226 { 1227 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1228 struct hclge_mbx_vlan_filter *vlan_filter; 1229 struct hclge_vf_to_pf_msg send_msg; 1230 int ret; 1231 1232 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1233 return -EINVAL; 1234 1235 if (proto != htons(ETH_P_8021Q)) 1236 return -EPROTONOSUPPORT; 1237 1238 /* When device is resetting or reset failed, firmware is unable to 1239 * handle mailbox. Just record the vlan id, and remove it after 1240 * reset finished. 1241 */ 1242 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1243 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1244 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1245 return -EBUSY; 1246 } else if (!is_kill && test_bit(vlan_id, hdev->vlan_del_fail_bmap)) { 1247 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1248 } 1249 1250 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1251 HCLGE_MBX_VLAN_FILTER); 1252 vlan_filter = (struct hclge_mbx_vlan_filter *)send_msg.data; 1253 vlan_filter->is_kill = is_kill; 1254 vlan_filter->vlan_id = cpu_to_le16(vlan_id); 1255 vlan_filter->proto = cpu_to_le16(be16_to_cpu(proto)); 1256 1257 /* when remove hw vlan filter failed, record the vlan id, 1258 * and try to remove it from hw later, to be consistence 1259 * with stack. 1260 */ 1261 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1262 if (is_kill && ret) 1263 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1264 1265 return ret; 1266 } 1267 1268 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1269 { 1270 #define HCLGEVF_MAX_SYNC_COUNT 60 1271 struct hnae3_handle *handle = &hdev->nic; 1272 int ret, sync_cnt = 0; 1273 u16 vlan_id; 1274 1275 if (bitmap_empty(hdev->vlan_del_fail_bmap, VLAN_N_VID)) 1276 return; 1277 1278 rtnl_lock(); 1279 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1280 while (vlan_id != VLAN_N_VID) { 1281 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1282 vlan_id, true); 1283 if (ret) 1284 break; 1285 1286 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1287 sync_cnt++; 1288 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1289 break; 1290 1291 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1292 } 1293 rtnl_unlock(); 1294 } 1295 1296 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1297 { 1298 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1299 struct hclge_vf_to_pf_msg send_msg; 1300 1301 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1302 HCLGE_MBX_VLAN_RX_OFF_CFG); 1303 send_msg.data[0] = enable ? 1 : 0; 1304 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1305 } 1306 1307 static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1308 { 1309 #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1310 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1311 struct hclge_vf_to_pf_msg send_msg; 1312 u8 return_status = 0; 1313 int ret; 1314 u16 i; 1315 1316 /* disable vf queue before send queue reset msg to PF */ 1317 ret = hclgevf_tqp_enable(handle, false); 1318 if (ret) { 1319 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 1320 ret); 1321 return ret; 1322 } 1323 1324 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1325 1326 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 1327 sizeof(return_status)); 1328 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 1329 return ret; 1330 1331 for (i = 1; i < handle->kinfo.num_tqps; i++) { 1332 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1333 *(__le16 *)send_msg.data = cpu_to_le16(i); 1334 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1335 if (ret) 1336 return ret; 1337 } 1338 1339 return 0; 1340 } 1341 1342 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1343 { 1344 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1345 struct hclge_mbx_mtu_info *mtu_info; 1346 struct hclge_vf_to_pf_msg send_msg; 1347 1348 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1349 mtu_info = (struct hclge_mbx_mtu_info *)send_msg.data; 1350 mtu_info->mtu = cpu_to_le32(new_mtu); 1351 1352 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1353 } 1354 1355 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1356 enum hnae3_reset_notify_type type) 1357 { 1358 struct hnae3_client *client = hdev->nic_client; 1359 struct hnae3_handle *handle = &hdev->nic; 1360 int ret; 1361 1362 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1363 !client) 1364 return 0; 1365 1366 if (!client->ops->reset_notify) 1367 return -EOPNOTSUPP; 1368 1369 ret = client->ops->reset_notify(handle, type); 1370 if (ret) 1371 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1372 type, ret); 1373 1374 return ret; 1375 } 1376 1377 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1378 enum hnae3_reset_notify_type type) 1379 { 1380 struct hnae3_client *client = hdev->roce_client; 1381 struct hnae3_handle *handle = &hdev->roce; 1382 int ret; 1383 1384 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1385 return 0; 1386 1387 if (!client->ops->reset_notify) 1388 return -EOPNOTSUPP; 1389 1390 ret = client->ops->reset_notify(handle, type); 1391 if (ret) 1392 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1393 type, ret); 1394 return ret; 1395 } 1396 1397 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1398 { 1399 #define HCLGEVF_RESET_WAIT_US 20000 1400 #define HCLGEVF_RESET_WAIT_CNT 2000 1401 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1402 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1403 1404 u32 val; 1405 int ret; 1406 1407 if (hdev->reset_type == HNAE3_VF_RESET) 1408 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1409 HCLGEVF_VF_RST_ING, val, 1410 !(val & HCLGEVF_VF_RST_ING_BIT), 1411 HCLGEVF_RESET_WAIT_US, 1412 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1413 else 1414 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1415 HCLGEVF_RST_ING, val, 1416 !(val & HCLGEVF_RST_ING_BITS), 1417 HCLGEVF_RESET_WAIT_US, 1418 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1419 1420 /* hardware completion status should be available by this time */ 1421 if (ret) { 1422 dev_err(&hdev->pdev->dev, 1423 "couldn't get reset done status from h/w, timeout!\n"); 1424 return ret; 1425 } 1426 1427 /* we will wait a bit more to let reset of the stack to complete. This 1428 * might happen in case reset assertion was made by PF. Yes, this also 1429 * means we might end up waiting bit more even for VF reset. 1430 */ 1431 if (hdev->reset_type == HNAE3_VF_FULL_RESET) 1432 msleep(5000); 1433 else 1434 msleep(500); 1435 1436 return 0; 1437 } 1438 1439 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1440 { 1441 u32 reg_val; 1442 1443 reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 1444 if (enable) 1445 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1446 else 1447 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1448 1449 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 1450 reg_val); 1451 } 1452 1453 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1454 { 1455 int ret; 1456 1457 /* uninitialize the nic client */ 1458 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1459 if (ret) 1460 return ret; 1461 1462 /* re-initialize the hclge device */ 1463 ret = hclgevf_reset_hdev(hdev); 1464 if (ret) { 1465 dev_err(&hdev->pdev->dev, 1466 "hclge device re-init failed, VF is disabled!\n"); 1467 return ret; 1468 } 1469 1470 /* bring up the nic client again */ 1471 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1472 if (ret) 1473 return ret; 1474 1475 /* clear handshake status with IMP */ 1476 hclgevf_reset_handshake(hdev, false); 1477 1478 /* bring up the nic to enable TX/RX again */ 1479 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1480 } 1481 1482 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1483 { 1484 #define HCLGEVF_RESET_SYNC_TIME 100 1485 1486 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1487 struct hclge_vf_to_pf_msg send_msg; 1488 int ret; 1489 1490 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1491 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1492 if (ret) { 1493 dev_err(&hdev->pdev->dev, 1494 "failed to assert VF reset, ret = %d\n", ret); 1495 return ret; 1496 } 1497 hdev->rst_stats.vf_func_rst_cnt++; 1498 } 1499 1500 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1501 /* inform hardware that preparatory work is done */ 1502 msleep(HCLGEVF_RESET_SYNC_TIME); 1503 hclgevf_reset_handshake(hdev, true); 1504 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1505 hdev->reset_type); 1506 1507 return 0; 1508 } 1509 1510 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1511 { 1512 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1513 hdev->rst_stats.vf_func_rst_cnt); 1514 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1515 hdev->rst_stats.flr_rst_cnt); 1516 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1517 hdev->rst_stats.vf_rst_cnt); 1518 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1519 hdev->rst_stats.rst_done_cnt); 1520 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1521 hdev->rst_stats.hw_rst_done_cnt); 1522 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1523 hdev->rst_stats.rst_cnt); 1524 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1525 hdev->rst_stats.rst_fail_cnt); 1526 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1527 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1528 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1529 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 1530 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1531 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 1532 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1533 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1534 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1535 } 1536 1537 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1538 { 1539 /* recover handshake status with IMP when reset fail */ 1540 hclgevf_reset_handshake(hdev, true); 1541 hdev->rst_stats.rst_fail_cnt++; 1542 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1543 hdev->rst_stats.rst_fail_cnt); 1544 1545 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1546 set_bit(hdev->reset_type, &hdev->reset_pending); 1547 1548 if (hclgevf_is_reset_pending(hdev)) { 1549 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1550 hclgevf_reset_task_schedule(hdev); 1551 } else { 1552 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1553 hclgevf_dump_rst_info(hdev); 1554 } 1555 } 1556 1557 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1558 { 1559 int ret; 1560 1561 hdev->rst_stats.rst_cnt++; 1562 1563 /* perform reset of the stack & ae device for a client */ 1564 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1565 if (ret) 1566 return ret; 1567 1568 rtnl_lock(); 1569 /* bring down the nic to stop any ongoing TX/RX */ 1570 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1571 rtnl_unlock(); 1572 if (ret) 1573 return ret; 1574 1575 return hclgevf_reset_prepare_wait(hdev); 1576 } 1577 1578 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1579 { 1580 int ret; 1581 1582 hdev->rst_stats.hw_rst_done_cnt++; 1583 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1584 if (ret) 1585 return ret; 1586 1587 rtnl_lock(); 1588 /* now, re-initialize the nic client and ae device */ 1589 ret = hclgevf_reset_stack(hdev); 1590 rtnl_unlock(); 1591 if (ret) { 1592 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1593 return ret; 1594 } 1595 1596 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1597 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1598 * times 1599 */ 1600 if (ret && 1601 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1602 return ret; 1603 1604 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1605 if (ret) 1606 return ret; 1607 1608 hdev->last_reset_time = jiffies; 1609 hdev->rst_stats.rst_done_cnt++; 1610 hdev->rst_stats.rst_fail_cnt = 0; 1611 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1612 1613 return 0; 1614 } 1615 1616 static void hclgevf_reset(struct hclgevf_dev *hdev) 1617 { 1618 if (hclgevf_reset_prepare(hdev)) 1619 goto err_reset; 1620 1621 /* check if VF could successfully fetch the hardware reset completion 1622 * status from the hardware 1623 */ 1624 if (hclgevf_reset_wait(hdev)) { 1625 /* can't do much in this situation, will disable VF */ 1626 dev_err(&hdev->pdev->dev, 1627 "failed to fetch H/W reset completion status\n"); 1628 goto err_reset; 1629 } 1630 1631 if (hclgevf_reset_rebuild(hdev)) 1632 goto err_reset; 1633 1634 return; 1635 1636 err_reset: 1637 hclgevf_reset_err_handle(hdev); 1638 } 1639 1640 static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr) 1641 { 1642 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1643 1644 /* return the highest priority reset level amongst all */ 1645 if (test_bit(HNAE3_VF_RESET, addr)) { 1646 rst_level = HNAE3_VF_RESET; 1647 clear_bit(HNAE3_VF_RESET, addr); 1648 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1649 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1650 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1651 rst_level = HNAE3_VF_FULL_RESET; 1652 clear_bit(HNAE3_VF_FULL_RESET, addr); 1653 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1654 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1655 rst_level = HNAE3_VF_PF_FUNC_RESET; 1656 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1657 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1658 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1659 rst_level = HNAE3_VF_FUNC_RESET; 1660 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1661 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1662 rst_level = HNAE3_FLR_RESET; 1663 clear_bit(HNAE3_FLR_RESET, addr); 1664 } 1665 1666 return rst_level; 1667 } 1668 1669 static void hclgevf_reset_event(struct pci_dev *pdev, 1670 struct hnae3_handle *handle) 1671 { 1672 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1673 struct hclgevf_dev *hdev = ae_dev->priv; 1674 1675 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1676 1677 if (hdev->default_reset_request) 1678 hdev->reset_level = 1679 hclgevf_get_reset_level(&hdev->default_reset_request); 1680 else 1681 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1682 1683 /* reset of this VF requested */ 1684 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1685 hclgevf_reset_task_schedule(hdev); 1686 1687 hdev->last_reset_time = jiffies; 1688 } 1689 1690 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1691 enum hnae3_reset_type rst_type) 1692 { 1693 struct hclgevf_dev *hdev = ae_dev->priv; 1694 1695 set_bit(rst_type, &hdev->default_reset_request); 1696 } 1697 1698 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1699 { 1700 writel(en ? 1 : 0, vector->addr); 1701 } 1702 1703 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 1704 enum hnae3_reset_type rst_type) 1705 { 1706 #define HCLGEVF_RESET_RETRY_WAIT_MS 500 1707 #define HCLGEVF_RESET_RETRY_CNT 5 1708 1709 struct hclgevf_dev *hdev = ae_dev->priv; 1710 int retry_cnt = 0; 1711 int ret; 1712 1713 while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 1714 down(&hdev->reset_sem); 1715 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1716 hdev->reset_type = rst_type; 1717 ret = hclgevf_reset_prepare(hdev); 1718 if (!ret && !hdev->reset_pending) 1719 break; 1720 1721 dev_err(&hdev->pdev->dev, 1722 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 1723 ret, hdev->reset_pending, retry_cnt); 1724 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1725 up(&hdev->reset_sem); 1726 msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 1727 } 1728 1729 /* disable misc vector before reset done */ 1730 hclgevf_enable_vector(&hdev->misc_vector, false); 1731 1732 if (hdev->reset_type == HNAE3_FLR_RESET) 1733 hdev->rst_stats.flr_rst_cnt++; 1734 } 1735 1736 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 1737 { 1738 struct hclgevf_dev *hdev = ae_dev->priv; 1739 int ret; 1740 1741 hclgevf_enable_vector(&hdev->misc_vector, true); 1742 1743 ret = hclgevf_reset_rebuild(hdev); 1744 if (ret) 1745 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1746 ret); 1747 1748 hdev->reset_type = HNAE3_NONE_RESET; 1749 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1750 up(&hdev->reset_sem); 1751 } 1752 1753 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1754 { 1755 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1756 1757 return hdev->fw_version; 1758 } 1759 1760 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1761 { 1762 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1763 1764 vector->vector_irq = pci_irq_vector(hdev->pdev, 1765 HCLGEVF_MISC_VECTOR_NUM); 1766 vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1767 /* vector status always valid for Vector 0 */ 1768 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1769 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1770 1771 hdev->num_msi_left -= 1; 1772 hdev->num_msi_used += 1; 1773 } 1774 1775 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1776 { 1777 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1778 test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 1779 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1780 &hdev->state)) 1781 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1782 } 1783 1784 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1785 { 1786 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1787 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1788 &hdev->state)) 1789 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1790 } 1791 1792 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1793 unsigned long delay) 1794 { 1795 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1796 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1797 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1798 } 1799 1800 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 1801 { 1802 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1803 1804 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1805 return; 1806 1807 down(&hdev->reset_sem); 1808 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1809 1810 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1811 &hdev->reset_state)) { 1812 /* PF has intimated that it is about to reset the hardware. 1813 * We now have to poll & check if hardware has actually 1814 * completed the reset sequence. On hardware reset completion, 1815 * VF needs to reset the client and ae device. 1816 */ 1817 hdev->reset_attempts = 0; 1818 1819 hdev->last_reset_time = jiffies; 1820 hdev->reset_type = 1821 hclgevf_get_reset_level(&hdev->reset_pending); 1822 if (hdev->reset_type != HNAE3_NONE_RESET) 1823 hclgevf_reset(hdev); 1824 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1825 &hdev->reset_state)) { 1826 /* we could be here when either of below happens: 1827 * 1. reset was initiated due to watchdog timeout caused by 1828 * a. IMP was earlier reset and our TX got choked down and 1829 * which resulted in watchdog reacting and inducing VF 1830 * reset. This also means our cmdq would be unreliable. 1831 * b. problem in TX due to other lower layer(example link 1832 * layer not functioning properly etc.) 1833 * 2. VF reset might have been initiated due to some config 1834 * change. 1835 * 1836 * NOTE: Theres no clear way to detect above cases than to react 1837 * to the response of PF for this reset request. PF will ack the 1838 * 1b and 2. cases but we will not get any intimation about 1a 1839 * from PF as cmdq would be in unreliable state i.e. mailbox 1840 * communication between PF and VF would be broken. 1841 * 1842 * if we are never geting into pending state it means either: 1843 * 1. PF is not receiving our request which could be due to IMP 1844 * reset 1845 * 2. PF is screwed 1846 * We cannot do much for 2. but to check first we can try reset 1847 * our PCIe + stack and see if it alleviates the problem. 1848 */ 1849 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1850 /* prepare for full reset of stack + pcie interface */ 1851 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1852 1853 /* "defer" schedule the reset task again */ 1854 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1855 } else { 1856 hdev->reset_attempts++; 1857 1858 set_bit(hdev->reset_level, &hdev->reset_pending); 1859 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1860 } 1861 hclgevf_reset_task_schedule(hdev); 1862 } 1863 1864 hdev->reset_type = HNAE3_NONE_RESET; 1865 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1866 up(&hdev->reset_sem); 1867 } 1868 1869 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1870 { 1871 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1872 return; 1873 1874 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1875 return; 1876 1877 hclgevf_mbx_async_handler(hdev); 1878 1879 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1880 } 1881 1882 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1883 { 1884 struct hclge_vf_to_pf_msg send_msg; 1885 int ret; 1886 1887 if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1888 return; 1889 1890 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 1891 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1892 if (ret) 1893 dev_err(&hdev->pdev->dev, 1894 "VF sends keep alive cmd failed(=%d)\n", ret); 1895 } 1896 1897 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1898 { 1899 unsigned long delta = round_jiffies_relative(HZ); 1900 struct hnae3_handle *handle = &hdev->nic; 1901 1902 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state) || 1903 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1904 return; 1905 1906 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1907 delta = jiffies - hdev->last_serv_processed; 1908 1909 if (delta < round_jiffies_relative(HZ)) { 1910 delta = round_jiffies_relative(HZ) - delta; 1911 goto out; 1912 } 1913 } 1914 1915 hdev->serv_processed_cnt++; 1916 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1917 hclgevf_keep_alive(hdev); 1918 1919 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1920 hdev->last_serv_processed = jiffies; 1921 goto out; 1922 } 1923 1924 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1925 hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 1926 1927 /* VF does not need to request link status when this bit is set, because 1928 * PF will push its link status to VFs when link status changed. 1929 */ 1930 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 1931 hclgevf_request_link_info(hdev); 1932 1933 hclgevf_update_link_mode(hdev); 1934 1935 hclgevf_sync_vlan_filter(hdev); 1936 1937 hclgevf_sync_mac_table(hdev); 1938 1939 hclgevf_sync_promisc_mode(hdev); 1940 1941 hdev->last_serv_processed = jiffies; 1942 1943 out: 1944 hclgevf_task_schedule(hdev, delta); 1945 } 1946 1947 static void hclgevf_service_task(struct work_struct *work) 1948 { 1949 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1950 service_task.work); 1951 1952 hclgevf_reset_service_task(hdev); 1953 hclgevf_mailbox_service_task(hdev); 1954 hclgevf_periodic_service_task(hdev); 1955 1956 /* Handle reset and mbx again in case periodical task delays the 1957 * handling by calling hclgevf_task_schedule() in 1958 * hclgevf_periodic_service_task() 1959 */ 1960 hclgevf_reset_service_task(hdev); 1961 hclgevf_mailbox_service_task(hdev); 1962 } 1963 1964 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1965 { 1966 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 1967 } 1968 1969 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1970 u32 *clearval) 1971 { 1972 u32 val, cmdq_stat_reg, rst_ing_reg; 1973 1974 /* fetch the events from their corresponding regs */ 1975 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1976 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 1977 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1978 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1979 dev_info(&hdev->pdev->dev, 1980 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1981 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1982 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1983 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1984 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1985 hdev->rst_stats.vf_rst_cnt++; 1986 /* set up VF hardware reset status, its PF will clear 1987 * this status when PF has initialized done. 1988 */ 1989 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 1990 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 1991 val | HCLGEVF_VF_RST_ING_BIT); 1992 return HCLGEVF_VECTOR0_EVENT_RST; 1993 } 1994 1995 /* check for vector0 mailbox(=CMDQ RX) event source */ 1996 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1997 /* for revision 0x21, clearing interrupt is writing bit 0 1998 * to the clear register, writing bit 1 means to keep the 1999 * old value. 2000 * for revision 0x20, the clear register is a read & write 2001 * register, so we should just write 0 to the bit we are 2002 * handling, and keep other bits as cmdq_stat_reg. 2003 */ 2004 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2005 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2006 else 2007 *clearval = cmdq_stat_reg & 2008 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2009 2010 return HCLGEVF_VECTOR0_EVENT_MBX; 2011 } 2012 2013 /* print other vector0 event source */ 2014 dev_info(&hdev->pdev->dev, 2015 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2016 cmdq_stat_reg); 2017 2018 return HCLGEVF_VECTOR0_EVENT_OTHER; 2019 } 2020 2021 static void hclgevf_reset_timer(struct timer_list *t) 2022 { 2023 struct hclgevf_dev *hdev = from_timer(hdev, t, reset_timer); 2024 2025 hclgevf_clear_event_cause(hdev, HCLGEVF_VECTOR0_EVENT_RST); 2026 hclgevf_reset_task_schedule(hdev); 2027 } 2028 2029 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2030 { 2031 #define HCLGEVF_RESET_DELAY 5 2032 2033 enum hclgevf_evt_cause event_cause; 2034 struct hclgevf_dev *hdev = data; 2035 u32 clearval; 2036 2037 hclgevf_enable_vector(&hdev->misc_vector, false); 2038 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2039 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2040 hclgevf_clear_event_cause(hdev, clearval); 2041 2042 switch (event_cause) { 2043 case HCLGEVF_VECTOR0_EVENT_RST: 2044 mod_timer(&hdev->reset_timer, 2045 jiffies + msecs_to_jiffies(HCLGEVF_RESET_DELAY)); 2046 break; 2047 case HCLGEVF_VECTOR0_EVENT_MBX: 2048 hclgevf_mbx_handler(hdev); 2049 break; 2050 default: 2051 break; 2052 } 2053 2054 hclgevf_enable_vector(&hdev->misc_vector, true); 2055 2056 return IRQ_HANDLED; 2057 } 2058 2059 static int hclgevf_configure(struct hclgevf_dev *hdev) 2060 { 2061 int ret; 2062 2063 hdev->gro_en = true; 2064 2065 ret = hclgevf_get_basic_info(hdev); 2066 if (ret) 2067 return ret; 2068 2069 /* get current port based vlan state from PF */ 2070 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2071 if (ret) 2072 return ret; 2073 2074 /* get queue configuration from PF */ 2075 ret = hclgevf_get_queue_info(hdev); 2076 if (ret) 2077 return ret; 2078 2079 /* get queue depth info from PF */ 2080 ret = hclgevf_get_queue_depth(hdev); 2081 if (ret) 2082 return ret; 2083 2084 return hclgevf_get_pf_media_type(hdev); 2085 } 2086 2087 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2088 { 2089 struct pci_dev *pdev = ae_dev->pdev; 2090 struct hclgevf_dev *hdev; 2091 2092 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2093 if (!hdev) 2094 return -ENOMEM; 2095 2096 hdev->pdev = pdev; 2097 hdev->ae_dev = ae_dev; 2098 ae_dev->priv = hdev; 2099 2100 return 0; 2101 } 2102 2103 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2104 { 2105 struct hnae3_handle *roce = &hdev->roce; 2106 struct hnae3_handle *nic = &hdev->nic; 2107 2108 roce->rinfo.num_vectors = hdev->num_roce_msix; 2109 2110 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2111 hdev->num_msi_left == 0) 2112 return -EINVAL; 2113 2114 roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2115 2116 roce->rinfo.netdev = nic->kinfo.netdev; 2117 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2118 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2119 2120 roce->pdev = nic->pdev; 2121 roce->ae_algo = nic->ae_algo; 2122 roce->numa_node_mask = nic->numa_node_mask; 2123 2124 return 0; 2125 } 2126 2127 static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2128 { 2129 struct hclgevf_cfg_gro_status_cmd *req; 2130 struct hclge_desc desc; 2131 int ret; 2132 2133 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 2134 return 0; 2135 2136 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, 2137 false); 2138 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2139 2140 req->gro_en = hdev->gro_en ? 1 : 0; 2141 2142 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2143 if (ret) 2144 dev_err(&hdev->pdev->dev, 2145 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2146 2147 return ret; 2148 } 2149 2150 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2151 { 2152 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 2153 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 2154 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 2155 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 2156 int ret; 2157 2158 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2159 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, 2160 rss_cfg->rss_algo, 2161 rss_cfg->rss_hash_key); 2162 if (ret) 2163 return ret; 2164 2165 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, rss_cfg); 2166 if (ret) 2167 return ret; 2168 } 2169 2170 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 2171 rss_cfg->rss_indirection_tbl); 2172 if (ret) 2173 return ret; 2174 2175 hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map, 2176 tc_offset, tc_valid, tc_size); 2177 2178 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 2179 tc_valid, tc_size); 2180 } 2181 2182 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2183 { 2184 struct hnae3_handle *nic = &hdev->nic; 2185 int ret; 2186 2187 ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2188 if (ret) { 2189 dev_err(&hdev->pdev->dev, 2190 "failed to enable rx vlan offload, ret = %d\n", ret); 2191 return ret; 2192 } 2193 2194 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2195 false); 2196 } 2197 2198 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2199 { 2200 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2201 2202 unsigned long last = hdev->serv_processed_cnt; 2203 int i = 0; 2204 2205 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2206 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2207 last == hdev->serv_processed_cnt) 2208 usleep_range(1, 1); 2209 } 2210 2211 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2212 { 2213 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2214 2215 if (enable) { 2216 hclgevf_task_schedule(hdev, 0); 2217 } else { 2218 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2219 2220 /* flush memory to make sure DOWN is seen by service task */ 2221 smp_mb__before_atomic(); 2222 hclgevf_flush_link_update(hdev); 2223 } 2224 } 2225 2226 static int hclgevf_ae_start(struct hnae3_handle *handle) 2227 { 2228 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2229 2230 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2231 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2232 2233 hclge_comm_reset_tqp_stats(handle); 2234 2235 hclgevf_request_link_info(hdev); 2236 2237 hclgevf_update_link_mode(hdev); 2238 2239 return 0; 2240 } 2241 2242 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2243 { 2244 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2245 2246 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2247 2248 if (hdev->reset_type != HNAE3_VF_RESET) 2249 hclgevf_reset_tqp(handle); 2250 2251 hclge_comm_reset_tqp_stats(handle); 2252 hclgevf_update_link_status(hdev, 0); 2253 } 2254 2255 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2256 { 2257 #define HCLGEVF_STATE_ALIVE 1 2258 #define HCLGEVF_STATE_NOT_ALIVE 0 2259 2260 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2261 struct hclge_vf_to_pf_msg send_msg; 2262 2263 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2264 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2265 HCLGEVF_STATE_NOT_ALIVE; 2266 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2267 } 2268 2269 static int hclgevf_client_start(struct hnae3_handle *handle) 2270 { 2271 return hclgevf_set_alive(handle, true); 2272 } 2273 2274 static void hclgevf_client_stop(struct hnae3_handle *handle) 2275 { 2276 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2277 int ret; 2278 2279 ret = hclgevf_set_alive(handle, false); 2280 if (ret) 2281 dev_warn(&hdev->pdev->dev, 2282 "%s failed %d\n", __func__, ret); 2283 } 2284 2285 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2286 { 2287 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2288 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2289 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2290 2291 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2292 2293 mutex_init(&hdev->mbx_resp.mbx_mutex); 2294 sema_init(&hdev->reset_sem, 1); 2295 2296 spin_lock_init(&hdev->mac_table.mac_list_lock); 2297 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2298 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2299 2300 /* bring the device down */ 2301 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2302 } 2303 2304 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2305 { 2306 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2307 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2308 2309 if (hdev->service_task.work.func) 2310 cancel_delayed_work_sync(&hdev->service_task); 2311 2312 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2313 } 2314 2315 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2316 { 2317 struct pci_dev *pdev = hdev->pdev; 2318 int vectors; 2319 int i; 2320 2321 if (hnae3_dev_roce_supported(hdev)) 2322 vectors = pci_alloc_irq_vectors(pdev, 2323 hdev->roce_base_msix_offset + 1, 2324 hdev->num_msi, 2325 PCI_IRQ_MSIX); 2326 else 2327 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2328 hdev->num_msi, 2329 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2330 2331 if (vectors < 0) { 2332 dev_err(&pdev->dev, 2333 "failed(%d) to allocate MSI/MSI-X vectors\n", 2334 vectors); 2335 return vectors; 2336 } 2337 if (vectors < hdev->num_msi) 2338 dev_warn(&hdev->pdev->dev, 2339 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2340 hdev->num_msi, vectors); 2341 2342 hdev->num_msi = vectors; 2343 hdev->num_msi_left = vectors; 2344 2345 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2346 sizeof(u16), GFP_KERNEL); 2347 if (!hdev->vector_status) { 2348 pci_free_irq_vectors(pdev); 2349 return -ENOMEM; 2350 } 2351 2352 for (i = 0; i < hdev->num_msi; i++) 2353 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2354 2355 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2356 sizeof(int), GFP_KERNEL); 2357 if (!hdev->vector_irq) { 2358 devm_kfree(&pdev->dev, hdev->vector_status); 2359 pci_free_irq_vectors(pdev); 2360 return -ENOMEM; 2361 } 2362 2363 return 0; 2364 } 2365 2366 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2367 { 2368 struct pci_dev *pdev = hdev->pdev; 2369 2370 devm_kfree(&pdev->dev, hdev->vector_status); 2371 devm_kfree(&pdev->dev, hdev->vector_irq); 2372 pci_free_irq_vectors(pdev); 2373 } 2374 2375 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2376 { 2377 int ret; 2378 2379 hclgevf_get_misc_vector(hdev); 2380 2381 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2382 HCLGEVF_NAME, pci_name(hdev->pdev)); 2383 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2384 0, hdev->misc_vector.name, hdev); 2385 if (ret) { 2386 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2387 hdev->misc_vector.vector_irq); 2388 return ret; 2389 } 2390 2391 hclgevf_clear_event_cause(hdev, 0); 2392 2393 /* enable misc. vector(vector 0) */ 2394 hclgevf_enable_vector(&hdev->misc_vector, true); 2395 2396 return ret; 2397 } 2398 2399 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2400 { 2401 /* disable misc vector(vector 0) */ 2402 hclgevf_enable_vector(&hdev->misc_vector, false); 2403 synchronize_irq(hdev->misc_vector.vector_irq); 2404 free_irq(hdev->misc_vector.vector_irq, hdev); 2405 hclgevf_free_vector(hdev, 0); 2406 } 2407 2408 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2409 { 2410 struct device *dev = &hdev->pdev->dev; 2411 2412 dev_info(dev, "VF info begin:\n"); 2413 2414 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2415 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2416 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2417 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2418 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2419 dev_info(dev, "PF media type of this VF: %u\n", 2420 hdev->hw.mac.media_type); 2421 2422 dev_info(dev, "VF info end.\n"); 2423 } 2424 2425 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2426 struct hnae3_client *client) 2427 { 2428 struct hclgevf_dev *hdev = ae_dev->priv; 2429 int rst_cnt = hdev->rst_stats.rst_cnt; 2430 int ret; 2431 2432 ret = client->ops->init_instance(&hdev->nic); 2433 if (ret) 2434 return ret; 2435 2436 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2437 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2438 rst_cnt != hdev->rst_stats.rst_cnt) { 2439 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2440 2441 client->ops->uninit_instance(&hdev->nic, 0); 2442 return -EBUSY; 2443 } 2444 2445 hnae3_set_client_init_flag(client, ae_dev, 1); 2446 2447 if (netif_msg_drv(&hdev->nic)) 2448 hclgevf_info_show(hdev); 2449 2450 return 0; 2451 } 2452 2453 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2454 struct hnae3_client *client) 2455 { 2456 struct hclgevf_dev *hdev = ae_dev->priv; 2457 int ret; 2458 2459 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2460 !hdev->nic_client) 2461 return 0; 2462 2463 ret = hclgevf_init_roce_base_info(hdev); 2464 if (ret) 2465 return ret; 2466 2467 ret = client->ops->init_instance(&hdev->roce); 2468 if (ret) 2469 return ret; 2470 2471 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2472 hnae3_set_client_init_flag(client, ae_dev, 1); 2473 2474 return 0; 2475 } 2476 2477 static int hclgevf_init_client_instance(struct hnae3_client *client, 2478 struct hnae3_ae_dev *ae_dev) 2479 { 2480 struct hclgevf_dev *hdev = ae_dev->priv; 2481 int ret; 2482 2483 switch (client->type) { 2484 case HNAE3_CLIENT_KNIC: 2485 hdev->nic_client = client; 2486 hdev->nic.client = client; 2487 2488 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2489 if (ret) 2490 goto clear_nic; 2491 2492 ret = hclgevf_init_roce_client_instance(ae_dev, 2493 hdev->roce_client); 2494 if (ret) 2495 goto clear_roce; 2496 2497 break; 2498 case HNAE3_CLIENT_ROCE: 2499 if (hnae3_dev_roce_supported(hdev)) { 2500 hdev->roce_client = client; 2501 hdev->roce.client = client; 2502 } 2503 2504 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2505 if (ret) 2506 goto clear_roce; 2507 2508 break; 2509 default: 2510 return -EINVAL; 2511 } 2512 2513 return 0; 2514 2515 clear_nic: 2516 hdev->nic_client = NULL; 2517 hdev->nic.client = NULL; 2518 return ret; 2519 clear_roce: 2520 hdev->roce_client = NULL; 2521 hdev->roce.client = NULL; 2522 return ret; 2523 } 2524 2525 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2526 struct hnae3_ae_dev *ae_dev) 2527 { 2528 struct hclgevf_dev *hdev = ae_dev->priv; 2529 2530 /* un-init roce, if it exists */ 2531 if (hdev->roce_client) { 2532 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2533 msleep(HCLGEVF_WAIT_RESET_DONE); 2534 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2535 2536 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2537 hdev->roce_client = NULL; 2538 hdev->roce.client = NULL; 2539 } 2540 2541 /* un-init nic/unic, if this was not called by roce client */ 2542 if (client->ops->uninit_instance && hdev->nic_client && 2543 client->type != HNAE3_CLIENT_ROCE) { 2544 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2545 msleep(HCLGEVF_WAIT_RESET_DONE); 2546 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2547 2548 client->ops->uninit_instance(&hdev->nic, 0); 2549 hdev->nic_client = NULL; 2550 hdev->nic.client = NULL; 2551 } 2552 } 2553 2554 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2555 { 2556 struct pci_dev *pdev = hdev->pdev; 2557 struct hclgevf_hw *hw = &hdev->hw; 2558 2559 /* for device does not have device memory, return directly */ 2560 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2561 return 0; 2562 2563 hw->hw.mem_base = 2564 devm_ioremap_wc(&pdev->dev, 2565 pci_resource_start(pdev, HCLGEVF_MEM_BAR), 2566 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2567 if (!hw->hw.mem_base) { 2568 dev_err(&pdev->dev, "failed to map device memory\n"); 2569 return -EFAULT; 2570 } 2571 2572 return 0; 2573 } 2574 2575 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2576 { 2577 struct pci_dev *pdev = hdev->pdev; 2578 struct hclgevf_hw *hw; 2579 int ret; 2580 2581 ret = pci_enable_device(pdev); 2582 if (ret) { 2583 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2584 return ret; 2585 } 2586 2587 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2588 if (ret) { 2589 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2590 goto err_disable_device; 2591 } 2592 2593 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2594 if (ret) { 2595 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2596 goto err_disable_device; 2597 } 2598 2599 pci_set_master(pdev); 2600 hw = &hdev->hw; 2601 hw->hw.io_base = pci_iomap(pdev, 2, 0); 2602 if (!hw->hw.io_base) { 2603 dev_err(&pdev->dev, "can't map configuration register space\n"); 2604 ret = -ENOMEM; 2605 goto err_release_regions; 2606 } 2607 2608 ret = hclgevf_dev_mem_map(hdev); 2609 if (ret) 2610 goto err_unmap_io_base; 2611 2612 return 0; 2613 2614 err_unmap_io_base: 2615 pci_iounmap(pdev, hdev->hw.hw.io_base); 2616 err_release_regions: 2617 pci_release_regions(pdev); 2618 err_disable_device: 2619 pci_disable_device(pdev); 2620 2621 return ret; 2622 } 2623 2624 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2625 { 2626 struct pci_dev *pdev = hdev->pdev; 2627 2628 if (hdev->hw.hw.mem_base) 2629 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 2630 2631 pci_iounmap(pdev, hdev->hw.hw.io_base); 2632 pci_release_regions(pdev); 2633 pci_disable_device(pdev); 2634 } 2635 2636 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2637 { 2638 struct hclgevf_query_res_cmd *req; 2639 struct hclge_desc desc; 2640 int ret; 2641 2642 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true); 2643 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2644 if (ret) { 2645 dev_err(&hdev->pdev->dev, 2646 "query vf resource failed, ret = %d.\n", ret); 2647 return ret; 2648 } 2649 2650 req = (struct hclgevf_query_res_cmd *)desc.data; 2651 2652 if (hnae3_dev_roce_supported(hdev)) { 2653 hdev->roce_base_msix_offset = 2654 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 2655 HCLGEVF_MSIX_OFT_ROCEE_M, 2656 HCLGEVF_MSIX_OFT_ROCEE_S); 2657 hdev->num_roce_msix = 2658 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2659 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2660 2661 /* nic's msix numbers is always equals to the roce's. */ 2662 hdev->num_nic_msix = hdev->num_roce_msix; 2663 2664 /* VF should have NIC vectors and Roce vectors, NIC vectors 2665 * are queued before Roce vectors. The offset is fixed to 64. 2666 */ 2667 hdev->num_msi = hdev->num_roce_msix + 2668 hdev->roce_base_msix_offset; 2669 } else { 2670 hdev->num_msi = 2671 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2672 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2673 2674 hdev->num_nic_msix = hdev->num_msi; 2675 } 2676 2677 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2678 dev_err(&hdev->pdev->dev, 2679 "Just %u msi resources, not enough for vf(min:2).\n", 2680 hdev->num_nic_msix); 2681 return -EINVAL; 2682 } 2683 2684 return 0; 2685 } 2686 2687 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2688 { 2689 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2690 2691 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2692 2693 ae_dev->dev_specs.max_non_tso_bd_num = 2694 HCLGEVF_MAX_NON_TSO_BD_NUM; 2695 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2696 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2697 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2698 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2699 } 2700 2701 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 2702 struct hclge_desc *desc) 2703 { 2704 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2705 struct hclgevf_dev_specs_0_cmd *req0; 2706 struct hclgevf_dev_specs_1_cmd *req1; 2707 2708 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 2709 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 2710 2711 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 2712 ae_dev->dev_specs.rss_ind_tbl_size = 2713 le16_to_cpu(req0->rss_ind_tbl_size); 2714 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 2715 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 2716 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 2717 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 2718 } 2719 2720 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 2721 { 2722 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 2723 2724 if (!dev_specs->max_non_tso_bd_num) 2725 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 2726 if (!dev_specs->rss_ind_tbl_size) 2727 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2728 if (!dev_specs->rss_key_size) 2729 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2730 if (!dev_specs->max_int_gl) 2731 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2732 if (!dev_specs->max_frm_size) 2733 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2734 } 2735 2736 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 2737 { 2738 struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 2739 int ret; 2740 int i; 2741 2742 /* set default specifications as devices lower than version V3 do not 2743 * support querying specifications from firmware. 2744 */ 2745 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 2746 hclgevf_set_default_dev_specs(hdev); 2747 return 0; 2748 } 2749 2750 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2751 hclgevf_cmd_setup_basic_desc(&desc[i], 2752 HCLGE_OPC_QUERY_DEV_SPECS, true); 2753 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2754 } 2755 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 2756 2757 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 2758 if (ret) 2759 return ret; 2760 2761 hclgevf_parse_dev_specs(hdev, desc); 2762 hclgevf_check_dev_specs(hdev); 2763 2764 return 0; 2765 } 2766 2767 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2768 { 2769 struct pci_dev *pdev = hdev->pdev; 2770 int ret = 0; 2771 2772 if ((hdev->reset_type == HNAE3_VF_FULL_RESET || 2773 hdev->reset_type == HNAE3_FLR_RESET) && 2774 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2775 hclgevf_misc_irq_uninit(hdev); 2776 hclgevf_uninit_msi(hdev); 2777 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2778 } 2779 2780 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2781 pci_set_master(pdev); 2782 ret = hclgevf_init_msi(hdev); 2783 if (ret) { 2784 dev_err(&pdev->dev, 2785 "failed(%d) to init MSI/MSI-X\n", ret); 2786 return ret; 2787 } 2788 2789 ret = hclgevf_misc_irq_init(hdev); 2790 if (ret) { 2791 hclgevf_uninit_msi(hdev); 2792 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2793 ret); 2794 return ret; 2795 } 2796 2797 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2798 } 2799 2800 return ret; 2801 } 2802 2803 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2804 { 2805 struct hclge_vf_to_pf_msg send_msg; 2806 2807 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2808 HCLGE_MBX_VPORT_LIST_CLEAR); 2809 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2810 } 2811 2812 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 2813 { 2814 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2815 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 2816 } 2817 2818 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 2819 { 2820 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2821 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 2822 } 2823 2824 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2825 { 2826 struct pci_dev *pdev = hdev->pdev; 2827 int ret; 2828 2829 ret = hclgevf_pci_reset(hdev); 2830 if (ret) { 2831 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2832 return ret; 2833 } 2834 2835 hclgevf_arq_init(hdev); 2836 2837 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2838 &hdev->fw_version, false, 2839 hdev->reset_pending); 2840 if (ret) { 2841 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2842 return ret; 2843 } 2844 2845 ret = hclgevf_rss_init_hw(hdev); 2846 if (ret) { 2847 dev_err(&hdev->pdev->dev, 2848 "failed(%d) to initialize RSS\n", ret); 2849 return ret; 2850 } 2851 2852 ret = hclgevf_config_gro(hdev); 2853 if (ret) 2854 return ret; 2855 2856 ret = hclgevf_init_vlan_config(hdev); 2857 if (ret) { 2858 dev_err(&hdev->pdev->dev, 2859 "failed(%d) to initialize VLAN config\n", ret); 2860 return ret; 2861 } 2862 2863 /* get current port based vlan state from PF */ 2864 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2865 if (ret) 2866 return ret; 2867 2868 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 2869 2870 hclgevf_init_rxd_adv_layout(hdev); 2871 2872 dev_info(&hdev->pdev->dev, "Reset done\n"); 2873 2874 return 0; 2875 } 2876 2877 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2878 { 2879 struct pci_dev *pdev = hdev->pdev; 2880 int ret; 2881 2882 ret = hclgevf_pci_init(hdev); 2883 if (ret) 2884 return ret; 2885 2886 ret = hclgevf_devlink_init(hdev); 2887 if (ret) 2888 goto err_devlink_init; 2889 2890 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 2891 if (ret) 2892 goto err_cmd_queue_init; 2893 2894 hclgevf_arq_init(hdev); 2895 2896 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclgevf_cmq_ops); 2897 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2898 &hdev->fw_version, false, 2899 hdev->reset_pending); 2900 if (ret) 2901 goto err_cmd_init; 2902 2903 /* Get vf resource */ 2904 ret = hclgevf_query_vf_resource(hdev); 2905 if (ret) 2906 goto err_cmd_init; 2907 2908 ret = hclgevf_query_dev_specs(hdev); 2909 if (ret) { 2910 dev_err(&pdev->dev, 2911 "failed to query dev specifications, ret = %d\n", ret); 2912 goto err_cmd_init; 2913 } 2914 2915 ret = hclgevf_init_msi(hdev); 2916 if (ret) { 2917 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2918 goto err_cmd_init; 2919 } 2920 2921 hclgevf_state_init(hdev); 2922 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2923 hdev->reset_type = HNAE3_NONE_RESET; 2924 2925 ret = hclgevf_misc_irq_init(hdev); 2926 if (ret) 2927 goto err_misc_irq_init; 2928 2929 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2930 2931 ret = hclgevf_configure(hdev); 2932 if (ret) { 2933 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2934 goto err_config; 2935 } 2936 2937 ret = hclgevf_alloc_tqps(hdev); 2938 if (ret) { 2939 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2940 goto err_config; 2941 } 2942 2943 ret = hclgevf_set_handle_info(hdev); 2944 if (ret) 2945 goto err_config; 2946 2947 ret = hclgevf_config_gro(hdev); 2948 if (ret) 2949 goto err_config; 2950 2951 /* Initialize RSS for this VF */ 2952 ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev, 2953 &hdev->rss_cfg); 2954 if (ret) { 2955 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 2956 goto err_config; 2957 } 2958 2959 ret = hclgevf_rss_init_hw(hdev); 2960 if (ret) { 2961 dev_err(&hdev->pdev->dev, 2962 "failed(%d) to initialize RSS\n", ret); 2963 goto err_config; 2964 } 2965 2966 /* ensure vf tbl list as empty before init */ 2967 ret = hclgevf_clear_vport_list(hdev); 2968 if (ret) { 2969 dev_err(&pdev->dev, 2970 "failed to clear tbl list configuration, ret = %d.\n", 2971 ret); 2972 goto err_config; 2973 } 2974 2975 ret = hclgevf_init_vlan_config(hdev); 2976 if (ret) { 2977 dev_err(&hdev->pdev->dev, 2978 "failed(%d) to initialize VLAN config\n", ret); 2979 goto err_config; 2980 } 2981 2982 hclgevf_init_rxd_adv_layout(hdev); 2983 2984 set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 2985 2986 hdev->last_reset_time = jiffies; 2987 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2988 HCLGEVF_DRIVER_NAME); 2989 2990 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2991 timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0); 2992 2993 return 0; 2994 2995 err_config: 2996 hclgevf_misc_irq_uninit(hdev); 2997 err_misc_irq_init: 2998 hclgevf_state_uninit(hdev); 2999 hclgevf_uninit_msi(hdev); 3000 err_cmd_init: 3001 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3002 err_cmd_queue_init: 3003 hclgevf_devlink_uninit(hdev); 3004 err_devlink_init: 3005 hclgevf_pci_uninit(hdev); 3006 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3007 return ret; 3008 } 3009 3010 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3011 { 3012 struct hclge_vf_to_pf_msg send_msg; 3013 3014 hclgevf_state_uninit(hdev); 3015 hclgevf_uninit_rxd_adv_layout(hdev); 3016 3017 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3018 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3019 3020 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3021 hclgevf_misc_irq_uninit(hdev); 3022 hclgevf_uninit_msi(hdev); 3023 } 3024 3025 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3026 hclgevf_devlink_uninit(hdev); 3027 hclgevf_pci_uninit(hdev); 3028 hclgevf_uninit_mac_list(hdev); 3029 } 3030 3031 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3032 { 3033 struct pci_dev *pdev = ae_dev->pdev; 3034 int ret; 3035 3036 ret = hclgevf_alloc_hdev(ae_dev); 3037 if (ret) { 3038 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3039 return ret; 3040 } 3041 3042 ret = hclgevf_init_hdev(ae_dev->priv); 3043 if (ret) { 3044 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3045 return ret; 3046 } 3047 3048 return 0; 3049 } 3050 3051 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3052 { 3053 struct hclgevf_dev *hdev = ae_dev->priv; 3054 3055 hclgevf_uninit_hdev(hdev); 3056 ae_dev->priv = NULL; 3057 } 3058 3059 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3060 { 3061 struct hnae3_handle *nic = &hdev->nic; 3062 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3063 3064 return min_t(u32, hdev->rss_size_max, 3065 hdev->num_tqps / kinfo->tc_info.num_tc); 3066 } 3067 3068 /** 3069 * hclgevf_get_channels - Get the current channels enabled and max supported. 3070 * @handle: hardware information for network interface 3071 * @ch: ethtool channels structure 3072 * 3073 * We don't support separate tx and rx queues as channels. The other count 3074 * represents how many queues are being used for control. max_combined counts 3075 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3076 * q_vectors since we support a lot more queue pairs than q_vectors. 3077 **/ 3078 static void hclgevf_get_channels(struct hnae3_handle *handle, 3079 struct ethtool_channels *ch) 3080 { 3081 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3082 3083 ch->max_combined = hclgevf_get_max_channels(hdev); 3084 ch->other_count = 0; 3085 ch->max_other = 0; 3086 ch->combined_count = handle->kinfo.rss_size; 3087 } 3088 3089 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3090 u16 *alloc_tqps, u16 *max_rss_size) 3091 { 3092 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3093 3094 *alloc_tqps = hdev->num_tqps; 3095 *max_rss_size = hdev->rss_size_max; 3096 } 3097 3098 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3099 u32 new_tqps_num) 3100 { 3101 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3102 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3103 u16 max_rss_size; 3104 3105 kinfo->req_rss_size = new_tqps_num; 3106 3107 max_rss_size = min_t(u16, hdev->rss_size_max, 3108 hdev->num_tqps / kinfo->tc_info.num_tc); 3109 3110 /* Use the user's configuration when it is not larger than 3111 * max_rss_size, otherwise, use the maximum specification value. 3112 */ 3113 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3114 kinfo->req_rss_size <= max_rss_size) 3115 kinfo->rss_size = kinfo->req_rss_size; 3116 else if (kinfo->rss_size > max_rss_size || 3117 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3118 kinfo->rss_size = max_rss_size; 3119 3120 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3121 } 3122 3123 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3124 bool rxfh_configured) 3125 { 3126 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3127 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3128 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 3129 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 3130 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 3131 u16 cur_rss_size = kinfo->rss_size; 3132 u16 cur_tqps = kinfo->num_tqps; 3133 u32 *rss_indir; 3134 unsigned int i; 3135 int ret; 3136 3137 hclgevf_update_rss_size(handle, new_tqps_num); 3138 3139 hclge_comm_get_rss_tc_info(kinfo->rss_size, hdev->hw_tc_map, 3140 tc_offset, tc_valid, tc_size); 3141 ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 3142 tc_valid, tc_size); 3143 if (ret) 3144 return ret; 3145 3146 /* RSS indirection table has been configured by user */ 3147 if (rxfh_configured) 3148 goto out; 3149 3150 /* Reinitializes the rss indirect table according to the new RSS size */ 3151 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3152 sizeof(u32), GFP_KERNEL); 3153 if (!rss_indir) 3154 return -ENOMEM; 3155 3156 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3157 rss_indir[i] = i % kinfo->rss_size; 3158 3159 hdev->rss_cfg.rss_size = kinfo->rss_size; 3160 3161 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3162 if (ret) 3163 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3164 ret); 3165 3166 kfree(rss_indir); 3167 3168 out: 3169 if (!ret) 3170 dev_info(&hdev->pdev->dev, 3171 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3172 cur_rss_size, kinfo->rss_size, 3173 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3174 3175 return ret; 3176 } 3177 3178 static int hclgevf_get_status(struct hnae3_handle *handle) 3179 { 3180 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3181 3182 return hdev->hw.mac.link; 3183 } 3184 3185 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3186 u8 *auto_neg, u32 *speed, 3187 u8 *duplex, u32 *lane_num) 3188 { 3189 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3190 3191 if (speed) 3192 *speed = hdev->hw.mac.speed; 3193 if (duplex) 3194 *duplex = hdev->hw.mac.duplex; 3195 if (auto_neg) 3196 *auto_neg = AUTONEG_DISABLE; 3197 } 3198 3199 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3200 u8 duplex) 3201 { 3202 hdev->hw.mac.speed = speed; 3203 hdev->hw.mac.duplex = duplex; 3204 } 3205 3206 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3207 { 3208 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3209 bool gro_en_old = hdev->gro_en; 3210 int ret; 3211 3212 hdev->gro_en = enable; 3213 ret = hclgevf_config_gro(hdev); 3214 if (ret) 3215 hdev->gro_en = gro_en_old; 3216 3217 return ret; 3218 } 3219 3220 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3221 u8 *module_type) 3222 { 3223 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3224 3225 if (media_type) 3226 *media_type = hdev->hw.mac.media_type; 3227 3228 if (module_type) 3229 *module_type = hdev->hw.mac.module_type; 3230 } 3231 3232 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3233 { 3234 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3235 3236 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3237 } 3238 3239 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3240 { 3241 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3242 3243 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3244 } 3245 3246 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3247 { 3248 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3249 3250 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3251 } 3252 3253 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3254 { 3255 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3256 3257 return hdev->rst_stats.hw_rst_done_cnt; 3258 } 3259 3260 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3261 unsigned long *supported, 3262 unsigned long *advertising) 3263 { 3264 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3265 3266 *supported = hdev->hw.mac.supported; 3267 *advertising = hdev->hw.mac.advertising; 3268 } 3269 3270 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3271 struct hclge_mbx_port_base_vlan *port_base_vlan) 3272 { 3273 struct hnae3_handle *nic = &hdev->nic; 3274 struct hclge_vf_to_pf_msg send_msg; 3275 int ret; 3276 3277 rtnl_lock(); 3278 3279 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3280 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3281 dev_warn(&hdev->pdev->dev, 3282 "is resetting when updating port based vlan info\n"); 3283 rtnl_unlock(); 3284 return; 3285 } 3286 3287 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3288 if (ret) { 3289 rtnl_unlock(); 3290 return; 3291 } 3292 3293 /* send msg to PF and wait update port based vlan info */ 3294 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3295 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3296 memcpy(send_msg.data, port_base_vlan, sizeof(*port_base_vlan)); 3297 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3298 if (!ret) { 3299 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3300 nic->port_base_vlan_state = state; 3301 else 3302 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3303 } 3304 3305 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3306 rtnl_unlock(); 3307 } 3308 3309 static const struct hnae3_ae_ops hclgevf_ops = { 3310 .init_ae_dev = hclgevf_init_ae_dev, 3311 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3312 .reset_prepare = hclgevf_reset_prepare_general, 3313 .reset_done = hclgevf_reset_done, 3314 .init_client_instance = hclgevf_init_client_instance, 3315 .uninit_client_instance = hclgevf_uninit_client_instance, 3316 .start = hclgevf_ae_start, 3317 .stop = hclgevf_ae_stop, 3318 .client_start = hclgevf_client_start, 3319 .client_stop = hclgevf_client_stop, 3320 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3321 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3322 .get_vector = hclgevf_get_vector, 3323 .put_vector = hclgevf_put_vector, 3324 .reset_queue = hclgevf_reset_tqp, 3325 .get_mac_addr = hclgevf_get_mac_addr, 3326 .set_mac_addr = hclgevf_set_mac_addr, 3327 .add_uc_addr = hclgevf_add_uc_addr, 3328 .rm_uc_addr = hclgevf_rm_uc_addr, 3329 .add_mc_addr = hclgevf_add_mc_addr, 3330 .rm_mc_addr = hclgevf_rm_mc_addr, 3331 .get_stats = hclgevf_get_stats, 3332 .update_stats = hclgevf_update_stats, 3333 .get_strings = hclgevf_get_strings, 3334 .get_sset_count = hclgevf_get_sset_count, 3335 .get_rss_key_size = hclge_comm_get_rss_key_size, 3336 .get_rss = hclgevf_get_rss, 3337 .set_rss = hclgevf_set_rss, 3338 .get_rss_tuple = hclgevf_get_rss_tuple, 3339 .set_rss_tuple = hclgevf_set_rss_tuple, 3340 .get_tc_size = hclgevf_get_tc_size, 3341 .get_fw_version = hclgevf_get_fw_version, 3342 .set_vlan_filter = hclgevf_set_vlan_filter, 3343 .enable_vlan_filter = hclgevf_enable_vlan_filter, 3344 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3345 .reset_event = hclgevf_reset_event, 3346 .set_default_reset_request = hclgevf_set_def_reset_request, 3347 .set_channels = hclgevf_set_channels, 3348 .get_channels = hclgevf_get_channels, 3349 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3350 .get_regs_len = hclgevf_get_regs_len, 3351 .get_regs = hclgevf_get_regs, 3352 .get_status = hclgevf_get_status, 3353 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3354 .get_media_type = hclgevf_get_media_type, 3355 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3356 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3357 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3358 .set_gro_en = hclgevf_gro_en, 3359 .set_mtu = hclgevf_set_mtu, 3360 .get_global_queue_id = hclgevf_get_qid_global, 3361 .set_timer_task = hclgevf_set_timer_task, 3362 .get_link_mode = hclgevf_get_link_mode, 3363 .set_promisc_mode = hclgevf_set_promisc_mode, 3364 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3365 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3366 }; 3367 3368 static struct hnae3_ae_algo ae_algovf = { 3369 .ops = &hclgevf_ops, 3370 .pdev_id_table = ae_algovf_pci_tbl, 3371 }; 3372 3373 static int __init hclgevf_init(void) 3374 { 3375 pr_info("%s is initializing\n", HCLGEVF_NAME); 3376 3377 hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 3378 if (!hclgevf_wq) { 3379 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3380 return -ENOMEM; 3381 } 3382 3383 hnae3_register_ae_algo(&ae_algovf); 3384 3385 return 0; 3386 } 3387 3388 static void __exit hclgevf_exit(void) 3389 { 3390 hnae3_unregister_ae_algo(&ae_algovf); 3391 destroy_workqueue(hclgevf_wq); 3392 } 3393 module_init(hclgevf_init); 3394 module_exit(hclgevf_exit); 3395 3396 MODULE_LICENSE("GPL"); 3397 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3398 MODULE_DESCRIPTION("HCLGEVF Driver"); 3399 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3400