1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 #include "hclgevf_devlink.h" 12 #include "hclge_comm_rss.h" 13 14 #define HCLGEVF_NAME "hclgevf" 15 16 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 17 18 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 19 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 20 unsigned long delay); 21 22 static struct hnae3_ae_algo ae_algovf; 23 24 static struct workqueue_struct *hclgevf_wq; 25 26 static const struct pci_device_id ae_algovf_pci_tbl[] = { 27 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 28 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 29 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 30 /* required last entry */ 31 {0, } 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 35 36 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 37 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 38 HCLGE_COMM_NIC_CSQ_DEPTH_REG, 39 HCLGE_COMM_NIC_CSQ_TAIL_REG, 40 HCLGE_COMM_NIC_CSQ_HEAD_REG, 41 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 42 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 43 HCLGE_COMM_NIC_CRQ_DEPTH_REG, 44 HCLGE_COMM_NIC_CRQ_TAIL_REG, 45 HCLGE_COMM_NIC_CRQ_HEAD_REG, 46 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 47 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG, 48 HCLGE_COMM_CMDQ_INTR_EN_REG, 49 HCLGE_COMM_CMDQ_INTR_GEN_REG}; 50 51 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 52 HCLGEVF_RST_ING, 53 HCLGEVF_GRO_EN_REG}; 54 55 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 56 HCLGEVF_RING_RX_ADDR_H_REG, 57 HCLGEVF_RING_RX_BD_NUM_REG, 58 HCLGEVF_RING_RX_BD_LENGTH_REG, 59 HCLGEVF_RING_RX_MERGE_EN_REG, 60 HCLGEVF_RING_RX_TAIL_REG, 61 HCLGEVF_RING_RX_HEAD_REG, 62 HCLGEVF_RING_RX_FBD_NUM_REG, 63 HCLGEVF_RING_RX_OFFSET_REG, 64 HCLGEVF_RING_RX_FBD_OFFSET_REG, 65 HCLGEVF_RING_RX_STASH_REG, 66 HCLGEVF_RING_RX_BD_ERR_REG, 67 HCLGEVF_RING_TX_ADDR_L_REG, 68 HCLGEVF_RING_TX_ADDR_H_REG, 69 HCLGEVF_RING_TX_BD_NUM_REG, 70 HCLGEVF_RING_TX_PRIORITY_REG, 71 HCLGEVF_RING_TX_TC_REG, 72 HCLGEVF_RING_TX_MERGE_EN_REG, 73 HCLGEVF_RING_TX_TAIL_REG, 74 HCLGEVF_RING_TX_HEAD_REG, 75 HCLGEVF_RING_TX_FBD_NUM_REG, 76 HCLGEVF_RING_TX_OFFSET_REG, 77 HCLGEVF_RING_TX_EBD_NUM_REG, 78 HCLGEVF_RING_TX_EBD_OFFSET_REG, 79 HCLGEVF_RING_TX_BD_ERR_REG, 80 HCLGEVF_RING_EN_REG}; 81 82 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 83 HCLGEVF_TQP_INTR_GL0_REG, 84 HCLGEVF_TQP_INTR_GL1_REG, 85 HCLGEVF_TQP_INTR_GL2_REG, 86 HCLGEVF_TQP_INTR_RL_REG}; 87 88 /* hclgevf_cmd_send - send command to command queue 89 * @hw: pointer to the hw struct 90 * @desc: prefilled descriptor for describing the command 91 * @num : the number of descriptors to be sent 92 * 93 * This is the main send command for command queue, it 94 * sends the queue, cleans the queue, etc 95 */ 96 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 97 { 98 return hclge_comm_cmd_send(&hw->hw, desc, num); 99 } 100 101 void hclgevf_arq_init(struct hclgevf_dev *hdev) 102 { 103 struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 104 105 spin_lock(&cmdq->crq.lock); 106 /* initialize the pointers of async rx queue of mailbox */ 107 hdev->arq.hdev = hdev; 108 hdev->arq.head = 0; 109 hdev->arq.tail = 0; 110 atomic_set(&hdev->arq.count, 0); 111 spin_unlock(&cmdq->crq.lock); 112 } 113 114 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 115 { 116 if (!handle->client) 117 return container_of(handle, struct hclgevf_dev, nic); 118 else if (handle->client->type == HNAE3_CLIENT_ROCE) 119 return container_of(handle, struct hclgevf_dev, roce); 120 else 121 return container_of(handle, struct hclgevf_dev, nic); 122 } 123 124 static void hclgevf_update_stats(struct hnae3_handle *handle, 125 struct net_device_stats *net_stats) 126 { 127 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 128 int status; 129 130 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 131 if (status) 132 dev_err(&hdev->pdev->dev, 133 "VF update of TQPS stats fail, status = %d.\n", 134 status); 135 } 136 137 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 138 { 139 if (strset == ETH_SS_TEST) 140 return -EOPNOTSUPP; 141 else if (strset == ETH_SS_STATS) 142 return hclge_comm_tqps_get_sset_count(handle); 143 144 return 0; 145 } 146 147 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 148 u8 *data) 149 { 150 u8 *p = (char *)data; 151 152 if (strset == ETH_SS_STATS) 153 p = hclge_comm_tqps_get_strings(handle, p); 154 } 155 156 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 157 { 158 hclge_comm_tqps_get_stats(handle, data); 159 } 160 161 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 162 u8 subcode) 163 { 164 if (msg) { 165 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 166 msg->code = code; 167 msg->subcode = subcode; 168 } 169 } 170 171 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 172 { 173 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 174 u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 175 struct hclge_basic_info *basic_info; 176 struct hclge_vf_to_pf_msg send_msg; 177 unsigned long caps; 178 int status; 179 180 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 181 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 182 sizeof(resp_msg)); 183 if (status) { 184 dev_err(&hdev->pdev->dev, 185 "failed to get basic info from pf, ret = %d", status); 186 return status; 187 } 188 189 basic_info = (struct hclge_basic_info *)resp_msg; 190 191 hdev->hw_tc_map = basic_info->hw_tc_map; 192 hdev->mbx_api_version = le16_to_cpu(basic_info->mbx_api_version); 193 caps = le32_to_cpu(basic_info->pf_caps); 194 if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 195 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 196 197 return 0; 198 } 199 200 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 201 { 202 struct hnae3_handle *nic = &hdev->nic; 203 struct hclge_vf_to_pf_msg send_msg; 204 u8 resp_msg; 205 int ret; 206 207 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 208 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 209 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 210 sizeof(u8)); 211 if (ret) { 212 dev_err(&hdev->pdev->dev, 213 "VF request to get port based vlan state failed %d", 214 ret); 215 return ret; 216 } 217 218 nic->port_base_vlan_state = resp_msg; 219 220 return 0; 221 } 222 223 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 224 { 225 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 226 227 struct hclge_mbx_vf_queue_info *queue_info; 228 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 229 struct hclge_vf_to_pf_msg send_msg; 230 int status; 231 232 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 233 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 234 HCLGEVF_TQPS_RSS_INFO_LEN); 235 if (status) { 236 dev_err(&hdev->pdev->dev, 237 "VF request to get tqp info from PF failed %d", 238 status); 239 return status; 240 } 241 242 queue_info = (struct hclge_mbx_vf_queue_info *)resp_msg; 243 hdev->num_tqps = le16_to_cpu(queue_info->num_tqps); 244 hdev->rss_size_max = le16_to_cpu(queue_info->rss_size); 245 hdev->rx_buf_len = le16_to_cpu(queue_info->rx_buf_len); 246 247 return 0; 248 } 249 250 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 251 { 252 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 253 254 struct hclge_mbx_vf_queue_depth *queue_depth; 255 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 256 struct hclge_vf_to_pf_msg send_msg; 257 int ret; 258 259 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 260 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 261 HCLGEVF_TQPS_DEPTH_INFO_LEN); 262 if (ret) { 263 dev_err(&hdev->pdev->dev, 264 "VF request to get tqp depth info from PF failed %d", 265 ret); 266 return ret; 267 } 268 269 queue_depth = (struct hclge_mbx_vf_queue_depth *)resp_msg; 270 hdev->num_tx_desc = le16_to_cpu(queue_depth->num_tx_desc); 271 hdev->num_rx_desc = le16_to_cpu(queue_depth->num_rx_desc); 272 273 return 0; 274 } 275 276 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 277 { 278 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 279 struct hclge_vf_to_pf_msg send_msg; 280 u16 qid_in_pf = 0; 281 u8 resp_data[2]; 282 int ret; 283 284 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 285 *(__le16 *)send_msg.data = cpu_to_le16(queue_id); 286 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 287 sizeof(resp_data)); 288 if (!ret) 289 qid_in_pf = le16_to_cpu(*(__le16 *)resp_data); 290 291 return qid_in_pf; 292 } 293 294 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 295 { 296 struct hclge_vf_to_pf_msg send_msg; 297 u8 resp_msg[2]; 298 int ret; 299 300 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 301 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 302 sizeof(resp_msg)); 303 if (ret) { 304 dev_err(&hdev->pdev->dev, 305 "VF request to get the pf port media type failed %d", 306 ret); 307 return ret; 308 } 309 310 hdev->hw.mac.media_type = resp_msg[0]; 311 hdev->hw.mac.module_type = resp_msg[1]; 312 313 return 0; 314 } 315 316 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 317 { 318 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 319 struct hclge_comm_tqp *tqp; 320 int i; 321 322 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 323 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 324 if (!hdev->htqp) 325 return -ENOMEM; 326 327 tqp = hdev->htqp; 328 329 for (i = 0; i < hdev->num_tqps; i++) { 330 tqp->dev = &hdev->pdev->dev; 331 tqp->index = i; 332 333 tqp->q.ae_algo = &ae_algovf; 334 tqp->q.buf_size = hdev->rx_buf_len; 335 tqp->q.tx_desc_num = hdev->num_tx_desc; 336 tqp->q.rx_desc_num = hdev->num_rx_desc; 337 338 /* need an extended offset to configure queues >= 339 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 340 */ 341 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 342 tqp->q.io_base = hdev->hw.hw.io_base + 343 HCLGEVF_TQP_REG_OFFSET + 344 i * HCLGEVF_TQP_REG_SIZE; 345 else 346 tqp->q.io_base = hdev->hw.hw.io_base + 347 HCLGEVF_TQP_REG_OFFSET + 348 HCLGEVF_TQP_EXT_REG_OFFSET + 349 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 350 HCLGEVF_TQP_REG_SIZE; 351 352 /* when device supports tx push and has device memory, 353 * the queue can execute push mode or doorbell mode on 354 * device memory. 355 */ 356 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 357 tqp->q.mem_base = hdev->hw.hw.mem_base + 358 HCLGEVF_TQP_MEM_OFFSET(hdev, i); 359 360 tqp++; 361 } 362 363 return 0; 364 } 365 366 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 367 { 368 struct hnae3_handle *nic = &hdev->nic; 369 struct hnae3_knic_private_info *kinfo; 370 u16 new_tqps = hdev->num_tqps; 371 unsigned int i; 372 u8 num_tc = 0; 373 374 kinfo = &nic->kinfo; 375 kinfo->num_tx_desc = hdev->num_tx_desc; 376 kinfo->num_rx_desc = hdev->num_rx_desc; 377 kinfo->rx_buf_len = hdev->rx_buf_len; 378 for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++) 379 if (hdev->hw_tc_map & BIT(i)) 380 num_tc++; 381 382 num_tc = num_tc ? num_tc : 1; 383 kinfo->tc_info.num_tc = num_tc; 384 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 385 new_tqps = kinfo->rss_size * num_tc; 386 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 387 388 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 389 sizeof(struct hnae3_queue *), GFP_KERNEL); 390 if (!kinfo->tqp) 391 return -ENOMEM; 392 393 for (i = 0; i < kinfo->num_tqps; i++) { 394 hdev->htqp[i].q.handle = &hdev->nic; 395 hdev->htqp[i].q.tqp_index = i; 396 kinfo->tqp[i] = &hdev->htqp[i].q; 397 } 398 399 /* after init the max rss_size and tqps, adjust the default tqp numbers 400 * and rss size with the actual vector numbers 401 */ 402 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 403 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 404 kinfo->rss_size); 405 406 return 0; 407 } 408 409 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 410 { 411 struct hclge_vf_to_pf_msg send_msg; 412 int status; 413 414 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 415 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 416 if (status) 417 dev_err(&hdev->pdev->dev, 418 "VF failed to fetch link status(%d) from PF", status); 419 } 420 421 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 422 { 423 struct hnae3_handle *rhandle = &hdev->roce; 424 struct hnae3_handle *handle = &hdev->nic; 425 struct hnae3_client *rclient; 426 struct hnae3_client *client; 427 428 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 429 return; 430 431 client = handle->client; 432 rclient = hdev->roce_client; 433 434 link_state = 435 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 436 if (link_state != hdev->hw.mac.link) { 437 hdev->hw.mac.link = link_state; 438 client->ops->link_status_change(handle, !!link_state); 439 if (rclient && rclient->ops->link_status_change) 440 rclient->ops->link_status_change(rhandle, !!link_state); 441 } 442 443 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 444 } 445 446 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 447 { 448 #define HCLGEVF_ADVERTISING 0 449 #define HCLGEVF_SUPPORTED 1 450 451 struct hclge_vf_to_pf_msg send_msg; 452 453 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 454 send_msg.data[0] = HCLGEVF_ADVERTISING; 455 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 456 send_msg.data[0] = HCLGEVF_SUPPORTED; 457 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 458 } 459 460 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 461 { 462 struct hnae3_handle *nic = &hdev->nic; 463 int ret; 464 465 nic->ae_algo = &ae_algovf; 466 nic->pdev = hdev->pdev; 467 nic->numa_node_mask = hdev->numa_node_mask; 468 nic->flags |= HNAE3_SUPPORT_VF; 469 nic->kinfo.io_base = hdev->hw.hw.io_base; 470 471 ret = hclgevf_knic_setup(hdev); 472 if (ret) 473 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 474 ret); 475 return ret; 476 } 477 478 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 479 { 480 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 481 dev_warn(&hdev->pdev->dev, 482 "vector(vector_id %d) has been freed.\n", vector_id); 483 return; 484 } 485 486 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 487 hdev->num_msi_left += 1; 488 hdev->num_msi_used -= 1; 489 } 490 491 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 492 struct hnae3_vector_info *vector_info) 493 { 494 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 495 struct hnae3_vector_info *vector = vector_info; 496 int alloc = 0; 497 int i, j; 498 499 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 500 vector_num = min(hdev->num_msi_left, vector_num); 501 502 for (j = 0; j < vector_num; j++) { 503 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 504 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 505 vector->vector = pci_irq_vector(hdev->pdev, i); 506 vector->io_addr = hdev->hw.hw.io_base + 507 HCLGEVF_VECTOR_REG_BASE + 508 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 509 hdev->vector_status[i] = 0; 510 hdev->vector_irq[i] = vector->vector; 511 512 vector++; 513 alloc++; 514 515 break; 516 } 517 } 518 } 519 hdev->num_msi_left -= alloc; 520 hdev->num_msi_used += alloc; 521 522 return alloc; 523 } 524 525 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 526 { 527 int i; 528 529 for (i = 0; i < hdev->num_msi; i++) 530 if (vector == hdev->vector_irq[i]) 531 return i; 532 533 return -EINVAL; 534 } 535 536 /* for revision 0x20, vf shared the same rss config with pf */ 537 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 538 { 539 #define HCLGEVF_RSS_MBX_RESP_LEN 8 540 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 541 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 542 struct hclge_vf_to_pf_msg send_msg; 543 u16 msg_num, hash_key_index; 544 u8 index; 545 int ret; 546 547 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 548 msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 549 HCLGEVF_RSS_MBX_RESP_LEN; 550 for (index = 0; index < msg_num; index++) { 551 send_msg.data[0] = index; 552 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 553 HCLGEVF_RSS_MBX_RESP_LEN); 554 if (ret) { 555 dev_err(&hdev->pdev->dev, 556 "VF get rss hash key from PF failed, ret=%d", 557 ret); 558 return ret; 559 } 560 561 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 562 if (index == msg_num - 1) 563 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 564 &resp_msg[0], 565 HCLGE_COMM_RSS_KEY_SIZE - hash_key_index); 566 else 567 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 568 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 569 } 570 571 return 0; 572 } 573 574 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 575 u8 *hfunc) 576 { 577 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 578 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 579 int ret; 580 581 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 582 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 583 } else { 584 if (hfunc) 585 *hfunc = ETH_RSS_HASH_TOP; 586 if (key) { 587 ret = hclgevf_get_rss_hash_key(hdev); 588 if (ret) 589 return ret; 590 memcpy(key, rss_cfg->rss_hash_key, 591 HCLGE_COMM_RSS_KEY_SIZE); 592 } 593 } 594 595 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 596 hdev->ae_dev->dev_specs.rss_ind_tbl_size); 597 598 return 0; 599 } 600 601 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 602 const u8 *key, const u8 hfunc) 603 { 604 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 605 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 606 int ret, i; 607 608 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 609 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, 610 hfunc); 611 if (ret) 612 return ret; 613 } 614 615 /* update the shadow RSS table with user specified qids */ 616 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 617 rss_cfg->rss_indirection_tbl[i] = indir[i]; 618 619 /* update the hardware */ 620 return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 621 rss_cfg->rss_indirection_tbl); 622 } 623 624 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 625 struct ethtool_rxnfc *nfc) 626 { 627 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 628 int ret; 629 630 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 631 return -EOPNOTSUPP; 632 633 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 634 &hdev->rss_cfg, nfc); 635 if (ret) 636 dev_err(&hdev->pdev->dev, 637 "failed to set rss tuple, ret = %d.\n", ret); 638 639 return ret; 640 } 641 642 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 643 struct ethtool_rxnfc *nfc) 644 { 645 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 646 u8 tuple_sets; 647 int ret; 648 649 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 650 return -EOPNOTSUPP; 651 652 nfc->data = 0; 653 654 ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type, 655 &tuple_sets); 656 if (ret || !tuple_sets) 657 return ret; 658 659 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 660 661 return 0; 662 } 663 664 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 665 { 666 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 667 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 668 669 return rss_cfg->rss_size; 670 } 671 672 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 673 int vector_id, 674 struct hnae3_ring_chain_node *ring_chain) 675 { 676 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 677 struct hclge_vf_to_pf_msg send_msg; 678 struct hnae3_ring_chain_node *node; 679 int status; 680 int i = 0; 681 682 memset(&send_msg, 0, sizeof(send_msg)); 683 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 684 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 685 send_msg.vector_id = vector_id; 686 687 for (node = ring_chain; node; node = node->next) { 688 send_msg.param[i].ring_type = 689 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 690 691 send_msg.param[i].tqp_index = node->tqp_index; 692 send_msg.param[i].int_gl_index = 693 hnae3_get_field(node->int_gl_idx, 694 HNAE3_RING_GL_IDX_M, 695 HNAE3_RING_GL_IDX_S); 696 697 i++; 698 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 699 send_msg.ring_num = i; 700 701 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 702 NULL, 0); 703 if (status) { 704 dev_err(&hdev->pdev->dev, 705 "Map TQP fail, status is %d.\n", 706 status); 707 return status; 708 } 709 i = 0; 710 } 711 } 712 713 return 0; 714 } 715 716 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 717 struct hnae3_ring_chain_node *ring_chain) 718 { 719 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 720 int vector_id; 721 722 vector_id = hclgevf_get_vector_index(hdev, vector); 723 if (vector_id < 0) { 724 dev_err(&handle->pdev->dev, 725 "Get vector index fail. ret =%d\n", vector_id); 726 return vector_id; 727 } 728 729 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 730 } 731 732 static int hclgevf_unmap_ring_from_vector( 733 struct hnae3_handle *handle, 734 int vector, 735 struct hnae3_ring_chain_node *ring_chain) 736 { 737 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 738 int ret, vector_id; 739 740 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 741 return 0; 742 743 vector_id = hclgevf_get_vector_index(hdev, vector); 744 if (vector_id < 0) { 745 dev_err(&handle->pdev->dev, 746 "Get vector index fail. ret =%d\n", vector_id); 747 return vector_id; 748 } 749 750 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 751 if (ret) 752 dev_err(&handle->pdev->dev, 753 "Unmap ring from vector fail. vector=%d, ret =%d\n", 754 vector_id, 755 ret); 756 757 return ret; 758 } 759 760 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 761 { 762 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 763 int vector_id; 764 765 vector_id = hclgevf_get_vector_index(hdev, vector); 766 if (vector_id < 0) { 767 dev_err(&handle->pdev->dev, 768 "hclgevf_put_vector get vector index fail. ret =%d\n", 769 vector_id); 770 return vector_id; 771 } 772 773 hclgevf_free_vector(hdev, vector_id); 774 775 return 0; 776 } 777 778 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 779 bool en_uc_pmc, bool en_mc_pmc, 780 bool en_bc_pmc) 781 { 782 struct hnae3_handle *handle = &hdev->nic; 783 struct hclge_vf_to_pf_msg send_msg; 784 int ret; 785 786 memset(&send_msg, 0, sizeof(send_msg)); 787 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 788 send_msg.en_bc = en_bc_pmc ? 1 : 0; 789 send_msg.en_uc = en_uc_pmc ? 1 : 0; 790 send_msg.en_mc = en_mc_pmc ? 1 : 0; 791 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 792 &handle->priv_flags) ? 1 : 0; 793 794 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 795 if (ret) 796 dev_err(&hdev->pdev->dev, 797 "Set promisc mode fail, status is %d.\n", ret); 798 799 return ret; 800 } 801 802 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 803 bool en_mc_pmc) 804 { 805 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 806 bool en_bc_pmc; 807 808 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 809 810 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 811 en_bc_pmc); 812 } 813 814 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 815 { 816 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 817 818 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 819 hclgevf_task_schedule(hdev, 0); 820 } 821 822 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 823 { 824 struct hnae3_handle *handle = &hdev->nic; 825 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 826 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 827 int ret; 828 829 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 830 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 831 if (!ret) 832 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 833 } 834 } 835 836 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 837 u16 stream_id, bool enable) 838 { 839 struct hclgevf_cfg_com_tqp_queue_cmd *req; 840 struct hclge_desc desc; 841 842 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 843 844 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 845 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 846 req->stream_id = cpu_to_le16(stream_id); 847 if (enable) 848 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 849 850 return hclgevf_cmd_send(&hdev->hw, &desc, 1); 851 } 852 853 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 854 { 855 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 856 int ret; 857 u16 i; 858 859 for (i = 0; i < handle->kinfo.num_tqps; i++) { 860 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 861 if (ret) 862 return ret; 863 } 864 865 return 0; 866 } 867 868 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 869 { 870 struct hclge_vf_to_pf_msg send_msg; 871 u8 host_mac[ETH_ALEN]; 872 int status; 873 874 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 875 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 876 ETH_ALEN); 877 if (status) { 878 dev_err(&hdev->pdev->dev, 879 "fail to get VF MAC from host %d", status); 880 return status; 881 } 882 883 ether_addr_copy(p, host_mac); 884 885 return 0; 886 } 887 888 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 889 { 890 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 891 u8 host_mac_addr[ETH_ALEN]; 892 893 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 894 return; 895 896 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 897 if (hdev->has_pf_mac) 898 ether_addr_copy(p, host_mac_addr); 899 else 900 ether_addr_copy(p, hdev->hw.mac.mac_addr); 901 } 902 903 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 904 bool is_first) 905 { 906 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 907 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 908 struct hclge_vf_to_pf_msg send_msg; 909 u8 *new_mac_addr = (u8 *)p; 910 int status; 911 912 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 913 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 914 ether_addr_copy(send_msg.data, new_mac_addr); 915 if (is_first && !hdev->has_pf_mac) 916 eth_zero_addr(&send_msg.data[ETH_ALEN]); 917 else 918 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 919 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 920 if (!status) 921 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 922 923 return status; 924 } 925 926 static struct hclgevf_mac_addr_node * 927 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 928 { 929 struct hclgevf_mac_addr_node *mac_node, *tmp; 930 931 list_for_each_entry_safe(mac_node, tmp, list, node) 932 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 933 return mac_node; 934 935 return NULL; 936 } 937 938 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 939 enum HCLGEVF_MAC_NODE_STATE state) 940 { 941 switch (state) { 942 /* from set_rx_mode or tmp_add_list */ 943 case HCLGEVF_MAC_TO_ADD: 944 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 945 mac_node->state = HCLGEVF_MAC_ACTIVE; 946 break; 947 /* only from set_rx_mode */ 948 case HCLGEVF_MAC_TO_DEL: 949 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 950 list_del(&mac_node->node); 951 kfree(mac_node); 952 } else { 953 mac_node->state = HCLGEVF_MAC_TO_DEL; 954 } 955 break; 956 /* only from tmp_add_list, the mac_node->state won't be 957 * HCLGEVF_MAC_ACTIVE 958 */ 959 case HCLGEVF_MAC_ACTIVE: 960 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 961 mac_node->state = HCLGEVF_MAC_ACTIVE; 962 break; 963 } 964 } 965 966 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 967 enum HCLGEVF_MAC_NODE_STATE state, 968 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 969 const unsigned char *addr) 970 { 971 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 972 struct hclgevf_mac_addr_node *mac_node; 973 struct list_head *list; 974 975 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 976 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 977 978 spin_lock_bh(&hdev->mac_table.mac_list_lock); 979 980 /* if the mac addr is already in the mac list, no need to add a new 981 * one into it, just check the mac addr state, convert it to a new 982 * state, or just remove it, or do nothing. 983 */ 984 mac_node = hclgevf_find_mac_node(list, addr); 985 if (mac_node) { 986 hclgevf_update_mac_node(mac_node, state); 987 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 988 return 0; 989 } 990 /* if this address is never added, unnecessary to delete */ 991 if (state == HCLGEVF_MAC_TO_DEL) { 992 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 993 return -ENOENT; 994 } 995 996 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 997 if (!mac_node) { 998 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 999 return -ENOMEM; 1000 } 1001 1002 mac_node->state = state; 1003 ether_addr_copy(mac_node->mac_addr, addr); 1004 list_add_tail(&mac_node->node, list); 1005 1006 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1007 return 0; 1008 } 1009 1010 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1011 const unsigned char *addr) 1012 { 1013 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1014 HCLGEVF_MAC_ADDR_UC, addr); 1015 } 1016 1017 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1018 const unsigned char *addr) 1019 { 1020 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1021 HCLGEVF_MAC_ADDR_UC, addr); 1022 } 1023 1024 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1025 const unsigned char *addr) 1026 { 1027 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1028 HCLGEVF_MAC_ADDR_MC, addr); 1029 } 1030 1031 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1032 const unsigned char *addr) 1033 { 1034 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1035 HCLGEVF_MAC_ADDR_MC, addr); 1036 } 1037 1038 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1039 struct hclgevf_mac_addr_node *mac_node, 1040 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1041 { 1042 struct hclge_vf_to_pf_msg send_msg; 1043 u8 code, subcode; 1044 1045 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1046 code = HCLGE_MBX_SET_UNICAST; 1047 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1048 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1049 else 1050 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1051 } else { 1052 code = HCLGE_MBX_SET_MULTICAST; 1053 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1054 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1055 else 1056 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1057 } 1058 1059 hclgevf_build_send_msg(&send_msg, code, subcode); 1060 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1061 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1062 } 1063 1064 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1065 struct list_head *list, 1066 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1067 { 1068 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1069 struct hclgevf_mac_addr_node *mac_node, *tmp; 1070 int ret; 1071 1072 list_for_each_entry_safe(mac_node, tmp, list, node) { 1073 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1074 if (ret) { 1075 hnae3_format_mac_addr(format_mac_addr, 1076 mac_node->mac_addr); 1077 dev_err(&hdev->pdev->dev, 1078 "failed to configure mac %s, state = %d, ret = %d\n", 1079 format_mac_addr, mac_node->state, ret); 1080 return; 1081 } 1082 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1083 mac_node->state = HCLGEVF_MAC_ACTIVE; 1084 } else { 1085 list_del(&mac_node->node); 1086 kfree(mac_node); 1087 } 1088 } 1089 } 1090 1091 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1092 struct list_head *mac_list) 1093 { 1094 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1095 1096 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1097 /* if the mac address from tmp_add_list is not in the 1098 * uc/mc_mac_list, it means have received a TO_DEL request 1099 * during the time window of sending mac config request to PF 1100 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1101 * then it will be removed at next time. If is TO_ADD, it means 1102 * send TO_ADD request failed, so just remove the mac node. 1103 */ 1104 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1105 if (new_node) { 1106 hclgevf_update_mac_node(new_node, mac_node->state); 1107 list_del(&mac_node->node); 1108 kfree(mac_node); 1109 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1110 mac_node->state = HCLGEVF_MAC_TO_DEL; 1111 list_move_tail(&mac_node->node, mac_list); 1112 } else { 1113 list_del(&mac_node->node); 1114 kfree(mac_node); 1115 } 1116 } 1117 } 1118 1119 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1120 struct list_head *mac_list) 1121 { 1122 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1123 1124 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1125 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1126 if (new_node) { 1127 /* If the mac addr is exist in the mac list, it means 1128 * received a new request TO_ADD during the time window 1129 * of sending mac addr configurrequest to PF, so just 1130 * change the mac state to ACTIVE. 1131 */ 1132 new_node->state = HCLGEVF_MAC_ACTIVE; 1133 list_del(&mac_node->node); 1134 kfree(mac_node); 1135 } else { 1136 list_move_tail(&mac_node->node, mac_list); 1137 } 1138 } 1139 } 1140 1141 static void hclgevf_clear_list(struct list_head *list) 1142 { 1143 struct hclgevf_mac_addr_node *mac_node, *tmp; 1144 1145 list_for_each_entry_safe(mac_node, tmp, list, node) { 1146 list_del(&mac_node->node); 1147 kfree(mac_node); 1148 } 1149 } 1150 1151 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1152 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1153 { 1154 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1155 struct list_head tmp_add_list, tmp_del_list; 1156 struct list_head *list; 1157 1158 INIT_LIST_HEAD(&tmp_add_list); 1159 INIT_LIST_HEAD(&tmp_del_list); 1160 1161 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1162 * we can add/delete these mac addr outside the spin lock 1163 */ 1164 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1165 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1166 1167 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1168 1169 list_for_each_entry_safe(mac_node, tmp, list, node) { 1170 switch (mac_node->state) { 1171 case HCLGEVF_MAC_TO_DEL: 1172 list_move_tail(&mac_node->node, &tmp_del_list); 1173 break; 1174 case HCLGEVF_MAC_TO_ADD: 1175 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1176 if (!new_node) 1177 goto stop_traverse; 1178 1179 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1180 new_node->state = mac_node->state; 1181 list_add_tail(&new_node->node, &tmp_add_list); 1182 break; 1183 default: 1184 break; 1185 } 1186 } 1187 1188 stop_traverse: 1189 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1190 1191 /* delete first, in order to get max mac table space for adding */ 1192 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1193 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1194 1195 /* if some mac addresses were added/deleted fail, move back to the 1196 * mac_list, and retry at next time. 1197 */ 1198 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1199 1200 hclgevf_sync_from_del_list(&tmp_del_list, list); 1201 hclgevf_sync_from_add_list(&tmp_add_list, list); 1202 1203 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1204 } 1205 1206 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1207 { 1208 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1209 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1210 } 1211 1212 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1213 { 1214 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1215 1216 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1217 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1218 1219 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1220 } 1221 1222 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1223 { 1224 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1225 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1226 struct hclge_vf_to_pf_msg send_msg; 1227 1228 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1229 return -EOPNOTSUPP; 1230 1231 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1232 HCLGE_MBX_ENABLE_VLAN_FILTER); 1233 send_msg.data[0] = enable ? 1 : 0; 1234 1235 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1236 } 1237 1238 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1239 __be16 proto, u16 vlan_id, 1240 bool is_kill) 1241 { 1242 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1243 struct hclge_mbx_vlan_filter *vlan_filter; 1244 struct hclge_vf_to_pf_msg send_msg; 1245 int ret; 1246 1247 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1248 return -EINVAL; 1249 1250 if (proto != htons(ETH_P_8021Q)) 1251 return -EPROTONOSUPPORT; 1252 1253 /* When device is resetting or reset failed, firmware is unable to 1254 * handle mailbox. Just record the vlan id, and remove it after 1255 * reset finished. 1256 */ 1257 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1258 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1259 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1260 return -EBUSY; 1261 } 1262 1263 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1264 HCLGE_MBX_VLAN_FILTER); 1265 vlan_filter = (struct hclge_mbx_vlan_filter *)send_msg.data; 1266 vlan_filter->is_kill = is_kill; 1267 vlan_filter->vlan_id = cpu_to_le16(vlan_id); 1268 vlan_filter->proto = cpu_to_le16(be16_to_cpu(proto)); 1269 1270 /* when remove hw vlan filter failed, record the vlan id, 1271 * and try to remove it from hw later, to be consistence 1272 * with stack. 1273 */ 1274 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1275 if (is_kill && ret) 1276 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1277 1278 return ret; 1279 } 1280 1281 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1282 { 1283 #define HCLGEVF_MAX_SYNC_COUNT 60 1284 struct hnae3_handle *handle = &hdev->nic; 1285 int ret, sync_cnt = 0; 1286 u16 vlan_id; 1287 1288 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1289 while (vlan_id != VLAN_N_VID) { 1290 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1291 vlan_id, true); 1292 if (ret) 1293 return; 1294 1295 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1296 sync_cnt++; 1297 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1298 return; 1299 1300 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1301 } 1302 } 1303 1304 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1305 { 1306 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1307 struct hclge_vf_to_pf_msg send_msg; 1308 1309 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1310 HCLGE_MBX_VLAN_RX_OFF_CFG); 1311 send_msg.data[0] = enable ? 1 : 0; 1312 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1313 } 1314 1315 static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1316 { 1317 #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1318 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1319 struct hclge_vf_to_pf_msg send_msg; 1320 u8 return_status = 0; 1321 int ret; 1322 u16 i; 1323 1324 /* disable vf queue before send queue reset msg to PF */ 1325 ret = hclgevf_tqp_enable(handle, false); 1326 if (ret) { 1327 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 1328 ret); 1329 return ret; 1330 } 1331 1332 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1333 1334 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 1335 sizeof(return_status)); 1336 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 1337 return ret; 1338 1339 for (i = 1; i < handle->kinfo.num_tqps; i++) { 1340 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1341 *(__le16 *)send_msg.data = cpu_to_le16(i); 1342 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1343 if (ret) 1344 return ret; 1345 } 1346 1347 return 0; 1348 } 1349 1350 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1351 { 1352 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1353 struct hclge_mbx_mtu_info *mtu_info; 1354 struct hclge_vf_to_pf_msg send_msg; 1355 1356 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1357 mtu_info = (struct hclge_mbx_mtu_info *)send_msg.data; 1358 mtu_info->mtu = cpu_to_le32(new_mtu); 1359 1360 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1361 } 1362 1363 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1364 enum hnae3_reset_notify_type type) 1365 { 1366 struct hnae3_client *client = hdev->nic_client; 1367 struct hnae3_handle *handle = &hdev->nic; 1368 int ret; 1369 1370 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1371 !client) 1372 return 0; 1373 1374 if (!client->ops->reset_notify) 1375 return -EOPNOTSUPP; 1376 1377 ret = client->ops->reset_notify(handle, type); 1378 if (ret) 1379 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1380 type, ret); 1381 1382 return ret; 1383 } 1384 1385 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1386 enum hnae3_reset_notify_type type) 1387 { 1388 struct hnae3_client *client = hdev->roce_client; 1389 struct hnae3_handle *handle = &hdev->roce; 1390 int ret; 1391 1392 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1393 return 0; 1394 1395 if (!client->ops->reset_notify) 1396 return -EOPNOTSUPP; 1397 1398 ret = client->ops->reset_notify(handle, type); 1399 if (ret) 1400 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1401 type, ret); 1402 return ret; 1403 } 1404 1405 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1406 { 1407 #define HCLGEVF_RESET_WAIT_US 20000 1408 #define HCLGEVF_RESET_WAIT_CNT 2000 1409 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1410 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1411 1412 u32 val; 1413 int ret; 1414 1415 if (hdev->reset_type == HNAE3_VF_RESET) 1416 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1417 HCLGEVF_VF_RST_ING, val, 1418 !(val & HCLGEVF_VF_RST_ING_BIT), 1419 HCLGEVF_RESET_WAIT_US, 1420 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1421 else 1422 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1423 HCLGEVF_RST_ING, val, 1424 !(val & HCLGEVF_RST_ING_BITS), 1425 HCLGEVF_RESET_WAIT_US, 1426 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1427 1428 /* hardware completion status should be available by this time */ 1429 if (ret) { 1430 dev_err(&hdev->pdev->dev, 1431 "couldn't get reset done status from h/w, timeout!\n"); 1432 return ret; 1433 } 1434 1435 /* we will wait a bit more to let reset of the stack to complete. This 1436 * might happen in case reset assertion was made by PF. Yes, this also 1437 * means we might end up waiting bit more even for VF reset. 1438 */ 1439 if (hdev->reset_type == HNAE3_VF_FULL_RESET) 1440 msleep(5000); 1441 else 1442 msleep(500); 1443 1444 return 0; 1445 } 1446 1447 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1448 { 1449 u32 reg_val; 1450 1451 reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 1452 if (enable) 1453 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1454 else 1455 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1456 1457 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 1458 reg_val); 1459 } 1460 1461 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1462 { 1463 int ret; 1464 1465 /* uninitialize the nic client */ 1466 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1467 if (ret) 1468 return ret; 1469 1470 /* re-initialize the hclge device */ 1471 ret = hclgevf_reset_hdev(hdev); 1472 if (ret) { 1473 dev_err(&hdev->pdev->dev, 1474 "hclge device re-init failed, VF is disabled!\n"); 1475 return ret; 1476 } 1477 1478 /* bring up the nic client again */ 1479 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1480 if (ret) 1481 return ret; 1482 1483 /* clear handshake status with IMP */ 1484 hclgevf_reset_handshake(hdev, false); 1485 1486 /* bring up the nic to enable TX/RX again */ 1487 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1488 } 1489 1490 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1491 { 1492 #define HCLGEVF_RESET_SYNC_TIME 100 1493 1494 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1495 struct hclge_vf_to_pf_msg send_msg; 1496 int ret; 1497 1498 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1499 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1500 if (ret) { 1501 dev_err(&hdev->pdev->dev, 1502 "failed to assert VF reset, ret = %d\n", ret); 1503 return ret; 1504 } 1505 hdev->rst_stats.vf_func_rst_cnt++; 1506 } 1507 1508 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1509 /* inform hardware that preparatory work is done */ 1510 msleep(HCLGEVF_RESET_SYNC_TIME); 1511 hclgevf_reset_handshake(hdev, true); 1512 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1513 hdev->reset_type); 1514 1515 return 0; 1516 } 1517 1518 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1519 { 1520 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1521 hdev->rst_stats.vf_func_rst_cnt); 1522 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1523 hdev->rst_stats.flr_rst_cnt); 1524 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1525 hdev->rst_stats.vf_rst_cnt); 1526 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1527 hdev->rst_stats.rst_done_cnt); 1528 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1529 hdev->rst_stats.hw_rst_done_cnt); 1530 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1531 hdev->rst_stats.rst_cnt); 1532 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1533 hdev->rst_stats.rst_fail_cnt); 1534 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1535 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1536 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1537 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 1538 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1539 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 1540 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1541 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1542 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1543 } 1544 1545 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1546 { 1547 /* recover handshake status with IMP when reset fail */ 1548 hclgevf_reset_handshake(hdev, true); 1549 hdev->rst_stats.rst_fail_cnt++; 1550 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1551 hdev->rst_stats.rst_fail_cnt); 1552 1553 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1554 set_bit(hdev->reset_type, &hdev->reset_pending); 1555 1556 if (hclgevf_is_reset_pending(hdev)) { 1557 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1558 hclgevf_reset_task_schedule(hdev); 1559 } else { 1560 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1561 hclgevf_dump_rst_info(hdev); 1562 } 1563 } 1564 1565 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1566 { 1567 int ret; 1568 1569 hdev->rst_stats.rst_cnt++; 1570 1571 /* perform reset of the stack & ae device for a client */ 1572 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1573 if (ret) 1574 return ret; 1575 1576 rtnl_lock(); 1577 /* bring down the nic to stop any ongoing TX/RX */ 1578 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1579 rtnl_unlock(); 1580 if (ret) 1581 return ret; 1582 1583 return hclgevf_reset_prepare_wait(hdev); 1584 } 1585 1586 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1587 { 1588 int ret; 1589 1590 hdev->rst_stats.hw_rst_done_cnt++; 1591 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1592 if (ret) 1593 return ret; 1594 1595 rtnl_lock(); 1596 /* now, re-initialize the nic client and ae device */ 1597 ret = hclgevf_reset_stack(hdev); 1598 rtnl_unlock(); 1599 if (ret) { 1600 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1601 return ret; 1602 } 1603 1604 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1605 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1606 * times 1607 */ 1608 if (ret && 1609 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1610 return ret; 1611 1612 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1613 if (ret) 1614 return ret; 1615 1616 hdev->last_reset_time = jiffies; 1617 hdev->rst_stats.rst_done_cnt++; 1618 hdev->rst_stats.rst_fail_cnt = 0; 1619 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1620 1621 return 0; 1622 } 1623 1624 static void hclgevf_reset(struct hclgevf_dev *hdev) 1625 { 1626 if (hclgevf_reset_prepare(hdev)) 1627 goto err_reset; 1628 1629 /* check if VF could successfully fetch the hardware reset completion 1630 * status from the hardware 1631 */ 1632 if (hclgevf_reset_wait(hdev)) { 1633 /* can't do much in this situation, will disable VF */ 1634 dev_err(&hdev->pdev->dev, 1635 "failed to fetch H/W reset completion status\n"); 1636 goto err_reset; 1637 } 1638 1639 if (hclgevf_reset_rebuild(hdev)) 1640 goto err_reset; 1641 1642 return; 1643 1644 err_reset: 1645 hclgevf_reset_err_handle(hdev); 1646 } 1647 1648 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1649 unsigned long *addr) 1650 { 1651 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1652 1653 /* return the highest priority reset level amongst all */ 1654 if (test_bit(HNAE3_VF_RESET, addr)) { 1655 rst_level = HNAE3_VF_RESET; 1656 clear_bit(HNAE3_VF_RESET, addr); 1657 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1658 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1659 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1660 rst_level = HNAE3_VF_FULL_RESET; 1661 clear_bit(HNAE3_VF_FULL_RESET, addr); 1662 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1663 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1664 rst_level = HNAE3_VF_PF_FUNC_RESET; 1665 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1666 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1667 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1668 rst_level = HNAE3_VF_FUNC_RESET; 1669 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1670 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1671 rst_level = HNAE3_FLR_RESET; 1672 clear_bit(HNAE3_FLR_RESET, addr); 1673 } 1674 1675 return rst_level; 1676 } 1677 1678 static void hclgevf_reset_event(struct pci_dev *pdev, 1679 struct hnae3_handle *handle) 1680 { 1681 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1682 struct hclgevf_dev *hdev = ae_dev->priv; 1683 1684 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1685 1686 if (hdev->default_reset_request) 1687 hdev->reset_level = 1688 hclgevf_get_reset_level(hdev, 1689 &hdev->default_reset_request); 1690 else 1691 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1692 1693 /* reset of this VF requested */ 1694 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1695 hclgevf_reset_task_schedule(hdev); 1696 1697 hdev->last_reset_time = jiffies; 1698 } 1699 1700 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1701 enum hnae3_reset_type rst_type) 1702 { 1703 struct hclgevf_dev *hdev = ae_dev->priv; 1704 1705 set_bit(rst_type, &hdev->default_reset_request); 1706 } 1707 1708 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1709 { 1710 writel(en ? 1 : 0, vector->addr); 1711 } 1712 1713 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 1714 enum hnae3_reset_type rst_type) 1715 { 1716 #define HCLGEVF_RESET_RETRY_WAIT_MS 500 1717 #define HCLGEVF_RESET_RETRY_CNT 5 1718 1719 struct hclgevf_dev *hdev = ae_dev->priv; 1720 int retry_cnt = 0; 1721 int ret; 1722 1723 while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 1724 down(&hdev->reset_sem); 1725 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1726 hdev->reset_type = rst_type; 1727 ret = hclgevf_reset_prepare(hdev); 1728 if (!ret && !hdev->reset_pending) 1729 break; 1730 1731 dev_err(&hdev->pdev->dev, 1732 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 1733 ret, hdev->reset_pending, retry_cnt); 1734 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1735 up(&hdev->reset_sem); 1736 msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 1737 } 1738 1739 /* disable misc vector before reset done */ 1740 hclgevf_enable_vector(&hdev->misc_vector, false); 1741 1742 if (hdev->reset_type == HNAE3_FLR_RESET) 1743 hdev->rst_stats.flr_rst_cnt++; 1744 } 1745 1746 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 1747 { 1748 struct hclgevf_dev *hdev = ae_dev->priv; 1749 int ret; 1750 1751 hclgevf_enable_vector(&hdev->misc_vector, true); 1752 1753 ret = hclgevf_reset_rebuild(hdev); 1754 if (ret) 1755 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1756 ret); 1757 1758 hdev->reset_type = HNAE3_NONE_RESET; 1759 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1760 up(&hdev->reset_sem); 1761 } 1762 1763 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1764 { 1765 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1766 1767 return hdev->fw_version; 1768 } 1769 1770 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1771 { 1772 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1773 1774 vector->vector_irq = pci_irq_vector(hdev->pdev, 1775 HCLGEVF_MISC_VECTOR_NUM); 1776 vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1777 /* vector status always valid for Vector 0 */ 1778 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1779 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1780 1781 hdev->num_msi_left -= 1; 1782 hdev->num_msi_used += 1; 1783 } 1784 1785 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1786 { 1787 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1788 test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 1789 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1790 &hdev->state)) 1791 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1792 } 1793 1794 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1795 { 1796 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1797 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1798 &hdev->state)) 1799 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1800 } 1801 1802 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1803 unsigned long delay) 1804 { 1805 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1806 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1807 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1808 } 1809 1810 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 1811 { 1812 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1813 1814 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1815 return; 1816 1817 down(&hdev->reset_sem); 1818 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1819 1820 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1821 &hdev->reset_state)) { 1822 /* PF has intimated that it is about to reset the hardware. 1823 * We now have to poll & check if hardware has actually 1824 * completed the reset sequence. On hardware reset completion, 1825 * VF needs to reset the client and ae device. 1826 */ 1827 hdev->reset_attempts = 0; 1828 1829 hdev->last_reset_time = jiffies; 1830 hdev->reset_type = 1831 hclgevf_get_reset_level(hdev, &hdev->reset_pending); 1832 if (hdev->reset_type != HNAE3_NONE_RESET) 1833 hclgevf_reset(hdev); 1834 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1835 &hdev->reset_state)) { 1836 /* we could be here when either of below happens: 1837 * 1. reset was initiated due to watchdog timeout caused by 1838 * a. IMP was earlier reset and our TX got choked down and 1839 * which resulted in watchdog reacting and inducing VF 1840 * reset. This also means our cmdq would be unreliable. 1841 * b. problem in TX due to other lower layer(example link 1842 * layer not functioning properly etc.) 1843 * 2. VF reset might have been initiated due to some config 1844 * change. 1845 * 1846 * NOTE: Theres no clear way to detect above cases than to react 1847 * to the response of PF for this reset request. PF will ack the 1848 * 1b and 2. cases but we will not get any intimation about 1a 1849 * from PF as cmdq would be in unreliable state i.e. mailbox 1850 * communication between PF and VF would be broken. 1851 * 1852 * if we are never geting into pending state it means either: 1853 * 1. PF is not receiving our request which could be due to IMP 1854 * reset 1855 * 2. PF is screwed 1856 * We cannot do much for 2. but to check first we can try reset 1857 * our PCIe + stack and see if it alleviates the problem. 1858 */ 1859 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1860 /* prepare for full reset of stack + pcie interface */ 1861 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1862 1863 /* "defer" schedule the reset task again */ 1864 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1865 } else { 1866 hdev->reset_attempts++; 1867 1868 set_bit(hdev->reset_level, &hdev->reset_pending); 1869 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1870 } 1871 hclgevf_reset_task_schedule(hdev); 1872 } 1873 1874 hdev->reset_type = HNAE3_NONE_RESET; 1875 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1876 up(&hdev->reset_sem); 1877 } 1878 1879 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1880 { 1881 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1882 return; 1883 1884 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1885 return; 1886 1887 hclgevf_mbx_async_handler(hdev); 1888 1889 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1890 } 1891 1892 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1893 { 1894 struct hclge_vf_to_pf_msg send_msg; 1895 int ret; 1896 1897 if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1898 return; 1899 1900 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 1901 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1902 if (ret) 1903 dev_err(&hdev->pdev->dev, 1904 "VF sends keep alive cmd failed(=%d)\n", ret); 1905 } 1906 1907 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1908 { 1909 unsigned long delta = round_jiffies_relative(HZ); 1910 struct hnae3_handle *handle = &hdev->nic; 1911 1912 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1913 return; 1914 1915 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1916 delta = jiffies - hdev->last_serv_processed; 1917 1918 if (delta < round_jiffies_relative(HZ)) { 1919 delta = round_jiffies_relative(HZ) - delta; 1920 goto out; 1921 } 1922 } 1923 1924 hdev->serv_processed_cnt++; 1925 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1926 hclgevf_keep_alive(hdev); 1927 1928 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1929 hdev->last_serv_processed = jiffies; 1930 goto out; 1931 } 1932 1933 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1934 hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 1935 1936 /* VF does not need to request link status when this bit is set, because 1937 * PF will push its link status to VFs when link status changed. 1938 */ 1939 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 1940 hclgevf_request_link_info(hdev); 1941 1942 hclgevf_update_link_mode(hdev); 1943 1944 hclgevf_sync_vlan_filter(hdev); 1945 1946 hclgevf_sync_mac_table(hdev); 1947 1948 hclgevf_sync_promisc_mode(hdev); 1949 1950 hdev->last_serv_processed = jiffies; 1951 1952 out: 1953 hclgevf_task_schedule(hdev, delta); 1954 } 1955 1956 static void hclgevf_service_task(struct work_struct *work) 1957 { 1958 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1959 service_task.work); 1960 1961 hclgevf_reset_service_task(hdev); 1962 hclgevf_mailbox_service_task(hdev); 1963 hclgevf_periodic_service_task(hdev); 1964 1965 /* Handle reset and mbx again in case periodical task delays the 1966 * handling by calling hclgevf_task_schedule() in 1967 * hclgevf_periodic_service_task() 1968 */ 1969 hclgevf_reset_service_task(hdev); 1970 hclgevf_mailbox_service_task(hdev); 1971 } 1972 1973 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1974 { 1975 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 1976 } 1977 1978 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1979 u32 *clearval) 1980 { 1981 u32 val, cmdq_stat_reg, rst_ing_reg; 1982 1983 /* fetch the events from their corresponding regs */ 1984 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1985 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 1986 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1987 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1988 dev_info(&hdev->pdev->dev, 1989 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1990 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1991 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1992 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1993 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1994 hdev->rst_stats.vf_rst_cnt++; 1995 /* set up VF hardware reset status, its PF will clear 1996 * this status when PF has initialized done. 1997 */ 1998 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 1999 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2000 val | HCLGEVF_VF_RST_ING_BIT); 2001 return HCLGEVF_VECTOR0_EVENT_RST; 2002 } 2003 2004 /* check for vector0 mailbox(=CMDQ RX) event source */ 2005 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2006 /* for revision 0x21, clearing interrupt is writing bit 0 2007 * to the clear register, writing bit 1 means to keep the 2008 * old value. 2009 * for revision 0x20, the clear register is a read & write 2010 * register, so we should just write 0 to the bit we are 2011 * handling, and keep other bits as cmdq_stat_reg. 2012 */ 2013 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2014 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2015 else 2016 *clearval = cmdq_stat_reg & 2017 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2018 2019 return HCLGEVF_VECTOR0_EVENT_MBX; 2020 } 2021 2022 /* print other vector0 event source */ 2023 dev_info(&hdev->pdev->dev, 2024 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2025 cmdq_stat_reg); 2026 2027 return HCLGEVF_VECTOR0_EVENT_OTHER; 2028 } 2029 2030 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2031 { 2032 enum hclgevf_evt_cause event_cause; 2033 struct hclgevf_dev *hdev = data; 2034 u32 clearval; 2035 2036 hclgevf_enable_vector(&hdev->misc_vector, false); 2037 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2038 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2039 hclgevf_clear_event_cause(hdev, clearval); 2040 2041 switch (event_cause) { 2042 case HCLGEVF_VECTOR0_EVENT_RST: 2043 hclgevf_reset_task_schedule(hdev); 2044 break; 2045 case HCLGEVF_VECTOR0_EVENT_MBX: 2046 hclgevf_mbx_handler(hdev); 2047 break; 2048 default: 2049 break; 2050 } 2051 2052 hclgevf_enable_vector(&hdev->misc_vector, true); 2053 2054 return IRQ_HANDLED; 2055 } 2056 2057 static int hclgevf_configure(struct hclgevf_dev *hdev) 2058 { 2059 int ret; 2060 2061 hdev->gro_en = true; 2062 2063 ret = hclgevf_get_basic_info(hdev); 2064 if (ret) 2065 return ret; 2066 2067 /* get current port based vlan state from PF */ 2068 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2069 if (ret) 2070 return ret; 2071 2072 /* get queue configuration from PF */ 2073 ret = hclgevf_get_queue_info(hdev); 2074 if (ret) 2075 return ret; 2076 2077 /* get queue depth info from PF */ 2078 ret = hclgevf_get_queue_depth(hdev); 2079 if (ret) 2080 return ret; 2081 2082 return hclgevf_get_pf_media_type(hdev); 2083 } 2084 2085 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2086 { 2087 struct pci_dev *pdev = ae_dev->pdev; 2088 struct hclgevf_dev *hdev; 2089 2090 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2091 if (!hdev) 2092 return -ENOMEM; 2093 2094 hdev->pdev = pdev; 2095 hdev->ae_dev = ae_dev; 2096 ae_dev->priv = hdev; 2097 2098 return 0; 2099 } 2100 2101 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2102 { 2103 struct hnae3_handle *roce = &hdev->roce; 2104 struct hnae3_handle *nic = &hdev->nic; 2105 2106 roce->rinfo.num_vectors = hdev->num_roce_msix; 2107 2108 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2109 hdev->num_msi_left == 0) 2110 return -EINVAL; 2111 2112 roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2113 2114 roce->rinfo.netdev = nic->kinfo.netdev; 2115 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2116 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2117 2118 roce->pdev = nic->pdev; 2119 roce->ae_algo = nic->ae_algo; 2120 roce->numa_node_mask = nic->numa_node_mask; 2121 2122 return 0; 2123 } 2124 2125 static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2126 { 2127 struct hclgevf_cfg_gro_status_cmd *req; 2128 struct hclge_desc desc; 2129 int ret; 2130 2131 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 2132 return 0; 2133 2134 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, 2135 false); 2136 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2137 2138 req->gro_en = hdev->gro_en ? 1 : 0; 2139 2140 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2141 if (ret) 2142 dev_err(&hdev->pdev->dev, 2143 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2144 2145 return ret; 2146 } 2147 2148 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2149 { 2150 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 2151 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 2152 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 2153 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 2154 int ret; 2155 2156 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2157 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, 2158 rss_cfg->rss_algo, 2159 rss_cfg->rss_hash_key); 2160 if (ret) 2161 return ret; 2162 2163 ret = hclge_comm_set_rss_input_tuple(&hdev->nic, &hdev->hw.hw, 2164 false, rss_cfg); 2165 if (ret) 2166 return ret; 2167 } 2168 2169 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 2170 rss_cfg->rss_indirection_tbl); 2171 if (ret) 2172 return ret; 2173 2174 hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map, 2175 tc_offset, tc_valid, tc_size); 2176 2177 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 2178 tc_valid, tc_size); 2179 } 2180 2181 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2182 { 2183 struct hnae3_handle *nic = &hdev->nic; 2184 int ret; 2185 2186 ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2187 if (ret) { 2188 dev_err(&hdev->pdev->dev, 2189 "failed to enable rx vlan offload, ret = %d\n", ret); 2190 return ret; 2191 } 2192 2193 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2194 false); 2195 } 2196 2197 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2198 { 2199 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2200 2201 unsigned long last = hdev->serv_processed_cnt; 2202 int i = 0; 2203 2204 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2205 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2206 last == hdev->serv_processed_cnt) 2207 usleep_range(1, 1); 2208 } 2209 2210 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2211 { 2212 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2213 2214 if (enable) { 2215 hclgevf_task_schedule(hdev, 0); 2216 } else { 2217 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2218 2219 /* flush memory to make sure DOWN is seen by service task */ 2220 smp_mb__before_atomic(); 2221 hclgevf_flush_link_update(hdev); 2222 } 2223 } 2224 2225 static int hclgevf_ae_start(struct hnae3_handle *handle) 2226 { 2227 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2228 2229 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2230 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2231 2232 hclge_comm_reset_tqp_stats(handle); 2233 2234 hclgevf_request_link_info(hdev); 2235 2236 hclgevf_update_link_mode(hdev); 2237 2238 return 0; 2239 } 2240 2241 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2242 { 2243 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2244 2245 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2246 2247 if (hdev->reset_type != HNAE3_VF_RESET) 2248 hclgevf_reset_tqp(handle); 2249 2250 hclge_comm_reset_tqp_stats(handle); 2251 hclgevf_update_link_status(hdev, 0); 2252 } 2253 2254 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2255 { 2256 #define HCLGEVF_STATE_ALIVE 1 2257 #define HCLGEVF_STATE_NOT_ALIVE 0 2258 2259 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2260 struct hclge_vf_to_pf_msg send_msg; 2261 2262 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2263 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2264 HCLGEVF_STATE_NOT_ALIVE; 2265 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2266 } 2267 2268 static int hclgevf_client_start(struct hnae3_handle *handle) 2269 { 2270 return hclgevf_set_alive(handle, true); 2271 } 2272 2273 static void hclgevf_client_stop(struct hnae3_handle *handle) 2274 { 2275 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2276 int ret; 2277 2278 ret = hclgevf_set_alive(handle, false); 2279 if (ret) 2280 dev_warn(&hdev->pdev->dev, 2281 "%s failed %d\n", __func__, ret); 2282 } 2283 2284 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2285 { 2286 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2287 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2288 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2289 2290 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2291 2292 mutex_init(&hdev->mbx_resp.mbx_mutex); 2293 sema_init(&hdev->reset_sem, 1); 2294 2295 spin_lock_init(&hdev->mac_table.mac_list_lock); 2296 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2297 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2298 2299 /* bring the device down */ 2300 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2301 } 2302 2303 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2304 { 2305 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2306 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2307 2308 if (hdev->service_task.work.func) 2309 cancel_delayed_work_sync(&hdev->service_task); 2310 2311 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2312 } 2313 2314 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2315 { 2316 struct pci_dev *pdev = hdev->pdev; 2317 int vectors; 2318 int i; 2319 2320 if (hnae3_dev_roce_supported(hdev)) 2321 vectors = pci_alloc_irq_vectors(pdev, 2322 hdev->roce_base_msix_offset + 1, 2323 hdev->num_msi, 2324 PCI_IRQ_MSIX); 2325 else 2326 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2327 hdev->num_msi, 2328 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2329 2330 if (vectors < 0) { 2331 dev_err(&pdev->dev, 2332 "failed(%d) to allocate MSI/MSI-X vectors\n", 2333 vectors); 2334 return vectors; 2335 } 2336 if (vectors < hdev->num_msi) 2337 dev_warn(&hdev->pdev->dev, 2338 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2339 hdev->num_msi, vectors); 2340 2341 hdev->num_msi = vectors; 2342 hdev->num_msi_left = vectors; 2343 2344 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2345 sizeof(u16), GFP_KERNEL); 2346 if (!hdev->vector_status) { 2347 pci_free_irq_vectors(pdev); 2348 return -ENOMEM; 2349 } 2350 2351 for (i = 0; i < hdev->num_msi; i++) 2352 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2353 2354 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2355 sizeof(int), GFP_KERNEL); 2356 if (!hdev->vector_irq) { 2357 devm_kfree(&pdev->dev, hdev->vector_status); 2358 pci_free_irq_vectors(pdev); 2359 return -ENOMEM; 2360 } 2361 2362 return 0; 2363 } 2364 2365 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2366 { 2367 struct pci_dev *pdev = hdev->pdev; 2368 2369 devm_kfree(&pdev->dev, hdev->vector_status); 2370 devm_kfree(&pdev->dev, hdev->vector_irq); 2371 pci_free_irq_vectors(pdev); 2372 } 2373 2374 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2375 { 2376 int ret; 2377 2378 hclgevf_get_misc_vector(hdev); 2379 2380 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2381 HCLGEVF_NAME, pci_name(hdev->pdev)); 2382 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2383 0, hdev->misc_vector.name, hdev); 2384 if (ret) { 2385 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2386 hdev->misc_vector.vector_irq); 2387 return ret; 2388 } 2389 2390 hclgevf_clear_event_cause(hdev, 0); 2391 2392 /* enable misc. vector(vector 0) */ 2393 hclgevf_enable_vector(&hdev->misc_vector, true); 2394 2395 return ret; 2396 } 2397 2398 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2399 { 2400 /* disable misc vector(vector 0) */ 2401 hclgevf_enable_vector(&hdev->misc_vector, false); 2402 synchronize_irq(hdev->misc_vector.vector_irq); 2403 free_irq(hdev->misc_vector.vector_irq, hdev); 2404 hclgevf_free_vector(hdev, 0); 2405 } 2406 2407 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2408 { 2409 struct device *dev = &hdev->pdev->dev; 2410 2411 dev_info(dev, "VF info begin:\n"); 2412 2413 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2414 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2415 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2416 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2417 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2418 dev_info(dev, "PF media type of this VF: %u\n", 2419 hdev->hw.mac.media_type); 2420 2421 dev_info(dev, "VF info end.\n"); 2422 } 2423 2424 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2425 struct hnae3_client *client) 2426 { 2427 struct hclgevf_dev *hdev = ae_dev->priv; 2428 int rst_cnt = hdev->rst_stats.rst_cnt; 2429 int ret; 2430 2431 ret = client->ops->init_instance(&hdev->nic); 2432 if (ret) 2433 return ret; 2434 2435 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2436 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2437 rst_cnt != hdev->rst_stats.rst_cnt) { 2438 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2439 2440 client->ops->uninit_instance(&hdev->nic, 0); 2441 return -EBUSY; 2442 } 2443 2444 hnae3_set_client_init_flag(client, ae_dev, 1); 2445 2446 if (netif_msg_drv(&hdev->nic)) 2447 hclgevf_info_show(hdev); 2448 2449 return 0; 2450 } 2451 2452 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2453 struct hnae3_client *client) 2454 { 2455 struct hclgevf_dev *hdev = ae_dev->priv; 2456 int ret; 2457 2458 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2459 !hdev->nic_client) 2460 return 0; 2461 2462 ret = hclgevf_init_roce_base_info(hdev); 2463 if (ret) 2464 return ret; 2465 2466 ret = client->ops->init_instance(&hdev->roce); 2467 if (ret) 2468 return ret; 2469 2470 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2471 hnae3_set_client_init_flag(client, ae_dev, 1); 2472 2473 return 0; 2474 } 2475 2476 static int hclgevf_init_client_instance(struct hnae3_client *client, 2477 struct hnae3_ae_dev *ae_dev) 2478 { 2479 struct hclgevf_dev *hdev = ae_dev->priv; 2480 int ret; 2481 2482 switch (client->type) { 2483 case HNAE3_CLIENT_KNIC: 2484 hdev->nic_client = client; 2485 hdev->nic.client = client; 2486 2487 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2488 if (ret) 2489 goto clear_nic; 2490 2491 ret = hclgevf_init_roce_client_instance(ae_dev, 2492 hdev->roce_client); 2493 if (ret) 2494 goto clear_roce; 2495 2496 break; 2497 case HNAE3_CLIENT_ROCE: 2498 if (hnae3_dev_roce_supported(hdev)) { 2499 hdev->roce_client = client; 2500 hdev->roce.client = client; 2501 } 2502 2503 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2504 if (ret) 2505 goto clear_roce; 2506 2507 break; 2508 default: 2509 return -EINVAL; 2510 } 2511 2512 return 0; 2513 2514 clear_nic: 2515 hdev->nic_client = NULL; 2516 hdev->nic.client = NULL; 2517 return ret; 2518 clear_roce: 2519 hdev->roce_client = NULL; 2520 hdev->roce.client = NULL; 2521 return ret; 2522 } 2523 2524 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2525 struct hnae3_ae_dev *ae_dev) 2526 { 2527 struct hclgevf_dev *hdev = ae_dev->priv; 2528 2529 /* un-init roce, if it exists */ 2530 if (hdev->roce_client) { 2531 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2532 msleep(HCLGEVF_WAIT_RESET_DONE); 2533 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2534 2535 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2536 hdev->roce_client = NULL; 2537 hdev->roce.client = NULL; 2538 } 2539 2540 /* un-init nic/unic, if this was not called by roce client */ 2541 if (client->ops->uninit_instance && hdev->nic_client && 2542 client->type != HNAE3_CLIENT_ROCE) { 2543 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2544 msleep(HCLGEVF_WAIT_RESET_DONE); 2545 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2546 2547 client->ops->uninit_instance(&hdev->nic, 0); 2548 hdev->nic_client = NULL; 2549 hdev->nic.client = NULL; 2550 } 2551 } 2552 2553 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2554 { 2555 struct pci_dev *pdev = hdev->pdev; 2556 struct hclgevf_hw *hw = &hdev->hw; 2557 2558 /* for device does not have device memory, return directly */ 2559 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2560 return 0; 2561 2562 hw->hw.mem_base = 2563 devm_ioremap_wc(&pdev->dev, 2564 pci_resource_start(pdev, HCLGEVF_MEM_BAR), 2565 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2566 if (!hw->hw.mem_base) { 2567 dev_err(&pdev->dev, "failed to map device memory\n"); 2568 return -EFAULT; 2569 } 2570 2571 return 0; 2572 } 2573 2574 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2575 { 2576 struct pci_dev *pdev = hdev->pdev; 2577 struct hclgevf_hw *hw; 2578 int ret; 2579 2580 ret = pci_enable_device(pdev); 2581 if (ret) { 2582 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2583 return ret; 2584 } 2585 2586 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2587 if (ret) { 2588 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2589 goto err_disable_device; 2590 } 2591 2592 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2593 if (ret) { 2594 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2595 goto err_disable_device; 2596 } 2597 2598 pci_set_master(pdev); 2599 hw = &hdev->hw; 2600 hw->hw.io_base = pci_iomap(pdev, 2, 0); 2601 if (!hw->hw.io_base) { 2602 dev_err(&pdev->dev, "can't map configuration register space\n"); 2603 ret = -ENOMEM; 2604 goto err_release_regions; 2605 } 2606 2607 ret = hclgevf_dev_mem_map(hdev); 2608 if (ret) 2609 goto err_unmap_io_base; 2610 2611 return 0; 2612 2613 err_unmap_io_base: 2614 pci_iounmap(pdev, hdev->hw.hw.io_base); 2615 err_release_regions: 2616 pci_release_regions(pdev); 2617 err_disable_device: 2618 pci_disable_device(pdev); 2619 2620 return ret; 2621 } 2622 2623 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2624 { 2625 struct pci_dev *pdev = hdev->pdev; 2626 2627 if (hdev->hw.hw.mem_base) 2628 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 2629 2630 pci_iounmap(pdev, hdev->hw.hw.io_base); 2631 pci_release_regions(pdev); 2632 pci_disable_device(pdev); 2633 } 2634 2635 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2636 { 2637 struct hclgevf_query_res_cmd *req; 2638 struct hclge_desc desc; 2639 int ret; 2640 2641 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true); 2642 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2643 if (ret) { 2644 dev_err(&hdev->pdev->dev, 2645 "query vf resource failed, ret = %d.\n", ret); 2646 return ret; 2647 } 2648 2649 req = (struct hclgevf_query_res_cmd *)desc.data; 2650 2651 if (hnae3_dev_roce_supported(hdev)) { 2652 hdev->roce_base_msix_offset = 2653 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 2654 HCLGEVF_MSIX_OFT_ROCEE_M, 2655 HCLGEVF_MSIX_OFT_ROCEE_S); 2656 hdev->num_roce_msix = 2657 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2658 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2659 2660 /* nic's msix numbers is always equals to the roce's. */ 2661 hdev->num_nic_msix = hdev->num_roce_msix; 2662 2663 /* VF should have NIC vectors and Roce vectors, NIC vectors 2664 * are queued before Roce vectors. The offset is fixed to 64. 2665 */ 2666 hdev->num_msi = hdev->num_roce_msix + 2667 hdev->roce_base_msix_offset; 2668 } else { 2669 hdev->num_msi = 2670 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2671 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2672 2673 hdev->num_nic_msix = hdev->num_msi; 2674 } 2675 2676 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2677 dev_err(&hdev->pdev->dev, 2678 "Just %u msi resources, not enough for vf(min:2).\n", 2679 hdev->num_nic_msix); 2680 return -EINVAL; 2681 } 2682 2683 return 0; 2684 } 2685 2686 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2687 { 2688 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2689 2690 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2691 2692 ae_dev->dev_specs.max_non_tso_bd_num = 2693 HCLGEVF_MAX_NON_TSO_BD_NUM; 2694 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2695 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2696 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2697 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2698 } 2699 2700 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 2701 struct hclge_desc *desc) 2702 { 2703 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2704 struct hclgevf_dev_specs_0_cmd *req0; 2705 struct hclgevf_dev_specs_1_cmd *req1; 2706 2707 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 2708 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 2709 2710 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 2711 ae_dev->dev_specs.rss_ind_tbl_size = 2712 le16_to_cpu(req0->rss_ind_tbl_size); 2713 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 2714 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 2715 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 2716 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 2717 } 2718 2719 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 2720 { 2721 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 2722 2723 if (!dev_specs->max_non_tso_bd_num) 2724 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 2725 if (!dev_specs->rss_ind_tbl_size) 2726 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2727 if (!dev_specs->rss_key_size) 2728 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2729 if (!dev_specs->max_int_gl) 2730 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2731 if (!dev_specs->max_frm_size) 2732 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2733 } 2734 2735 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 2736 { 2737 struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 2738 int ret; 2739 int i; 2740 2741 /* set default specifications as devices lower than version V3 do not 2742 * support querying specifications from firmware. 2743 */ 2744 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 2745 hclgevf_set_default_dev_specs(hdev); 2746 return 0; 2747 } 2748 2749 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2750 hclgevf_cmd_setup_basic_desc(&desc[i], 2751 HCLGE_OPC_QUERY_DEV_SPECS, true); 2752 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2753 } 2754 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 2755 2756 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 2757 if (ret) 2758 return ret; 2759 2760 hclgevf_parse_dev_specs(hdev, desc); 2761 hclgevf_check_dev_specs(hdev); 2762 2763 return 0; 2764 } 2765 2766 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2767 { 2768 struct pci_dev *pdev = hdev->pdev; 2769 int ret = 0; 2770 2771 if ((hdev->reset_type == HNAE3_VF_FULL_RESET || 2772 hdev->reset_type == HNAE3_FLR_RESET) && 2773 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2774 hclgevf_misc_irq_uninit(hdev); 2775 hclgevf_uninit_msi(hdev); 2776 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2777 } 2778 2779 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2780 pci_set_master(pdev); 2781 ret = hclgevf_init_msi(hdev); 2782 if (ret) { 2783 dev_err(&pdev->dev, 2784 "failed(%d) to init MSI/MSI-X\n", ret); 2785 return ret; 2786 } 2787 2788 ret = hclgevf_misc_irq_init(hdev); 2789 if (ret) { 2790 hclgevf_uninit_msi(hdev); 2791 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2792 ret); 2793 return ret; 2794 } 2795 2796 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2797 } 2798 2799 return ret; 2800 } 2801 2802 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2803 { 2804 struct hclge_vf_to_pf_msg send_msg; 2805 2806 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2807 HCLGE_MBX_VPORT_LIST_CLEAR); 2808 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2809 } 2810 2811 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 2812 { 2813 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2814 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 2815 } 2816 2817 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 2818 { 2819 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2820 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 2821 } 2822 2823 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2824 { 2825 struct pci_dev *pdev = hdev->pdev; 2826 int ret; 2827 2828 ret = hclgevf_pci_reset(hdev); 2829 if (ret) { 2830 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2831 return ret; 2832 } 2833 2834 hclgevf_arq_init(hdev); 2835 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2836 &hdev->fw_version, false, 2837 hdev->reset_pending); 2838 if (ret) { 2839 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2840 return ret; 2841 } 2842 2843 ret = hclgevf_rss_init_hw(hdev); 2844 if (ret) { 2845 dev_err(&hdev->pdev->dev, 2846 "failed(%d) to initialize RSS\n", ret); 2847 return ret; 2848 } 2849 2850 ret = hclgevf_config_gro(hdev); 2851 if (ret) 2852 return ret; 2853 2854 ret = hclgevf_init_vlan_config(hdev); 2855 if (ret) { 2856 dev_err(&hdev->pdev->dev, 2857 "failed(%d) to initialize VLAN config\n", ret); 2858 return ret; 2859 } 2860 2861 /* get current port based vlan state from PF */ 2862 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2863 if (ret) 2864 return ret; 2865 2866 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 2867 2868 hclgevf_init_rxd_adv_layout(hdev); 2869 2870 dev_info(&hdev->pdev->dev, "Reset done\n"); 2871 2872 return 0; 2873 } 2874 2875 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2876 { 2877 struct pci_dev *pdev = hdev->pdev; 2878 int ret; 2879 2880 ret = hclgevf_pci_init(hdev); 2881 if (ret) 2882 return ret; 2883 2884 ret = hclgevf_devlink_init(hdev); 2885 if (ret) 2886 goto err_devlink_init; 2887 2888 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 2889 if (ret) 2890 goto err_cmd_queue_init; 2891 2892 hclgevf_arq_init(hdev); 2893 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2894 &hdev->fw_version, false, 2895 hdev->reset_pending); 2896 if (ret) 2897 goto err_cmd_init; 2898 2899 /* Get vf resource */ 2900 ret = hclgevf_query_vf_resource(hdev); 2901 if (ret) 2902 goto err_cmd_init; 2903 2904 ret = hclgevf_query_dev_specs(hdev); 2905 if (ret) { 2906 dev_err(&pdev->dev, 2907 "failed to query dev specifications, ret = %d\n", ret); 2908 goto err_cmd_init; 2909 } 2910 2911 ret = hclgevf_init_msi(hdev); 2912 if (ret) { 2913 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2914 goto err_cmd_init; 2915 } 2916 2917 hclgevf_state_init(hdev); 2918 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2919 hdev->reset_type = HNAE3_NONE_RESET; 2920 2921 ret = hclgevf_misc_irq_init(hdev); 2922 if (ret) 2923 goto err_misc_irq_init; 2924 2925 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2926 2927 ret = hclgevf_configure(hdev); 2928 if (ret) { 2929 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2930 goto err_config; 2931 } 2932 2933 ret = hclgevf_alloc_tqps(hdev); 2934 if (ret) { 2935 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2936 goto err_config; 2937 } 2938 2939 ret = hclgevf_set_handle_info(hdev); 2940 if (ret) 2941 goto err_config; 2942 2943 ret = hclgevf_config_gro(hdev); 2944 if (ret) 2945 goto err_config; 2946 2947 /* Initialize RSS for this VF */ 2948 ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev, 2949 &hdev->rss_cfg); 2950 if (ret) { 2951 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 2952 goto err_config; 2953 } 2954 2955 ret = hclgevf_rss_init_hw(hdev); 2956 if (ret) { 2957 dev_err(&hdev->pdev->dev, 2958 "failed(%d) to initialize RSS\n", ret); 2959 goto err_config; 2960 } 2961 2962 /* ensure vf tbl list as empty before init */ 2963 ret = hclgevf_clear_vport_list(hdev); 2964 if (ret) { 2965 dev_err(&pdev->dev, 2966 "failed to clear tbl list configuration, ret = %d.\n", 2967 ret); 2968 goto err_config; 2969 } 2970 2971 ret = hclgevf_init_vlan_config(hdev); 2972 if (ret) { 2973 dev_err(&hdev->pdev->dev, 2974 "failed(%d) to initialize VLAN config\n", ret); 2975 goto err_config; 2976 } 2977 2978 hclgevf_init_rxd_adv_layout(hdev); 2979 2980 set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 2981 2982 hdev->last_reset_time = jiffies; 2983 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2984 HCLGEVF_DRIVER_NAME); 2985 2986 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2987 2988 return 0; 2989 2990 err_config: 2991 hclgevf_misc_irq_uninit(hdev); 2992 err_misc_irq_init: 2993 hclgevf_state_uninit(hdev); 2994 hclgevf_uninit_msi(hdev); 2995 err_cmd_init: 2996 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 2997 err_cmd_queue_init: 2998 hclgevf_devlink_uninit(hdev); 2999 err_devlink_init: 3000 hclgevf_pci_uninit(hdev); 3001 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3002 return ret; 3003 } 3004 3005 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3006 { 3007 struct hclge_vf_to_pf_msg send_msg; 3008 3009 hclgevf_state_uninit(hdev); 3010 hclgevf_uninit_rxd_adv_layout(hdev); 3011 3012 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3013 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3014 3015 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3016 hclgevf_misc_irq_uninit(hdev); 3017 hclgevf_uninit_msi(hdev); 3018 } 3019 3020 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3021 hclgevf_devlink_uninit(hdev); 3022 hclgevf_pci_uninit(hdev); 3023 hclgevf_uninit_mac_list(hdev); 3024 } 3025 3026 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3027 { 3028 struct pci_dev *pdev = ae_dev->pdev; 3029 int ret; 3030 3031 ret = hclgevf_alloc_hdev(ae_dev); 3032 if (ret) { 3033 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3034 return ret; 3035 } 3036 3037 ret = hclgevf_init_hdev(ae_dev->priv); 3038 if (ret) { 3039 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3040 return ret; 3041 } 3042 3043 return 0; 3044 } 3045 3046 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3047 { 3048 struct hclgevf_dev *hdev = ae_dev->priv; 3049 3050 hclgevf_uninit_hdev(hdev); 3051 ae_dev->priv = NULL; 3052 } 3053 3054 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3055 { 3056 struct hnae3_handle *nic = &hdev->nic; 3057 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3058 3059 return min_t(u32, hdev->rss_size_max, 3060 hdev->num_tqps / kinfo->tc_info.num_tc); 3061 } 3062 3063 /** 3064 * hclgevf_get_channels - Get the current channels enabled and max supported. 3065 * @handle: hardware information for network interface 3066 * @ch: ethtool channels structure 3067 * 3068 * We don't support separate tx and rx queues as channels. The other count 3069 * represents how many queues are being used for control. max_combined counts 3070 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3071 * q_vectors since we support a lot more queue pairs than q_vectors. 3072 **/ 3073 static void hclgevf_get_channels(struct hnae3_handle *handle, 3074 struct ethtool_channels *ch) 3075 { 3076 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3077 3078 ch->max_combined = hclgevf_get_max_channels(hdev); 3079 ch->other_count = 0; 3080 ch->max_other = 0; 3081 ch->combined_count = handle->kinfo.rss_size; 3082 } 3083 3084 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3085 u16 *alloc_tqps, u16 *max_rss_size) 3086 { 3087 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3088 3089 *alloc_tqps = hdev->num_tqps; 3090 *max_rss_size = hdev->rss_size_max; 3091 } 3092 3093 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3094 u32 new_tqps_num) 3095 { 3096 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3097 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3098 u16 max_rss_size; 3099 3100 kinfo->req_rss_size = new_tqps_num; 3101 3102 max_rss_size = min_t(u16, hdev->rss_size_max, 3103 hdev->num_tqps / kinfo->tc_info.num_tc); 3104 3105 /* Use the user's configuration when it is not larger than 3106 * max_rss_size, otherwise, use the maximum specification value. 3107 */ 3108 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3109 kinfo->req_rss_size <= max_rss_size) 3110 kinfo->rss_size = kinfo->req_rss_size; 3111 else if (kinfo->rss_size > max_rss_size || 3112 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3113 kinfo->rss_size = max_rss_size; 3114 3115 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3116 } 3117 3118 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3119 bool rxfh_configured) 3120 { 3121 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3122 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3123 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 3124 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 3125 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 3126 u16 cur_rss_size = kinfo->rss_size; 3127 u16 cur_tqps = kinfo->num_tqps; 3128 u32 *rss_indir; 3129 unsigned int i; 3130 int ret; 3131 3132 hclgevf_update_rss_size(handle, new_tqps_num); 3133 3134 hclge_comm_get_rss_tc_info(kinfo->rss_size, hdev->hw_tc_map, 3135 tc_offset, tc_valid, tc_size); 3136 ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 3137 tc_valid, tc_size); 3138 if (ret) 3139 return ret; 3140 3141 /* RSS indirection table has been configured by user */ 3142 if (rxfh_configured) 3143 goto out; 3144 3145 /* Reinitializes the rss indirect table according to the new RSS size */ 3146 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3147 sizeof(u32), GFP_KERNEL); 3148 if (!rss_indir) 3149 return -ENOMEM; 3150 3151 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3152 rss_indir[i] = i % kinfo->rss_size; 3153 3154 hdev->rss_cfg.rss_size = kinfo->rss_size; 3155 3156 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3157 if (ret) 3158 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3159 ret); 3160 3161 kfree(rss_indir); 3162 3163 out: 3164 if (!ret) 3165 dev_info(&hdev->pdev->dev, 3166 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3167 cur_rss_size, kinfo->rss_size, 3168 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3169 3170 return ret; 3171 } 3172 3173 static int hclgevf_get_status(struct hnae3_handle *handle) 3174 { 3175 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3176 3177 return hdev->hw.mac.link; 3178 } 3179 3180 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3181 u8 *auto_neg, u32 *speed, 3182 u8 *duplex, u32 *lane_num) 3183 { 3184 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3185 3186 if (speed) 3187 *speed = hdev->hw.mac.speed; 3188 if (duplex) 3189 *duplex = hdev->hw.mac.duplex; 3190 if (auto_neg) 3191 *auto_neg = AUTONEG_DISABLE; 3192 } 3193 3194 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3195 u8 duplex) 3196 { 3197 hdev->hw.mac.speed = speed; 3198 hdev->hw.mac.duplex = duplex; 3199 } 3200 3201 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3202 { 3203 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3204 bool gro_en_old = hdev->gro_en; 3205 int ret; 3206 3207 hdev->gro_en = enable; 3208 ret = hclgevf_config_gro(hdev); 3209 if (ret) 3210 hdev->gro_en = gro_en_old; 3211 3212 return ret; 3213 } 3214 3215 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3216 u8 *module_type) 3217 { 3218 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3219 3220 if (media_type) 3221 *media_type = hdev->hw.mac.media_type; 3222 3223 if (module_type) 3224 *module_type = hdev->hw.mac.module_type; 3225 } 3226 3227 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3228 { 3229 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3230 3231 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3232 } 3233 3234 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3235 { 3236 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3237 3238 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3239 } 3240 3241 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3242 { 3243 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3244 3245 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3246 } 3247 3248 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3249 { 3250 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3251 3252 return hdev->rst_stats.hw_rst_done_cnt; 3253 } 3254 3255 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3256 unsigned long *supported, 3257 unsigned long *advertising) 3258 { 3259 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3260 3261 *supported = hdev->hw.mac.supported; 3262 *advertising = hdev->hw.mac.advertising; 3263 } 3264 3265 #define MAX_SEPARATE_NUM 4 3266 #define SEPARATOR_VALUE 0xFDFCFBFA 3267 #define REG_NUM_PER_LINE 4 3268 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3269 3270 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3271 { 3272 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3273 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3274 3275 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3276 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3277 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3278 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3279 3280 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3281 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3282 } 3283 3284 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3285 void *data) 3286 { 3287 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3288 int i, j, reg_um, separator_num; 3289 u32 *reg = data; 3290 3291 *version = hdev->fw_version; 3292 3293 /* fetching per-VF registers values from VF PCIe register space */ 3294 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3295 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3296 for (i = 0; i < reg_um; i++) 3297 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3298 for (i = 0; i < separator_num; i++) 3299 *reg++ = SEPARATOR_VALUE; 3300 3301 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3302 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3303 for (i = 0; i < reg_um; i++) 3304 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3305 for (i = 0; i < separator_num; i++) 3306 *reg++ = SEPARATOR_VALUE; 3307 3308 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3309 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3310 for (j = 0; j < hdev->num_tqps; j++) { 3311 for (i = 0; i < reg_um; i++) 3312 *reg++ = hclgevf_read_dev(&hdev->hw, 3313 ring_reg_addr_list[i] + 3314 HCLGEVF_TQP_REG_SIZE * j); 3315 for (i = 0; i < separator_num; i++) 3316 *reg++ = SEPARATOR_VALUE; 3317 } 3318 3319 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3320 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3321 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3322 for (i = 0; i < reg_um; i++) 3323 *reg++ = hclgevf_read_dev(&hdev->hw, 3324 tqp_intr_reg_addr_list[i] + 3325 4 * j); 3326 for (i = 0; i < separator_num; i++) 3327 *reg++ = SEPARATOR_VALUE; 3328 } 3329 } 3330 3331 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3332 struct hclge_mbx_port_base_vlan *port_base_vlan) 3333 { 3334 struct hnae3_handle *nic = &hdev->nic; 3335 struct hclge_vf_to_pf_msg send_msg; 3336 int ret; 3337 3338 rtnl_lock(); 3339 3340 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3341 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3342 dev_warn(&hdev->pdev->dev, 3343 "is resetting when updating port based vlan info\n"); 3344 rtnl_unlock(); 3345 return; 3346 } 3347 3348 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3349 if (ret) { 3350 rtnl_unlock(); 3351 return; 3352 } 3353 3354 /* send msg to PF and wait update port based vlan info */ 3355 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3356 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3357 memcpy(send_msg.data, port_base_vlan, sizeof(*port_base_vlan)); 3358 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3359 if (!ret) { 3360 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3361 nic->port_base_vlan_state = state; 3362 else 3363 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3364 } 3365 3366 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3367 rtnl_unlock(); 3368 } 3369 3370 static const struct hnae3_ae_ops hclgevf_ops = { 3371 .init_ae_dev = hclgevf_init_ae_dev, 3372 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3373 .reset_prepare = hclgevf_reset_prepare_general, 3374 .reset_done = hclgevf_reset_done, 3375 .init_client_instance = hclgevf_init_client_instance, 3376 .uninit_client_instance = hclgevf_uninit_client_instance, 3377 .start = hclgevf_ae_start, 3378 .stop = hclgevf_ae_stop, 3379 .client_start = hclgevf_client_start, 3380 .client_stop = hclgevf_client_stop, 3381 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3382 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3383 .get_vector = hclgevf_get_vector, 3384 .put_vector = hclgevf_put_vector, 3385 .reset_queue = hclgevf_reset_tqp, 3386 .get_mac_addr = hclgevf_get_mac_addr, 3387 .set_mac_addr = hclgevf_set_mac_addr, 3388 .add_uc_addr = hclgevf_add_uc_addr, 3389 .rm_uc_addr = hclgevf_rm_uc_addr, 3390 .add_mc_addr = hclgevf_add_mc_addr, 3391 .rm_mc_addr = hclgevf_rm_mc_addr, 3392 .get_stats = hclgevf_get_stats, 3393 .update_stats = hclgevf_update_stats, 3394 .get_strings = hclgevf_get_strings, 3395 .get_sset_count = hclgevf_get_sset_count, 3396 .get_rss_key_size = hclge_comm_get_rss_key_size, 3397 .get_rss = hclgevf_get_rss, 3398 .set_rss = hclgevf_set_rss, 3399 .get_rss_tuple = hclgevf_get_rss_tuple, 3400 .set_rss_tuple = hclgevf_set_rss_tuple, 3401 .get_tc_size = hclgevf_get_tc_size, 3402 .get_fw_version = hclgevf_get_fw_version, 3403 .set_vlan_filter = hclgevf_set_vlan_filter, 3404 .enable_vlan_filter = hclgevf_enable_vlan_filter, 3405 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3406 .reset_event = hclgevf_reset_event, 3407 .set_default_reset_request = hclgevf_set_def_reset_request, 3408 .set_channels = hclgevf_set_channels, 3409 .get_channels = hclgevf_get_channels, 3410 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3411 .get_regs_len = hclgevf_get_regs_len, 3412 .get_regs = hclgevf_get_regs, 3413 .get_status = hclgevf_get_status, 3414 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3415 .get_media_type = hclgevf_get_media_type, 3416 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3417 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3418 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3419 .set_gro_en = hclgevf_gro_en, 3420 .set_mtu = hclgevf_set_mtu, 3421 .get_global_queue_id = hclgevf_get_qid_global, 3422 .set_timer_task = hclgevf_set_timer_task, 3423 .get_link_mode = hclgevf_get_link_mode, 3424 .set_promisc_mode = hclgevf_set_promisc_mode, 3425 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3426 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3427 }; 3428 3429 static struct hnae3_ae_algo ae_algovf = { 3430 .ops = &hclgevf_ops, 3431 .pdev_id_table = ae_algovf_pci_tbl, 3432 }; 3433 3434 static int __init hclgevf_init(void) 3435 { 3436 pr_info("%s is initializing\n", HCLGEVF_NAME); 3437 3438 hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 3439 if (!hclgevf_wq) { 3440 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3441 return -ENOMEM; 3442 } 3443 3444 hnae3_register_ae_algo(&ae_algovf); 3445 3446 return 0; 3447 } 3448 3449 static void __exit hclgevf_exit(void) 3450 { 3451 hnae3_unregister_ae_algo(&ae_algovf); 3452 destroy_workqueue(hclgevf_wq); 3453 } 3454 module_init(hclgevf_init); 3455 module_exit(hclgevf_exit); 3456 3457 MODULE_LICENSE("GPL"); 3458 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3459 MODULE_DESCRIPTION("HCLGEVF Driver"); 3460 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3461