1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_TM_H 5 #define __HCLGE_TM_H 6 7 #include <linux/types.h> 8 9 /* MAC Pause */ 10 #define HCLGE_TX_MAC_PAUSE_EN_MSK BIT(0) 11 #define HCLGE_RX_MAC_PAUSE_EN_MSK BIT(1) 12 13 #define HCLGE_TM_PORT_BASE_MODE_MSK BIT(0) 14 15 #define HCLGE_DEFAULT_PAUSE_TRANS_GAP 0xFF 16 #define HCLGE_DEFAULT_PAUSE_TRANS_TIME 0xFFFF 17 18 /* SP or DWRR */ 19 #define HCLGE_TM_TX_SCHD_DWRR_MSK BIT(0) 20 #define HCLGE_TM_TX_SCHD_SP_MSK (0xFE) 21 22 struct hclge_pg_to_pri_link_cmd { 23 u8 pg_id; 24 u8 rsvd1[3]; 25 u8 pri_bit_map; 26 }; 27 28 struct hclge_qs_to_pri_link_cmd { 29 __le16 qs_id; 30 __le16 rsvd; 31 u8 priority; 32 #define HCLGE_TM_QS_PRI_LINK_VLD_MSK BIT(0) 33 u8 link_vld; 34 }; 35 36 struct hclge_nq_to_qs_link_cmd { 37 __le16 nq_id; 38 __le16 rsvd; 39 #define HCLGE_TM_Q_QS_LINK_VLD_MSK BIT(10) 40 __le16 qset_id; 41 }; 42 43 struct hclge_pg_weight_cmd { 44 u8 pg_id; 45 u8 dwrr; 46 }; 47 48 struct hclge_priority_weight_cmd { 49 u8 pri_id; 50 u8 dwrr; 51 }; 52 53 struct hclge_qs_weight_cmd { 54 __le16 qs_id; 55 u8 dwrr; 56 }; 57 58 struct hclge_ets_tc_weight_cmd { 59 u8 tc_weight[HNAE3_MAX_TC]; 60 u8 weight_offset; 61 u8 rsvd[15]; 62 }; 63 64 #define HCLGE_TM_SHAP_IR_B_MSK GENMASK(7, 0) 65 #define HCLGE_TM_SHAP_IR_B_LSH 0 66 #define HCLGE_TM_SHAP_IR_U_MSK GENMASK(11, 8) 67 #define HCLGE_TM_SHAP_IR_U_LSH 8 68 #define HCLGE_TM_SHAP_IR_S_MSK GENMASK(15, 12) 69 #define HCLGE_TM_SHAP_IR_S_LSH 12 70 #define HCLGE_TM_SHAP_BS_B_MSK GENMASK(20, 16) 71 #define HCLGE_TM_SHAP_BS_B_LSH 16 72 #define HCLGE_TM_SHAP_BS_S_MSK GENMASK(25, 21) 73 #define HCLGE_TM_SHAP_BS_S_LSH 21 74 75 enum hclge_shap_bucket { 76 HCLGE_TM_SHAP_C_BUCKET = 0, 77 HCLGE_TM_SHAP_P_BUCKET, 78 }; 79 80 struct hclge_pri_shapping_cmd { 81 u8 pri_id; 82 u8 rsvd[3]; 83 __le32 pri_shapping_para; 84 }; 85 86 struct hclge_pg_shapping_cmd { 87 u8 pg_id; 88 u8 rsvd[3]; 89 __le32 pg_shapping_para; 90 }; 91 92 #define HCLGE_BP_GRP_NUM 32 93 #define HCLGE_BP_SUB_GRP_ID_S 0 94 #define HCLGE_BP_SUB_GRP_ID_M GENMASK(4, 0) 95 #define HCLGE_BP_GRP_ID_S 5 96 #define HCLGE_BP_GRP_ID_M GENMASK(9, 5) 97 struct hclge_bp_to_qs_map_cmd { 98 u8 tc_id; 99 u8 rsvd[2]; 100 u8 qs_group_id; 101 __le32 qs_bit_map; 102 u32 rsvd1; 103 }; 104 105 struct hclge_pfc_en_cmd { 106 u8 tx_rx_en_bitmap; 107 u8 pri_en_bitmap; 108 }; 109 110 struct hclge_cfg_pause_param_cmd { 111 u8 mac_addr[ETH_ALEN]; 112 u8 pause_trans_gap; 113 u8 rsvd; 114 __le16 pause_trans_time; 115 u8 rsvd1[6]; 116 /* extra mac address to do double check for pause frame */ 117 u8 mac_addr_extra[ETH_ALEN]; 118 u16 rsvd2; 119 }; 120 121 struct hclge_pfc_stats_cmd { 122 __le64 pkt_num[3]; 123 }; 124 125 struct hclge_port_shapping_cmd { 126 __le32 port_shapping_para; 127 }; 128 129 #define hclge_tm_set_field(dest, string, val) \ 130 hnae3_set_field((dest), \ 131 (HCLGE_TM_SHAP_##string##_MSK), \ 132 (HCLGE_TM_SHAP_##string##_LSH), val) 133 #define hclge_tm_get_field(src, string) \ 134 hnae3_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \ 135 (HCLGE_TM_SHAP_##string##_LSH)) 136 137 int hclge_tm_schd_init(struct hclge_dev *hdev); 138 int hclge_pause_setup_hw(struct hclge_dev *hdev); 139 int hclge_tm_schd_mode_hw(struct hclge_dev *hdev); 140 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc); 141 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc); 142 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev); 143 int hclge_tm_map_cfg(struct hclge_dev *hdev); 144 int hclge_tm_init_hw(struct hclge_dev *hdev); 145 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx); 146 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr); 147 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats); 148 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats); 149 #endif 150