1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_TM_H 5 #define __HCLGE_TM_H 6 7 #include <linux/types.h> 8 9 /* MAC Pause */ 10 #define HCLGE_TX_MAC_PAUSE_EN_MSK BIT(0) 11 #define HCLGE_RX_MAC_PAUSE_EN_MSK BIT(1) 12 13 #define HCLGE_TM_PORT_BASE_MODE_MSK BIT(0) 14 15 #define HCLGE_DEFAULT_PAUSE_TRANS_GAP 0x7F 16 #define HCLGE_DEFAULT_PAUSE_TRANS_TIME 0xFFFF 17 18 /* SP or DWRR */ 19 #define HCLGE_TM_TX_SCHD_DWRR_MSK BIT(0) 20 #define HCLGE_TM_TX_SCHD_SP_MSK (0xFE) 21 22 #define HCLGE_ETHER_MAX_RATE 100000 23 24 struct hclge_pg_to_pri_link_cmd { 25 u8 pg_id; 26 u8 rsvd1[3]; 27 u8 pri_bit_map; 28 }; 29 30 struct hclge_qs_to_pri_link_cmd { 31 __le16 qs_id; 32 __le16 rsvd; 33 u8 priority; 34 #define HCLGE_TM_QS_PRI_LINK_VLD_MSK BIT(0) 35 u8 link_vld; 36 }; 37 38 struct hclge_nq_to_qs_link_cmd { 39 __le16 nq_id; 40 __le16 rsvd; 41 #define HCLGE_TM_Q_QS_LINK_VLD_MSK BIT(10) 42 #define HCLGE_TM_QS_ID_L_MSK GENMASK(9, 0) 43 #define HCLGE_TM_QS_ID_L_S 0 44 #define HCLGE_TM_QS_ID_H_MSK GENMASK(14, 10) 45 #define HCLGE_TM_QS_ID_H_S 10 46 #define HCLGE_TM_QS_ID_H_EXT_S 11 47 #define HCLGE_TM_QS_ID_H_EXT_MSK GENMASK(15, 11) 48 __le16 qset_id; 49 }; 50 51 struct hclge_tqp_tx_queue_tc_cmd { 52 __le16 queue_id; 53 __le16 rsvd; 54 u8 tc_id; 55 u8 rev[3]; 56 }; 57 58 struct hclge_pg_weight_cmd { 59 u8 pg_id; 60 u8 dwrr; 61 }; 62 63 struct hclge_priority_weight_cmd { 64 u8 pri_id; 65 u8 dwrr; 66 }; 67 68 struct hclge_qs_weight_cmd { 69 __le16 qs_id; 70 u8 dwrr; 71 }; 72 73 struct hclge_ets_tc_weight_cmd { 74 u8 tc_weight[HNAE3_MAX_TC]; 75 u8 weight_offset; 76 u8 rsvd[15]; 77 }; 78 79 #define HCLGE_TM_SHAP_IR_B_MSK GENMASK(7, 0) 80 #define HCLGE_TM_SHAP_IR_B_LSH 0 81 #define HCLGE_TM_SHAP_IR_U_MSK GENMASK(11, 8) 82 #define HCLGE_TM_SHAP_IR_U_LSH 8 83 #define HCLGE_TM_SHAP_IR_S_MSK GENMASK(15, 12) 84 #define HCLGE_TM_SHAP_IR_S_LSH 12 85 #define HCLGE_TM_SHAP_BS_B_MSK GENMASK(20, 16) 86 #define HCLGE_TM_SHAP_BS_B_LSH 16 87 #define HCLGE_TM_SHAP_BS_S_MSK GENMASK(25, 21) 88 #define HCLGE_TM_SHAP_BS_S_LSH 21 89 90 enum hclge_shap_bucket { 91 HCLGE_TM_SHAP_C_BUCKET = 0, 92 HCLGE_TM_SHAP_P_BUCKET, 93 }; 94 95 /* set bit HCLGE_TM_RATE_VLD to 1 means use 'rate' to config shaping */ 96 #define HCLGE_TM_RATE_VLD 0 97 98 struct hclge_pri_shapping_cmd { 99 u8 pri_id; 100 u8 rsvd[3]; 101 __le32 pri_shapping_para; 102 u8 flag; 103 u8 rsvd1[3]; 104 __le32 pri_rate; 105 }; 106 107 struct hclge_pg_shapping_cmd { 108 u8 pg_id; 109 u8 rsvd[3]; 110 __le32 pg_shapping_para; 111 u8 flag; 112 u8 rsvd1[3]; 113 __le32 pg_rate; 114 }; 115 116 struct hclge_qs_shapping_cmd { 117 __le16 qs_id; 118 u8 rsvd[2]; 119 __le32 qs_shapping_para; 120 u8 flag; 121 u8 rsvd1[3]; 122 __le32 qs_rate; 123 }; 124 125 #define HCLGE_BP_GRP_NUM 32 126 #define HCLGE_BP_SUB_GRP_ID_S 0 127 #define HCLGE_BP_SUB_GRP_ID_M GENMASK(4, 0) 128 #define HCLGE_BP_GRP_ID_S 5 129 #define HCLGE_BP_GRP_ID_M GENMASK(9, 5) 130 131 #define HCLGE_BP_EXT_GRP_NUM 40 132 #define HCLGE_BP_EXT_GRP_ID_S 5 133 #define HCLGE_BP_EXT_GRP_ID_M GENMASK(10, 5) 134 135 struct hclge_bp_to_qs_map_cmd { 136 u8 tc_id; 137 u8 rsvd[2]; 138 u8 qs_group_id; 139 __le32 qs_bit_map; 140 u32 rsvd1; 141 }; 142 143 struct hclge_pfc_en_cmd { 144 u8 tx_rx_en_bitmap; 145 u8 pri_en_bitmap; 146 }; 147 148 struct hclge_cfg_pause_param_cmd { 149 u8 mac_addr[ETH_ALEN]; 150 u8 pause_trans_gap; 151 u8 rsvd; 152 __le16 pause_trans_time; 153 u8 rsvd1[6]; 154 /* extra mac address to do double check for pause frame */ 155 u8 mac_addr_extra[ETH_ALEN]; 156 u16 rsvd2; 157 }; 158 159 struct hclge_pfc_stats_cmd { 160 __le64 pkt_num[3]; 161 }; 162 163 struct hclge_port_shapping_cmd { 164 __le32 port_shapping_para; 165 u8 flag; 166 u8 rsvd[3]; 167 __le32 port_rate; 168 }; 169 170 struct hclge_shaper_ir_para { 171 u8 ir_b; /* IR_B parameter of IR shaper */ 172 u8 ir_u; /* IR_U parameter of IR shaper */ 173 u8 ir_s; /* IR_S parameter of IR shaper */ 174 }; 175 176 #define hclge_tm_set_field(dest, string, val) \ 177 hnae3_set_field((dest), \ 178 (HCLGE_TM_SHAP_##string##_MSK), \ 179 (HCLGE_TM_SHAP_##string##_LSH), val) 180 #define hclge_tm_get_field(src, string) \ 181 hnae3_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \ 182 (HCLGE_TM_SHAP_##string##_LSH)) 183 184 int hclge_tm_schd_init(struct hclge_dev *hdev); 185 int hclge_tm_vport_map_update(struct hclge_dev *hdev); 186 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init); 187 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev); 188 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc); 189 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc); 190 void hclge_tm_pfc_info_update(struct hclge_dev *hdev); 191 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev); 192 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init); 193 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx); 194 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr); 195 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats); 196 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats); 197 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate); 198 199 #endif 200