1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 6 #include "hclge_cmd.h" 7 #include "hclge_main.h" 8 #include "hclge_tm.h" 9 10 enum hclge_shaper_level { 11 HCLGE_SHAPER_LVL_PRI = 0, 12 HCLGE_SHAPER_LVL_PG = 1, 13 HCLGE_SHAPER_LVL_PORT = 2, 14 HCLGE_SHAPER_LVL_QSET = 3, 15 HCLGE_SHAPER_LVL_CNT = 4, 16 HCLGE_SHAPER_LVL_VF = 0, 17 HCLGE_SHAPER_LVL_PF = 1, 18 }; 19 20 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3 21 #define HCLGE_TM_PFC_NUM_GET_PER_CMD 3 22 23 #define HCLGE_SHAPER_BS_U_DEF 5 24 #define HCLGE_SHAPER_BS_S_DEF 20 25 26 /* hclge_shaper_para_calc: calculate ir parameter for the shaper 27 * @ir: Rate to be config, its unit is Mbps 28 * @shaper_level: the shaper level. eg: port, pg, priority, queueset 29 * @ir_para: parameters of IR shaper 30 * @max_tm_rate: max tm rate is available to config 31 * 32 * the formula: 33 * 34 * IR_b * (2 ^ IR_u) * 8 35 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps) 36 * Tick * (2 ^ IR_s) 37 * 38 * @return: 0: calculate sucessful, negative: fail 39 */ 40 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level, 41 struct hclge_shaper_ir_para *ir_para, 42 u32 max_tm_rate) 43 { 44 #define DIVISOR_CLK (1000 * 8) 45 #define DIVISOR_IR_B_126 (126 * DIVISOR_CLK) 46 47 static const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = { 48 6 * 256, /* Prioriy level */ 49 6 * 32, /* Prioriy group level */ 50 6 * 8, /* Port level */ 51 6 * 256 /* Qset level */ 52 }; 53 u8 ir_u_calc = 0; 54 u8 ir_s_calc = 0; 55 u32 ir_calc; 56 u32 tick; 57 58 /* Calc tick */ 59 if (shaper_level >= HCLGE_SHAPER_LVL_CNT || 60 ir > max_tm_rate) 61 return -EINVAL; 62 63 tick = tick_array[shaper_level]; 64 65 /** 66 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0 67 * the formula is changed to: 68 * 126 * 1 * 8 69 * ir_calc = ---------------- * 1000 70 * tick * 1 71 */ 72 ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick; 73 74 if (ir_calc == ir) { 75 ir_para->ir_b = 126; 76 ir_para->ir_u = 0; 77 ir_para->ir_s = 0; 78 79 return 0; 80 } else if (ir_calc > ir) { 81 /* Increasing the denominator to select ir_s value */ 82 while (ir_calc >= ir && ir) { 83 ir_s_calc++; 84 ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc)); 85 } 86 87 ir_para->ir_b = (ir * tick * (1 << ir_s_calc) + 88 (DIVISOR_CLK >> 1)) / DIVISOR_CLK; 89 } else { 90 /* Increasing the numerator to select ir_u value */ 91 u32 numerator; 92 93 while (ir_calc < ir) { 94 ir_u_calc++; 95 numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc); 96 ir_calc = (numerator + (tick >> 1)) / tick; 97 } 98 99 if (ir_calc == ir) { 100 ir_para->ir_b = 126; 101 } else { 102 u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc); 103 ir_para->ir_b = (ir * tick + (denominator >> 1)) / 104 denominator; 105 } 106 } 107 108 ir_para->ir_u = ir_u_calc; 109 ir_para->ir_s = ir_s_calc; 110 111 return 0; 112 } 113 114 static int hclge_pfc_stats_get(struct hclge_dev *hdev, 115 enum hclge_opcode_type opcode, u64 *stats) 116 { 117 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM]; 118 int ret, i, j; 119 120 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT || 121 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT)) 122 return -EINVAL; 123 124 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) { 125 hclge_cmd_setup_basic_desc(&desc[i], opcode, true); 126 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 127 } 128 129 hclge_cmd_setup_basic_desc(&desc[i], opcode, true); 130 131 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM); 132 if (ret) 133 return ret; 134 135 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) { 136 struct hclge_pfc_stats_cmd *pfc_stats = 137 (struct hclge_pfc_stats_cmd *)desc[i].data; 138 139 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) { 140 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j; 141 142 if (index < HCLGE_MAX_TC_NUM) 143 stats[index] = 144 le64_to_cpu(pfc_stats->pkt_num[j]); 145 } 146 } 147 return 0; 148 } 149 150 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats) 151 { 152 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats); 153 } 154 155 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats) 156 { 157 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats); 158 } 159 160 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx) 161 { 162 struct hclge_desc desc; 163 164 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false); 165 166 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) | 167 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0)); 168 169 return hclge_cmd_send(&hdev->hw, &desc, 1); 170 } 171 172 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap, 173 u8 pfc_bitmap) 174 { 175 struct hclge_desc desc; 176 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data; 177 178 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false); 179 180 pfc->tx_rx_en_bitmap = tx_rx_bitmap; 181 pfc->pri_en_bitmap = pfc_bitmap; 182 183 return hclge_cmd_send(&hdev->hw, &desc, 1); 184 } 185 186 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr, 187 u8 pause_trans_gap, u16 pause_trans_time) 188 { 189 struct hclge_cfg_pause_param_cmd *pause_param; 190 struct hclge_desc desc; 191 192 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 193 194 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false); 195 196 ether_addr_copy(pause_param->mac_addr, addr); 197 ether_addr_copy(pause_param->mac_addr_extra, addr); 198 pause_param->pause_trans_gap = pause_trans_gap; 199 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time); 200 201 return hclge_cmd_send(&hdev->hw, &desc, 1); 202 } 203 204 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr) 205 { 206 struct hclge_cfg_pause_param_cmd *pause_param; 207 struct hclge_desc desc; 208 u16 trans_time; 209 u8 trans_gap; 210 int ret; 211 212 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 213 214 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 215 216 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 217 if (ret) 218 return ret; 219 220 trans_gap = pause_param->pause_trans_gap; 221 trans_time = le16_to_cpu(pause_param->pause_trans_time); 222 223 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, trans_time); 224 } 225 226 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id) 227 { 228 u8 tc; 229 230 tc = hdev->tm_info.prio_tc[pri_id]; 231 232 if (tc >= hdev->tm_info.num_tc) 233 return -EINVAL; 234 235 /** 236 * the register for priority has four bytes, the first bytes includes 237 * priority0 and priority1, the higher 4bit stands for priority1 238 * while the lower 4bit stands for priority0, as below: 239 * first byte: | pri_1 | pri_0 | 240 * second byte: | pri_3 | pri_2 | 241 * third byte: | pri_5 | pri_4 | 242 * fourth byte: | pri_7 | pri_6 | 243 */ 244 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4); 245 246 return 0; 247 } 248 249 static int hclge_up_to_tc_map(struct hclge_dev *hdev) 250 { 251 struct hclge_desc desc; 252 u8 *pri = (u8 *)desc.data; 253 u8 pri_id; 254 int ret; 255 256 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false); 257 258 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) { 259 ret = hclge_fill_pri_array(hdev, pri, pri_id); 260 if (ret) 261 return ret; 262 } 263 264 return hclge_cmd_send(&hdev->hw, &desc, 1); 265 } 266 267 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev, 268 u8 pg_id, u8 pri_bit_map) 269 { 270 struct hclge_pg_to_pri_link_cmd *map; 271 struct hclge_desc desc; 272 273 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false); 274 275 map = (struct hclge_pg_to_pri_link_cmd *)desc.data; 276 277 map->pg_id = pg_id; 278 map->pri_bit_map = pri_bit_map; 279 280 return hclge_cmd_send(&hdev->hw, &desc, 1); 281 } 282 283 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev, 284 u16 qs_id, u8 pri) 285 { 286 struct hclge_qs_to_pri_link_cmd *map; 287 struct hclge_desc desc; 288 289 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false); 290 291 map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 292 293 map->qs_id = cpu_to_le16(qs_id); 294 map->priority = pri; 295 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK; 296 297 return hclge_cmd_send(&hdev->hw, &desc, 1); 298 } 299 300 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev, 301 u16 q_id, u16 qs_id) 302 { 303 struct hclge_nq_to_qs_link_cmd *map; 304 struct hclge_desc desc; 305 u16 qs_id_l; 306 u16 qs_id_h; 307 308 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false); 309 310 map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 311 312 map->nq_id = cpu_to_le16(q_id); 313 314 /* convert qs_id to the following format to support qset_id >= 1024 315 * qs_id: | 15 | 14 ~ 10 | 9 ~ 0 | 316 * / / \ \ 317 * / / \ \ 318 * qset_id: | 15 ~ 11 | 10 | 9 ~ 0 | 319 * | qs_id_h | vld | qs_id_l | 320 */ 321 qs_id_l = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_L_MSK, 322 HCLGE_TM_QS_ID_L_S); 323 qs_id_h = hnae3_get_field(qs_id, HCLGE_TM_QS_ID_H_MSK, 324 HCLGE_TM_QS_ID_H_S); 325 hnae3_set_field(qs_id, HCLGE_TM_QS_ID_L_MSK, HCLGE_TM_QS_ID_L_S, 326 qs_id_l); 327 hnae3_set_field(qs_id, HCLGE_TM_QS_ID_H_EXT_MSK, HCLGE_TM_QS_ID_H_EXT_S, 328 qs_id_h); 329 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK); 330 331 return hclge_cmd_send(&hdev->hw, &desc, 1); 332 } 333 334 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id, 335 u8 dwrr) 336 { 337 struct hclge_pg_weight_cmd *weight; 338 struct hclge_desc desc; 339 340 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false); 341 342 weight = (struct hclge_pg_weight_cmd *)desc.data; 343 344 weight->pg_id = pg_id; 345 weight->dwrr = dwrr; 346 347 return hclge_cmd_send(&hdev->hw, &desc, 1); 348 } 349 350 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id, 351 u8 dwrr) 352 { 353 struct hclge_priority_weight_cmd *weight; 354 struct hclge_desc desc; 355 356 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false); 357 358 weight = (struct hclge_priority_weight_cmd *)desc.data; 359 360 weight->pri_id = pri_id; 361 weight->dwrr = dwrr; 362 363 return hclge_cmd_send(&hdev->hw, &desc, 1); 364 } 365 366 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id, 367 u8 dwrr) 368 { 369 struct hclge_qs_weight_cmd *weight; 370 struct hclge_desc desc; 371 372 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false); 373 374 weight = (struct hclge_qs_weight_cmd *)desc.data; 375 376 weight->qs_id = cpu_to_le16(qs_id); 377 weight->dwrr = dwrr; 378 379 return hclge_cmd_send(&hdev->hw, &desc, 1); 380 } 381 382 static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s, 383 u8 bs_b, u8 bs_s) 384 { 385 u32 shapping_para = 0; 386 387 hclge_tm_set_field(shapping_para, IR_B, ir_b); 388 hclge_tm_set_field(shapping_para, IR_U, ir_u); 389 hclge_tm_set_field(shapping_para, IR_S, ir_s); 390 hclge_tm_set_field(shapping_para, BS_B, bs_b); 391 hclge_tm_set_field(shapping_para, BS_S, bs_s); 392 393 return shapping_para; 394 } 395 396 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev, 397 enum hclge_shap_bucket bucket, u8 pg_id, 398 u32 shapping_para, u32 rate) 399 { 400 struct hclge_pg_shapping_cmd *shap_cfg_cmd; 401 enum hclge_opcode_type opcode; 402 struct hclge_desc desc; 403 404 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING : 405 HCLGE_OPC_TM_PG_C_SHAPPING; 406 hclge_cmd_setup_basic_desc(&desc, opcode, false); 407 408 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 409 410 shap_cfg_cmd->pg_id = pg_id; 411 412 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para); 413 414 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 415 416 shap_cfg_cmd->pg_rate = cpu_to_le32(rate); 417 418 return hclge_cmd_send(&hdev->hw, &desc, 1); 419 } 420 421 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev) 422 { 423 struct hclge_port_shapping_cmd *shap_cfg_cmd; 424 struct hclge_shaper_ir_para ir_para; 425 struct hclge_desc desc; 426 u32 shapping_para; 427 int ret; 428 429 ret = hclge_shaper_para_calc(hdev->hw.mac.speed, HCLGE_SHAPER_LVL_PORT, 430 &ir_para, 431 hdev->ae_dev->dev_specs.max_tm_rate); 432 if (ret) 433 return ret; 434 435 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false); 436 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data; 437 438 shapping_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u, 439 ir_para.ir_s, 440 HCLGE_SHAPER_BS_U_DEF, 441 HCLGE_SHAPER_BS_S_DEF); 442 443 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para); 444 445 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 446 447 shap_cfg_cmd->port_rate = cpu_to_le32(hdev->hw.mac.speed); 448 449 return hclge_cmd_send(&hdev->hw, &desc, 1); 450 } 451 452 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev, 453 enum hclge_shap_bucket bucket, u8 pri_id, 454 u32 shapping_para, u32 rate) 455 { 456 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 457 enum hclge_opcode_type opcode; 458 struct hclge_desc desc; 459 460 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING : 461 HCLGE_OPC_TM_PRI_C_SHAPPING; 462 463 hclge_cmd_setup_basic_desc(&desc, opcode, false); 464 465 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 466 467 shap_cfg_cmd->pri_id = pri_id; 468 469 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para); 470 471 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 472 473 shap_cfg_cmd->pri_rate = cpu_to_le32(rate); 474 475 return hclge_cmd_send(&hdev->hw, &desc, 1); 476 } 477 478 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id) 479 { 480 struct hclge_desc desc; 481 482 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false); 483 484 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR) 485 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 486 else 487 desc.data[1] = 0; 488 489 desc.data[0] = cpu_to_le32(pg_id); 490 491 return hclge_cmd_send(&hdev->hw, &desc, 1); 492 } 493 494 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id) 495 { 496 struct hclge_desc desc; 497 498 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false); 499 500 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR) 501 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 502 else 503 desc.data[1] = 0; 504 505 desc.data[0] = cpu_to_le32(pri_id); 506 507 return hclge_cmd_send(&hdev->hw, &desc, 1); 508 } 509 510 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode) 511 { 512 struct hclge_desc desc; 513 514 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false); 515 516 if (mode == HCLGE_SCH_MODE_DWRR) 517 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK); 518 else 519 desc.data[1] = 0; 520 521 desc.data[0] = cpu_to_le32(qs_id); 522 523 return hclge_cmd_send(&hdev->hw, &desc, 1); 524 } 525 526 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id, 527 u32 bit_map) 528 { 529 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 530 struct hclge_desc desc; 531 532 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING, 533 false); 534 535 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 536 537 bp_to_qs_map_cmd->tc_id = tc; 538 bp_to_qs_map_cmd->qs_group_id = grp_id; 539 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map); 540 541 return hclge_cmd_send(&hdev->hw, &desc, 1); 542 } 543 544 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate) 545 { 546 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 547 struct hclge_qs_shapping_cmd *shap_cfg_cmd; 548 struct hclge_shaper_ir_para ir_para; 549 struct hclge_dev *hdev = vport->back; 550 struct hclge_desc desc; 551 u32 shaper_para; 552 int ret, i; 553 554 if (!max_tx_rate) 555 max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate; 556 557 ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET, 558 &ir_para, 559 hdev->ae_dev->dev_specs.max_tm_rate); 560 if (ret) 561 return ret; 562 563 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u, 564 ir_para.ir_s, 565 HCLGE_SHAPER_BS_U_DEF, 566 HCLGE_SHAPER_BS_S_DEF); 567 568 for (i = 0; i < kinfo->num_tc; i++) { 569 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG, 570 false); 571 572 shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data; 573 shap_cfg_cmd->qs_id = cpu_to_le16(vport->qs_offset + i); 574 shap_cfg_cmd->qs_shapping_para = cpu_to_le32(shaper_para); 575 576 hnae3_set_bit(shap_cfg_cmd->flag, HCLGE_TM_RATE_VLD, 1); 577 shap_cfg_cmd->qs_rate = cpu_to_le32(max_tx_rate); 578 579 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 580 if (ret) { 581 dev_err(&hdev->pdev->dev, 582 "vf%u, qs%u failed to set tx_rate:%d, ret=%d\n", 583 vport->vport_id, shap_cfg_cmd->qs_id, 584 max_tx_rate, ret); 585 return ret; 586 } 587 } 588 589 return 0; 590 } 591 592 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) 593 { 594 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 595 struct hclge_dev *hdev = vport->back; 596 u16 max_rss_size; 597 u8 i; 598 599 /* TC configuration is shared by PF/VF in one port, only allow 600 * one tc for VF for simplicity. VF's vport_id is non zero. 601 */ 602 kinfo->num_tc = vport->vport_id ? 1 : 603 min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc); 604 vport->qs_offset = (vport->vport_id ? HNAE3_MAX_TC : 0) + 605 (vport->vport_id ? (vport->vport_id - 1) : 0); 606 607 max_rss_size = min_t(u16, hdev->rss_size_max, 608 vport->alloc_tqps / kinfo->num_tc); 609 610 /* Set to user value, no larger than max_rss_size. */ 611 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 612 kinfo->req_rss_size <= max_rss_size) { 613 dev_info(&hdev->pdev->dev, "rss changes from %u to %u\n", 614 kinfo->rss_size, kinfo->req_rss_size); 615 kinfo->rss_size = kinfo->req_rss_size; 616 } else if (kinfo->rss_size > max_rss_size || 617 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) { 618 /* if user not set rss, the rss_size should compare with the 619 * valid msi numbers to ensure one to one map between tqp and 620 * irq as default. 621 */ 622 if (!kinfo->req_rss_size) 623 max_rss_size = min_t(u16, max_rss_size, 624 (hdev->num_nic_msi - 1) / 625 kinfo->num_tc); 626 627 /* Set to the maximum specification value (max_rss_size). */ 628 kinfo->rss_size = max_rss_size; 629 } 630 631 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 632 vport->dwrr = 100; /* 100 percent as init */ 633 vport->alloc_rss_size = kinfo->rss_size; 634 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit; 635 636 for (i = 0; i < HNAE3_MAX_TC; i++) { 637 if (hdev->hw_tc_map & BIT(i) && i < kinfo->num_tc) { 638 kinfo->tc_info[i].enable = true; 639 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; 640 kinfo->tc_info[i].tqp_count = kinfo->rss_size; 641 kinfo->tc_info[i].tc = i; 642 } else { 643 /* Set to default queue if TC is disable */ 644 kinfo->tc_info[i].enable = false; 645 kinfo->tc_info[i].tqp_offset = 0; 646 kinfo->tc_info[i].tqp_count = 1; 647 kinfo->tc_info[i].tc = 0; 648 } 649 } 650 651 memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc, 652 sizeof_field(struct hnae3_knic_private_info, prio_tc)); 653 } 654 655 static void hclge_tm_vport_info_update(struct hclge_dev *hdev) 656 { 657 struct hclge_vport *vport = hdev->vport; 658 u32 i; 659 660 for (i = 0; i < hdev->num_alloc_vport; i++) { 661 hclge_tm_vport_tc_info_update(vport); 662 663 vport++; 664 } 665 } 666 667 static void hclge_tm_tc_info_init(struct hclge_dev *hdev) 668 { 669 u8 i; 670 671 for (i = 0; i < hdev->tm_info.num_tc; i++) { 672 hdev->tm_info.tc_info[i].tc_id = i; 673 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR; 674 hdev->tm_info.tc_info[i].pgid = 0; 675 hdev->tm_info.tc_info[i].bw_limit = 676 hdev->tm_info.pg_info[0].bw_limit; 677 } 678 679 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 680 hdev->tm_info.prio_tc[i] = 681 (i >= hdev->tm_info.num_tc) ? 0 : i; 682 683 /* DCB is enabled if we have more than 1 TC or pfc_en is 684 * non-zero. 685 */ 686 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en) 687 hdev->flag |= HCLGE_FLAG_DCB_ENABLE; 688 else 689 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 690 } 691 692 static void hclge_tm_pg_info_init(struct hclge_dev *hdev) 693 { 694 #define BW_PERCENT 100 695 696 u8 i; 697 698 for (i = 0; i < hdev->tm_info.num_pg; i++) { 699 int k; 700 701 hdev->tm_info.pg_dwrr[i] = i ? 0 : BW_PERCENT; 702 703 hdev->tm_info.pg_info[i].pg_id = i; 704 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR; 705 706 hdev->tm_info.pg_info[i].bw_limit = 707 hdev->ae_dev->dev_specs.max_tm_rate; 708 709 if (i != 0) 710 continue; 711 712 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map; 713 for (k = 0; k < hdev->tm_info.num_tc; k++) 714 hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT; 715 } 716 } 717 718 static void hclge_pfc_info_init(struct hclge_dev *hdev) 719 { 720 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) { 721 if (hdev->fc_mode_last_time == HCLGE_FC_PFC) 722 dev_warn(&hdev->pdev->dev, 723 "DCB is disable, but last mode is FC_PFC\n"); 724 725 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 726 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) { 727 /* fc_mode_last_time record the last fc_mode when 728 * DCB is enabled, so that fc_mode can be set to 729 * the correct value when DCB is disabled. 730 */ 731 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 732 hdev->tm_info.fc_mode = HCLGE_FC_PFC; 733 } 734 } 735 736 static void hclge_tm_schd_info_init(struct hclge_dev *hdev) 737 { 738 hclge_tm_pg_info_init(hdev); 739 740 hclge_tm_tc_info_init(hdev); 741 742 hclge_tm_vport_info_update(hdev); 743 744 hclge_pfc_info_init(hdev); 745 } 746 747 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev) 748 { 749 int ret; 750 u32 i; 751 752 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 753 return 0; 754 755 for (i = 0; i < hdev->tm_info.num_pg; i++) { 756 /* Cfg mapping */ 757 ret = hclge_tm_pg_to_pri_map_cfg( 758 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map); 759 if (ret) 760 return ret; 761 } 762 763 return 0; 764 } 765 766 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev) 767 { 768 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; 769 struct hclge_shaper_ir_para ir_para; 770 u32 shaper_para; 771 int ret; 772 u32 i; 773 774 /* Cfg pg schd */ 775 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 776 return 0; 777 778 /* Pg to pri */ 779 for (i = 0; i < hdev->tm_info.num_pg; i++) { 780 u32 rate = hdev->tm_info.pg_info[i].bw_limit; 781 782 /* Calc shaper para */ 783 ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PG, 784 &ir_para, max_tm_rate); 785 if (ret) 786 return ret; 787 788 shaper_para = hclge_tm_get_shapping_para(0, 0, 0, 789 HCLGE_SHAPER_BS_U_DEF, 790 HCLGE_SHAPER_BS_S_DEF); 791 ret = hclge_tm_pg_shapping_cfg(hdev, 792 HCLGE_TM_SHAP_C_BUCKET, i, 793 shaper_para, rate); 794 if (ret) 795 return ret; 796 797 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, 798 ir_para.ir_u, 799 ir_para.ir_s, 800 HCLGE_SHAPER_BS_U_DEF, 801 HCLGE_SHAPER_BS_S_DEF); 802 ret = hclge_tm_pg_shapping_cfg(hdev, 803 HCLGE_TM_SHAP_P_BUCKET, i, 804 shaper_para, rate); 805 if (ret) 806 return ret; 807 } 808 809 return 0; 810 } 811 812 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev) 813 { 814 int ret; 815 u32 i; 816 817 /* cfg pg schd */ 818 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) 819 return 0; 820 821 /* pg to prio */ 822 for (i = 0; i < hdev->tm_info.num_pg; i++) { 823 /* Cfg dwrr */ 824 ret = hclge_tm_pg_weight_cfg(hdev, i, hdev->tm_info.pg_dwrr[i]); 825 if (ret) 826 return ret; 827 } 828 829 return 0; 830 } 831 832 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev, 833 struct hclge_vport *vport) 834 { 835 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 836 struct hnae3_queue **tqp = kinfo->tqp; 837 struct hnae3_tc_info *v_tc_info; 838 u32 i, j; 839 int ret; 840 841 for (i = 0; i < kinfo->num_tc; i++) { 842 v_tc_info = &kinfo->tc_info[i]; 843 for (j = 0; j < v_tc_info->tqp_count; j++) { 844 struct hnae3_queue *q = tqp[v_tc_info->tqp_offset + j]; 845 846 ret = hclge_tm_q_to_qs_map_cfg(hdev, 847 hclge_get_queue_id(q), 848 vport->qs_offset + i); 849 if (ret) 850 return ret; 851 } 852 } 853 854 return 0; 855 } 856 857 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev) 858 { 859 struct hclge_vport *vport = hdev->vport; 860 int ret; 861 u32 i, k; 862 863 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 864 /* Cfg qs -> pri mapping, one by one mapping */ 865 for (k = 0; k < hdev->num_alloc_vport; k++) { 866 struct hnae3_knic_private_info *kinfo = 867 &vport[k].nic.kinfo; 868 869 for (i = 0; i < kinfo->num_tc; i++) { 870 ret = hclge_tm_qs_to_pri_map_cfg( 871 hdev, vport[k].qs_offset + i, i); 872 if (ret) 873 return ret; 874 } 875 } 876 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) { 877 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */ 878 for (k = 0; k < hdev->num_alloc_vport; k++) 879 for (i = 0; i < HNAE3_MAX_TC; i++) { 880 ret = hclge_tm_qs_to_pri_map_cfg( 881 hdev, vport[k].qs_offset + i, k); 882 if (ret) 883 return ret; 884 } 885 } else { 886 return -EINVAL; 887 } 888 889 /* Cfg q -> qs mapping */ 890 for (i = 0; i < hdev->num_alloc_vport; i++) { 891 ret = hclge_vport_q_to_qs_map(hdev, vport); 892 if (ret) 893 return ret; 894 895 vport++; 896 } 897 898 return 0; 899 } 900 901 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev) 902 { 903 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; 904 struct hclge_shaper_ir_para ir_para; 905 u32 shaper_para; 906 int ret; 907 u32 i; 908 909 for (i = 0; i < hdev->tm_info.num_tc; i++) { 910 u32 rate = hdev->tm_info.tc_info[i].bw_limit; 911 912 ret = hclge_shaper_para_calc(rate, HCLGE_SHAPER_LVL_PRI, 913 &ir_para, max_tm_rate); 914 if (ret) 915 return ret; 916 917 shaper_para = hclge_tm_get_shapping_para(0, 0, 0, 918 HCLGE_SHAPER_BS_U_DEF, 919 HCLGE_SHAPER_BS_S_DEF); 920 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i, 921 shaper_para, rate); 922 if (ret) 923 return ret; 924 925 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, 926 ir_para.ir_u, 927 ir_para.ir_s, 928 HCLGE_SHAPER_BS_U_DEF, 929 HCLGE_SHAPER_BS_S_DEF); 930 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i, 931 shaper_para, rate); 932 if (ret) 933 return ret; 934 } 935 936 return 0; 937 } 938 939 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport) 940 { 941 struct hclge_dev *hdev = vport->back; 942 struct hclge_shaper_ir_para ir_para; 943 u32 shaper_para; 944 int ret; 945 946 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF, 947 &ir_para, 948 hdev->ae_dev->dev_specs.max_tm_rate); 949 if (ret) 950 return ret; 951 952 shaper_para = hclge_tm_get_shapping_para(0, 0, 0, 953 HCLGE_SHAPER_BS_U_DEF, 954 HCLGE_SHAPER_BS_S_DEF); 955 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, 956 vport->vport_id, shaper_para, 957 vport->bw_limit); 958 if (ret) 959 return ret; 960 961 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u, 962 ir_para.ir_s, 963 HCLGE_SHAPER_BS_U_DEF, 964 HCLGE_SHAPER_BS_S_DEF); 965 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, 966 vport->vport_id, shaper_para, 967 vport->bw_limit); 968 if (ret) 969 return ret; 970 971 return 0; 972 } 973 974 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport) 975 { 976 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 977 struct hclge_dev *hdev = vport->back; 978 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate; 979 struct hclge_shaper_ir_para ir_para; 980 u32 i; 981 int ret; 982 983 for (i = 0; i < kinfo->num_tc; i++) { 984 ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit, 985 HCLGE_SHAPER_LVL_QSET, 986 &ir_para, max_tm_rate); 987 if (ret) 988 return ret; 989 } 990 991 return 0; 992 } 993 994 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev) 995 { 996 struct hclge_vport *vport = hdev->vport; 997 int ret; 998 u32 i; 999 1000 /* Need config vport shaper */ 1001 for (i = 0; i < hdev->num_alloc_vport; i++) { 1002 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport); 1003 if (ret) 1004 return ret; 1005 1006 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport); 1007 if (ret) 1008 return ret; 1009 1010 vport++; 1011 } 1012 1013 return 0; 1014 } 1015 1016 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev) 1017 { 1018 int ret; 1019 1020 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1021 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev); 1022 if (ret) 1023 return ret; 1024 } else { 1025 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev); 1026 if (ret) 1027 return ret; 1028 } 1029 1030 return 0; 1031 } 1032 1033 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev) 1034 { 1035 struct hclge_vport *vport = hdev->vport; 1036 struct hclge_pg_info *pg_info; 1037 u8 dwrr; 1038 int ret; 1039 u32 i, k; 1040 1041 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1042 pg_info = 1043 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; 1044 dwrr = pg_info->tc_dwrr[i]; 1045 1046 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr); 1047 if (ret) 1048 return ret; 1049 1050 for (k = 0; k < hdev->num_alloc_vport; k++) { 1051 ret = hclge_tm_qs_weight_cfg( 1052 hdev, vport[k].qs_offset + i, 1053 vport[k].dwrr); 1054 if (ret) 1055 return ret; 1056 } 1057 } 1058 1059 return 0; 1060 } 1061 1062 static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev) 1063 { 1064 #define DEFAULT_TC_WEIGHT 1 1065 #define DEFAULT_TC_OFFSET 14 1066 1067 struct hclge_ets_tc_weight_cmd *ets_weight; 1068 struct hclge_desc desc; 1069 unsigned int i; 1070 1071 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false); 1072 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data; 1073 1074 for (i = 0; i < HNAE3_MAX_TC; i++) { 1075 struct hclge_pg_info *pg_info; 1076 1077 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT; 1078 1079 if (!(hdev->hw_tc_map & BIT(i))) 1080 continue; 1081 1082 pg_info = 1083 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid]; 1084 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i]; 1085 } 1086 1087 ets_weight->weight_offset = DEFAULT_TC_OFFSET; 1088 1089 return hclge_cmd_send(&hdev->hw, &desc, 1); 1090 } 1091 1092 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport) 1093 { 1094 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1095 struct hclge_dev *hdev = vport->back; 1096 int ret; 1097 u8 i; 1098 1099 /* Vf dwrr */ 1100 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr); 1101 if (ret) 1102 return ret; 1103 1104 /* Qset dwrr */ 1105 for (i = 0; i < kinfo->num_tc; i++) { 1106 ret = hclge_tm_qs_weight_cfg( 1107 hdev, vport->qs_offset + i, 1108 hdev->tm_info.pg_info[0].tc_dwrr[i]); 1109 if (ret) 1110 return ret; 1111 } 1112 1113 return 0; 1114 } 1115 1116 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev) 1117 { 1118 struct hclge_vport *vport = hdev->vport; 1119 int ret; 1120 u32 i; 1121 1122 for (i = 0; i < hdev->num_alloc_vport; i++) { 1123 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport); 1124 if (ret) 1125 return ret; 1126 1127 vport++; 1128 } 1129 1130 return 0; 1131 } 1132 1133 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev) 1134 { 1135 int ret; 1136 1137 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1138 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev); 1139 if (ret) 1140 return ret; 1141 1142 if (!hnae3_dev_dcb_supported(hdev)) 1143 return 0; 1144 1145 ret = hclge_tm_ets_tc_dwrr_cfg(hdev); 1146 if (ret == -EOPNOTSUPP) { 1147 dev_warn(&hdev->pdev->dev, 1148 "fw %08x does't support ets tc weight cmd\n", 1149 hdev->fw_version); 1150 ret = 0; 1151 } 1152 1153 return ret; 1154 } else { 1155 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev); 1156 if (ret) 1157 return ret; 1158 } 1159 1160 return 0; 1161 } 1162 1163 static int hclge_tm_map_cfg(struct hclge_dev *hdev) 1164 { 1165 int ret; 1166 1167 ret = hclge_up_to_tc_map(hdev); 1168 if (ret) 1169 return ret; 1170 1171 ret = hclge_tm_pg_to_pri_map(hdev); 1172 if (ret) 1173 return ret; 1174 1175 return hclge_tm_pri_q_qs_cfg(hdev); 1176 } 1177 1178 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev) 1179 { 1180 int ret; 1181 1182 ret = hclge_tm_port_shaper_cfg(hdev); 1183 if (ret) 1184 return ret; 1185 1186 ret = hclge_tm_pg_shaper_cfg(hdev); 1187 if (ret) 1188 return ret; 1189 1190 return hclge_tm_pri_shaper_cfg(hdev); 1191 } 1192 1193 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev) 1194 { 1195 int ret; 1196 1197 ret = hclge_tm_pg_dwrr_cfg(hdev); 1198 if (ret) 1199 return ret; 1200 1201 return hclge_tm_pri_dwrr_cfg(hdev); 1202 } 1203 1204 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev) 1205 { 1206 int ret; 1207 u8 i; 1208 1209 /* Only being config on TC-Based scheduler mode */ 1210 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) 1211 return 0; 1212 1213 for (i = 0; i < hdev->tm_info.num_pg; i++) { 1214 ret = hclge_tm_pg_schd_mode_cfg(hdev, i); 1215 if (ret) 1216 return ret; 1217 } 1218 1219 return 0; 1220 } 1221 1222 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport) 1223 { 1224 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1225 struct hclge_dev *hdev = vport->back; 1226 int ret; 1227 u8 i; 1228 1229 if (vport->vport_id >= HNAE3_MAX_TC) 1230 return -EINVAL; 1231 1232 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id); 1233 if (ret) 1234 return ret; 1235 1236 for (i = 0; i < kinfo->num_tc; i++) { 1237 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode; 1238 1239 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i, 1240 sch_mode); 1241 if (ret) 1242 return ret; 1243 } 1244 1245 return 0; 1246 } 1247 1248 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev) 1249 { 1250 struct hclge_vport *vport = hdev->vport; 1251 int ret; 1252 u8 i, k; 1253 1254 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) { 1255 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1256 ret = hclge_tm_pri_schd_mode_cfg(hdev, i); 1257 if (ret) 1258 return ret; 1259 1260 for (k = 0; k < hdev->num_alloc_vport; k++) { 1261 ret = hclge_tm_qs_schd_mode_cfg( 1262 hdev, vport[k].qs_offset + i, 1263 HCLGE_SCH_MODE_DWRR); 1264 if (ret) 1265 return ret; 1266 } 1267 } 1268 } else { 1269 for (i = 0; i < hdev->num_alloc_vport; i++) { 1270 ret = hclge_tm_schd_mode_vnet_base_cfg(vport); 1271 if (ret) 1272 return ret; 1273 1274 vport++; 1275 } 1276 } 1277 1278 return 0; 1279 } 1280 1281 static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev) 1282 { 1283 int ret; 1284 1285 ret = hclge_tm_lvl2_schd_mode_cfg(hdev); 1286 if (ret) 1287 return ret; 1288 1289 return hclge_tm_lvl34_schd_mode_cfg(hdev); 1290 } 1291 1292 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev) 1293 { 1294 int ret; 1295 1296 /* Cfg tm mapping */ 1297 ret = hclge_tm_map_cfg(hdev); 1298 if (ret) 1299 return ret; 1300 1301 /* Cfg tm shaper */ 1302 ret = hclge_tm_shaper_cfg(hdev); 1303 if (ret) 1304 return ret; 1305 1306 /* Cfg dwrr */ 1307 ret = hclge_tm_dwrr_cfg(hdev); 1308 if (ret) 1309 return ret; 1310 1311 /* Cfg schd mode for each level schd */ 1312 return hclge_tm_schd_mode_hw(hdev); 1313 } 1314 1315 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev) 1316 { 1317 struct hclge_mac *mac = &hdev->hw.mac; 1318 1319 return hclge_pause_param_cfg(hdev, mac->mac_addr, 1320 HCLGE_DEFAULT_PAUSE_TRANS_GAP, 1321 HCLGE_DEFAULT_PAUSE_TRANS_TIME); 1322 } 1323 1324 static int hclge_pfc_setup_hw(struct hclge_dev *hdev) 1325 { 1326 u8 enable_bitmap = 0; 1327 1328 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 1329 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK | 1330 HCLGE_RX_MAC_PAUSE_EN_MSK; 1331 1332 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap, 1333 hdev->tm_info.pfc_en); 1334 } 1335 1336 /* for the queues that use for backpress, divides to several groups, 1337 * each group contains 32 queue sets, which can be represented by u32 bitmap. 1338 */ 1339 static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc) 1340 { 1341 u16 grp_id_shift = HCLGE_BP_GRP_ID_S; 1342 u16 grp_id_mask = HCLGE_BP_GRP_ID_M; 1343 u8 grp_num = HCLGE_BP_GRP_NUM; 1344 int i; 1345 1346 if (hdev->num_tqps > HCLGE_TQP_MAX_SIZE_DEV_V2) { 1347 grp_num = HCLGE_BP_EXT_GRP_NUM; 1348 grp_id_mask = HCLGE_BP_EXT_GRP_ID_M; 1349 grp_id_shift = HCLGE_BP_EXT_GRP_ID_S; 1350 } 1351 1352 for (i = 0; i < grp_num; i++) { 1353 u32 qs_bitmap = 0; 1354 int k, ret; 1355 1356 for (k = 0; k < hdev->num_alloc_vport; k++) { 1357 struct hclge_vport *vport = &hdev->vport[k]; 1358 u16 qs_id = vport->qs_offset + tc; 1359 u8 grp, sub_grp; 1360 1361 grp = hnae3_get_field(qs_id, grp_id_mask, grp_id_shift); 1362 sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M, 1363 HCLGE_BP_SUB_GRP_ID_S); 1364 if (i == grp) 1365 qs_bitmap |= (1 << sub_grp); 1366 } 1367 1368 ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap); 1369 if (ret) 1370 return ret; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev) 1377 { 1378 bool tx_en, rx_en; 1379 1380 switch (hdev->tm_info.fc_mode) { 1381 case HCLGE_FC_NONE: 1382 tx_en = false; 1383 rx_en = false; 1384 break; 1385 case HCLGE_FC_RX_PAUSE: 1386 tx_en = false; 1387 rx_en = true; 1388 break; 1389 case HCLGE_FC_TX_PAUSE: 1390 tx_en = true; 1391 rx_en = false; 1392 break; 1393 case HCLGE_FC_FULL: 1394 tx_en = true; 1395 rx_en = true; 1396 break; 1397 case HCLGE_FC_PFC: 1398 tx_en = false; 1399 rx_en = false; 1400 break; 1401 default: 1402 tx_en = true; 1403 rx_en = true; 1404 } 1405 1406 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 1407 } 1408 1409 static int hclge_tm_bp_setup(struct hclge_dev *hdev) 1410 { 1411 int ret; 1412 int i; 1413 1414 for (i = 0; i < hdev->tm_info.num_tc; i++) { 1415 ret = hclge_bp_setup_hw(hdev, i); 1416 if (ret) 1417 return ret; 1418 } 1419 1420 return 0; 1421 } 1422 1423 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init) 1424 { 1425 int ret; 1426 1427 ret = hclge_pause_param_setup_hw(hdev); 1428 if (ret) 1429 return ret; 1430 1431 ret = hclge_mac_pause_setup_hw(hdev); 1432 if (ret) 1433 return ret; 1434 1435 /* Only DCB-supported dev supports qset back pressure and pfc cmd */ 1436 if (!hnae3_dev_dcb_supported(hdev)) 1437 return 0; 1438 1439 /* GE MAC does not support PFC, when driver is initializing and MAC 1440 * is in GE Mode, ignore the error here, otherwise initialization 1441 * will fail. 1442 */ 1443 ret = hclge_pfc_setup_hw(hdev); 1444 if (init && ret == -EOPNOTSUPP) 1445 dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n"); 1446 else if (ret) { 1447 dev_err(&hdev->pdev->dev, "config pfc failed! ret = %d\n", 1448 ret); 1449 return ret; 1450 } 1451 1452 return hclge_tm_bp_setup(hdev); 1453 } 1454 1455 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc) 1456 { 1457 struct hclge_vport *vport = hdev->vport; 1458 struct hnae3_knic_private_info *kinfo; 1459 u32 i, k; 1460 1461 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 1462 hdev->tm_info.prio_tc[i] = prio_tc[i]; 1463 1464 for (k = 0; k < hdev->num_alloc_vport; k++) { 1465 kinfo = &vport[k].nic.kinfo; 1466 kinfo->prio_tc[i] = prio_tc[i]; 1467 } 1468 } 1469 } 1470 1471 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc) 1472 { 1473 u8 bit_map = 0; 1474 u8 i; 1475 1476 hdev->tm_info.num_tc = num_tc; 1477 1478 for (i = 0; i < hdev->tm_info.num_tc; i++) 1479 bit_map |= BIT(i); 1480 1481 if (!bit_map) { 1482 bit_map = 1; 1483 hdev->tm_info.num_tc = 1; 1484 } 1485 1486 hdev->hw_tc_map = bit_map; 1487 1488 hclge_tm_schd_info_init(hdev); 1489 } 1490 1491 void hclge_tm_pfc_info_update(struct hclge_dev *hdev) 1492 { 1493 /* DCB is enabled if we have more than 1 TC or pfc_en is 1494 * non-zero. 1495 */ 1496 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en) 1497 hdev->flag |= HCLGE_FLAG_DCB_ENABLE; 1498 else 1499 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 1500 1501 hclge_pfc_info_init(hdev); 1502 } 1503 1504 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init) 1505 { 1506 int ret; 1507 1508 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) && 1509 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE)) 1510 return -ENOTSUPP; 1511 1512 ret = hclge_tm_schd_setup_hw(hdev); 1513 if (ret) 1514 return ret; 1515 1516 ret = hclge_pause_setup_hw(hdev, init); 1517 if (ret) 1518 return ret; 1519 1520 return 0; 1521 } 1522 1523 int hclge_tm_schd_init(struct hclge_dev *hdev) 1524 { 1525 /* fc_mode is HCLGE_FC_FULL on reset */ 1526 hdev->tm_info.fc_mode = HCLGE_FC_FULL; 1527 hdev->fc_mode_last_time = hdev->tm_info.fc_mode; 1528 1529 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE && 1530 hdev->tm_info.num_pg != 1) 1531 return -EINVAL; 1532 1533 hclge_tm_schd_info_init(hdev); 1534 1535 return hclge_tm_init_hw(hdev, true); 1536 } 1537 1538 int hclge_tm_vport_map_update(struct hclge_dev *hdev) 1539 { 1540 struct hclge_vport *vport = hdev->vport; 1541 int ret; 1542 1543 hclge_tm_vport_tc_info_update(vport); 1544 1545 ret = hclge_vport_q_to_qs_map(hdev, vport); 1546 if (ret) 1547 return ret; 1548 1549 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) 1550 return 0; 1551 1552 return hclge_tm_bp_setup(hdev); 1553 } 1554