1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2021 Hisilicon Limited. 3 4 #include <linux/skbuff.h> 5 #include "hclge_main.h" 6 #include "hnae3.h" 7 8 static int hclge_ptp_get_cycle(struct hclge_dev *hdev) 9 { 10 struct hclge_ptp *ptp = hdev->ptp; 11 12 ptp->cycle.quo = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG) & 13 HCLGE_PTP_CYCLE_QUO_MASK; 14 ptp->cycle.numer = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG); 15 ptp->cycle.den = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); 16 17 if (ptp->cycle.den == 0) { 18 dev_err(&hdev->pdev->dev, "invalid ptp cycle denominator!\n"); 19 return -EINVAL; 20 } 21 22 return 0; 23 } 24 25 static int hclge_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 26 { 27 struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); 28 struct hclge_ptp_cycle *cycle = &hdev->ptp->cycle; 29 u64 adj_val, adj_base; 30 unsigned long flags; 31 u32 quo, numerator; 32 33 adj_base = (u64)cycle->quo * (u64)cycle->den + (u64)cycle->numer; 34 adj_val = adjust_by_scaled_ppm(adj_base, scaled_ppm); 35 36 /* This clock cycle is defined by three part: quotient, numerator 37 * and denominator. For example, 2.5ns, the quotient is 2, 38 * denominator is fixed to ptp->cycle.den, and numerator 39 * is 0.5 * ptp->cycle.den. 40 */ 41 quo = div_u64_rem(adj_val, cycle->den, &numerator); 42 43 spin_lock_irqsave(&hdev->ptp->lock, flags); 44 writel(quo & HCLGE_PTP_CYCLE_QUO_MASK, 45 hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG); 46 writel(numerator, hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG); 47 writel(cycle->den, hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); 48 writel(HCLGE_PTP_CYCLE_ADJ_EN, 49 hdev->ptp->io_base + HCLGE_PTP_CYCLE_CFG_REG); 50 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 51 52 return 0; 53 } 54 55 bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb) 56 { 57 struct hclge_vport *vport = hclge_get_vport(handle); 58 struct hclge_dev *hdev = vport->back; 59 struct hclge_ptp *ptp = hdev->ptp; 60 61 if (!ptp) 62 return false; 63 64 if (!test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) || 65 test_and_set_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) { 66 ptp->tx_skipped++; 67 return false; 68 } 69 70 ptp->tx_start = jiffies; 71 ptp->tx_skb = skb_get(skb); 72 ptp->tx_cnt++; 73 74 return true; 75 } 76 77 void hclge_ptp_clean_tx_hwts(struct hclge_dev *hdev) 78 { 79 struct sk_buff *skb = hdev->ptp->tx_skb; 80 struct skb_shared_hwtstamps hwts; 81 u32 hi, lo; 82 u64 ns; 83 84 ns = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_NSEC_REG) & 85 HCLGE_PTP_TX_TS_NSEC_MASK; 86 lo = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_L_REG); 87 hi = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_H_REG) & 88 HCLGE_PTP_TX_TS_SEC_H_MASK; 89 hdev->ptp->last_tx_seqid = readl(hdev->ptp->io_base + 90 HCLGE_PTP_TX_TS_SEQID_REG); 91 92 if (skb) { 93 hdev->ptp->tx_skb = NULL; 94 hdev->ptp->tx_cleaned++; 95 96 ns += (((u64)hi) << 32 | lo) * NSEC_PER_SEC; 97 hwts.hwtstamp = ns_to_ktime(ns); 98 skb_tstamp_tx(skb, &hwts); 99 dev_kfree_skb_any(skb); 100 } 101 102 clear_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state); 103 } 104 105 void hclge_ptp_get_rx_hwts(struct hnae3_handle *handle, struct sk_buff *skb, 106 u32 nsec, u32 sec) 107 { 108 struct hclge_vport *vport = hclge_get_vport(handle); 109 struct hclge_dev *hdev = vport->back; 110 unsigned long flags; 111 u64 ns = nsec; 112 u32 sec_h; 113 114 if (!hdev->ptp || !test_bit(HCLGE_PTP_FLAG_RX_EN, &hdev->ptp->flags)) 115 return; 116 117 /* Since the BD does not have enough space for the higher 16 bits of 118 * second, and this part will not change frequently, so read it 119 * from register. 120 */ 121 spin_lock_irqsave(&hdev->ptp->lock, flags); 122 sec_h = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_SEC_H_REG); 123 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 124 125 ns += (((u64)sec_h) << HCLGE_PTP_SEC_H_OFFSET | sec) * NSEC_PER_SEC; 126 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); 127 hdev->ptp->last_rx = jiffies; 128 hdev->ptp->rx_cnt++; 129 } 130 131 static int hclge_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, 132 struct ptp_system_timestamp *sts) 133 { 134 struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); 135 unsigned long flags; 136 u32 hi, lo; 137 u64 ns; 138 139 spin_lock_irqsave(&hdev->ptp->lock, flags); 140 ns = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_NSEC_REG); 141 hi = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_SEC_H_REG); 142 lo = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_SEC_L_REG); 143 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 144 145 ns += (((u64)hi) << HCLGE_PTP_SEC_H_OFFSET | lo) * NSEC_PER_SEC; 146 *ts = ns_to_timespec64(ns); 147 148 return 0; 149 } 150 151 static int hclge_ptp_settime(struct ptp_clock_info *ptp, 152 const struct timespec64 *ts) 153 { 154 struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); 155 unsigned long flags; 156 157 spin_lock_irqsave(&hdev->ptp->lock, flags); 158 writel(ts->tv_nsec, hdev->ptp->io_base + HCLGE_PTP_TIME_NSEC_REG); 159 writel(ts->tv_sec >> HCLGE_PTP_SEC_H_OFFSET, 160 hdev->ptp->io_base + HCLGE_PTP_TIME_SEC_H_REG); 161 writel(ts->tv_sec & HCLGE_PTP_SEC_L_MASK, 162 hdev->ptp->io_base + HCLGE_PTP_TIME_SEC_L_REG); 163 /* synchronize the time of phc */ 164 writel(HCLGE_PTP_TIME_SYNC_EN, 165 hdev->ptp->io_base + HCLGE_PTP_TIME_SYNC_REG); 166 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 167 168 return 0; 169 } 170 171 static int hclge_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 172 { 173 struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); 174 unsigned long flags; 175 bool is_neg = false; 176 u32 adj_val = 0; 177 178 if (delta < 0) { 179 adj_val |= HCLGE_PTP_TIME_NSEC_NEG; 180 delta = -delta; 181 is_neg = true; 182 } 183 184 if (delta > HCLGE_PTP_TIME_NSEC_MASK) { 185 struct timespec64 ts; 186 s64 ns; 187 188 hclge_ptp_gettimex(ptp, &ts, NULL); 189 ns = timespec64_to_ns(&ts); 190 ns = is_neg ? ns - delta : ns + delta; 191 ts = ns_to_timespec64(ns); 192 return hclge_ptp_settime(ptp, &ts); 193 } 194 195 adj_val |= delta & HCLGE_PTP_TIME_NSEC_MASK; 196 197 spin_lock_irqsave(&hdev->ptp->lock, flags); 198 writel(adj_val, hdev->ptp->io_base + HCLGE_PTP_TIME_NSEC_REG); 199 writel(HCLGE_PTP_TIME_ADJ_EN, 200 hdev->ptp->io_base + HCLGE_PTP_TIME_ADJ_REG); 201 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 202 203 return 0; 204 } 205 206 int hclge_ptp_get_cfg(struct hclge_dev *hdev, struct ifreq *ifr) 207 { 208 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state)) 209 return -EOPNOTSUPP; 210 211 return copy_to_user(ifr->ifr_data, &hdev->ptp->ts_cfg, 212 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 213 } 214 215 static int hclge_ptp_int_en(struct hclge_dev *hdev, bool en) 216 { 217 struct hclge_ptp_int_cmd *req; 218 struct hclge_desc desc; 219 int ret; 220 221 req = (struct hclge_ptp_int_cmd *)desc.data; 222 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PTP_INT_EN, false); 223 req->int_en = en ? 1 : 0; 224 225 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 226 if (ret) 227 dev_err(&hdev->pdev->dev, 228 "failed to %s ptp interrupt, ret = %d\n", 229 en ? "enable" : "disable", ret); 230 231 return ret; 232 } 233 234 int hclge_ptp_cfg_qry(struct hclge_dev *hdev, u32 *cfg) 235 { 236 struct hclge_ptp_cfg_cmd *req; 237 struct hclge_desc desc; 238 int ret; 239 240 req = (struct hclge_ptp_cfg_cmd *)desc.data; 241 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PTP_MODE_CFG, true); 242 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 243 if (ret) { 244 dev_err(&hdev->pdev->dev, 245 "failed to query ptp config, ret = %d\n", ret); 246 return ret; 247 } 248 249 *cfg = le32_to_cpu(req->cfg); 250 251 return 0; 252 } 253 254 static int hclge_ptp_cfg(struct hclge_dev *hdev, u32 cfg) 255 { 256 struct hclge_ptp_cfg_cmd *req; 257 struct hclge_desc desc; 258 int ret; 259 260 req = (struct hclge_ptp_cfg_cmd *)desc.data; 261 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PTP_MODE_CFG, false); 262 req->cfg = cpu_to_le32(cfg); 263 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 264 if (ret) 265 dev_err(&hdev->pdev->dev, 266 "failed to config ptp, ret = %d\n", ret); 267 268 return ret; 269 } 270 271 static int hclge_ptp_set_tx_mode(struct hwtstamp_config *cfg, 272 unsigned long *flags, u32 *ptp_cfg) 273 { 274 switch (cfg->tx_type) { 275 case HWTSTAMP_TX_OFF: 276 clear_bit(HCLGE_PTP_FLAG_TX_EN, flags); 277 break; 278 case HWTSTAMP_TX_ON: 279 set_bit(HCLGE_PTP_FLAG_TX_EN, flags); 280 *ptp_cfg |= HCLGE_PTP_TX_EN_B; 281 break; 282 default: 283 return -ERANGE; 284 } 285 286 return 0; 287 } 288 289 static int hclge_ptp_set_rx_mode(struct hwtstamp_config *cfg, 290 unsigned long *flags, u32 *ptp_cfg) 291 { 292 int rx_filter = cfg->rx_filter; 293 294 switch (cfg->rx_filter) { 295 case HWTSTAMP_FILTER_NONE: 296 clear_bit(HCLGE_PTP_FLAG_RX_EN, flags); 297 break; 298 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 299 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 300 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 301 set_bit(HCLGE_PTP_FLAG_RX_EN, flags); 302 *ptp_cfg |= HCLGE_PTP_RX_EN_B; 303 *ptp_cfg |= HCLGE_PTP_UDP_FULL_TYPE << HCLGE_PTP_UDP_EN_SHIFT; 304 rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 305 break; 306 case HWTSTAMP_FILTER_PTP_V2_EVENT: 307 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 308 case HWTSTAMP_FILTER_PTP_V2_SYNC: 309 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 310 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 311 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 312 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 313 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 314 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 315 set_bit(HCLGE_PTP_FLAG_RX_EN, flags); 316 *ptp_cfg |= HCLGE_PTP_RX_EN_B; 317 *ptp_cfg |= HCLGE_PTP_UDP_FULL_TYPE << HCLGE_PTP_UDP_EN_SHIFT; 318 *ptp_cfg |= HCLGE_PTP_MSG1_V2_DEFAULT << HCLGE_PTP_MSG1_SHIFT; 319 *ptp_cfg |= HCLGE_PTP_MSG0_V2_EVENT << HCLGE_PTP_MSG0_SHIFT; 320 *ptp_cfg |= HCLGE_PTP_MSG_TYPE_V2 << HCLGE_PTP_MSG_TYPE_SHIFT; 321 rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 322 break; 323 case HWTSTAMP_FILTER_ALL: 324 default: 325 return -ERANGE; 326 } 327 328 cfg->rx_filter = rx_filter; 329 330 return 0; 331 } 332 333 static int hclge_ptp_set_ts_mode(struct hclge_dev *hdev, 334 struct hwtstamp_config *cfg) 335 { 336 unsigned long flags = hdev->ptp->flags; 337 u32 ptp_cfg = 0; 338 int ret; 339 340 if (test_bit(HCLGE_PTP_FLAG_EN, &hdev->ptp->flags)) 341 ptp_cfg |= HCLGE_PTP_EN_B; 342 343 ret = hclge_ptp_set_tx_mode(cfg, &flags, &ptp_cfg); 344 if (ret) 345 return ret; 346 347 ret = hclge_ptp_set_rx_mode(cfg, &flags, &ptp_cfg); 348 if (ret) 349 return ret; 350 351 ret = hclge_ptp_cfg(hdev, ptp_cfg); 352 if (ret) 353 return ret; 354 355 hdev->ptp->flags = flags; 356 hdev->ptp->ptp_cfg = ptp_cfg; 357 358 return 0; 359 } 360 361 int hclge_ptp_set_cfg(struct hclge_dev *hdev, struct ifreq *ifr) 362 { 363 struct hwtstamp_config cfg; 364 int ret; 365 366 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state)) { 367 dev_err(&hdev->pdev->dev, "phc is unsupported\n"); 368 return -EOPNOTSUPP; 369 } 370 371 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 372 return -EFAULT; 373 374 ret = hclge_ptp_set_ts_mode(hdev, &cfg); 375 if (ret) 376 return ret; 377 378 hdev->ptp->ts_cfg = cfg; 379 380 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 381 } 382 383 int hclge_ptp_get_ts_info(struct hnae3_handle *handle, 384 struct kernel_ethtool_ts_info *info) 385 { 386 struct hclge_vport *vport = hclge_get_vport(handle); 387 struct hclge_dev *hdev = vport->back; 388 389 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state)) { 390 dev_err(&hdev->pdev->dev, "phc is unsupported\n"); 391 return -EOPNOTSUPP; 392 } 393 394 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 395 SOF_TIMESTAMPING_TX_HARDWARE | 396 SOF_TIMESTAMPING_RX_HARDWARE | 397 SOF_TIMESTAMPING_RAW_HARDWARE; 398 399 if (hdev->ptp->clock) 400 info->phc_index = ptp_clock_index(hdev->ptp->clock); 401 402 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 403 404 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 405 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 406 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 407 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ); 408 409 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 410 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 411 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | 412 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 413 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) | 414 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 415 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 416 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ); 417 418 return 0; 419 } 420 421 static int hclge_ptp_create_clock(struct hclge_dev *hdev) 422 { 423 struct hclge_ptp *ptp; 424 425 ptp = devm_kzalloc(&hdev->pdev->dev, sizeof(*ptp), GFP_KERNEL); 426 if (!ptp) 427 return -ENOMEM; 428 429 ptp->hdev = hdev; 430 snprintf(ptp->info.name, sizeof(ptp->info.name), "%s", 431 HCLGE_DRIVER_NAME); 432 ptp->info.owner = THIS_MODULE; 433 ptp->info.max_adj = HCLGE_PTP_CYCLE_ADJ_MAX; 434 ptp->info.n_ext_ts = 0; 435 ptp->info.pps = 0; 436 ptp->info.adjfine = hclge_ptp_adjfine; 437 ptp->info.adjtime = hclge_ptp_adjtime; 438 ptp->info.gettimex64 = hclge_ptp_gettimex; 439 ptp->info.settime64 = hclge_ptp_settime; 440 441 ptp->info.n_alarm = 0; 442 ptp->clock = ptp_clock_register(&ptp->info, &hdev->pdev->dev); 443 if (IS_ERR(ptp->clock)) { 444 dev_err(&hdev->pdev->dev, 445 "%d failed to register ptp clock, ret = %ld\n", 446 ptp->info.n_alarm, PTR_ERR(ptp->clock)); 447 return -ENODEV; 448 } else if (!ptp->clock) { 449 dev_err(&hdev->pdev->dev, "failed to register ptp clock\n"); 450 return -ENODEV; 451 } 452 453 spin_lock_init(&ptp->lock); 454 ptp->io_base = hdev->hw.hw.io_base + HCLGE_PTP_REG_OFFSET; 455 ptp->ts_cfg.rx_filter = HWTSTAMP_FILTER_NONE; 456 ptp->ts_cfg.tx_type = HWTSTAMP_TX_OFF; 457 hdev->ptp = ptp; 458 459 return 0; 460 } 461 462 static void hclge_ptp_destroy_clock(struct hclge_dev *hdev) 463 { 464 ptp_clock_unregister(hdev->ptp->clock); 465 hdev->ptp->clock = NULL; 466 devm_kfree(&hdev->pdev->dev, hdev->ptp); 467 hdev->ptp = NULL; 468 } 469 470 int hclge_ptp_init(struct hclge_dev *hdev) 471 { 472 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 473 struct timespec64 ts; 474 int ret; 475 476 if (!test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps)) 477 return 0; 478 479 if (!hdev->ptp) { 480 ret = hclge_ptp_create_clock(hdev); 481 if (ret) 482 return ret; 483 484 ret = hclge_ptp_get_cycle(hdev); 485 if (ret) 486 return ret; 487 } 488 489 ret = hclge_ptp_int_en(hdev, true); 490 if (ret) 491 goto out; 492 493 set_bit(HCLGE_PTP_FLAG_EN, &hdev->ptp->flags); 494 ret = hclge_ptp_adjfine(&hdev->ptp->info, 0); 495 if (ret) { 496 dev_err(&hdev->pdev->dev, 497 "failed to init freq, ret = %d\n", ret); 498 goto out; 499 } 500 501 ret = hclge_ptp_set_ts_mode(hdev, &hdev->ptp->ts_cfg); 502 if (ret) { 503 dev_err(&hdev->pdev->dev, 504 "failed to init ts mode, ret = %d\n", ret); 505 goto out; 506 } 507 508 ktime_get_real_ts64(&ts); 509 ret = hclge_ptp_settime(&hdev->ptp->info, &ts); 510 if (ret) { 511 dev_err(&hdev->pdev->dev, 512 "failed to init ts time, ret = %d\n", ret); 513 goto out; 514 } 515 516 set_bit(HCLGE_STATE_PTP_EN, &hdev->state); 517 dev_info(&hdev->pdev->dev, "phc initializes ok!\n"); 518 519 return 0; 520 521 out: 522 hclge_ptp_destroy_clock(hdev); 523 524 return ret; 525 } 526 527 void hclge_ptp_uninit(struct hclge_dev *hdev) 528 { 529 struct hclge_ptp *ptp = hdev->ptp; 530 531 if (!ptp) 532 return; 533 534 hclge_ptp_int_en(hdev, false); 535 clear_bit(HCLGE_STATE_PTP_EN, &hdev->state); 536 clear_bit(HCLGE_PTP_FLAG_EN, &ptp->flags); 537 ptp->ts_cfg.rx_filter = HWTSTAMP_FILTER_NONE; 538 ptp->ts_cfg.tx_type = HWTSTAMP_TX_OFF; 539 540 if (hclge_ptp_set_ts_mode(hdev, &ptp->ts_cfg)) 541 dev_err(&hdev->pdev->dev, "failed to disable phc\n"); 542 543 if (ptp->tx_skb) { 544 struct sk_buff *skb = ptp->tx_skb; 545 546 ptp->tx_skb = NULL; 547 dev_kfree_skb_any(skb); 548 } 549 550 hclge_ptp_destroy_clock(hdev); 551 } 552