1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 12 #include "hclge_cmd.h" 13 #include "hnae3.h" 14 15 #define HCLGE_MOD_VERSION "1.0" 16 #define HCLGE_DRIVER_NAME "hclge" 17 18 #define HCLGE_MAX_PF_NUM 8 19 20 #define HCLGE_VF_VPORT_START_NUM 1 21 22 #define HCLGE_RD_FIRST_STATS_NUM 2 23 #define HCLGE_RD_OTHER_STATS_NUM 4 24 25 #define HCLGE_INVALID_VPORT 0xffff 26 27 #define HCLGE_PF_CFG_BLOCK_SIZE 32 28 #define HCLGE_PF_CFG_DESC_NUM \ 29 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 30 31 #define HCLGE_VECTOR_REG_BASE 0x20000 32 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 33 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 34 35 #define HCLGE_VECTOR_REG_OFFSET 0x4 36 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 37 #define HCLGE_VECTOR_VF_OFFSET 0x100000 38 39 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 40 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 41 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 42 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010 43 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014 44 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 45 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C 46 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 47 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024 48 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028 49 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 50 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 51 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 52 53 /* bar registers for common func */ 54 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600 55 #define HCLGE_GRO_EN_REG 0x28000 56 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 57 58 /* bar registers for rcb */ 59 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 60 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 61 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 62 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 63 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 64 #define HCLGE_RING_RX_TAIL_REG 0x80018 65 #define HCLGE_RING_RX_HEAD_REG 0x8001C 66 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 67 #define HCLGE_RING_RX_OFFSET_REG 0x80024 68 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 69 #define HCLGE_RING_RX_STASH_REG 0x80030 70 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 71 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 72 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 73 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 74 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 75 #define HCLGE_RING_TX_TC_REG 0x80050 76 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 77 #define HCLGE_RING_TX_TAIL_REG 0x80058 78 #define HCLGE_RING_TX_HEAD_REG 0x8005C 79 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 80 #define HCLGE_RING_TX_OFFSET_REG 0x80064 81 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 82 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 83 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 84 #define HCLGE_RING_EN_REG 0x80090 85 86 /* bar registers for tqp interrupt */ 87 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 88 #define HCLGE_TQP_INTR_GL0_REG 0x20100 89 #define HCLGE_TQP_INTR_GL1_REG 0x20200 90 #define HCLGE_TQP_INTR_GL2_REG 0x20300 91 #define HCLGE_TQP_INTR_RL_REG 0x20900 92 93 #define HCLGE_RSS_IND_TBL_SIZE 512 94 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 95 #define HCLGE_RSS_KEY_SIZE 40 96 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 97 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 98 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 99 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 100 101 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 102 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 103 #define HCLGE_D_PORT_BIT BIT(0) 104 #define HCLGE_S_PORT_BIT BIT(1) 105 #define HCLGE_D_IP_BIT BIT(2) 106 #define HCLGE_S_IP_BIT BIT(3) 107 #define HCLGE_V_TAG_BIT BIT(4) 108 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 109 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT) 110 111 #define HCLGE_RSS_TC_SIZE_0 1 112 #define HCLGE_RSS_TC_SIZE_1 2 113 #define HCLGE_RSS_TC_SIZE_2 4 114 #define HCLGE_RSS_TC_SIZE_3 8 115 #define HCLGE_RSS_TC_SIZE_4 16 116 #define HCLGE_RSS_TC_SIZE_5 32 117 #define HCLGE_RSS_TC_SIZE_6 64 118 #define HCLGE_RSS_TC_SIZE_7 128 119 120 #define HCLGE_UMV_TBL_SIZE 3072 121 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 122 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 123 124 #define HCLGE_TQP_RESET_TRY_TIMES 200 125 126 #define HCLGE_PHY_PAGE_MDIX 0 127 #define HCLGE_PHY_PAGE_COPPER 0 128 129 /* Page Selection Reg. */ 130 #define HCLGE_PHY_PAGE_REG 22 131 132 /* Copper Specific Control Register */ 133 #define HCLGE_PHY_CSC_REG 16 134 135 /* Copper Specific Status Register */ 136 #define HCLGE_PHY_CSS_REG 17 137 138 #define HCLGE_PHY_MDIX_CTRL_S 5 139 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 140 141 #define HCLGE_PHY_MDIX_STATUS_B 6 142 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 143 144 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 145 146 /* Factor used to calculate offset and bitmap of VF num */ 147 #define HCLGE_VF_NUM_PER_CMD 64 148 149 #define HCLGE_MAX_QSET_NUM 1024 150 151 #define HCLGE_DBG_RESET_INFO_LEN 1024 152 153 enum HLCGE_PORT_TYPE { 154 HOST_PORT, 155 NETWORK_PORT 156 }; 157 158 #define PF_VPORT_ID 0 159 160 #define HCLGE_PF_ID_S 0 161 #define HCLGE_PF_ID_M GENMASK(2, 0) 162 #define HCLGE_VF_ID_S 3 163 #define HCLGE_VF_ID_M GENMASK(10, 3) 164 #define HCLGE_PORT_TYPE_B 11 165 #define HCLGE_NETWORK_PORT_ID_S 0 166 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 167 168 /* Reset related Registers */ 169 #define HCLGE_PF_OTHER_INT_REG 0x20600 170 #define HCLGE_MISC_RESET_STS_REG 0x20700 171 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 172 #define HCLGE_GLOBAL_RESET_REG 0x20A00 173 #define HCLGE_GLOBAL_RESET_BIT 0 174 #define HCLGE_CORE_RESET_BIT 1 175 #define HCLGE_IMP_RESET_BIT 2 176 #define HCLGE_RESET_INT_M GENMASK(7, 5) 177 #define HCLGE_FUN_RST_ING 0x20C00 178 #define HCLGE_FUN_RST_ING_B 0 179 180 /* Vector0 register bits define */ 181 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 182 #define HCLGE_VECTOR0_CORERESET_INT_B 6 183 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 184 185 /* Vector0 interrupt CMDQ event source register(RW) */ 186 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 187 /* CMDQ register bits for RX event(=MBX event) */ 188 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 189 190 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 191 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 192 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 193 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U 194 195 #define HCLGE_MAC_DEFAULT_FRAME \ 196 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 197 #define HCLGE_MAC_MIN_FRAME 64 198 #define HCLGE_MAC_MAX_FRAME 9728 199 200 #define HCLGE_SUPPORT_1G_BIT BIT(0) 201 #define HCLGE_SUPPORT_10G_BIT BIT(1) 202 #define HCLGE_SUPPORT_25G_BIT BIT(2) 203 #define HCLGE_SUPPORT_50G_BIT BIT(3) 204 #define HCLGE_SUPPORT_100G_BIT BIT(4) 205 /* to be compatible with exsit board */ 206 #define HCLGE_SUPPORT_40G_BIT BIT(5) 207 #define HCLGE_SUPPORT_100M_BIT BIT(6) 208 #define HCLGE_SUPPORT_10M_BIT BIT(7) 209 #define HCLGE_SUPPORT_200G_BIT BIT(8) 210 #define HCLGE_SUPPORT_GE \ 211 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 212 213 enum HCLGE_DEV_STATE { 214 HCLGE_STATE_REINITING, 215 HCLGE_STATE_DOWN, 216 HCLGE_STATE_DISABLED, 217 HCLGE_STATE_REMOVING, 218 HCLGE_STATE_NIC_REGISTERED, 219 HCLGE_STATE_ROCE_REGISTERED, 220 HCLGE_STATE_SERVICE_INITED, 221 HCLGE_STATE_RST_SERVICE_SCHED, 222 HCLGE_STATE_RST_HANDLING, 223 HCLGE_STATE_MBX_SERVICE_SCHED, 224 HCLGE_STATE_MBX_HANDLING, 225 HCLGE_STATE_ERR_SERVICE_SCHED, 226 HCLGE_STATE_STATISTICS_UPDATING, 227 HCLGE_STATE_CMD_DISABLE, 228 HCLGE_STATE_LINK_UPDATING, 229 HCLGE_STATE_RST_FAIL, 230 HCLGE_STATE_FD_TBL_CHANGED, 231 HCLGE_STATE_FD_CLEAR_ALL, 232 HCLGE_STATE_FD_USER_DEF_CHANGED, 233 HCLGE_STATE_MAX 234 }; 235 236 enum hclge_evt_cause { 237 HCLGE_VECTOR0_EVENT_RST, 238 HCLGE_VECTOR0_EVENT_MBX, 239 HCLGE_VECTOR0_EVENT_ERR, 240 HCLGE_VECTOR0_EVENT_OTHER, 241 }; 242 243 enum HCLGE_MAC_SPEED { 244 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 245 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 246 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 251 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 252 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 253 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 254 }; 255 256 enum HCLGE_MAC_DUPLEX { 257 HCLGE_MAC_HALF, 258 HCLGE_MAC_FULL 259 }; 260 261 #define QUERY_SFP_SPEED 0 262 #define QUERY_ACTIVE_SPEED 1 263 264 struct hclge_mac { 265 u8 mac_id; 266 u8 phy_addr; 267 u8 flag; 268 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 269 u8 mac_addr[ETH_ALEN]; 270 u8 autoneg; 271 u8 duplex; 272 u8 support_autoneg; 273 u8 speed_type; /* 0: sfp speed, 1: active speed */ 274 u32 speed; 275 u32 max_speed; 276 u32 speed_ability; /* speed ability supported by current media */ 277 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 278 u32 fec_mode; /* active fec mode */ 279 u32 user_fec_mode; 280 u32 fec_ability; 281 int link; /* store the link status of mac & phy (if phy exists) */ 282 struct phy_device *phydev; 283 struct mii_bus *mdio_bus; 284 phy_interface_t phy_if; 285 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 286 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 287 }; 288 289 struct hclge_hw { 290 void __iomem *io_base; 291 void __iomem *mem_base; 292 struct hclge_mac mac; 293 int num_vec; 294 struct hclge_cmq cmq; 295 }; 296 297 /* TQP stats */ 298 struct hlcge_tqp_stats { 299 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 300 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 301 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 302 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 303 }; 304 305 struct hclge_tqp { 306 /* copy of device pointer from pci_dev, 307 * used when perform DMA mapping 308 */ 309 struct device *dev; 310 struct hnae3_queue q; 311 struct hlcge_tqp_stats tqp_stats; 312 u16 index; /* Global index in a NIC controller */ 313 314 bool alloced; 315 }; 316 317 enum hclge_fc_mode { 318 HCLGE_FC_NONE, 319 HCLGE_FC_RX_PAUSE, 320 HCLGE_FC_TX_PAUSE, 321 HCLGE_FC_FULL, 322 HCLGE_FC_PFC, 323 HCLGE_FC_DEFAULT 324 }; 325 326 #define HCLGE_FILTER_TYPE_VF 0 327 #define HCLGE_FILTER_TYPE_PORT 1 328 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 329 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 330 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 331 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 332 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 333 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 334 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 335 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 336 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 337 338 enum hclge_vlan_fltr_cap { 339 HCLGE_VLAN_FLTR_DEF, 340 HCLGE_VLAN_FLTR_CAN_MDF, 341 }; 342 enum hclge_link_fail_code { 343 HCLGE_LF_NORMAL, 344 HCLGE_LF_REF_CLOCK_LOST, 345 HCLGE_LF_XSFP_TX_DISABLE, 346 HCLGE_LF_XSFP_ABSENT, 347 }; 348 349 #define HCLGE_LINK_STATUS_DOWN 0 350 #define HCLGE_LINK_STATUS_UP 1 351 352 #define HCLGE_PG_NUM 4 353 #define HCLGE_SCH_MODE_SP 0 354 #define HCLGE_SCH_MODE_DWRR 1 355 struct hclge_pg_info { 356 u8 pg_id; 357 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 358 u8 tc_bit_map; 359 u32 bw_limit; 360 u8 tc_dwrr[HNAE3_MAX_TC]; 361 }; 362 363 struct hclge_tc_info { 364 u8 tc_id; 365 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 366 u8 pgid; 367 u32 bw_limit; 368 }; 369 370 struct hclge_cfg { 371 u8 tc_num; 372 u8 vlan_fliter_cap; 373 u16 tqp_desc_num; 374 u16 rx_buf_len; 375 u16 vf_rss_size_max; 376 u16 pf_rss_size_max; 377 u8 phy_addr; 378 u8 media_type; 379 u8 mac_addr[ETH_ALEN]; 380 u8 default_speed; 381 u32 numa_node_map; 382 u16 speed_ability; 383 u16 umv_space; 384 }; 385 386 struct hclge_tm_info { 387 u8 num_tc; 388 u8 num_pg; /* It must be 1 if vNET-Base schd */ 389 u8 pg_dwrr[HCLGE_PG_NUM]; 390 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 391 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 392 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 393 enum hclge_fc_mode fc_mode; 394 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 395 u8 pfc_en; /* PFC enabled or not for user priority */ 396 }; 397 398 struct hclge_comm_stats_str { 399 char desc[ETH_GSTRING_LEN]; 400 unsigned long offset; 401 }; 402 403 /* mac stats ,opcode id: 0x0032 */ 404 struct hclge_mac_stats { 405 u64 mac_tx_mac_pause_num; 406 u64 mac_rx_mac_pause_num; 407 u64 mac_tx_pfc_pri0_pkt_num; 408 u64 mac_tx_pfc_pri1_pkt_num; 409 u64 mac_tx_pfc_pri2_pkt_num; 410 u64 mac_tx_pfc_pri3_pkt_num; 411 u64 mac_tx_pfc_pri4_pkt_num; 412 u64 mac_tx_pfc_pri5_pkt_num; 413 u64 mac_tx_pfc_pri6_pkt_num; 414 u64 mac_tx_pfc_pri7_pkt_num; 415 u64 mac_rx_pfc_pri0_pkt_num; 416 u64 mac_rx_pfc_pri1_pkt_num; 417 u64 mac_rx_pfc_pri2_pkt_num; 418 u64 mac_rx_pfc_pri3_pkt_num; 419 u64 mac_rx_pfc_pri4_pkt_num; 420 u64 mac_rx_pfc_pri5_pkt_num; 421 u64 mac_rx_pfc_pri6_pkt_num; 422 u64 mac_rx_pfc_pri7_pkt_num; 423 u64 mac_tx_total_pkt_num; 424 u64 mac_tx_total_oct_num; 425 u64 mac_tx_good_pkt_num; 426 u64 mac_tx_bad_pkt_num; 427 u64 mac_tx_good_oct_num; 428 u64 mac_tx_bad_oct_num; 429 u64 mac_tx_uni_pkt_num; 430 u64 mac_tx_multi_pkt_num; 431 u64 mac_tx_broad_pkt_num; 432 u64 mac_tx_undersize_pkt_num; 433 u64 mac_tx_oversize_pkt_num; 434 u64 mac_tx_64_oct_pkt_num; 435 u64 mac_tx_65_127_oct_pkt_num; 436 u64 mac_tx_128_255_oct_pkt_num; 437 u64 mac_tx_256_511_oct_pkt_num; 438 u64 mac_tx_512_1023_oct_pkt_num; 439 u64 mac_tx_1024_1518_oct_pkt_num; 440 u64 mac_tx_1519_2047_oct_pkt_num; 441 u64 mac_tx_2048_4095_oct_pkt_num; 442 u64 mac_tx_4096_8191_oct_pkt_num; 443 u64 rsv0; 444 u64 mac_tx_8192_9216_oct_pkt_num; 445 u64 mac_tx_9217_12287_oct_pkt_num; 446 u64 mac_tx_12288_16383_oct_pkt_num; 447 u64 mac_tx_1519_max_good_oct_pkt_num; 448 u64 mac_tx_1519_max_bad_oct_pkt_num; 449 450 u64 mac_rx_total_pkt_num; 451 u64 mac_rx_total_oct_num; 452 u64 mac_rx_good_pkt_num; 453 u64 mac_rx_bad_pkt_num; 454 u64 mac_rx_good_oct_num; 455 u64 mac_rx_bad_oct_num; 456 u64 mac_rx_uni_pkt_num; 457 u64 mac_rx_multi_pkt_num; 458 u64 mac_rx_broad_pkt_num; 459 u64 mac_rx_undersize_pkt_num; 460 u64 mac_rx_oversize_pkt_num; 461 u64 mac_rx_64_oct_pkt_num; 462 u64 mac_rx_65_127_oct_pkt_num; 463 u64 mac_rx_128_255_oct_pkt_num; 464 u64 mac_rx_256_511_oct_pkt_num; 465 u64 mac_rx_512_1023_oct_pkt_num; 466 u64 mac_rx_1024_1518_oct_pkt_num; 467 u64 mac_rx_1519_2047_oct_pkt_num; 468 u64 mac_rx_2048_4095_oct_pkt_num; 469 u64 mac_rx_4096_8191_oct_pkt_num; 470 u64 rsv1; 471 u64 mac_rx_8192_9216_oct_pkt_num; 472 u64 mac_rx_9217_12287_oct_pkt_num; 473 u64 mac_rx_12288_16383_oct_pkt_num; 474 u64 mac_rx_1519_max_good_oct_pkt_num; 475 u64 mac_rx_1519_max_bad_oct_pkt_num; 476 477 u64 mac_tx_fragment_pkt_num; 478 u64 mac_tx_undermin_pkt_num; 479 u64 mac_tx_jabber_pkt_num; 480 u64 mac_tx_err_all_pkt_num; 481 u64 mac_tx_from_app_good_pkt_num; 482 u64 mac_tx_from_app_bad_pkt_num; 483 u64 mac_rx_fragment_pkt_num; 484 u64 mac_rx_undermin_pkt_num; 485 u64 mac_rx_jabber_pkt_num; 486 u64 mac_rx_fcs_err_pkt_num; 487 u64 mac_rx_send_app_good_pkt_num; 488 u64 mac_rx_send_app_bad_pkt_num; 489 u64 mac_tx_pfc_pause_pkt_num; 490 u64 mac_rx_pfc_pause_pkt_num; 491 u64 mac_tx_ctrl_pkt_num; 492 u64 mac_rx_ctrl_pkt_num; 493 }; 494 495 #define HCLGE_STATS_TIMER_INTERVAL 300UL 496 497 struct hclge_vlan_type_cfg { 498 u16 rx_ot_fst_vlan_type; 499 u16 rx_ot_sec_vlan_type; 500 u16 rx_in_fst_vlan_type; 501 u16 rx_in_sec_vlan_type; 502 u16 tx_ot_vlan_type; 503 u16 tx_in_vlan_type; 504 }; 505 506 enum HCLGE_FD_MODE { 507 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 508 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 509 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 510 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 511 }; 512 513 enum HCLGE_FD_KEY_TYPE { 514 HCLGE_FD_KEY_BASE_ON_PTYPE, 515 HCLGE_FD_KEY_BASE_ON_TUPLE, 516 }; 517 518 enum HCLGE_FD_STAGE { 519 HCLGE_FD_STAGE_1, 520 HCLGE_FD_STAGE_2, 521 MAX_STAGE_NUM, 522 }; 523 524 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 525 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 526 * tuples of non-tunnel packet 527 */ 528 enum HCLGE_FD_TUPLE { 529 OUTER_DST_MAC, 530 OUTER_SRC_MAC, 531 OUTER_VLAN_TAG_FST, 532 OUTER_VLAN_TAG_SEC, 533 OUTER_ETH_TYPE, 534 OUTER_L2_RSV, 535 OUTER_IP_TOS, 536 OUTER_IP_PROTO, 537 OUTER_SRC_IP, 538 OUTER_DST_IP, 539 OUTER_L3_RSV, 540 OUTER_SRC_PORT, 541 OUTER_DST_PORT, 542 OUTER_L4_RSV, 543 OUTER_TUN_VNI, 544 OUTER_TUN_FLOW_ID, 545 INNER_DST_MAC, 546 INNER_SRC_MAC, 547 INNER_VLAN_TAG_FST, 548 INNER_VLAN_TAG_SEC, 549 INNER_ETH_TYPE, 550 INNER_L2_RSV, 551 INNER_IP_TOS, 552 INNER_IP_PROTO, 553 INNER_SRC_IP, 554 INNER_DST_IP, 555 INNER_L3_RSV, 556 INNER_SRC_PORT, 557 INNER_DST_PORT, 558 INNER_L4_RSV, 559 MAX_TUPLE, 560 }; 561 562 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 563 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 564 565 enum HCLGE_FD_META_DATA { 566 PACKET_TYPE_ID, 567 IP_FRAGEMENT, 568 ROCE_TYPE, 569 NEXT_KEY, 570 VLAN_NUMBER, 571 SRC_VPORT, 572 DST_VPORT, 573 TUNNEL_PACKET, 574 MAX_META_DATA, 575 }; 576 577 enum HCLGE_FD_KEY_OPT { 578 KEY_OPT_U8, 579 KEY_OPT_LE16, 580 KEY_OPT_LE32, 581 KEY_OPT_MAC, 582 KEY_OPT_IP, 583 KEY_OPT_VNI, 584 }; 585 586 struct key_info { 587 u8 key_type; 588 u8 key_length; /* use bit as unit */ 589 enum HCLGE_FD_KEY_OPT key_opt; 590 int offset; 591 int moffset; 592 }; 593 594 #define MAX_KEY_LENGTH 400 595 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 596 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 597 #define MAX_META_DATA_LENGTH 32 598 599 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 600 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 601 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 602 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 603 604 /* assigned by firmware, the real filter number for each pf may be less */ 605 #define MAX_FD_FILTER_NUM 4096 606 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 607 608 enum HCLGE_FD_ACTIVE_RULE_TYPE { 609 HCLGE_FD_RULE_NONE, 610 HCLGE_FD_ARFS_ACTIVE, 611 HCLGE_FD_EP_ACTIVE, 612 HCLGE_FD_TC_FLOWER_ACTIVE, 613 }; 614 615 enum HCLGE_FD_PACKET_TYPE { 616 NIC_PACKET, 617 ROCE_PACKET, 618 }; 619 620 enum HCLGE_FD_ACTION { 621 HCLGE_FD_ACTION_SELECT_QUEUE, 622 HCLGE_FD_ACTION_DROP_PACKET, 623 HCLGE_FD_ACTION_SELECT_TC, 624 }; 625 626 enum HCLGE_FD_NODE_STATE { 627 HCLGE_FD_TO_ADD, 628 HCLGE_FD_TO_DEL, 629 HCLGE_FD_ACTIVE, 630 HCLGE_FD_DELETED, 631 }; 632 633 enum HCLGE_FD_USER_DEF_LAYER { 634 HCLGE_FD_USER_DEF_NONE, 635 HCLGE_FD_USER_DEF_L2, 636 HCLGE_FD_USER_DEF_L3, 637 HCLGE_FD_USER_DEF_L4, 638 }; 639 640 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 641 struct hclge_fd_user_def_cfg { 642 u16 ref_cnt; 643 u16 offset; 644 }; 645 646 struct hclge_fd_user_def_info { 647 enum HCLGE_FD_USER_DEF_LAYER layer; 648 u16 data; 649 u16 data_mask; 650 u16 offset; 651 }; 652 653 struct hclge_fd_key_cfg { 654 u8 key_sel; 655 u8 inner_sipv6_word_en; 656 u8 inner_dipv6_word_en; 657 u8 outer_sipv6_word_en; 658 u8 outer_dipv6_word_en; 659 u32 tuple_active; 660 u32 meta_data_active; 661 }; 662 663 struct hclge_fd_cfg { 664 u8 fd_mode; 665 u16 max_key_length; /* use bit as unit */ 666 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 667 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 668 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 669 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 670 }; 671 672 #define IPV4_INDEX 3 673 #define IPV6_SIZE 4 674 struct hclge_fd_rule_tuples { 675 u8 src_mac[ETH_ALEN]; 676 u8 dst_mac[ETH_ALEN]; 677 /* Be compatible for ip address of both ipv4 and ipv6. 678 * For ipv4 address, we store it in src/dst_ip[3]. 679 */ 680 u32 src_ip[IPV6_SIZE]; 681 u32 dst_ip[IPV6_SIZE]; 682 u16 src_port; 683 u16 dst_port; 684 u16 vlan_tag1; 685 u16 ether_proto; 686 u16 l2_user_def; 687 u16 l3_user_def; 688 u32 l4_user_def; 689 u8 ip_tos; 690 u8 ip_proto; 691 }; 692 693 struct hclge_fd_rule { 694 struct hlist_node rule_node; 695 struct hclge_fd_rule_tuples tuples; 696 struct hclge_fd_rule_tuples tuples_mask; 697 u32 unused_tuple; 698 u32 flow_type; 699 union { 700 struct { 701 unsigned long cookie; 702 u8 tc; 703 } cls_flower; 704 struct { 705 u16 flow_id; /* only used for arfs */ 706 } arfs; 707 struct { 708 struct hclge_fd_user_def_info user_def; 709 } ep; 710 }; 711 u16 queue_id; 712 u16 vf_id; 713 u16 location; 714 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 715 enum HCLGE_FD_NODE_STATE state; 716 u8 action; 717 }; 718 719 struct hclge_fd_ad_data { 720 u16 ad_id; 721 u8 drop_packet; 722 u8 forward_to_direct_queue; 723 u16 queue_id; 724 u8 use_counter; 725 u8 counter_id; 726 u8 use_next_stage; 727 u8 write_rule_id_to_bd; 728 u8 next_input_key; 729 u16 rule_id; 730 u16 tc_size; 731 u8 override_tc; 732 }; 733 734 enum HCLGE_MAC_NODE_STATE { 735 HCLGE_MAC_TO_ADD, 736 HCLGE_MAC_TO_DEL, 737 HCLGE_MAC_ACTIVE 738 }; 739 740 struct hclge_mac_node { 741 struct list_head node; 742 enum HCLGE_MAC_NODE_STATE state; 743 u8 mac_addr[ETH_ALEN]; 744 }; 745 746 enum HCLGE_MAC_ADDR_TYPE { 747 HCLGE_MAC_ADDR_UC, 748 HCLGE_MAC_ADDR_MC 749 }; 750 751 struct hclge_vport_vlan_cfg { 752 struct list_head node; 753 int hd_tbl_status; 754 u16 vlan_id; 755 }; 756 757 struct hclge_rst_stats { 758 u32 reset_done_cnt; /* the number of reset has completed */ 759 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 760 u32 pf_rst_cnt; /* the number of PF reset */ 761 u32 flr_rst_cnt; /* the number of FLR */ 762 u32 global_rst_cnt; /* the number of GLOBAL */ 763 u32 imp_rst_cnt; /* the number of IMP reset */ 764 u32 reset_cnt; /* the number of reset */ 765 u32 reset_fail_cnt; /* the number of reset fail */ 766 }; 767 768 /* time and register status when mac tunnel interruption occur */ 769 struct hclge_mac_tnl_stats { 770 u64 time; 771 u32 status; 772 }; 773 774 #define HCLGE_RESET_INTERVAL (10 * HZ) 775 #define HCLGE_WAIT_RESET_DONE 100 776 777 #pragma pack(1) 778 struct hclge_vf_vlan_cfg { 779 u8 mbx_cmd; 780 u8 subcode; 781 union { 782 struct { 783 u8 is_kill; 784 u16 vlan; 785 u16 proto; 786 }; 787 u8 enable; 788 }; 789 }; 790 791 #pragma pack() 792 793 /* For each bit of TCAM entry, it uses a pair of 'x' and 794 * 'y' to indicate which value to match, like below: 795 * ---------------------------------- 796 * | bit x | bit y | search value | 797 * ---------------------------------- 798 * | 0 | 0 | always hit | 799 * ---------------------------------- 800 * | 1 | 0 | match '0' | 801 * ---------------------------------- 802 * | 0 | 1 | match '1' | 803 * ---------------------------------- 804 * | 1 | 1 | invalid | 805 * ---------------------------------- 806 * Then for input key(k) and mask(v), we can calculate the value by 807 * the formulae: 808 * x = (~k) & v 809 * y = (k ^ ~v) & k 810 */ 811 #define calc_x(x, k, v) (x = ~(k) & (v)) 812 #define calc_y(y, k, v) \ 813 do { \ 814 const typeof(k) _k_ = (k); \ 815 const typeof(v) _v_ = (v); \ 816 (y) = (_k_ ^ ~_v_) & (_k_); \ 817 } while (0) 818 819 #define HCLGE_MAC_TNL_LOG_SIZE 8 820 #define HCLGE_VPORT_NUM 256 821 struct hclge_dev { 822 struct pci_dev *pdev; 823 struct hnae3_ae_dev *ae_dev; 824 struct hclge_hw hw; 825 struct hclge_misc_vector misc_vector; 826 struct hclge_mac_stats mac_stats; 827 unsigned long state; 828 unsigned long flr_state; 829 unsigned long last_reset_time; 830 831 enum hnae3_reset_type reset_type; 832 enum hnae3_reset_type reset_level; 833 unsigned long default_reset_request; 834 unsigned long reset_request; /* reset has been requested */ 835 unsigned long reset_pending; /* client rst is pending to be served */ 836 struct hclge_rst_stats rst_stats; 837 struct semaphore reset_sem; /* protect reset process */ 838 u32 fw_version; 839 u16 num_tqps; /* Num task queue pairs of this PF */ 840 u16 num_req_vfs; /* Num VFs requested for this PF */ 841 842 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 843 u16 alloc_rss_size; /* Allocated RSS task queue */ 844 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 845 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 846 847 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 848 u16 num_alloc_vport; /* Num vports this driver supports */ 849 u32 numa_node_mask; 850 u16 rx_buf_len; 851 u16 num_tx_desc; /* desc num of per tx queue */ 852 u16 num_rx_desc; /* desc num of per rx queue */ 853 u8 hw_tc_map; 854 enum hclge_fc_mode fc_mode_last_time; 855 u8 support_sfp_query; 856 857 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 858 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 859 u8 tx_sch_mode; 860 u8 tc_max; 861 u8 pfc_max; 862 863 u8 default_up; 864 u8 dcbx_cap; 865 struct hclge_tm_info tm_info; 866 867 u16 num_msi; 868 u16 num_msi_left; 869 u16 num_msi_used; 870 u32 base_msi_vector; 871 u16 *vector_status; 872 int *vector_irq; 873 u16 num_nic_msi; /* Num of nic vectors for this PF */ 874 u16 num_roce_msi; /* Num of roce vectors for this PF */ 875 int roce_base_vector; 876 877 unsigned long service_timer_period; 878 unsigned long service_timer_previous; 879 struct timer_list reset_timer; 880 struct delayed_work service_task; 881 882 bool cur_promisc; 883 int num_alloc_vfs; /* Actual number of VFs allocated */ 884 885 struct hclge_tqp *htqp; 886 struct hclge_vport *vport; 887 888 struct dentry *hclge_dbgfs; 889 890 struct hnae3_client *nic_client; 891 struct hnae3_client *roce_client; 892 893 #define HCLGE_FLAG_MAIN BIT(0) 894 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 895 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 896 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 897 u32 flag; 898 899 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 900 u32 tx_buf_size; /* Tx buffer size for each TC */ 901 u32 dv_buf_size; /* Dv buffer size for each TC */ 902 903 u32 mps; /* Max packet size */ 904 /* vport_lock protect resource shared by vports */ 905 struct mutex vport_lock; 906 907 struct hclge_vlan_type_cfg vlan_type_cfg; 908 909 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 910 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 911 912 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 913 914 struct hclge_fd_cfg fd_cfg; 915 struct hlist_head fd_rule_list; 916 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 917 u16 hclge_fd_rule_num; 918 unsigned long serv_processed_cnt; 919 unsigned long last_serv_processed; 920 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 921 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 922 u8 fd_en; 923 924 u16 wanted_umv_size; 925 /* max available unicast mac vlan space */ 926 u16 max_umv_size; 927 /* private unicast mac vlan space, it's same for PF and its VFs */ 928 u16 priv_umv_size; 929 /* unicast mac vlan space shared by PF and its VFs */ 930 u16 share_umv_size; 931 932 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 933 HCLGE_MAC_TNL_LOG_SIZE); 934 935 /* affinity mask and notify for misc interrupt */ 936 cpumask_t affinity_mask; 937 struct irq_affinity_notify affinity_notify; 938 }; 939 940 /* VPort level vlan tag configuration for TX direction */ 941 struct hclge_tx_vtag_cfg { 942 bool accept_tag1; /* Whether accept tag1 packet from host */ 943 bool accept_untag1; /* Whether accept untag1 packet from host */ 944 bool accept_tag2; 945 bool accept_untag2; 946 bool insert_tag1_en; /* Whether insert inner vlan tag */ 947 bool insert_tag2_en; /* Whether insert outer vlan tag */ 948 u16 default_tag1; /* The default inner vlan tag to insert */ 949 u16 default_tag2; /* The default outer vlan tag to insert */ 950 bool tag_shift_mode_en; 951 }; 952 953 /* VPort level vlan tag configuration for RX direction */ 954 struct hclge_rx_vtag_cfg { 955 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 956 bool strip_tag1_en; /* Whether strip inner vlan tag */ 957 bool strip_tag2_en; /* Whether strip outer vlan tag */ 958 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 959 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 960 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 961 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 962 }; 963 964 struct hclge_rss_tuple_cfg { 965 u8 ipv4_tcp_en; 966 u8 ipv4_udp_en; 967 u8 ipv4_sctp_en; 968 u8 ipv4_fragment_en; 969 u8 ipv6_tcp_en; 970 u8 ipv6_udp_en; 971 u8 ipv6_sctp_en; 972 u8 ipv6_fragment_en; 973 }; 974 975 enum HCLGE_VPORT_STATE { 976 HCLGE_VPORT_STATE_ALIVE, 977 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 978 HCLGE_VPORT_STATE_PROMISC_CHANGE, 979 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 980 HCLGE_VPORT_STATE_MAX 981 }; 982 983 struct hclge_vlan_info { 984 u16 vlan_proto; /* so far support 802.1Q only */ 985 u16 qos; 986 u16 vlan_tag; 987 }; 988 989 struct hclge_port_base_vlan_config { 990 u16 state; 991 struct hclge_vlan_info vlan_info; 992 }; 993 994 struct hclge_vf_info { 995 int link_state; 996 u8 mac[ETH_ALEN]; 997 u32 spoofchk; 998 u32 max_tx_rate; 999 u32 trusted; 1000 u8 request_uc_en; 1001 u8 request_mc_en; 1002 u8 request_bc_en; 1003 }; 1004 1005 struct hclge_vport { 1006 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 1007 1008 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 1009 /* User configured lookup table entries */ 1010 u16 *rss_indirection_tbl; 1011 int rss_algo; /* User configured hash algorithm */ 1012 /* User configured rss tuple sets */ 1013 struct hclge_rss_tuple_cfg rss_tuple_sets; 1014 1015 u16 alloc_rss_size; 1016 1017 u16 qs_offset; 1018 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 1019 u8 dwrr; 1020 1021 bool req_vlan_fltr_en; 1022 bool cur_vlan_fltr_en; 1023 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 1024 struct hclge_port_base_vlan_config port_base_vlan_cfg; 1025 struct hclge_tx_vtag_cfg txvlan_cfg; 1026 struct hclge_rx_vtag_cfg rxvlan_cfg; 1027 1028 u16 used_umv_num; 1029 1030 u16 vport_id; 1031 struct hclge_dev *back; /* Back reference to associated dev */ 1032 struct hnae3_handle nic; 1033 struct hnae3_handle roce; 1034 1035 unsigned long state; 1036 unsigned long last_active_jiffies; 1037 u32 mps; /* Max packet size */ 1038 struct hclge_vf_info vf_info; 1039 1040 u8 overflow_promisc_flags; 1041 u8 last_promisc_flags; 1042 1043 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1044 struct list_head uc_mac_list; /* Store VF unicast table */ 1045 struct list_head mc_mac_list; /* Store VF multicast table */ 1046 struct list_head vlan_list; /* Store VF vlan table */ 1047 }; 1048 1049 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1050 bool en_mc_pmc, bool en_bc_pmc); 1051 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1052 const unsigned char *addr); 1053 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1054 const unsigned char *addr); 1055 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1056 const unsigned char *addr); 1057 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1058 const unsigned char *addr); 1059 1060 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1061 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1062 int vector_id, bool en, 1063 struct hnae3_ring_chain_node *ring_chain); 1064 1065 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1066 { 1067 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 1068 1069 return tqp->index; 1070 } 1071 1072 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 1073 { 1074 return !!hdev->reset_pending; 1075 } 1076 1077 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1078 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 1079 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1080 u16 vlan_id, bool is_kill); 1081 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1082 1083 int hclge_buffer_alloc(struct hclge_dev *hdev); 1084 int hclge_rss_init_hw(struct hclge_dev *hdev); 1085 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 1086 1087 void hclge_mbx_handler(struct hclge_dev *hdev); 1088 int hclge_reset_tqp(struct hnae3_handle *handle); 1089 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1090 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1091 int hclge_vport_start(struct hclge_vport *vport); 1092 void hclge_vport_stop(struct hclge_vport *vport); 1093 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1094 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1095 char *buf, int len); 1096 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1097 int hclge_notify_client(struct hclge_dev *hdev, 1098 enum hnae3_reset_notify_type type); 1099 int hclge_update_mac_list(struct hclge_vport *vport, 1100 enum HCLGE_MAC_NODE_STATE state, 1101 enum HCLGE_MAC_ADDR_TYPE mac_type, 1102 const unsigned char *addr); 1103 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1104 const u8 *old_addr, const u8 *new_addr); 1105 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1106 enum HCLGE_MAC_ADDR_TYPE mac_type); 1107 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1108 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1109 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1110 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1111 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1112 struct hclge_vlan_info *vlan_info); 1113 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1114 u16 state, 1115 struct hclge_vlan_info *vlan_info); 1116 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1117 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, 1118 struct hclge_desc *desc); 1119 void hclge_report_hw_error(struct hclge_dev *hdev, 1120 enum hnae3_hw_error_type type); 1121 void hclge_inform_vf_promisc_info(struct hclge_vport *vport); 1122 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1123 int hclge_push_vf_link_status(struct hclge_vport *vport); 1124 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); 1125 #endif 1126