1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 11 #include "hclge_cmd.h" 12 #include "hnae3.h" 13 14 #define HCLGE_MOD_VERSION "1.0" 15 #define HCLGE_DRIVER_NAME "hclge" 16 17 #define HCLGE_MAX_PF_NUM 8 18 19 #define HCLGE_INVALID_VPORT 0xffff 20 21 #define HCLGE_PF_CFG_BLOCK_SIZE 32 22 #define HCLGE_PF_CFG_DESC_NUM \ 23 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 24 25 #define HCLGE_VECTOR_REG_BASE 0x20000 26 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 27 28 #define HCLGE_VECTOR_REG_OFFSET 0x4 29 #define HCLGE_VECTOR_VF_OFFSET 0x100000 30 31 #define HCLGE_RSS_IND_TBL_SIZE 512 32 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 33 #define HCLGE_RSS_KEY_SIZE 40 34 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 35 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 36 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 37 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 38 #define HCLGE_RSS_CFG_TBL_NUM \ 39 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE) 40 41 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 42 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 43 #define HCLGE_D_PORT_BIT BIT(0) 44 #define HCLGE_S_PORT_BIT BIT(1) 45 #define HCLGE_D_IP_BIT BIT(2) 46 #define HCLGE_S_IP_BIT BIT(3) 47 #define HCLGE_V_TAG_BIT BIT(4) 48 49 #define HCLGE_RSS_TC_SIZE_0 1 50 #define HCLGE_RSS_TC_SIZE_1 2 51 #define HCLGE_RSS_TC_SIZE_2 4 52 #define HCLGE_RSS_TC_SIZE_3 8 53 #define HCLGE_RSS_TC_SIZE_4 16 54 #define HCLGE_RSS_TC_SIZE_5 32 55 #define HCLGE_RSS_TC_SIZE_6 64 56 #define HCLGE_RSS_TC_SIZE_7 128 57 58 #define HCLGE_UMV_TBL_SIZE 3072 59 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 60 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 61 62 #define HCLGE_TQP_RESET_TRY_TIMES 10 63 64 #define HCLGE_PHY_PAGE_MDIX 0 65 #define HCLGE_PHY_PAGE_COPPER 0 66 67 /* Page Selection Reg. */ 68 #define HCLGE_PHY_PAGE_REG 22 69 70 /* Copper Specific Control Register */ 71 #define HCLGE_PHY_CSC_REG 16 72 73 /* Copper Specific Status Register */ 74 #define HCLGE_PHY_CSS_REG 17 75 76 #define HCLGE_PHY_MDIX_CTRL_S 5 77 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 78 79 #define HCLGE_PHY_MDIX_STATUS_B 6 80 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 81 82 /* Factor used to calculate offset and bitmap of VF num */ 83 #define HCLGE_VF_NUM_PER_CMD 64 84 #define HCLGE_VF_NUM_PER_BYTE 8 85 86 enum HLCGE_PORT_TYPE { 87 HOST_PORT, 88 NETWORK_PORT 89 }; 90 91 #define HCLGE_PF_ID_S 0 92 #define HCLGE_PF_ID_M GENMASK(2, 0) 93 #define HCLGE_VF_ID_S 3 94 #define HCLGE_VF_ID_M GENMASK(10, 3) 95 #define HCLGE_PORT_TYPE_B 11 96 #define HCLGE_NETWORK_PORT_ID_S 0 97 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 98 99 /* Reset related Registers */ 100 #define HCLGE_MISC_RESET_STS_REG 0x20700 101 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 102 #define HCLGE_GLOBAL_RESET_REG 0x20A00 103 #define HCLGE_GLOBAL_RESET_BIT 0 104 #define HCLGE_CORE_RESET_BIT 1 105 #define HCLGE_IMP_RESET_BIT 2 106 #define HCLGE_FUN_RST_ING 0x20C00 107 #define HCLGE_FUN_RST_ING_B 0 108 109 /* Vector0 register bits define */ 110 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 111 #define HCLGE_VECTOR0_CORERESET_INT_B 6 112 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 113 114 /* Vector0 interrupt CMDQ event source register(RW) */ 115 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 116 /* CMDQ register bits for RX event(=MBX event) */ 117 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 118 119 #define HCLGE_MAC_DEFAULT_FRAME \ 120 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN + ETH_DATA_LEN) 121 #define HCLGE_MAC_MIN_FRAME 64 122 #define HCLGE_MAC_MAX_FRAME 9728 123 124 #define HCLGE_SUPPORT_1G_BIT BIT(0) 125 #define HCLGE_SUPPORT_10G_BIT BIT(1) 126 #define HCLGE_SUPPORT_25G_BIT BIT(2) 127 #define HCLGE_SUPPORT_50G_BIT BIT(3) 128 #define HCLGE_SUPPORT_100G_BIT BIT(4) 129 130 enum HCLGE_DEV_STATE { 131 HCLGE_STATE_REINITING, 132 HCLGE_STATE_DOWN, 133 HCLGE_STATE_DISABLED, 134 HCLGE_STATE_REMOVING, 135 HCLGE_STATE_SERVICE_INITED, 136 HCLGE_STATE_SERVICE_SCHED, 137 HCLGE_STATE_RST_SERVICE_SCHED, 138 HCLGE_STATE_RST_HANDLING, 139 HCLGE_STATE_MBX_SERVICE_SCHED, 140 HCLGE_STATE_MBX_HANDLING, 141 HCLGE_STATE_STATISTICS_UPDATING, 142 HCLGE_STATE_CMD_DISABLE, 143 HCLGE_STATE_MAX 144 }; 145 146 enum hclge_evt_cause { 147 HCLGE_VECTOR0_EVENT_RST, 148 HCLGE_VECTOR0_EVENT_MBX, 149 HCLGE_VECTOR0_EVENT_OTHER, 150 }; 151 152 #define HCLGE_MPF_ENBALE 1 153 154 enum HCLGE_MAC_SPEED { 155 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 156 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 157 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 158 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 159 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 160 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 161 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 162 HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */ 163 }; 164 165 enum HCLGE_MAC_DUPLEX { 166 HCLGE_MAC_HALF, 167 HCLGE_MAC_FULL 168 }; 169 170 struct hclge_mac { 171 u8 phy_addr; 172 u8 flag; 173 u8 media_type; 174 u8 mac_addr[ETH_ALEN]; 175 u8 autoneg; 176 u8 duplex; 177 u32 speed; 178 int link; /* store the link status of mac & phy (if phy exit)*/ 179 struct phy_device *phydev; 180 struct mii_bus *mdio_bus; 181 phy_interface_t phy_if; 182 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 183 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 184 }; 185 186 struct hclge_hw { 187 void __iomem *io_base; 188 struct hclge_mac mac; 189 int num_vec; 190 struct hclge_cmq cmq; 191 }; 192 193 /* TQP stats */ 194 struct hlcge_tqp_stats { 195 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 196 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 197 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 198 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 199 }; 200 201 struct hclge_tqp { 202 /* copy of device pointer from pci_dev, 203 * used when perform DMA mapping 204 */ 205 struct device *dev; 206 struct hnae3_queue q; 207 struct hlcge_tqp_stats tqp_stats; 208 u16 index; /* Global index in a NIC controller */ 209 210 bool alloced; 211 }; 212 213 enum hclge_fc_mode { 214 HCLGE_FC_NONE, 215 HCLGE_FC_RX_PAUSE, 216 HCLGE_FC_TX_PAUSE, 217 HCLGE_FC_FULL, 218 HCLGE_FC_PFC, 219 HCLGE_FC_DEFAULT 220 }; 221 222 #define HCLGE_PG_NUM 4 223 #define HCLGE_SCH_MODE_SP 0 224 #define HCLGE_SCH_MODE_DWRR 1 225 struct hclge_pg_info { 226 u8 pg_id; 227 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 228 u8 tc_bit_map; 229 u32 bw_limit; 230 u8 tc_dwrr[HNAE3_MAX_TC]; 231 }; 232 233 struct hclge_tc_info { 234 u8 tc_id; 235 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 236 u8 pgid; 237 u32 bw_limit; 238 }; 239 240 struct hclge_cfg { 241 u8 vmdq_vport_num; 242 u8 tc_num; 243 u16 tqp_desc_num; 244 u16 rx_buf_len; 245 u16 rss_size_max; 246 u8 phy_addr; 247 u8 media_type; 248 u8 mac_addr[ETH_ALEN]; 249 u8 default_speed; 250 u32 numa_node_map; 251 u8 speed_ability; 252 u16 umv_space; 253 }; 254 255 struct hclge_tm_info { 256 u8 num_tc; 257 u8 num_pg; /* It must be 1 if vNET-Base schd */ 258 u8 pg_dwrr[HCLGE_PG_NUM]; 259 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 260 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 261 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 262 enum hclge_fc_mode fc_mode; 263 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 264 }; 265 266 struct hclge_comm_stats_str { 267 char desc[ETH_GSTRING_LEN]; 268 unsigned long offset; 269 }; 270 271 /* mac stats ,opcode id: 0x0032 */ 272 struct hclge_mac_stats { 273 u64 mac_tx_mac_pause_num; 274 u64 mac_rx_mac_pause_num; 275 u64 mac_tx_pfc_pri0_pkt_num; 276 u64 mac_tx_pfc_pri1_pkt_num; 277 u64 mac_tx_pfc_pri2_pkt_num; 278 u64 mac_tx_pfc_pri3_pkt_num; 279 u64 mac_tx_pfc_pri4_pkt_num; 280 u64 mac_tx_pfc_pri5_pkt_num; 281 u64 mac_tx_pfc_pri6_pkt_num; 282 u64 mac_tx_pfc_pri7_pkt_num; 283 u64 mac_rx_pfc_pri0_pkt_num; 284 u64 mac_rx_pfc_pri1_pkt_num; 285 u64 mac_rx_pfc_pri2_pkt_num; 286 u64 mac_rx_pfc_pri3_pkt_num; 287 u64 mac_rx_pfc_pri4_pkt_num; 288 u64 mac_rx_pfc_pri5_pkt_num; 289 u64 mac_rx_pfc_pri6_pkt_num; 290 u64 mac_rx_pfc_pri7_pkt_num; 291 u64 mac_tx_total_pkt_num; 292 u64 mac_tx_total_oct_num; 293 u64 mac_tx_good_pkt_num; 294 u64 mac_tx_bad_pkt_num; 295 u64 mac_tx_good_oct_num; 296 u64 mac_tx_bad_oct_num; 297 u64 mac_tx_uni_pkt_num; 298 u64 mac_tx_multi_pkt_num; 299 u64 mac_tx_broad_pkt_num; 300 u64 mac_tx_undersize_pkt_num; 301 u64 mac_tx_oversize_pkt_num; 302 u64 mac_tx_64_oct_pkt_num; 303 u64 mac_tx_65_127_oct_pkt_num; 304 u64 mac_tx_128_255_oct_pkt_num; 305 u64 mac_tx_256_511_oct_pkt_num; 306 u64 mac_tx_512_1023_oct_pkt_num; 307 u64 mac_tx_1024_1518_oct_pkt_num; 308 u64 mac_tx_1519_2047_oct_pkt_num; 309 u64 mac_tx_2048_4095_oct_pkt_num; 310 u64 mac_tx_4096_8191_oct_pkt_num; 311 u64 rsv0; 312 u64 mac_tx_8192_9216_oct_pkt_num; 313 u64 mac_tx_9217_12287_oct_pkt_num; 314 u64 mac_tx_12288_16383_oct_pkt_num; 315 u64 mac_tx_1519_max_good_oct_pkt_num; 316 u64 mac_tx_1519_max_bad_oct_pkt_num; 317 318 u64 mac_rx_total_pkt_num; 319 u64 mac_rx_total_oct_num; 320 u64 mac_rx_good_pkt_num; 321 u64 mac_rx_bad_pkt_num; 322 u64 mac_rx_good_oct_num; 323 u64 mac_rx_bad_oct_num; 324 u64 mac_rx_uni_pkt_num; 325 u64 mac_rx_multi_pkt_num; 326 u64 mac_rx_broad_pkt_num; 327 u64 mac_rx_undersize_pkt_num; 328 u64 mac_rx_oversize_pkt_num; 329 u64 mac_rx_64_oct_pkt_num; 330 u64 mac_rx_65_127_oct_pkt_num; 331 u64 mac_rx_128_255_oct_pkt_num; 332 u64 mac_rx_256_511_oct_pkt_num; 333 u64 mac_rx_512_1023_oct_pkt_num; 334 u64 mac_rx_1024_1518_oct_pkt_num; 335 u64 mac_rx_1519_2047_oct_pkt_num; 336 u64 mac_rx_2048_4095_oct_pkt_num; 337 u64 mac_rx_4096_8191_oct_pkt_num; 338 u64 rsv1; 339 u64 mac_rx_8192_9216_oct_pkt_num; 340 u64 mac_rx_9217_12287_oct_pkt_num; 341 u64 mac_rx_12288_16383_oct_pkt_num; 342 u64 mac_rx_1519_max_good_oct_pkt_num; 343 u64 mac_rx_1519_max_bad_oct_pkt_num; 344 345 u64 mac_tx_fragment_pkt_num; 346 u64 mac_tx_undermin_pkt_num; 347 u64 mac_tx_jabber_pkt_num; 348 u64 mac_tx_err_all_pkt_num; 349 u64 mac_tx_from_app_good_pkt_num; 350 u64 mac_tx_from_app_bad_pkt_num; 351 u64 mac_rx_fragment_pkt_num; 352 u64 mac_rx_undermin_pkt_num; 353 u64 mac_rx_jabber_pkt_num; 354 u64 mac_rx_fcs_err_pkt_num; 355 u64 mac_rx_send_app_good_pkt_num; 356 u64 mac_rx_send_app_bad_pkt_num; 357 }; 358 359 #define HCLGE_STATS_TIMER_INTERVAL (60 * 5) 360 struct hclge_hw_stats { 361 struct hclge_mac_stats mac_stats; 362 u32 stats_timer; 363 }; 364 365 struct hclge_vlan_type_cfg { 366 u16 rx_ot_fst_vlan_type; 367 u16 rx_ot_sec_vlan_type; 368 u16 rx_in_fst_vlan_type; 369 u16 rx_in_sec_vlan_type; 370 u16 tx_ot_vlan_type; 371 u16 tx_in_vlan_type; 372 }; 373 374 enum HCLGE_FD_MODE { 375 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 376 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 377 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 378 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 379 }; 380 381 enum HCLGE_FD_KEY_TYPE { 382 HCLGE_FD_KEY_BASE_ON_PTYPE, 383 HCLGE_FD_KEY_BASE_ON_TUPLE, 384 }; 385 386 enum HCLGE_FD_STAGE { 387 HCLGE_FD_STAGE_1, 388 HCLGE_FD_STAGE_2, 389 }; 390 391 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 392 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 393 * tuples of non-tunnel packet 394 */ 395 enum HCLGE_FD_TUPLE { 396 OUTER_DST_MAC, 397 OUTER_SRC_MAC, 398 OUTER_VLAN_TAG_FST, 399 OUTER_VLAN_TAG_SEC, 400 OUTER_ETH_TYPE, 401 OUTER_L2_RSV, 402 OUTER_IP_TOS, 403 OUTER_IP_PROTO, 404 OUTER_SRC_IP, 405 OUTER_DST_IP, 406 OUTER_L3_RSV, 407 OUTER_SRC_PORT, 408 OUTER_DST_PORT, 409 OUTER_L4_RSV, 410 OUTER_TUN_VNI, 411 OUTER_TUN_FLOW_ID, 412 INNER_DST_MAC, 413 INNER_SRC_MAC, 414 INNER_VLAN_TAG_FST, 415 INNER_VLAN_TAG_SEC, 416 INNER_ETH_TYPE, 417 INNER_L2_RSV, 418 INNER_IP_TOS, 419 INNER_IP_PROTO, 420 INNER_SRC_IP, 421 INNER_DST_IP, 422 INNER_L3_RSV, 423 INNER_SRC_PORT, 424 INNER_DST_PORT, 425 INNER_L4_RSV, 426 MAX_TUPLE, 427 }; 428 429 enum HCLGE_FD_META_DATA { 430 PACKET_TYPE_ID, 431 IP_FRAGEMENT, 432 ROCE_TYPE, 433 NEXT_KEY, 434 VLAN_NUMBER, 435 SRC_VPORT, 436 DST_VPORT, 437 TUNNEL_PACKET, 438 MAX_META_DATA, 439 }; 440 441 struct key_info { 442 u8 key_type; 443 u8 key_length; 444 }; 445 446 static const struct key_info meta_data_key_info[] = { 447 { PACKET_TYPE_ID, 6}, 448 { IP_FRAGEMENT, 1}, 449 { ROCE_TYPE, 1}, 450 { NEXT_KEY, 5}, 451 { VLAN_NUMBER, 2}, 452 { SRC_VPORT, 12}, 453 { DST_VPORT, 12}, 454 { TUNNEL_PACKET, 1}, 455 }; 456 457 static const struct key_info tuple_key_info[] = { 458 { OUTER_DST_MAC, 48}, 459 { OUTER_SRC_MAC, 48}, 460 { OUTER_VLAN_TAG_FST, 16}, 461 { OUTER_VLAN_TAG_SEC, 16}, 462 { OUTER_ETH_TYPE, 16}, 463 { OUTER_L2_RSV, 16}, 464 { OUTER_IP_TOS, 8}, 465 { OUTER_IP_PROTO, 8}, 466 { OUTER_SRC_IP, 32}, 467 { OUTER_DST_IP, 32}, 468 { OUTER_L3_RSV, 16}, 469 { OUTER_SRC_PORT, 16}, 470 { OUTER_DST_PORT, 16}, 471 { OUTER_L4_RSV, 32}, 472 { OUTER_TUN_VNI, 24}, 473 { OUTER_TUN_FLOW_ID, 8}, 474 { INNER_DST_MAC, 48}, 475 { INNER_SRC_MAC, 48}, 476 { INNER_VLAN_TAG_FST, 16}, 477 { INNER_VLAN_TAG_SEC, 16}, 478 { INNER_ETH_TYPE, 16}, 479 { INNER_L2_RSV, 16}, 480 { INNER_IP_TOS, 8}, 481 { INNER_IP_PROTO, 8}, 482 { INNER_SRC_IP, 32}, 483 { INNER_DST_IP, 32}, 484 { INNER_L3_RSV, 16}, 485 { INNER_SRC_PORT, 16}, 486 { INNER_DST_PORT, 16}, 487 { INNER_L4_RSV, 32}, 488 }; 489 490 #define MAX_KEY_LENGTH 400 491 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 492 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 493 #define MAX_META_DATA_LENGTH 32 494 495 enum HCLGE_FD_PACKET_TYPE { 496 NIC_PACKET, 497 ROCE_PACKET, 498 }; 499 500 enum HCLGE_FD_ACTION { 501 HCLGE_FD_ACTION_ACCEPT_PACKET, 502 HCLGE_FD_ACTION_DROP_PACKET, 503 }; 504 505 struct hclge_fd_key_cfg { 506 u8 key_sel; 507 u8 inner_sipv6_word_en; 508 u8 inner_dipv6_word_en; 509 u8 outer_sipv6_word_en; 510 u8 outer_dipv6_word_en; 511 u32 tuple_active; 512 u32 meta_data_active; 513 }; 514 515 struct hclge_fd_cfg { 516 u8 fd_mode; 517 u8 fd_en; 518 u16 max_key_length; 519 u32 proto_support; 520 u32 rule_num[2]; /* rule entry number */ 521 u16 cnt_num[2]; /* rule hit counter number */ 522 struct hclge_fd_key_cfg key_cfg[2]; 523 }; 524 525 struct hclge_fd_rule_tuples { 526 u8 src_mac[6]; 527 u8 dst_mac[6]; 528 u32 src_ip[4]; 529 u32 dst_ip[4]; 530 u16 src_port; 531 u16 dst_port; 532 u16 vlan_tag1; 533 u16 ether_proto; 534 u8 ip_tos; 535 u8 ip_proto; 536 }; 537 538 struct hclge_fd_rule { 539 struct hlist_node rule_node; 540 struct hclge_fd_rule_tuples tuples; 541 struct hclge_fd_rule_tuples tuples_mask; 542 u32 unused_tuple; 543 u32 flow_type; 544 u8 action; 545 u16 vf_id; 546 u16 queue_id; 547 u16 location; 548 }; 549 550 struct hclge_fd_ad_data { 551 u16 ad_id; 552 u8 drop_packet; 553 u8 forward_to_direct_queue; 554 u16 queue_id; 555 u8 use_counter; 556 u8 counter_id; 557 u8 use_next_stage; 558 u8 write_rule_id_to_bd; 559 u8 next_input_key; 560 u16 rule_id; 561 }; 562 563 /* For each bit of TCAM entry, it uses a pair of 'x' and 564 * 'y' to indicate which value to match, like below: 565 * ---------------------------------- 566 * | bit x | bit y | search value | 567 * ---------------------------------- 568 * | 0 | 0 | always hit | 569 * ---------------------------------- 570 * | 1 | 0 | match '0' | 571 * ---------------------------------- 572 * | 0 | 1 | match '1' | 573 * ---------------------------------- 574 * | 1 | 1 | invalid | 575 * ---------------------------------- 576 * Then for input key(k) and mask(v), we can calculate the value by 577 * the formulae: 578 * x = (~k) & v 579 * y = (k ^ ~v) & k 580 */ 581 #define calc_x(x, k, v) ((x) = (~(k) & (v))) 582 #define calc_y(y, k, v) \ 583 do { \ 584 const typeof(k) _k_ = (k); \ 585 const typeof(v) _v_ = (v); \ 586 (y) = (_k_ ^ ~_v_) & (_k_); \ 587 } while (0) 588 589 #define HCLGE_VPORT_NUM 256 590 struct hclge_dev { 591 struct pci_dev *pdev; 592 struct hnae3_ae_dev *ae_dev; 593 struct hclge_hw hw; 594 struct hclge_misc_vector misc_vector; 595 struct hclge_hw_stats hw_stats; 596 unsigned long state; 597 unsigned long last_reset_time; 598 599 enum hnae3_reset_type reset_type; 600 enum hnae3_reset_type reset_level; 601 unsigned long default_reset_request; 602 unsigned long reset_request; /* reset has been requested */ 603 unsigned long reset_pending; /* client rst is pending to be served */ 604 unsigned long reset_count; /* the number of reset has been done */ 605 u32 reset_fail_cnt; 606 u32 fw_version; 607 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ 608 u16 num_tqps; /* Num task queue pairs of this PF */ 609 u16 num_req_vfs; /* Num VFs requested for this PF */ 610 611 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 612 u16 alloc_rss_size; /* Allocated RSS task queue */ 613 u16 rss_size_max; /* HW defined max RSS task queue */ 614 615 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 616 u16 num_alloc_vport; /* Num vports this driver supports */ 617 u32 numa_node_mask; 618 u16 rx_buf_len; 619 u16 num_desc; 620 u8 hw_tc_map; 621 u8 tc_num_last_time; 622 enum hclge_fc_mode fc_mode_last_time; 623 624 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 625 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 626 u8 tx_sch_mode; 627 u8 tc_max; 628 u8 pfc_max; 629 630 u8 default_up; 631 u8 dcbx_cap; 632 struct hclge_tm_info tm_info; 633 634 u16 num_msi; 635 u16 num_msi_left; 636 u16 num_msi_used; 637 u16 roce_base_msix_offset; 638 u32 base_msi_vector; 639 u16 *vector_status; 640 int *vector_irq; 641 u16 num_roce_msi; /* Num of roce vectors for this PF */ 642 int roce_base_vector; 643 644 u16 pending_udp_bitmap; 645 646 u16 rx_itr_default; 647 u16 tx_itr_default; 648 649 u16 adminq_work_limit; /* Num of admin receive queue desc to process */ 650 unsigned long service_timer_period; 651 unsigned long service_timer_previous; 652 struct timer_list service_timer; 653 struct timer_list reset_timer; 654 struct work_struct service_task; 655 struct work_struct rst_service_task; 656 struct work_struct mbx_service_task; 657 658 bool cur_promisc; 659 int num_alloc_vfs; /* Actual number of VFs allocated */ 660 661 struct hclge_tqp *htqp; 662 struct hclge_vport *vport; 663 664 struct dentry *hclge_dbgfs; 665 666 struct hnae3_client *nic_client; 667 struct hnae3_client *roce_client; 668 669 #define HCLGE_FLAG_MAIN BIT(0) 670 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 671 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 672 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 673 u32 flag; 674 675 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 676 u32 mps; /* Max packet size */ 677 678 struct hclge_vlan_type_cfg vlan_type_cfg; 679 680 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 681 682 struct hclge_fd_cfg fd_cfg; 683 struct hlist_head fd_rule_list; 684 u16 hclge_fd_rule_num; 685 686 u16 wanted_umv_size; 687 /* max available unicast mac vlan space */ 688 u16 max_umv_size; 689 /* private unicast mac vlan space, it's same for PF and its VFs */ 690 u16 priv_umv_size; 691 /* unicast mac vlan space shared by PF and its VFs */ 692 u16 share_umv_size; 693 struct mutex umv_mutex; /* protect share_umv_size */ 694 }; 695 696 /* VPort level vlan tag configuration for TX direction */ 697 struct hclge_tx_vtag_cfg { 698 bool accept_tag1; /* Whether accept tag1 packet from host */ 699 bool accept_untag1; /* Whether accept untag1 packet from host */ 700 bool accept_tag2; 701 bool accept_untag2; 702 bool insert_tag1_en; /* Whether insert inner vlan tag */ 703 bool insert_tag2_en; /* Whether insert outer vlan tag */ 704 u16 default_tag1; /* The default inner vlan tag to insert */ 705 u16 default_tag2; /* The default outer vlan tag to insert */ 706 }; 707 708 /* VPort level vlan tag configuration for RX direction */ 709 struct hclge_rx_vtag_cfg { 710 bool strip_tag1_en; /* Whether strip inner vlan tag */ 711 bool strip_tag2_en; /* Whether strip outer vlan tag */ 712 bool vlan1_vlan_prionly;/* Inner VLAN Tag up to descriptor Enable */ 713 bool vlan2_vlan_prionly;/* Outer VLAN Tag up to descriptor Enable */ 714 }; 715 716 struct hclge_rss_tuple_cfg { 717 u8 ipv4_tcp_en; 718 u8 ipv4_udp_en; 719 u8 ipv4_sctp_en; 720 u8 ipv4_fragment_en; 721 u8 ipv6_tcp_en; 722 u8 ipv6_udp_en; 723 u8 ipv6_sctp_en; 724 u8 ipv6_fragment_en; 725 }; 726 727 struct hclge_vport { 728 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 729 730 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 731 /* User configured lookup table entries */ 732 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE]; 733 int rss_algo; /* User configured hash algorithm */ 734 /* User configured rss tuple sets */ 735 struct hclge_rss_tuple_cfg rss_tuple_sets; 736 737 u16 alloc_rss_size; 738 739 u16 qs_offset; 740 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 741 u8 dwrr; 742 743 struct hclge_tx_vtag_cfg txvlan_cfg; 744 struct hclge_rx_vtag_cfg rxvlan_cfg; 745 746 u16 used_umv_num; 747 748 int vport_id; 749 struct hclge_dev *back; /* Back reference to associated dev */ 750 struct hnae3_handle nic; 751 struct hnae3_handle roce; 752 }; 753 754 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 755 bool en_mc, bool en_bc, int vport_id); 756 757 int hclge_add_uc_addr_common(struct hclge_vport *vport, 758 const unsigned char *addr); 759 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 760 const unsigned char *addr); 761 int hclge_add_mc_addr_common(struct hclge_vport *vport, 762 const unsigned char *addr); 763 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 764 const unsigned char *addr); 765 766 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 767 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 768 int vector_id, bool en, 769 struct hnae3_ring_chain_node *ring_chain); 770 771 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 772 { 773 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 774 775 return tqp->index; 776 } 777 778 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 779 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 780 u16 vlan_id, bool is_kill); 781 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 782 783 int hclge_buffer_alloc(struct hclge_dev *hdev); 784 int hclge_rss_init_hw(struct hclge_dev *hdev); 785 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 786 787 void hclge_mbx_handler(struct hclge_dev *hdev); 788 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id); 789 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id); 790 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 791 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 792 #endif 793