1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HCLGE_MAIN_H 11 #define __HCLGE_MAIN_H 12 #include <linux/fs.h> 13 #include <linux/types.h> 14 #include <linux/phy.h> 15 #include "hclge_cmd.h" 16 #include "hnae3.h" 17 18 #define HCLGE_MOD_VERSION "v1.0" 19 #define HCLGE_DRIVER_NAME "hclge" 20 21 #define HCLGE_INVALID_VPORT 0xffff 22 23 #define HCLGE_ROCE_VECTOR_OFFSET 96 24 25 #define HCLGE_PF_CFG_BLOCK_SIZE 32 26 #define HCLGE_PF_CFG_DESC_NUM \ 27 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 28 29 #define HCLGE_VECTOR_REG_BASE 0x20000 30 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 31 32 #define HCLGE_VECTOR_REG_OFFSET 0x4 33 #define HCLGE_VECTOR_VF_OFFSET 0x100000 34 35 #define HCLGE_RSS_IND_TBL_SIZE 512 36 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 37 #define HCLGE_RSS_KEY_SIZE 40 38 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 39 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 40 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 41 #define HCLGE_RSS_HASH_ALGO_MASK 0xf 42 #define HCLGE_RSS_CFG_TBL_NUM \ 43 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE) 44 45 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 46 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 47 #define HCLGE_D_PORT_BIT BIT(0) 48 #define HCLGE_S_PORT_BIT BIT(1) 49 #define HCLGE_D_IP_BIT BIT(2) 50 #define HCLGE_S_IP_BIT BIT(3) 51 #define HCLGE_V_TAG_BIT BIT(4) 52 53 #define HCLGE_RSS_TC_SIZE_0 1 54 #define HCLGE_RSS_TC_SIZE_1 2 55 #define HCLGE_RSS_TC_SIZE_2 4 56 #define HCLGE_RSS_TC_SIZE_3 8 57 #define HCLGE_RSS_TC_SIZE_4 16 58 #define HCLGE_RSS_TC_SIZE_5 32 59 #define HCLGE_RSS_TC_SIZE_6 64 60 #define HCLGE_RSS_TC_SIZE_7 128 61 62 #define HCLGE_TQP_RESET_TRY_TIMES 10 63 64 #define HCLGE_PHY_PAGE_MDIX 0 65 #define HCLGE_PHY_PAGE_COPPER 0 66 67 /* Page Selection Reg. */ 68 #define HCLGE_PHY_PAGE_REG 22 69 70 /* Copper Specific Control Register */ 71 #define HCLGE_PHY_CSC_REG 16 72 73 /* Copper Specific Status Register */ 74 #define HCLGE_PHY_CSS_REG 17 75 76 #define HCLGE_PHY_MDIX_CTRL_S (5) 77 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 78 79 #define HCLGE_PHY_MDIX_STATUS_B (6) 80 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B (11) 81 82 /* Factor used to calculate offset and bitmap of VF num */ 83 #define HCLGE_VF_NUM_PER_CMD 64 84 #define HCLGE_VF_NUM_PER_BYTE 8 85 86 /* Reset related Registers */ 87 #define HCLGE_MISC_RESET_STS_REG 0x20700 88 #define HCLGE_GLOBAL_RESET_REG 0x20A00 89 #define HCLGE_GLOBAL_RESET_BIT 0x0 90 #define HCLGE_CORE_RESET_BIT 0x1 91 #define HCLGE_FUN_RST_ING 0x20C00 92 #define HCLGE_FUN_RST_ING_B 0 93 94 /* Vector0 register bits define */ 95 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 96 #define HCLGE_VECTOR0_CORERESET_INT_B 6 97 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 98 99 /* Vector0 interrupt CMDQ event source register(RW) */ 100 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 101 /* CMDQ register bits for RX event(=MBX event) */ 102 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 103 104 enum HCLGE_DEV_STATE { 105 HCLGE_STATE_REINITING, 106 HCLGE_STATE_DOWN, 107 HCLGE_STATE_DISABLED, 108 HCLGE_STATE_REMOVING, 109 HCLGE_STATE_SERVICE_INITED, 110 HCLGE_STATE_SERVICE_SCHED, 111 HCLGE_STATE_RST_SERVICE_SCHED, 112 HCLGE_STATE_RST_HANDLING, 113 HCLGE_STATE_MBX_SERVICE_SCHED, 114 HCLGE_STATE_MBX_HANDLING, 115 HCLGE_STATE_MAX 116 }; 117 118 enum hclge_evt_cause { 119 HCLGE_VECTOR0_EVENT_RST, 120 HCLGE_VECTOR0_EVENT_MBX, 121 HCLGE_VECTOR0_EVENT_OTHER, 122 }; 123 124 #define HCLGE_MPF_ENBALE 1 125 struct hclge_caps { 126 u16 num_tqp; 127 u16 num_buffer_cell; 128 u32 flag; 129 u16 vmdq; 130 }; 131 132 enum HCLGE_MAC_SPEED { 133 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 134 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 135 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 136 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 137 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 138 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 139 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 140 HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */ 141 }; 142 143 enum HCLGE_MAC_DUPLEX { 144 HCLGE_MAC_HALF, 145 HCLGE_MAC_FULL 146 }; 147 148 enum hclge_mta_dmac_sel_type { 149 HCLGE_MAC_ADDR_47_36, 150 HCLGE_MAC_ADDR_46_35, 151 HCLGE_MAC_ADDR_45_34, 152 HCLGE_MAC_ADDR_44_33, 153 }; 154 155 struct hclge_mac { 156 u8 phy_addr; 157 u8 flag; 158 u8 media_type; 159 u8 mac_addr[ETH_ALEN]; 160 u8 autoneg; 161 u8 duplex; 162 u32 speed; 163 int link; /* store the link status of mac & phy (if phy exit)*/ 164 struct phy_device *phydev; 165 struct mii_bus *mdio_bus; 166 phy_interface_t phy_if; 167 }; 168 169 struct hclge_hw { 170 void __iomem *io_base; 171 struct hclge_mac mac; 172 int num_vec; 173 struct hclge_cmq cmq; 174 struct hclge_caps caps; 175 void *back; 176 }; 177 178 /* TQP stats */ 179 struct hlcge_tqp_stats { 180 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 181 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 182 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 183 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 184 }; 185 186 struct hclge_tqp { 187 struct device *dev; /* Device for DMA mapping */ 188 struct hnae3_queue q; 189 struct hlcge_tqp_stats tqp_stats; 190 u16 index; /* Global index in a NIC controller */ 191 192 bool alloced; 193 }; 194 195 enum hclge_fc_mode { 196 HCLGE_FC_NONE, 197 HCLGE_FC_RX_PAUSE, 198 HCLGE_FC_TX_PAUSE, 199 HCLGE_FC_FULL, 200 HCLGE_FC_PFC, 201 HCLGE_FC_DEFAULT 202 }; 203 204 #define HCLGE_PG_NUM 4 205 #define HCLGE_SCH_MODE_SP 0 206 #define HCLGE_SCH_MODE_DWRR 1 207 struct hclge_pg_info { 208 u8 pg_id; 209 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 210 u8 tc_bit_map; 211 u32 bw_limit; 212 u8 tc_dwrr[HNAE3_MAX_TC]; 213 }; 214 215 struct hclge_tc_info { 216 u8 tc_id; 217 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 218 u8 pgid; 219 u32 bw_limit; 220 }; 221 222 struct hclge_cfg { 223 u8 vmdq_vport_num; 224 u8 tc_num; 225 u16 tqp_desc_num; 226 u16 rx_buf_len; 227 u16 rss_size_max; 228 u8 phy_addr; 229 u8 media_type; 230 u8 mac_addr[ETH_ALEN]; 231 u8 default_speed; 232 u32 numa_node_map; 233 }; 234 235 struct hclge_tm_info { 236 u8 num_tc; 237 u8 num_pg; /* It must be 1 if vNET-Base schd */ 238 u8 pg_dwrr[HCLGE_PG_NUM]; 239 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 240 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 241 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 242 enum hclge_fc_mode fc_mode; 243 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 244 }; 245 246 struct hclge_comm_stats_str { 247 char desc[ETH_GSTRING_LEN]; 248 unsigned long offset; 249 }; 250 251 /* all 64bit stats, opcode id: 0x0030 */ 252 struct hclge_64_bit_stats { 253 /* query_igu_stat */ 254 u64 igu_rx_oversize_pkt; 255 u64 igu_rx_undersize_pkt; 256 u64 igu_rx_out_all_pkt; 257 u64 igu_rx_uni_pkt; 258 u64 igu_rx_multi_pkt; 259 u64 igu_rx_broad_pkt; 260 u64 rsv0; 261 262 /* query_egu_stat */ 263 u64 egu_tx_out_all_pkt; 264 u64 egu_tx_uni_pkt; 265 u64 egu_tx_multi_pkt; 266 u64 egu_tx_broad_pkt; 267 268 /* ssu_ppp packet stats */ 269 u64 ssu_ppp_mac_key_num; 270 u64 ssu_ppp_host_key_num; 271 u64 ppp_ssu_mac_rlt_num; 272 u64 ppp_ssu_host_rlt_num; 273 274 /* ssu_tx_in_out_dfx_stats */ 275 u64 ssu_tx_in_num; 276 u64 ssu_tx_out_num; 277 /* ssu_rx_in_out_dfx_stats */ 278 u64 ssu_rx_in_num; 279 u64 ssu_rx_out_num; 280 }; 281 282 /* all 32bit stats, opcode id: 0x0031 */ 283 struct hclge_32_bit_stats { 284 u64 igu_rx_err_pkt; 285 u64 igu_rx_no_eof_pkt; 286 u64 igu_rx_no_sof_pkt; 287 u64 egu_tx_1588_pkt; 288 u64 egu_tx_err_pkt; 289 u64 ssu_full_drop_num; 290 u64 ssu_part_drop_num; 291 u64 ppp_key_drop_num; 292 u64 ppp_rlt_drop_num; 293 u64 ssu_key_drop_num; 294 u64 pkt_curr_buf_cnt; 295 u64 qcn_fb_rcv_cnt; 296 u64 qcn_fb_drop_cnt; 297 u64 qcn_fb_invaild_cnt; 298 u64 rsv0; 299 u64 rx_packet_tc0_in_cnt; 300 u64 rx_packet_tc1_in_cnt; 301 u64 rx_packet_tc2_in_cnt; 302 u64 rx_packet_tc3_in_cnt; 303 u64 rx_packet_tc4_in_cnt; 304 u64 rx_packet_tc5_in_cnt; 305 u64 rx_packet_tc6_in_cnt; 306 u64 rx_packet_tc7_in_cnt; 307 u64 rx_packet_tc0_out_cnt; 308 u64 rx_packet_tc1_out_cnt; 309 u64 rx_packet_tc2_out_cnt; 310 u64 rx_packet_tc3_out_cnt; 311 u64 rx_packet_tc4_out_cnt; 312 u64 rx_packet_tc5_out_cnt; 313 u64 rx_packet_tc6_out_cnt; 314 u64 rx_packet_tc7_out_cnt; 315 316 /* Tx packet level statistics */ 317 u64 tx_packet_tc0_in_cnt; 318 u64 tx_packet_tc1_in_cnt; 319 u64 tx_packet_tc2_in_cnt; 320 u64 tx_packet_tc3_in_cnt; 321 u64 tx_packet_tc4_in_cnt; 322 u64 tx_packet_tc5_in_cnt; 323 u64 tx_packet_tc6_in_cnt; 324 u64 tx_packet_tc7_in_cnt; 325 u64 tx_packet_tc0_out_cnt; 326 u64 tx_packet_tc1_out_cnt; 327 u64 tx_packet_tc2_out_cnt; 328 u64 tx_packet_tc3_out_cnt; 329 u64 tx_packet_tc4_out_cnt; 330 u64 tx_packet_tc5_out_cnt; 331 u64 tx_packet_tc6_out_cnt; 332 u64 tx_packet_tc7_out_cnt; 333 334 /* packet buffer statistics */ 335 u64 pkt_curr_buf_tc0_cnt; 336 u64 pkt_curr_buf_tc1_cnt; 337 u64 pkt_curr_buf_tc2_cnt; 338 u64 pkt_curr_buf_tc3_cnt; 339 u64 pkt_curr_buf_tc4_cnt; 340 u64 pkt_curr_buf_tc5_cnt; 341 u64 pkt_curr_buf_tc6_cnt; 342 u64 pkt_curr_buf_tc7_cnt; 343 344 u64 mb_uncopy_num; 345 u64 lo_pri_unicast_rlt_drop_num; 346 u64 hi_pri_multicast_rlt_drop_num; 347 u64 lo_pri_multicast_rlt_drop_num; 348 u64 rx_oq_drop_pkt_cnt; 349 u64 tx_oq_drop_pkt_cnt; 350 u64 nic_l2_err_drop_pkt_cnt; 351 u64 roc_l2_err_drop_pkt_cnt; 352 }; 353 354 /* mac stats ,opcode id: 0x0032 */ 355 struct hclge_mac_stats { 356 u64 mac_tx_mac_pause_num; 357 u64 mac_rx_mac_pause_num; 358 u64 mac_tx_pfc_pri0_pkt_num; 359 u64 mac_tx_pfc_pri1_pkt_num; 360 u64 mac_tx_pfc_pri2_pkt_num; 361 u64 mac_tx_pfc_pri3_pkt_num; 362 u64 mac_tx_pfc_pri4_pkt_num; 363 u64 mac_tx_pfc_pri5_pkt_num; 364 u64 mac_tx_pfc_pri6_pkt_num; 365 u64 mac_tx_pfc_pri7_pkt_num; 366 u64 mac_rx_pfc_pri0_pkt_num; 367 u64 mac_rx_pfc_pri1_pkt_num; 368 u64 mac_rx_pfc_pri2_pkt_num; 369 u64 mac_rx_pfc_pri3_pkt_num; 370 u64 mac_rx_pfc_pri4_pkt_num; 371 u64 mac_rx_pfc_pri5_pkt_num; 372 u64 mac_rx_pfc_pri6_pkt_num; 373 u64 mac_rx_pfc_pri7_pkt_num; 374 u64 mac_tx_total_pkt_num; 375 u64 mac_tx_total_oct_num; 376 u64 mac_tx_good_pkt_num; 377 u64 mac_tx_bad_pkt_num; 378 u64 mac_tx_good_oct_num; 379 u64 mac_tx_bad_oct_num; 380 u64 mac_tx_uni_pkt_num; 381 u64 mac_tx_multi_pkt_num; 382 u64 mac_tx_broad_pkt_num; 383 u64 mac_tx_undersize_pkt_num; 384 u64 mac_tx_overrsize_pkt_num; 385 u64 mac_tx_64_oct_pkt_num; 386 u64 mac_tx_65_127_oct_pkt_num; 387 u64 mac_tx_128_255_oct_pkt_num; 388 u64 mac_tx_256_511_oct_pkt_num; 389 u64 mac_tx_512_1023_oct_pkt_num; 390 u64 mac_tx_1024_1518_oct_pkt_num; 391 u64 mac_tx_1519_max_oct_pkt_num; 392 u64 mac_rx_total_pkt_num; 393 u64 mac_rx_total_oct_num; 394 u64 mac_rx_good_pkt_num; 395 u64 mac_rx_bad_pkt_num; 396 u64 mac_rx_good_oct_num; 397 u64 mac_rx_bad_oct_num; 398 u64 mac_rx_uni_pkt_num; 399 u64 mac_rx_multi_pkt_num; 400 u64 mac_rx_broad_pkt_num; 401 u64 mac_rx_undersize_pkt_num; 402 u64 mac_rx_overrsize_pkt_num; 403 u64 mac_rx_64_oct_pkt_num; 404 u64 mac_rx_65_127_oct_pkt_num; 405 u64 mac_rx_128_255_oct_pkt_num; 406 u64 mac_rx_256_511_oct_pkt_num; 407 u64 mac_rx_512_1023_oct_pkt_num; 408 u64 mac_rx_1024_1518_oct_pkt_num; 409 u64 mac_rx_1519_max_oct_pkt_num; 410 411 u64 mac_trans_fragment_pkt_num; 412 u64 mac_trans_undermin_pkt_num; 413 u64 mac_trans_jabber_pkt_num; 414 u64 mac_trans_err_all_pkt_num; 415 u64 mac_trans_from_app_good_pkt_num; 416 u64 mac_trans_from_app_bad_pkt_num; 417 u64 mac_rcv_fragment_pkt_num; 418 u64 mac_rcv_undermin_pkt_num; 419 u64 mac_rcv_jabber_pkt_num; 420 u64 mac_rcv_fcs_err_pkt_num; 421 u64 mac_rcv_send_app_good_pkt_num; 422 u64 mac_rcv_send_app_bad_pkt_num; 423 }; 424 425 struct hclge_hw_stats { 426 struct hclge_mac_stats mac_stats; 427 struct hclge_64_bit_stats all_64_bit_stats; 428 struct hclge_32_bit_stats all_32_bit_stats; 429 }; 430 431 struct hclge_vlan_type_cfg { 432 u16 rx_ot_fst_vlan_type; 433 u16 rx_ot_sec_vlan_type; 434 u16 rx_in_fst_vlan_type; 435 u16 rx_in_sec_vlan_type; 436 u16 tx_ot_vlan_type; 437 u16 tx_in_vlan_type; 438 }; 439 440 struct hclge_dev { 441 struct pci_dev *pdev; 442 struct hnae3_ae_dev *ae_dev; 443 struct hclge_hw hw; 444 struct hclge_misc_vector misc_vector; 445 struct hclge_hw_stats hw_stats; 446 unsigned long state; 447 448 enum hnae3_reset_type reset_type; 449 unsigned long reset_request; /* reset has been requested */ 450 unsigned long reset_pending; /* client rst is pending to be served */ 451 u32 fw_version; 452 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ 453 u16 num_tqps; /* Num task queue pairs of this PF */ 454 u16 num_req_vfs; /* Num VFs requested for this PF */ 455 456 /* Base task tqp physical id of this PF */ 457 u16 base_tqp_pid; 458 u16 alloc_rss_size; /* Allocated RSS task queue */ 459 u16 rss_size_max; /* HW defined max RSS task queue */ 460 461 /* Num of guaranteed filters for this PF */ 462 u16 fdir_pf_filter_count; 463 u16 num_alloc_vport; /* Num vports this driver supports */ 464 u32 numa_node_mask; 465 u16 rx_buf_len; 466 u16 num_desc; 467 u8 hw_tc_map; 468 u8 tc_num_last_time; 469 enum hclge_fc_mode fc_mode_last_time; 470 471 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 472 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 473 u8 tx_sch_mode; 474 u8 tc_max; 475 u8 pfc_max; 476 477 u8 default_up; 478 u8 dcbx_cap; 479 struct hclge_tm_info tm_info; 480 481 u16 num_msi; 482 u16 num_msi_left; 483 u16 num_msi_used; 484 u32 base_msi_vector; 485 u16 *vector_status; 486 int *vector_irq; 487 u16 num_roce_msi; /* Num of roce vectors for this PF */ 488 int roce_base_vector; 489 490 u16 pending_udp_bitmap; 491 492 u16 rx_itr_default; 493 u16 tx_itr_default; 494 495 u16 adminq_work_limit; /* Num of admin receive queue desc to process */ 496 unsigned long service_timer_period; 497 unsigned long service_timer_previous; 498 struct timer_list service_timer; 499 struct work_struct service_task; 500 struct work_struct rst_service_task; 501 struct work_struct mbx_service_task; 502 503 bool cur_promisc; 504 int num_alloc_vfs; /* Actual number of VFs allocated */ 505 506 struct hclge_tqp *htqp; 507 struct hclge_vport *vport; 508 509 struct dentry *hclge_dbgfs; 510 511 struct hnae3_client *nic_client; 512 struct hnae3_client *roce_client; 513 514 #define HCLGE_FLAG_MAIN BIT(0) 515 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 516 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 517 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 518 u32 flag; 519 520 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 521 u32 mps; /* Max packet size */ 522 523 enum hclge_mta_dmac_sel_type mta_mac_sel_type; 524 bool enable_mta; /* Mutilcast filter enable */ 525 bool accept_mta_mc; /* Whether accept mta filter multicast */ 526 527 struct hclge_vlan_type_cfg vlan_type_cfg; 528 }; 529 530 /* VPort level vlan tag configuration for TX direction */ 531 struct hclge_tx_vtag_cfg { 532 bool accept_tag; /* Whether accept tagged packet from host */ 533 bool accept_untag; /* Whether accept untagged packet from host */ 534 bool insert_tag1_en; /* Whether insert inner vlan tag */ 535 bool insert_tag2_en; /* Whether insert outer vlan tag */ 536 u16 default_tag1; /* The default inner vlan tag to insert */ 537 u16 default_tag2; /* The default outer vlan tag to insert */ 538 }; 539 540 /* VPort level vlan tag configuration for RX direction */ 541 struct hclge_rx_vtag_cfg { 542 bool strip_tag1_en; /* Whether strip inner vlan tag */ 543 bool strip_tag2_en; /* Whether strip outer vlan tag */ 544 bool vlan1_vlan_prionly;/* Inner VLAN Tag up to descriptor Enable */ 545 bool vlan2_vlan_prionly;/* Outer VLAN Tag up to descriptor Enable */ 546 }; 547 548 struct hclge_vport { 549 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 550 551 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 552 /* User configured lookup table entries */ 553 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE]; 554 u16 alloc_rss_size; 555 556 u16 qs_offset; 557 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 558 u8 dwrr; 559 560 struct hclge_tx_vtag_cfg txvlan_cfg; 561 struct hclge_rx_vtag_cfg rxvlan_cfg; 562 563 int vport_id; 564 struct hclge_dev *back; /* Back reference to associated dev */ 565 struct hnae3_handle nic; 566 struct hnae3_handle roce; 567 }; 568 569 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 570 bool en_mc, bool en_bc, int vport_id); 571 572 int hclge_add_uc_addr_common(struct hclge_vport *vport, 573 const unsigned char *addr); 574 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 575 const unsigned char *addr); 576 int hclge_add_mc_addr_common(struct hclge_vport *vport, 577 const unsigned char *addr); 578 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 579 const unsigned char *addr); 580 581 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, 582 u8 func_id, 583 bool enable); 584 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 585 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 586 int vector_id, bool en, 587 struct hnae3_ring_chain_node *ring_chain); 588 589 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 590 { 591 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 592 593 return tqp->index; 594 } 595 596 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 597 int hclge_set_vf_vlan_common(struct hclge_dev *vport, int vfid, 598 bool is_kill, u16 vlan, u8 qos, __be16 proto); 599 600 int hclge_buffer_alloc(struct hclge_dev *hdev); 601 int hclge_rss_init_hw(struct hclge_dev *hdev); 602 603 void hclge_mbx_handler(struct hclge_dev *hdev); 604 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id); 605 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 606 #endif 607