1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 #include <net/devlink.h> 12 13 #include "hclge_cmd.h" 14 #include "hclge_ptp.h" 15 #include "hnae3.h" 16 #include "hclge_comm_rss.h" 17 #include "hclge_comm_tqp_stats.h" 18 19 #define HCLGE_MOD_VERSION "1.0" 20 #define HCLGE_DRIVER_NAME "hclge" 21 22 #define HCLGE_MAX_PF_NUM 8 23 24 #define HCLGE_VF_VPORT_START_NUM 1 25 26 #define HCLGE_RD_FIRST_STATS_NUM 2 27 #define HCLGE_RD_OTHER_STATS_NUM 4 28 29 #define HCLGE_INVALID_VPORT 0xffff 30 31 #define HCLGE_PF_CFG_BLOCK_SIZE 32 32 #define HCLGE_PF_CFG_DESC_NUM \ 33 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 34 35 #define HCLGE_VECTOR_REG_BASE 0x20000 36 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 37 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 38 39 #define HCLGE_VECTOR_REG_OFFSET 0x4 40 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 41 #define HCLGE_VECTOR_VF_OFFSET 0x100000 42 43 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 44 45 /* bar registers for common func */ 46 #define HCLGE_GRO_EN_REG 0x28000 47 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 48 49 /* bar registers for rcb */ 50 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 51 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 52 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 53 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 54 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 55 #define HCLGE_RING_RX_TAIL_REG 0x80018 56 #define HCLGE_RING_RX_HEAD_REG 0x8001C 57 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 58 #define HCLGE_RING_RX_OFFSET_REG 0x80024 59 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 60 #define HCLGE_RING_RX_STASH_REG 0x80030 61 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 62 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 63 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 64 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 65 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 66 #define HCLGE_RING_TX_TC_REG 0x80050 67 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 68 #define HCLGE_RING_TX_TAIL_REG 0x80058 69 #define HCLGE_RING_TX_HEAD_REG 0x8005C 70 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 71 #define HCLGE_RING_TX_OFFSET_REG 0x80064 72 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 73 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 74 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 75 #define HCLGE_RING_EN_REG 0x80090 76 77 /* bar registers for tqp interrupt */ 78 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 79 #define HCLGE_TQP_INTR_GL0_REG 0x20100 80 #define HCLGE_TQP_INTR_GL1_REG 0x20200 81 #define HCLGE_TQP_INTR_GL2_REG 0x20300 82 #define HCLGE_TQP_INTR_RL_REG 0x20900 83 84 #define HCLGE_RSS_IND_TBL_SIZE 512 85 86 #define HCLGE_RSS_TC_SIZE_0 1 87 #define HCLGE_RSS_TC_SIZE_1 2 88 #define HCLGE_RSS_TC_SIZE_2 4 89 #define HCLGE_RSS_TC_SIZE_3 8 90 #define HCLGE_RSS_TC_SIZE_4 16 91 #define HCLGE_RSS_TC_SIZE_5 32 92 #define HCLGE_RSS_TC_SIZE_6 64 93 #define HCLGE_RSS_TC_SIZE_7 128 94 95 #define HCLGE_UMV_TBL_SIZE 3072 96 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 97 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 98 99 #define HCLGE_TQP_RESET_TRY_TIMES 200 100 101 #define HCLGE_PHY_PAGE_MDIX 0 102 #define HCLGE_PHY_PAGE_COPPER 0 103 104 /* Page Selection Reg. */ 105 #define HCLGE_PHY_PAGE_REG 22 106 107 /* Copper Specific Control Register */ 108 #define HCLGE_PHY_CSC_REG 16 109 110 /* Copper Specific Status Register */ 111 #define HCLGE_PHY_CSS_REG 17 112 113 #define HCLGE_PHY_MDIX_CTRL_S 5 114 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 115 116 #define HCLGE_PHY_MDIX_STATUS_B 6 117 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 118 119 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 120 121 /* Factor used to calculate offset and bitmap of VF num */ 122 #define HCLGE_VF_NUM_PER_CMD 64 123 124 #define HCLGE_MAX_QSET_NUM 1024 125 126 #define HCLGE_DBG_RESET_INFO_LEN 1024 127 128 enum HLCGE_PORT_TYPE { 129 HOST_PORT, 130 NETWORK_PORT 131 }; 132 133 #define PF_VPORT_ID 0 134 135 #define HCLGE_PF_ID_S 0 136 #define HCLGE_PF_ID_M GENMASK(2, 0) 137 #define HCLGE_VF_ID_S 3 138 #define HCLGE_VF_ID_M GENMASK(10, 3) 139 #define HCLGE_PORT_TYPE_B 11 140 #define HCLGE_NETWORK_PORT_ID_S 0 141 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 142 143 /* Reset related Registers */ 144 #define HCLGE_PF_OTHER_INT_REG 0x20600 145 #define HCLGE_MISC_RESET_STS_REG 0x20700 146 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 147 #define HCLGE_GLOBAL_RESET_REG 0x20A00 148 #define HCLGE_GLOBAL_RESET_BIT 0 149 #define HCLGE_CORE_RESET_BIT 1 150 #define HCLGE_IMP_RESET_BIT 2 151 #define HCLGE_RESET_INT_M GENMASK(7, 5) 152 #define HCLGE_FUN_RST_ING 0x20C00 153 #define HCLGE_FUN_RST_ING_B 0 154 155 /* Vector0 register bits define */ 156 #define HCLGE_VECTOR0_REG_PTP_INT_B 0 157 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 158 #define HCLGE_VECTOR0_CORERESET_INT_B 6 159 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 160 161 /* Vector0 interrupt CMDQ event source register(RW) */ 162 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 163 /* CMDQ register bits for RX event(=MBX event) */ 164 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 165 166 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 167 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 168 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 169 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U 170 #define HCLGE_TRIGGER_IMP_RESET_B 7U 171 172 #define HCLGE_MAC_DEFAULT_FRAME \ 173 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 174 #define HCLGE_MAC_MIN_FRAME 64 175 #define HCLGE_MAC_MAX_FRAME 9728 176 177 #define HCLGE_SUPPORT_1G_BIT BIT(0) 178 #define HCLGE_SUPPORT_10G_BIT BIT(1) 179 #define HCLGE_SUPPORT_25G_BIT BIT(2) 180 #define HCLGE_SUPPORT_50G_BIT BIT(3) 181 #define HCLGE_SUPPORT_100G_BIT BIT(4) 182 /* to be compatible with exsit board */ 183 #define HCLGE_SUPPORT_40G_BIT BIT(5) 184 #define HCLGE_SUPPORT_100M_BIT BIT(6) 185 #define HCLGE_SUPPORT_10M_BIT BIT(7) 186 #define HCLGE_SUPPORT_200G_BIT BIT(8) 187 #define HCLGE_SUPPORT_GE \ 188 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 189 190 enum HCLGE_DEV_STATE { 191 HCLGE_STATE_REINITING, 192 HCLGE_STATE_DOWN, 193 HCLGE_STATE_DISABLED, 194 HCLGE_STATE_REMOVING, 195 HCLGE_STATE_NIC_REGISTERED, 196 HCLGE_STATE_ROCE_REGISTERED, 197 HCLGE_STATE_SERVICE_INITED, 198 HCLGE_STATE_RST_SERVICE_SCHED, 199 HCLGE_STATE_RST_HANDLING, 200 HCLGE_STATE_MBX_SERVICE_SCHED, 201 HCLGE_STATE_MBX_HANDLING, 202 HCLGE_STATE_ERR_SERVICE_SCHED, 203 HCLGE_STATE_STATISTICS_UPDATING, 204 HCLGE_STATE_LINK_UPDATING, 205 HCLGE_STATE_RST_FAIL, 206 HCLGE_STATE_FD_TBL_CHANGED, 207 HCLGE_STATE_FD_CLEAR_ALL, 208 HCLGE_STATE_FD_USER_DEF_CHANGED, 209 HCLGE_STATE_PTP_EN, 210 HCLGE_STATE_PTP_TX_HANDLING, 211 HCLGE_STATE_MAX 212 }; 213 214 enum hclge_evt_cause { 215 HCLGE_VECTOR0_EVENT_RST, 216 HCLGE_VECTOR0_EVENT_MBX, 217 HCLGE_VECTOR0_EVENT_ERR, 218 HCLGE_VECTOR0_EVENT_PTP, 219 HCLGE_VECTOR0_EVENT_OTHER, 220 }; 221 222 enum HCLGE_MAC_SPEED { 223 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 224 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 225 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 226 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 227 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 228 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 229 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 230 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 231 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 232 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 233 }; 234 235 enum HCLGE_MAC_DUPLEX { 236 HCLGE_MAC_HALF, 237 HCLGE_MAC_FULL 238 }; 239 240 #define QUERY_SFP_SPEED 0 241 #define QUERY_ACTIVE_SPEED 1 242 243 struct hclge_mac { 244 u8 mac_id; 245 u8 phy_addr; 246 u8 flag; 247 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 248 u8 mac_addr[ETH_ALEN]; 249 u8 autoneg; 250 u8 duplex; 251 u8 support_autoneg; 252 u8 speed_type; /* 0: sfp speed, 1: active speed */ 253 u32 speed; 254 u32 max_speed; 255 u32 speed_ability; /* speed ability supported by current media */ 256 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 257 u32 fec_mode; /* active fec mode */ 258 u32 user_fec_mode; 259 u32 fec_ability; 260 int link; /* store the link status of mac & phy (if phy exists) */ 261 struct phy_device *phydev; 262 struct mii_bus *mdio_bus; 263 phy_interface_t phy_if; 264 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 265 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 266 }; 267 268 struct hclge_hw { 269 struct hclge_comm_hw hw; 270 struct hclge_mac mac; 271 int num_vec; 272 }; 273 274 enum hclge_fc_mode { 275 HCLGE_FC_NONE, 276 HCLGE_FC_RX_PAUSE, 277 HCLGE_FC_TX_PAUSE, 278 HCLGE_FC_FULL, 279 HCLGE_FC_PFC, 280 HCLGE_FC_DEFAULT 281 }; 282 283 #define HCLGE_FILTER_TYPE_VF 0 284 #define HCLGE_FILTER_TYPE_PORT 1 285 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 286 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 287 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 288 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 289 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 290 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 291 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 292 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 293 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 294 295 enum hclge_vlan_fltr_cap { 296 HCLGE_VLAN_FLTR_DEF, 297 HCLGE_VLAN_FLTR_CAN_MDF, 298 }; 299 enum hclge_link_fail_code { 300 HCLGE_LF_NORMAL, 301 HCLGE_LF_REF_CLOCK_LOST, 302 HCLGE_LF_XSFP_TX_DISABLE, 303 HCLGE_LF_XSFP_ABSENT, 304 }; 305 306 #define HCLGE_LINK_STATUS_DOWN 0 307 #define HCLGE_LINK_STATUS_UP 1 308 309 #define HCLGE_PG_NUM 4 310 #define HCLGE_SCH_MODE_SP 0 311 #define HCLGE_SCH_MODE_DWRR 1 312 struct hclge_pg_info { 313 u8 pg_id; 314 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 315 u8 tc_bit_map; 316 u32 bw_limit; 317 u8 tc_dwrr[HNAE3_MAX_TC]; 318 }; 319 320 struct hclge_tc_info { 321 u8 tc_id; 322 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 323 u8 pgid; 324 u32 bw_limit; 325 }; 326 327 struct hclge_cfg { 328 u8 tc_num; 329 u8 vlan_fliter_cap; 330 u16 tqp_desc_num; 331 u16 rx_buf_len; 332 u16 vf_rss_size_max; 333 u16 pf_rss_size_max; 334 u8 phy_addr; 335 u8 media_type; 336 u8 mac_addr[ETH_ALEN]; 337 u8 default_speed; 338 u32 numa_node_map; 339 u32 tx_spare_buf_size; 340 u16 speed_ability; 341 u16 umv_space; 342 }; 343 344 struct hclge_tm_info { 345 u8 num_tc; 346 u8 num_pg; /* It must be 1 if vNET-Base schd */ 347 u8 pg_dwrr[HCLGE_PG_NUM]; 348 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 349 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 350 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 351 enum hclge_fc_mode fc_mode; 352 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 353 u8 pfc_en; /* PFC enabled or not for user priority */ 354 }; 355 356 /* max number of mac statistics on each version */ 357 #define HCLGE_MAC_STATS_MAX_NUM_V1 87 358 #define HCLGE_MAC_STATS_MAX_NUM_V2 105 359 360 struct hclge_comm_stats_str { 361 char desc[ETH_GSTRING_LEN]; 362 u32 stats_num; 363 unsigned long offset; 364 }; 365 366 /* mac stats ,opcode id: 0x0032 */ 367 struct hclge_mac_stats { 368 u64 mac_tx_mac_pause_num; 369 u64 mac_rx_mac_pause_num; 370 u64 rsv0; 371 u64 mac_tx_pfc_pri0_pkt_num; 372 u64 mac_tx_pfc_pri1_pkt_num; 373 u64 mac_tx_pfc_pri2_pkt_num; 374 u64 mac_tx_pfc_pri3_pkt_num; 375 u64 mac_tx_pfc_pri4_pkt_num; 376 u64 mac_tx_pfc_pri5_pkt_num; 377 u64 mac_tx_pfc_pri6_pkt_num; 378 u64 mac_tx_pfc_pri7_pkt_num; 379 u64 mac_rx_pfc_pri0_pkt_num; 380 u64 mac_rx_pfc_pri1_pkt_num; 381 u64 mac_rx_pfc_pri2_pkt_num; 382 u64 mac_rx_pfc_pri3_pkt_num; 383 u64 mac_rx_pfc_pri4_pkt_num; 384 u64 mac_rx_pfc_pri5_pkt_num; 385 u64 mac_rx_pfc_pri6_pkt_num; 386 u64 mac_rx_pfc_pri7_pkt_num; 387 u64 mac_tx_total_pkt_num; 388 u64 mac_tx_total_oct_num; 389 u64 mac_tx_good_pkt_num; 390 u64 mac_tx_bad_pkt_num; 391 u64 mac_tx_good_oct_num; 392 u64 mac_tx_bad_oct_num; 393 u64 mac_tx_uni_pkt_num; 394 u64 mac_tx_multi_pkt_num; 395 u64 mac_tx_broad_pkt_num; 396 u64 mac_tx_undersize_pkt_num; 397 u64 mac_tx_oversize_pkt_num; 398 u64 mac_tx_64_oct_pkt_num; 399 u64 mac_tx_65_127_oct_pkt_num; 400 u64 mac_tx_128_255_oct_pkt_num; 401 u64 mac_tx_256_511_oct_pkt_num; 402 u64 mac_tx_512_1023_oct_pkt_num; 403 u64 mac_tx_1024_1518_oct_pkt_num; 404 u64 mac_tx_1519_2047_oct_pkt_num; 405 u64 mac_tx_2048_4095_oct_pkt_num; 406 u64 mac_tx_4096_8191_oct_pkt_num; 407 u64 rsv1; 408 u64 mac_tx_8192_9216_oct_pkt_num; 409 u64 mac_tx_9217_12287_oct_pkt_num; 410 u64 mac_tx_12288_16383_oct_pkt_num; 411 u64 mac_tx_1519_max_good_oct_pkt_num; 412 u64 mac_tx_1519_max_bad_oct_pkt_num; 413 414 u64 mac_rx_total_pkt_num; 415 u64 mac_rx_total_oct_num; 416 u64 mac_rx_good_pkt_num; 417 u64 mac_rx_bad_pkt_num; 418 u64 mac_rx_good_oct_num; 419 u64 mac_rx_bad_oct_num; 420 u64 mac_rx_uni_pkt_num; 421 u64 mac_rx_multi_pkt_num; 422 u64 mac_rx_broad_pkt_num; 423 u64 mac_rx_undersize_pkt_num; 424 u64 mac_rx_oversize_pkt_num; 425 u64 mac_rx_64_oct_pkt_num; 426 u64 mac_rx_65_127_oct_pkt_num; 427 u64 mac_rx_128_255_oct_pkt_num; 428 u64 mac_rx_256_511_oct_pkt_num; 429 u64 mac_rx_512_1023_oct_pkt_num; 430 u64 mac_rx_1024_1518_oct_pkt_num; 431 u64 mac_rx_1519_2047_oct_pkt_num; 432 u64 mac_rx_2048_4095_oct_pkt_num; 433 u64 mac_rx_4096_8191_oct_pkt_num; 434 u64 rsv2; 435 u64 mac_rx_8192_9216_oct_pkt_num; 436 u64 mac_rx_9217_12287_oct_pkt_num; 437 u64 mac_rx_12288_16383_oct_pkt_num; 438 u64 mac_rx_1519_max_good_oct_pkt_num; 439 u64 mac_rx_1519_max_bad_oct_pkt_num; 440 441 u64 mac_tx_fragment_pkt_num; 442 u64 mac_tx_undermin_pkt_num; 443 u64 mac_tx_jabber_pkt_num; 444 u64 mac_tx_err_all_pkt_num; 445 u64 mac_tx_from_app_good_pkt_num; 446 u64 mac_tx_from_app_bad_pkt_num; 447 u64 mac_rx_fragment_pkt_num; 448 u64 mac_rx_undermin_pkt_num; 449 u64 mac_rx_jabber_pkt_num; 450 u64 mac_rx_fcs_err_pkt_num; 451 u64 mac_rx_send_app_good_pkt_num; 452 u64 mac_rx_send_app_bad_pkt_num; 453 u64 mac_tx_pfc_pause_pkt_num; 454 u64 mac_rx_pfc_pause_pkt_num; 455 u64 mac_tx_ctrl_pkt_num; 456 u64 mac_rx_ctrl_pkt_num; 457 458 /* duration of pfc */ 459 u64 mac_tx_pfc_pri0_xoff_time; 460 u64 mac_tx_pfc_pri1_xoff_time; 461 u64 mac_tx_pfc_pri2_xoff_time; 462 u64 mac_tx_pfc_pri3_xoff_time; 463 u64 mac_tx_pfc_pri4_xoff_time; 464 u64 mac_tx_pfc_pri5_xoff_time; 465 u64 mac_tx_pfc_pri6_xoff_time; 466 u64 mac_tx_pfc_pri7_xoff_time; 467 u64 mac_rx_pfc_pri0_xoff_time; 468 u64 mac_rx_pfc_pri1_xoff_time; 469 u64 mac_rx_pfc_pri2_xoff_time; 470 u64 mac_rx_pfc_pri3_xoff_time; 471 u64 mac_rx_pfc_pri4_xoff_time; 472 u64 mac_rx_pfc_pri5_xoff_time; 473 u64 mac_rx_pfc_pri6_xoff_time; 474 u64 mac_rx_pfc_pri7_xoff_time; 475 476 /* duration of pause */ 477 u64 mac_tx_pause_xoff_time; 478 u64 mac_rx_pause_xoff_time; 479 }; 480 481 #define HCLGE_STATS_TIMER_INTERVAL 300UL 482 483 struct hclge_vlan_type_cfg { 484 u16 rx_ot_fst_vlan_type; 485 u16 rx_ot_sec_vlan_type; 486 u16 rx_in_fst_vlan_type; 487 u16 rx_in_sec_vlan_type; 488 u16 tx_ot_vlan_type; 489 u16 tx_in_vlan_type; 490 }; 491 492 enum HCLGE_FD_MODE { 493 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 494 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 495 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 496 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 497 }; 498 499 enum HCLGE_FD_KEY_TYPE { 500 HCLGE_FD_KEY_BASE_ON_PTYPE, 501 HCLGE_FD_KEY_BASE_ON_TUPLE, 502 }; 503 504 enum HCLGE_FD_STAGE { 505 HCLGE_FD_STAGE_1, 506 HCLGE_FD_STAGE_2, 507 MAX_STAGE_NUM, 508 }; 509 510 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 511 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 512 * tuples of non-tunnel packet 513 */ 514 enum HCLGE_FD_TUPLE { 515 OUTER_DST_MAC, 516 OUTER_SRC_MAC, 517 OUTER_VLAN_TAG_FST, 518 OUTER_VLAN_TAG_SEC, 519 OUTER_ETH_TYPE, 520 OUTER_L2_RSV, 521 OUTER_IP_TOS, 522 OUTER_IP_PROTO, 523 OUTER_SRC_IP, 524 OUTER_DST_IP, 525 OUTER_L3_RSV, 526 OUTER_SRC_PORT, 527 OUTER_DST_PORT, 528 OUTER_L4_RSV, 529 OUTER_TUN_VNI, 530 OUTER_TUN_FLOW_ID, 531 INNER_DST_MAC, 532 INNER_SRC_MAC, 533 INNER_VLAN_TAG_FST, 534 INNER_VLAN_TAG_SEC, 535 INNER_ETH_TYPE, 536 INNER_L2_RSV, 537 INNER_IP_TOS, 538 INNER_IP_PROTO, 539 INNER_SRC_IP, 540 INNER_DST_IP, 541 INNER_L3_RSV, 542 INNER_SRC_PORT, 543 INNER_DST_PORT, 544 INNER_L4_RSV, 545 MAX_TUPLE, 546 }; 547 548 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 549 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 550 551 enum HCLGE_FD_META_DATA { 552 PACKET_TYPE_ID, 553 IP_FRAGEMENT, 554 ROCE_TYPE, 555 NEXT_KEY, 556 VLAN_NUMBER, 557 SRC_VPORT, 558 DST_VPORT, 559 TUNNEL_PACKET, 560 MAX_META_DATA, 561 }; 562 563 enum HCLGE_FD_KEY_OPT { 564 KEY_OPT_U8, 565 KEY_OPT_LE16, 566 KEY_OPT_LE32, 567 KEY_OPT_MAC, 568 KEY_OPT_IP, 569 KEY_OPT_VNI, 570 }; 571 572 struct key_info { 573 u8 key_type; 574 u8 key_length; /* use bit as unit */ 575 enum HCLGE_FD_KEY_OPT key_opt; 576 int offset; 577 int moffset; 578 }; 579 580 #define MAX_KEY_LENGTH 400 581 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 582 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 583 #define MAX_META_DATA_LENGTH 32 584 585 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 586 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 587 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 588 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 589 590 /* assigned by firmware, the real filter number for each pf may be less */ 591 #define MAX_FD_FILTER_NUM 4096 592 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 593 594 #define hclge_read_dev(a, reg) \ 595 hclge_comm_read_reg((a)->hw.io_base, reg) 596 #define hclge_write_dev(a, reg, value) \ 597 hclge_comm_write_reg((a)->hw.io_base, reg, value) 598 599 enum HCLGE_FD_ACTIVE_RULE_TYPE { 600 HCLGE_FD_RULE_NONE, 601 HCLGE_FD_ARFS_ACTIVE, 602 HCLGE_FD_EP_ACTIVE, 603 HCLGE_FD_TC_FLOWER_ACTIVE, 604 }; 605 606 enum HCLGE_FD_PACKET_TYPE { 607 NIC_PACKET, 608 ROCE_PACKET, 609 }; 610 611 enum HCLGE_FD_ACTION { 612 HCLGE_FD_ACTION_SELECT_QUEUE, 613 HCLGE_FD_ACTION_DROP_PACKET, 614 HCLGE_FD_ACTION_SELECT_TC, 615 }; 616 617 enum HCLGE_FD_NODE_STATE { 618 HCLGE_FD_TO_ADD, 619 HCLGE_FD_TO_DEL, 620 HCLGE_FD_ACTIVE, 621 HCLGE_FD_DELETED, 622 }; 623 624 enum HCLGE_FD_USER_DEF_LAYER { 625 HCLGE_FD_USER_DEF_NONE, 626 HCLGE_FD_USER_DEF_L2, 627 HCLGE_FD_USER_DEF_L3, 628 HCLGE_FD_USER_DEF_L4, 629 }; 630 631 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 632 struct hclge_fd_user_def_cfg { 633 u16 ref_cnt; 634 u16 offset; 635 }; 636 637 struct hclge_fd_user_def_info { 638 enum HCLGE_FD_USER_DEF_LAYER layer; 639 u16 data; 640 u16 data_mask; 641 u16 offset; 642 }; 643 644 struct hclge_fd_key_cfg { 645 u8 key_sel; 646 u8 inner_sipv6_word_en; 647 u8 inner_dipv6_word_en; 648 u8 outer_sipv6_word_en; 649 u8 outer_dipv6_word_en; 650 u32 tuple_active; 651 u32 meta_data_active; 652 }; 653 654 struct hclge_fd_cfg { 655 u8 fd_mode; 656 u16 max_key_length; /* use bit as unit */ 657 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 658 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 659 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 660 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 661 }; 662 663 #define IPV4_INDEX 3 664 #define IPV6_SIZE 4 665 struct hclge_fd_rule_tuples { 666 u8 src_mac[ETH_ALEN]; 667 u8 dst_mac[ETH_ALEN]; 668 /* Be compatible for ip address of both ipv4 and ipv6. 669 * For ipv4 address, we store it in src/dst_ip[3]. 670 */ 671 u32 src_ip[IPV6_SIZE]; 672 u32 dst_ip[IPV6_SIZE]; 673 u16 src_port; 674 u16 dst_port; 675 u16 vlan_tag1; 676 u16 ether_proto; 677 u16 l2_user_def; 678 u16 l3_user_def; 679 u32 l4_user_def; 680 u8 ip_tos; 681 u8 ip_proto; 682 }; 683 684 struct hclge_fd_rule { 685 struct hlist_node rule_node; 686 struct hclge_fd_rule_tuples tuples; 687 struct hclge_fd_rule_tuples tuples_mask; 688 u32 unused_tuple; 689 u32 flow_type; 690 union { 691 struct { 692 unsigned long cookie; 693 u8 tc; 694 } cls_flower; 695 struct { 696 u16 flow_id; /* only used for arfs */ 697 } arfs; 698 struct { 699 struct hclge_fd_user_def_info user_def; 700 } ep; 701 }; 702 u16 queue_id; 703 u16 vf_id; 704 u16 location; 705 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 706 enum HCLGE_FD_NODE_STATE state; 707 u8 action; 708 }; 709 710 struct hclge_fd_ad_data { 711 u16 ad_id; 712 u8 drop_packet; 713 u8 forward_to_direct_queue; 714 u16 queue_id; 715 u8 use_counter; 716 u8 counter_id; 717 u8 use_next_stage; 718 u8 write_rule_id_to_bd; 719 u8 next_input_key; 720 u16 rule_id; 721 u16 tc_size; 722 u8 override_tc; 723 }; 724 725 enum HCLGE_MAC_NODE_STATE { 726 HCLGE_MAC_TO_ADD, 727 HCLGE_MAC_TO_DEL, 728 HCLGE_MAC_ACTIVE 729 }; 730 731 struct hclge_mac_node { 732 struct list_head node; 733 enum HCLGE_MAC_NODE_STATE state; 734 u8 mac_addr[ETH_ALEN]; 735 }; 736 737 enum HCLGE_MAC_ADDR_TYPE { 738 HCLGE_MAC_ADDR_UC, 739 HCLGE_MAC_ADDR_MC 740 }; 741 742 struct hclge_vport_vlan_cfg { 743 struct list_head node; 744 int hd_tbl_status; 745 u16 vlan_id; 746 }; 747 748 struct hclge_rst_stats { 749 u32 reset_done_cnt; /* the number of reset has completed */ 750 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 751 u32 pf_rst_cnt; /* the number of PF reset */ 752 u32 flr_rst_cnt; /* the number of FLR */ 753 u32 global_rst_cnt; /* the number of GLOBAL */ 754 u32 imp_rst_cnt; /* the number of IMP reset */ 755 u32 reset_cnt; /* the number of reset */ 756 u32 reset_fail_cnt; /* the number of reset fail */ 757 }; 758 759 /* time and register status when mac tunnel interruption occur */ 760 struct hclge_mac_tnl_stats { 761 u64 time; 762 u32 status; 763 }; 764 765 #define HCLGE_RESET_INTERVAL (10 * HZ) 766 #define HCLGE_WAIT_RESET_DONE 100 767 768 #pragma pack(1) 769 struct hclge_vf_vlan_cfg { 770 u8 mbx_cmd; 771 u8 subcode; 772 union { 773 struct { 774 u8 is_kill; 775 u16 vlan; 776 u16 proto; 777 }; 778 u8 enable; 779 }; 780 }; 781 782 #pragma pack() 783 784 /* For each bit of TCAM entry, it uses a pair of 'x' and 785 * 'y' to indicate which value to match, like below: 786 * ---------------------------------- 787 * | bit x | bit y | search value | 788 * ---------------------------------- 789 * | 0 | 0 | always hit | 790 * ---------------------------------- 791 * | 1 | 0 | match '0' | 792 * ---------------------------------- 793 * | 0 | 1 | match '1' | 794 * ---------------------------------- 795 * | 1 | 1 | invalid | 796 * ---------------------------------- 797 * Then for input key(k) and mask(v), we can calculate the value by 798 * the formulae: 799 * x = (~k) & v 800 * y = (k ^ ~v) & k 801 */ 802 #define calc_x(x, k, v) (x = ~(k) & (v)) 803 #define calc_y(y, k, v) \ 804 do { \ 805 const typeof(k) _k_ = (k); \ 806 const typeof(v) _v_ = (v); \ 807 (y) = (_k_ ^ ~_v_) & (_k_); \ 808 } while (0) 809 810 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 811 #define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset))) 812 813 #define HCLGE_MAC_TNL_LOG_SIZE 8 814 #define HCLGE_VPORT_NUM 256 815 struct hclge_dev { 816 struct pci_dev *pdev; 817 struct hnae3_ae_dev *ae_dev; 818 struct hclge_hw hw; 819 struct hclge_misc_vector misc_vector; 820 struct hclge_mac_stats mac_stats; 821 unsigned long state; 822 unsigned long flr_state; 823 unsigned long last_reset_time; 824 825 enum hnae3_reset_type reset_type; 826 enum hnae3_reset_type reset_level; 827 unsigned long default_reset_request; 828 unsigned long reset_request; /* reset has been requested */ 829 unsigned long reset_pending; /* client rst is pending to be served */ 830 struct hclge_rst_stats rst_stats; 831 struct semaphore reset_sem; /* protect reset process */ 832 u32 fw_version; 833 u16 num_tqps; /* Num task queue pairs of this PF */ 834 u16 num_req_vfs; /* Num VFs requested for this PF */ 835 836 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 837 u16 alloc_rss_size; /* Allocated RSS task queue */ 838 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 839 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 840 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */ 841 842 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 843 u16 num_alloc_vport; /* Num vports this driver supports */ 844 u32 numa_node_mask; 845 u16 rx_buf_len; 846 u16 num_tx_desc; /* desc num of per tx queue */ 847 u16 num_rx_desc; /* desc num of per rx queue */ 848 u8 hw_tc_map; 849 enum hclge_fc_mode fc_mode_last_time; 850 u8 support_sfp_query; 851 852 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 853 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 854 u8 tx_sch_mode; 855 u8 tc_max; 856 u8 pfc_max; 857 858 u8 default_up; 859 u8 dcbx_cap; 860 struct hclge_tm_info tm_info; 861 862 u16 num_msi; 863 u16 num_msi_left; 864 u16 num_msi_used; 865 u16 *vector_status; 866 int *vector_irq; 867 u16 num_nic_msi; /* Num of nic vectors for this PF */ 868 u16 num_roce_msi; /* Num of roce vectors for this PF */ 869 870 unsigned long service_timer_period; 871 unsigned long service_timer_previous; 872 struct timer_list reset_timer; 873 struct delayed_work service_task; 874 875 bool cur_promisc; 876 int num_alloc_vfs; /* Actual number of VFs allocated */ 877 878 struct hclge_comm_tqp *htqp; 879 struct hclge_vport *vport; 880 881 struct dentry *hclge_dbgfs; 882 883 struct hnae3_client *nic_client; 884 struct hnae3_client *roce_client; 885 886 #define HCLGE_FLAG_MAIN BIT(0) 887 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 888 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 889 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 890 u32 flag; 891 892 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 893 u32 tx_buf_size; /* Tx buffer size for each TC */ 894 u32 dv_buf_size; /* Dv buffer size for each TC */ 895 896 u32 mps; /* Max packet size */ 897 /* vport_lock protect resource shared by vports */ 898 struct mutex vport_lock; 899 900 struct hclge_vlan_type_cfg vlan_type_cfg; 901 902 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 903 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 904 905 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 906 907 struct hclge_fd_cfg fd_cfg; 908 struct hlist_head fd_rule_list; 909 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 910 u16 hclge_fd_rule_num; 911 unsigned long serv_processed_cnt; 912 unsigned long last_serv_processed; 913 unsigned long last_rst_scheduled; 914 unsigned long last_mbx_scheduled; 915 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 916 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 917 u8 fd_en; 918 bool gro_en; 919 920 u16 wanted_umv_size; 921 /* max available unicast mac vlan space */ 922 u16 max_umv_size; 923 /* private unicast mac vlan space, it's same for PF and its VFs */ 924 u16 priv_umv_size; 925 /* unicast mac vlan space shared by PF and its VFs */ 926 u16 share_umv_size; 927 /* multicast mac address number used by PF and its VFs */ 928 u16 used_mc_mac_num; 929 930 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 931 HCLGE_MAC_TNL_LOG_SIZE); 932 933 /* affinity mask and notify for misc interrupt */ 934 cpumask_t affinity_mask; 935 struct hclge_ptp *ptp; 936 struct devlink *devlink; 937 struct hclge_comm_rss_cfg rss_cfg; 938 }; 939 940 /* VPort level vlan tag configuration for TX direction */ 941 struct hclge_tx_vtag_cfg { 942 bool accept_tag1; /* Whether accept tag1 packet from host */ 943 bool accept_untag1; /* Whether accept untag1 packet from host */ 944 bool accept_tag2; 945 bool accept_untag2; 946 bool insert_tag1_en; /* Whether insert inner vlan tag */ 947 bool insert_tag2_en; /* Whether insert outer vlan tag */ 948 u16 default_tag1; /* The default inner vlan tag to insert */ 949 u16 default_tag2; /* The default outer vlan tag to insert */ 950 bool tag_shift_mode_en; 951 }; 952 953 /* VPort level vlan tag configuration for RX direction */ 954 struct hclge_rx_vtag_cfg { 955 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 956 bool strip_tag1_en; /* Whether strip inner vlan tag */ 957 bool strip_tag2_en; /* Whether strip outer vlan tag */ 958 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 959 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 960 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 961 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 962 }; 963 964 enum HCLGE_VPORT_STATE { 965 HCLGE_VPORT_STATE_ALIVE, 966 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 967 HCLGE_VPORT_STATE_PROMISC_CHANGE, 968 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 969 HCLGE_VPORT_STATE_MAX 970 }; 971 972 struct hclge_vlan_info { 973 u16 vlan_proto; /* so far support 802.1Q only */ 974 u16 qos; 975 u16 vlan_tag; 976 }; 977 978 struct hclge_port_base_vlan_config { 979 u16 state; 980 struct hclge_vlan_info vlan_info; 981 }; 982 983 struct hclge_vf_info { 984 int link_state; 985 u8 mac[ETH_ALEN]; 986 u32 spoofchk; 987 u32 max_tx_rate; 988 u32 trusted; 989 u8 request_uc_en; 990 u8 request_mc_en; 991 u8 request_bc_en; 992 }; 993 994 struct hclge_vport { 995 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 996 997 u16 qs_offset; 998 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 999 u8 dwrr; 1000 1001 bool req_vlan_fltr_en; 1002 bool cur_vlan_fltr_en; 1003 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 1004 struct hclge_port_base_vlan_config port_base_vlan_cfg; 1005 struct hclge_tx_vtag_cfg txvlan_cfg; 1006 struct hclge_rx_vtag_cfg rxvlan_cfg; 1007 1008 u16 used_umv_num; 1009 1010 u16 vport_id; 1011 struct hclge_dev *back; /* Back reference to associated dev */ 1012 struct hnae3_handle nic; 1013 struct hnae3_handle roce; 1014 1015 unsigned long state; 1016 unsigned long last_active_jiffies; 1017 u32 mps; /* Max packet size */ 1018 struct hclge_vf_info vf_info; 1019 1020 u8 overflow_promisc_flags; 1021 u8 last_promisc_flags; 1022 1023 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1024 struct list_head uc_mac_list; /* Store VF unicast table */ 1025 struct list_head mc_mac_list; /* Store VF multicast table */ 1026 struct list_head vlan_list; /* Store VF vlan table */ 1027 }; 1028 1029 struct hclge_speed_bit_map { 1030 u32 speed; 1031 u32 speed_bit; 1032 }; 1033 1034 struct hclge_mac_speed_map { 1035 u32 speed_drv; /* speed defined in driver */ 1036 u32 speed_fw; /* speed defined in firmware */ 1037 }; 1038 1039 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1040 bool en_mc_pmc, bool en_bc_pmc); 1041 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1042 const unsigned char *addr); 1043 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1044 const unsigned char *addr); 1045 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1046 const unsigned char *addr); 1047 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1048 const unsigned char *addr); 1049 1050 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1051 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1052 int vector_id, bool en, 1053 struct hnae3_ring_chain_node *ring_chain); 1054 1055 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1056 { 1057 struct hclge_comm_tqp *tqp = 1058 container_of(queue, struct hclge_comm_tqp, q); 1059 1060 return tqp->index; 1061 } 1062 1063 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 1064 { 1065 return !!hdev->reset_pending; 1066 } 1067 1068 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1069 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 1070 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1071 u16 vlan_id, bool is_kill); 1072 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1073 1074 int hclge_buffer_alloc(struct hclge_dev *hdev); 1075 int hclge_rss_init_hw(struct hclge_dev *hdev); 1076 1077 void hclge_mbx_handler(struct hclge_dev *hdev); 1078 int hclge_reset_tqp(struct hnae3_handle *handle); 1079 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1080 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1081 int hclge_vport_start(struct hclge_vport *vport); 1082 void hclge_vport_stop(struct hclge_vport *vport); 1083 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1084 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1085 char *buf, int len); 1086 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1087 int hclge_notify_client(struct hclge_dev *hdev, 1088 enum hnae3_reset_notify_type type); 1089 int hclge_update_mac_list(struct hclge_vport *vport, 1090 enum HCLGE_MAC_NODE_STATE state, 1091 enum HCLGE_MAC_ADDR_TYPE mac_type, 1092 const unsigned char *addr); 1093 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1094 const u8 *old_addr, const u8 *new_addr); 1095 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1096 enum HCLGE_MAC_ADDR_TYPE mac_type); 1097 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1098 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1099 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1100 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1101 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1102 struct hclge_vlan_info *vlan_info); 1103 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1104 u16 state, 1105 struct hclge_vlan_info *vlan_info); 1106 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1107 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, 1108 struct hclge_desc *desc); 1109 void hclge_report_hw_error(struct hclge_dev *hdev, 1110 enum hnae3_hw_error_type type); 1111 void hclge_inform_vf_promisc_info(struct hclge_vport *vport); 1112 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1113 int hclge_push_vf_link_status(struct hclge_vport *vport); 1114 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); 1115 int hclge_mac_update_stats(struct hclge_dev *hdev); 1116 #endif 1117