1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 12 #include "hclge_cmd.h" 13 #include "hnae3.h" 14 15 #define HCLGE_MOD_VERSION "1.0" 16 #define HCLGE_DRIVER_NAME "hclge" 17 18 #define HCLGE_MAX_PF_NUM 8 19 20 #define HCLGE_RD_FIRST_STATS_NUM 2 21 #define HCLGE_RD_OTHER_STATS_NUM 4 22 23 #define HCLGE_INVALID_VPORT 0xffff 24 25 #define HCLGE_PF_CFG_BLOCK_SIZE 32 26 #define HCLGE_PF_CFG_DESC_NUM \ 27 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 28 29 #define HCLGE_VECTOR_REG_BASE 0x20000 30 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 31 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 32 33 #define HCLGE_VECTOR_REG_OFFSET 0x4 34 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 35 #define HCLGE_VECTOR_VF_OFFSET 0x100000 36 37 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 38 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 39 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 40 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010 41 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014 42 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 43 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C 44 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 45 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024 46 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028 47 #define HCLGE_CMDQ_INTR_SRC_REG 0x27100 48 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 49 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 50 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 51 52 /* bar registers for common func */ 53 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600 54 #define HCLGE_RAS_OTHER_STS_REG 0x20B00 55 #define HCLGE_FUNC_RESET_STS_REG 0x20C00 56 #define HCLGE_GRO_EN_REG 0x28000 57 58 /* bar registers for rcb */ 59 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 60 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 61 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 62 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 63 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 64 #define HCLGE_RING_RX_TAIL_REG 0x80018 65 #define HCLGE_RING_RX_HEAD_REG 0x8001C 66 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 67 #define HCLGE_RING_RX_OFFSET_REG 0x80024 68 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 69 #define HCLGE_RING_RX_STASH_REG 0x80030 70 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 71 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 72 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 73 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 74 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 75 #define HCLGE_RING_TX_TC_REG 0x80050 76 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 77 #define HCLGE_RING_TX_TAIL_REG 0x80058 78 #define HCLGE_RING_TX_HEAD_REG 0x8005C 79 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 80 #define HCLGE_RING_TX_OFFSET_REG 0x80064 81 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 82 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 83 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 84 #define HCLGE_RING_EN_REG 0x80090 85 86 /* bar registers for tqp interrupt */ 87 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 88 #define HCLGE_TQP_INTR_GL0_REG 0x20100 89 #define HCLGE_TQP_INTR_GL1_REG 0x20200 90 #define HCLGE_TQP_INTR_GL2_REG 0x20300 91 #define HCLGE_TQP_INTR_RL_REG 0x20900 92 93 #define HCLGE_RSS_IND_TBL_SIZE 512 94 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 95 #define HCLGE_RSS_KEY_SIZE 40 96 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 97 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 98 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 99 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 100 #define HCLGE_RSS_CFG_TBL_NUM \ 101 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE) 102 103 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 104 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 105 #define HCLGE_D_PORT_BIT BIT(0) 106 #define HCLGE_S_PORT_BIT BIT(1) 107 #define HCLGE_D_IP_BIT BIT(2) 108 #define HCLGE_S_IP_BIT BIT(3) 109 #define HCLGE_V_TAG_BIT BIT(4) 110 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 111 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT) 112 113 #define HCLGE_RSS_TC_SIZE_0 1 114 #define HCLGE_RSS_TC_SIZE_1 2 115 #define HCLGE_RSS_TC_SIZE_2 4 116 #define HCLGE_RSS_TC_SIZE_3 8 117 #define HCLGE_RSS_TC_SIZE_4 16 118 #define HCLGE_RSS_TC_SIZE_5 32 119 #define HCLGE_RSS_TC_SIZE_6 64 120 #define HCLGE_RSS_TC_SIZE_7 128 121 122 #define HCLGE_UMV_TBL_SIZE 3072 123 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 124 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 125 126 #define HCLGE_TQP_RESET_TRY_TIMES 200 127 128 #define HCLGE_PHY_PAGE_MDIX 0 129 #define HCLGE_PHY_PAGE_COPPER 0 130 131 /* Page Selection Reg. */ 132 #define HCLGE_PHY_PAGE_REG 22 133 134 /* Copper Specific Control Register */ 135 #define HCLGE_PHY_CSC_REG 16 136 137 /* Copper Specific Status Register */ 138 #define HCLGE_PHY_CSS_REG 17 139 140 #define HCLGE_PHY_MDIX_CTRL_S 5 141 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 142 143 #define HCLGE_PHY_MDIX_STATUS_B 6 144 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 145 146 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 147 148 /* Factor used to calculate offset and bitmap of VF num */ 149 #define HCLGE_VF_NUM_PER_CMD 64 150 151 enum HLCGE_PORT_TYPE { 152 HOST_PORT, 153 NETWORK_PORT 154 }; 155 156 #define PF_VPORT_ID 0 157 158 #define HCLGE_PF_ID_S 0 159 #define HCLGE_PF_ID_M GENMASK(2, 0) 160 #define HCLGE_VF_ID_S 3 161 #define HCLGE_VF_ID_M GENMASK(10, 3) 162 #define HCLGE_PORT_TYPE_B 11 163 #define HCLGE_NETWORK_PORT_ID_S 0 164 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 165 166 /* Reset related Registers */ 167 #define HCLGE_PF_OTHER_INT_REG 0x20600 168 #define HCLGE_MISC_RESET_STS_REG 0x20700 169 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 170 #define HCLGE_GLOBAL_RESET_REG 0x20A00 171 #define HCLGE_GLOBAL_RESET_BIT 0 172 #define HCLGE_CORE_RESET_BIT 1 173 #define HCLGE_IMP_RESET_BIT 2 174 #define HCLGE_RESET_INT_M GENMASK(7, 5) 175 #define HCLGE_FUN_RST_ING 0x20C00 176 #define HCLGE_FUN_RST_ING_B 0 177 178 /* Vector0 register bits define */ 179 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 180 #define HCLGE_VECTOR0_CORERESET_INT_B 6 181 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 182 183 /* Vector0 interrupt CMDQ event source register(RW) */ 184 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 185 /* CMDQ register bits for RX event(=MBX event) */ 186 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 187 188 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 189 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 190 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 191 192 #define HCLGE_MAC_DEFAULT_FRAME \ 193 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 194 #define HCLGE_MAC_MIN_FRAME 64 195 #define HCLGE_MAC_MAX_FRAME 9728 196 197 #define HCLGE_SUPPORT_1G_BIT BIT(0) 198 #define HCLGE_SUPPORT_10G_BIT BIT(1) 199 #define HCLGE_SUPPORT_25G_BIT BIT(2) 200 #define HCLGE_SUPPORT_50G_BIT BIT(3) 201 #define HCLGE_SUPPORT_100G_BIT BIT(4) 202 /* to be compatible with exsit board */ 203 #define HCLGE_SUPPORT_40G_BIT BIT(5) 204 #define HCLGE_SUPPORT_100M_BIT BIT(6) 205 #define HCLGE_SUPPORT_10M_BIT BIT(7) 206 #define HCLGE_SUPPORT_200G_BIT BIT(8) 207 #define HCLGE_SUPPORT_GE \ 208 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 209 210 enum HCLGE_DEV_STATE { 211 HCLGE_STATE_REINITING, 212 HCLGE_STATE_DOWN, 213 HCLGE_STATE_DISABLED, 214 HCLGE_STATE_REMOVING, 215 HCLGE_STATE_NIC_REGISTERED, 216 HCLGE_STATE_ROCE_REGISTERED, 217 HCLGE_STATE_SERVICE_INITED, 218 HCLGE_STATE_RST_SERVICE_SCHED, 219 HCLGE_STATE_RST_HANDLING, 220 HCLGE_STATE_MBX_SERVICE_SCHED, 221 HCLGE_STATE_MBX_HANDLING, 222 HCLGE_STATE_STATISTICS_UPDATING, 223 HCLGE_STATE_CMD_DISABLE, 224 HCLGE_STATE_LINK_UPDATING, 225 HCLGE_STATE_PROMISC_CHANGED, 226 HCLGE_STATE_RST_FAIL, 227 HCLGE_STATE_MAX 228 }; 229 230 enum hclge_evt_cause { 231 HCLGE_VECTOR0_EVENT_RST, 232 HCLGE_VECTOR0_EVENT_MBX, 233 HCLGE_VECTOR0_EVENT_ERR, 234 HCLGE_VECTOR0_EVENT_OTHER, 235 }; 236 237 enum HCLGE_MAC_SPEED { 238 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 239 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 240 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 241 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 242 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 243 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 244 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 245 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 246 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 247 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 248 }; 249 250 enum HCLGE_MAC_DUPLEX { 251 HCLGE_MAC_HALF, 252 HCLGE_MAC_FULL 253 }; 254 255 #define QUERY_SFP_SPEED 0 256 #define QUERY_ACTIVE_SPEED 1 257 258 struct hclge_mac { 259 u8 mac_id; 260 u8 phy_addr; 261 u8 flag; 262 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 263 u8 mac_addr[ETH_ALEN]; 264 u8 autoneg; 265 u8 duplex; 266 u8 support_autoneg; 267 u8 speed_type; /* 0: sfp speed, 1: active speed */ 268 u32 speed; 269 u32 max_speed; 270 u32 speed_ability; /* speed ability supported by current media */ 271 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 272 u32 fec_mode; /* active fec mode */ 273 u32 user_fec_mode; 274 u32 fec_ability; 275 int link; /* store the link status of mac & phy (if phy exists) */ 276 struct phy_device *phydev; 277 struct mii_bus *mdio_bus; 278 phy_interface_t phy_if; 279 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 280 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 281 }; 282 283 struct hclge_hw { 284 void __iomem *io_base; 285 void __iomem *mem_base; 286 struct hclge_mac mac; 287 int num_vec; 288 struct hclge_cmq cmq; 289 }; 290 291 /* TQP stats */ 292 struct hlcge_tqp_stats { 293 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 294 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 295 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 296 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 297 }; 298 299 struct hclge_tqp { 300 /* copy of device pointer from pci_dev, 301 * used when perform DMA mapping 302 */ 303 struct device *dev; 304 struct hnae3_queue q; 305 struct hlcge_tqp_stats tqp_stats; 306 u16 index; /* Global index in a NIC controller */ 307 308 bool alloced; 309 }; 310 311 enum hclge_fc_mode { 312 HCLGE_FC_NONE, 313 HCLGE_FC_RX_PAUSE, 314 HCLGE_FC_TX_PAUSE, 315 HCLGE_FC_FULL, 316 HCLGE_FC_PFC, 317 HCLGE_FC_DEFAULT 318 }; 319 320 enum hclge_link_fail_code { 321 HCLGE_LF_NORMAL, 322 HCLGE_LF_REF_CLOCK_LOST, 323 HCLGE_LF_XSFP_TX_DISABLE, 324 HCLGE_LF_XSFP_ABSENT, 325 }; 326 327 #define HCLGE_LINK_STATUS_DOWN 0 328 #define HCLGE_LINK_STATUS_UP 1 329 330 #define HCLGE_PG_NUM 4 331 #define HCLGE_SCH_MODE_SP 0 332 #define HCLGE_SCH_MODE_DWRR 1 333 struct hclge_pg_info { 334 u8 pg_id; 335 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 336 u8 tc_bit_map; 337 u32 bw_limit; 338 u8 tc_dwrr[HNAE3_MAX_TC]; 339 }; 340 341 struct hclge_tc_info { 342 u8 tc_id; 343 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 344 u8 pgid; 345 u32 bw_limit; 346 }; 347 348 struct hclge_cfg { 349 u8 vmdq_vport_num; 350 u8 tc_num; 351 u16 tqp_desc_num; 352 u16 rx_buf_len; 353 u16 vf_rss_size_max; 354 u16 pf_rss_size_max; 355 u8 phy_addr; 356 u8 media_type; 357 u8 mac_addr[ETH_ALEN]; 358 u8 default_speed; 359 u32 numa_node_map; 360 u16 speed_ability; 361 u16 umv_space; 362 }; 363 364 struct hclge_tm_info { 365 u8 num_tc; 366 u8 num_pg; /* It must be 1 if vNET-Base schd */ 367 u8 pg_dwrr[HCLGE_PG_NUM]; 368 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 369 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 370 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 371 enum hclge_fc_mode fc_mode; 372 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 373 u8 pfc_en; /* PFC enabled or not for user priority */ 374 }; 375 376 struct hclge_comm_stats_str { 377 char desc[ETH_GSTRING_LEN]; 378 unsigned long offset; 379 }; 380 381 /* mac stats ,opcode id: 0x0032 */ 382 struct hclge_mac_stats { 383 u64 mac_tx_mac_pause_num; 384 u64 mac_rx_mac_pause_num; 385 u64 mac_tx_pfc_pri0_pkt_num; 386 u64 mac_tx_pfc_pri1_pkt_num; 387 u64 mac_tx_pfc_pri2_pkt_num; 388 u64 mac_tx_pfc_pri3_pkt_num; 389 u64 mac_tx_pfc_pri4_pkt_num; 390 u64 mac_tx_pfc_pri5_pkt_num; 391 u64 mac_tx_pfc_pri6_pkt_num; 392 u64 mac_tx_pfc_pri7_pkt_num; 393 u64 mac_rx_pfc_pri0_pkt_num; 394 u64 mac_rx_pfc_pri1_pkt_num; 395 u64 mac_rx_pfc_pri2_pkt_num; 396 u64 mac_rx_pfc_pri3_pkt_num; 397 u64 mac_rx_pfc_pri4_pkt_num; 398 u64 mac_rx_pfc_pri5_pkt_num; 399 u64 mac_rx_pfc_pri6_pkt_num; 400 u64 mac_rx_pfc_pri7_pkt_num; 401 u64 mac_tx_total_pkt_num; 402 u64 mac_tx_total_oct_num; 403 u64 mac_tx_good_pkt_num; 404 u64 mac_tx_bad_pkt_num; 405 u64 mac_tx_good_oct_num; 406 u64 mac_tx_bad_oct_num; 407 u64 mac_tx_uni_pkt_num; 408 u64 mac_tx_multi_pkt_num; 409 u64 mac_tx_broad_pkt_num; 410 u64 mac_tx_undersize_pkt_num; 411 u64 mac_tx_oversize_pkt_num; 412 u64 mac_tx_64_oct_pkt_num; 413 u64 mac_tx_65_127_oct_pkt_num; 414 u64 mac_tx_128_255_oct_pkt_num; 415 u64 mac_tx_256_511_oct_pkt_num; 416 u64 mac_tx_512_1023_oct_pkt_num; 417 u64 mac_tx_1024_1518_oct_pkt_num; 418 u64 mac_tx_1519_2047_oct_pkt_num; 419 u64 mac_tx_2048_4095_oct_pkt_num; 420 u64 mac_tx_4096_8191_oct_pkt_num; 421 u64 rsv0; 422 u64 mac_tx_8192_9216_oct_pkt_num; 423 u64 mac_tx_9217_12287_oct_pkt_num; 424 u64 mac_tx_12288_16383_oct_pkt_num; 425 u64 mac_tx_1519_max_good_oct_pkt_num; 426 u64 mac_tx_1519_max_bad_oct_pkt_num; 427 428 u64 mac_rx_total_pkt_num; 429 u64 mac_rx_total_oct_num; 430 u64 mac_rx_good_pkt_num; 431 u64 mac_rx_bad_pkt_num; 432 u64 mac_rx_good_oct_num; 433 u64 mac_rx_bad_oct_num; 434 u64 mac_rx_uni_pkt_num; 435 u64 mac_rx_multi_pkt_num; 436 u64 mac_rx_broad_pkt_num; 437 u64 mac_rx_undersize_pkt_num; 438 u64 mac_rx_oversize_pkt_num; 439 u64 mac_rx_64_oct_pkt_num; 440 u64 mac_rx_65_127_oct_pkt_num; 441 u64 mac_rx_128_255_oct_pkt_num; 442 u64 mac_rx_256_511_oct_pkt_num; 443 u64 mac_rx_512_1023_oct_pkt_num; 444 u64 mac_rx_1024_1518_oct_pkt_num; 445 u64 mac_rx_1519_2047_oct_pkt_num; 446 u64 mac_rx_2048_4095_oct_pkt_num; 447 u64 mac_rx_4096_8191_oct_pkt_num; 448 u64 rsv1; 449 u64 mac_rx_8192_9216_oct_pkt_num; 450 u64 mac_rx_9217_12287_oct_pkt_num; 451 u64 mac_rx_12288_16383_oct_pkt_num; 452 u64 mac_rx_1519_max_good_oct_pkt_num; 453 u64 mac_rx_1519_max_bad_oct_pkt_num; 454 455 u64 mac_tx_fragment_pkt_num; 456 u64 mac_tx_undermin_pkt_num; 457 u64 mac_tx_jabber_pkt_num; 458 u64 mac_tx_err_all_pkt_num; 459 u64 mac_tx_from_app_good_pkt_num; 460 u64 mac_tx_from_app_bad_pkt_num; 461 u64 mac_rx_fragment_pkt_num; 462 u64 mac_rx_undermin_pkt_num; 463 u64 mac_rx_jabber_pkt_num; 464 u64 mac_rx_fcs_err_pkt_num; 465 u64 mac_rx_send_app_good_pkt_num; 466 u64 mac_rx_send_app_bad_pkt_num; 467 u64 mac_tx_pfc_pause_pkt_num; 468 u64 mac_rx_pfc_pause_pkt_num; 469 u64 mac_tx_ctrl_pkt_num; 470 u64 mac_rx_ctrl_pkt_num; 471 }; 472 473 #define HCLGE_STATS_TIMER_INTERVAL 300UL 474 475 struct hclge_vlan_type_cfg { 476 u16 rx_ot_fst_vlan_type; 477 u16 rx_ot_sec_vlan_type; 478 u16 rx_in_fst_vlan_type; 479 u16 rx_in_sec_vlan_type; 480 u16 tx_ot_vlan_type; 481 u16 tx_in_vlan_type; 482 }; 483 484 enum HCLGE_FD_MODE { 485 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 486 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 487 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 488 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 489 }; 490 491 enum HCLGE_FD_KEY_TYPE { 492 HCLGE_FD_KEY_BASE_ON_PTYPE, 493 HCLGE_FD_KEY_BASE_ON_TUPLE, 494 }; 495 496 enum HCLGE_FD_STAGE { 497 HCLGE_FD_STAGE_1, 498 HCLGE_FD_STAGE_2, 499 MAX_STAGE_NUM, 500 }; 501 502 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 503 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 504 * tuples of non-tunnel packet 505 */ 506 enum HCLGE_FD_TUPLE { 507 OUTER_DST_MAC, 508 OUTER_SRC_MAC, 509 OUTER_VLAN_TAG_FST, 510 OUTER_VLAN_TAG_SEC, 511 OUTER_ETH_TYPE, 512 OUTER_L2_RSV, 513 OUTER_IP_TOS, 514 OUTER_IP_PROTO, 515 OUTER_SRC_IP, 516 OUTER_DST_IP, 517 OUTER_L3_RSV, 518 OUTER_SRC_PORT, 519 OUTER_DST_PORT, 520 OUTER_L4_RSV, 521 OUTER_TUN_VNI, 522 OUTER_TUN_FLOW_ID, 523 INNER_DST_MAC, 524 INNER_SRC_MAC, 525 INNER_VLAN_TAG_FST, 526 INNER_VLAN_TAG_SEC, 527 INNER_ETH_TYPE, 528 INNER_L2_RSV, 529 INNER_IP_TOS, 530 INNER_IP_PROTO, 531 INNER_SRC_IP, 532 INNER_DST_IP, 533 INNER_L3_RSV, 534 INNER_SRC_PORT, 535 INNER_DST_PORT, 536 INNER_L4_RSV, 537 MAX_TUPLE, 538 }; 539 540 enum HCLGE_FD_META_DATA { 541 PACKET_TYPE_ID, 542 IP_FRAGEMENT, 543 ROCE_TYPE, 544 NEXT_KEY, 545 VLAN_NUMBER, 546 SRC_VPORT, 547 DST_VPORT, 548 TUNNEL_PACKET, 549 MAX_META_DATA, 550 }; 551 552 struct key_info { 553 u8 key_type; 554 u8 key_length; /* use bit as unit */ 555 }; 556 557 #define MAX_KEY_LENGTH 400 558 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 559 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 560 #define MAX_META_DATA_LENGTH 32 561 562 /* assigned by firmware, the real filter number for each pf may be less */ 563 #define MAX_FD_FILTER_NUM 4096 564 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 565 566 enum HCLGE_FD_ACTIVE_RULE_TYPE { 567 HCLGE_FD_RULE_NONE, 568 HCLGE_FD_ARFS_ACTIVE, 569 HCLGE_FD_EP_ACTIVE, 570 HCLGE_FD_TC_FLOWER_ACTIVE, 571 }; 572 573 enum HCLGE_FD_PACKET_TYPE { 574 NIC_PACKET, 575 ROCE_PACKET, 576 }; 577 578 enum HCLGE_FD_ACTION { 579 HCLGE_FD_ACTION_SELECT_QUEUE, 580 HCLGE_FD_ACTION_DROP_PACKET, 581 HCLGE_FD_ACTION_SELECT_TC, 582 }; 583 584 struct hclge_fd_key_cfg { 585 u8 key_sel; 586 u8 inner_sipv6_word_en; 587 u8 inner_dipv6_word_en; 588 u8 outer_sipv6_word_en; 589 u8 outer_dipv6_word_en; 590 u32 tuple_active; 591 u32 meta_data_active; 592 }; 593 594 struct hclge_fd_cfg { 595 u8 fd_mode; 596 u16 max_key_length; /* use bit as unit */ 597 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 598 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 599 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 600 }; 601 602 #define IPV4_INDEX 3 603 #define IPV6_SIZE 4 604 struct hclge_fd_rule_tuples { 605 u8 src_mac[ETH_ALEN]; 606 u8 dst_mac[ETH_ALEN]; 607 /* Be compatible for ip address of both ipv4 and ipv6. 608 * For ipv4 address, we store it in src/dst_ip[3]. 609 */ 610 u32 src_ip[IPV6_SIZE]; 611 u32 dst_ip[IPV6_SIZE]; 612 u16 src_port; 613 u16 dst_port; 614 u16 vlan_tag1; 615 u16 ether_proto; 616 u8 ip_tos; 617 u8 ip_proto; 618 }; 619 620 struct hclge_fd_rule { 621 struct hlist_node rule_node; 622 struct hclge_fd_rule_tuples tuples; 623 struct hclge_fd_rule_tuples tuples_mask; 624 u32 unused_tuple; 625 u32 flow_type; 626 union { 627 struct { 628 unsigned long cookie; 629 u8 tc; 630 } cls_flower; 631 struct { 632 u16 flow_id; /* only used for arfs */ 633 } arfs; 634 }; 635 u16 queue_id; 636 u16 vf_id; 637 u16 location; 638 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 639 u8 action; 640 }; 641 642 struct hclge_fd_ad_data { 643 u16 ad_id; 644 u8 drop_packet; 645 u8 forward_to_direct_queue; 646 u16 queue_id; 647 u8 use_counter; 648 u8 counter_id; 649 u8 use_next_stage; 650 u8 write_rule_id_to_bd; 651 u8 next_input_key; 652 u16 rule_id; 653 u16 tc_size; 654 u8 override_tc; 655 }; 656 657 enum HCLGE_MAC_NODE_STATE { 658 HCLGE_MAC_TO_ADD, 659 HCLGE_MAC_TO_DEL, 660 HCLGE_MAC_ACTIVE 661 }; 662 663 struct hclge_mac_node { 664 struct list_head node; 665 enum HCLGE_MAC_NODE_STATE state; 666 u8 mac_addr[ETH_ALEN]; 667 }; 668 669 enum HCLGE_MAC_ADDR_TYPE { 670 HCLGE_MAC_ADDR_UC, 671 HCLGE_MAC_ADDR_MC 672 }; 673 674 struct hclge_vport_vlan_cfg { 675 struct list_head node; 676 int hd_tbl_status; 677 u16 vlan_id; 678 }; 679 680 struct hclge_rst_stats { 681 u32 reset_done_cnt; /* the number of reset has completed */ 682 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 683 u32 pf_rst_cnt; /* the number of PF reset */ 684 u32 flr_rst_cnt; /* the number of FLR */ 685 u32 global_rst_cnt; /* the number of GLOBAL */ 686 u32 imp_rst_cnt; /* the number of IMP reset */ 687 u32 reset_cnt; /* the number of reset */ 688 u32 reset_fail_cnt; /* the number of reset fail */ 689 }; 690 691 /* time and register status when mac tunnel interruption occur */ 692 struct hclge_mac_tnl_stats { 693 u64 time; 694 u32 status; 695 }; 696 697 #define HCLGE_RESET_INTERVAL (10 * HZ) 698 #define HCLGE_WAIT_RESET_DONE 100 699 700 #pragma pack(1) 701 struct hclge_vf_vlan_cfg { 702 u8 mbx_cmd; 703 u8 subcode; 704 u8 is_kill; 705 u16 vlan; 706 u16 proto; 707 }; 708 709 #pragma pack() 710 711 /* For each bit of TCAM entry, it uses a pair of 'x' and 712 * 'y' to indicate which value to match, like below: 713 * ---------------------------------- 714 * | bit x | bit y | search value | 715 * ---------------------------------- 716 * | 0 | 0 | always hit | 717 * ---------------------------------- 718 * | 1 | 0 | match '0' | 719 * ---------------------------------- 720 * | 0 | 1 | match '1' | 721 * ---------------------------------- 722 * | 1 | 1 | invalid | 723 * ---------------------------------- 724 * Then for input key(k) and mask(v), we can calculate the value by 725 * the formulae: 726 * x = (~k) & v 727 * y = (k ^ ~v) & k 728 */ 729 #define calc_x(x, k, v) ((x) = (~(k) & (v))) 730 #define calc_y(y, k, v) \ 731 do { \ 732 const typeof(k) _k_ = (k); \ 733 const typeof(v) _v_ = (v); \ 734 (y) = (_k_ ^ ~_v_) & (_k_); \ 735 } while (0) 736 737 #define HCLGE_MAC_TNL_LOG_SIZE 8 738 #define HCLGE_VPORT_NUM 256 739 struct hclge_dev { 740 struct pci_dev *pdev; 741 struct hnae3_ae_dev *ae_dev; 742 struct hclge_hw hw; 743 struct hclge_misc_vector misc_vector; 744 struct hclge_mac_stats mac_stats; 745 unsigned long state; 746 unsigned long flr_state; 747 unsigned long last_reset_time; 748 749 enum hnae3_reset_type reset_type; 750 enum hnae3_reset_type reset_level; 751 unsigned long default_reset_request; 752 unsigned long reset_request; /* reset has been requested */ 753 unsigned long reset_pending; /* client rst is pending to be served */ 754 struct hclge_rst_stats rst_stats; 755 struct semaphore reset_sem; /* protect reset process */ 756 u32 fw_version; 757 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ 758 u16 num_tqps; /* Num task queue pairs of this PF */ 759 u16 num_req_vfs; /* Num VFs requested for this PF */ 760 761 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 762 u16 alloc_rss_size; /* Allocated RSS task queue */ 763 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 764 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 765 766 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 767 u16 num_alloc_vport; /* Num vports this driver supports */ 768 u32 numa_node_mask; 769 u16 rx_buf_len; 770 u16 num_tx_desc; /* desc num of per tx queue */ 771 u16 num_rx_desc; /* desc num of per rx queue */ 772 u8 hw_tc_map; 773 enum hclge_fc_mode fc_mode_last_time; 774 u8 support_sfp_query; 775 776 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 777 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 778 u8 tx_sch_mode; 779 u8 tc_max; 780 u8 pfc_max; 781 782 u8 default_up; 783 u8 dcbx_cap; 784 struct hclge_tm_info tm_info; 785 786 u16 num_msi; 787 u16 num_msi_left; 788 u16 num_msi_used; 789 u32 base_msi_vector; 790 u16 *vector_status; 791 int *vector_irq; 792 u16 num_nic_msi; /* Num of nic vectors for this PF */ 793 u16 num_roce_msi; /* Num of roce vectors for this PF */ 794 int roce_base_vector; 795 796 unsigned long service_timer_period; 797 unsigned long service_timer_previous; 798 struct timer_list reset_timer; 799 struct delayed_work service_task; 800 801 bool cur_promisc; 802 int num_alloc_vfs; /* Actual number of VFs allocated */ 803 804 struct hclge_tqp *htqp; 805 struct hclge_vport *vport; 806 807 struct dentry *hclge_dbgfs; 808 809 struct hnae3_client *nic_client; 810 struct hnae3_client *roce_client; 811 812 #define HCLGE_FLAG_MAIN BIT(0) 813 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 814 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 815 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 816 u32 flag; 817 818 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 819 u32 tx_buf_size; /* Tx buffer size for each TC */ 820 u32 dv_buf_size; /* Dv buffer size for each TC */ 821 822 u32 mps; /* Max packet size */ 823 /* vport_lock protect resource shared by vports */ 824 struct mutex vport_lock; 825 826 struct hclge_vlan_type_cfg vlan_type_cfg; 827 828 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 829 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 830 831 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 832 833 struct hclge_fd_cfg fd_cfg; 834 struct hlist_head fd_rule_list; 835 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 836 u16 hclge_fd_rule_num; 837 unsigned long serv_processed_cnt; 838 unsigned long last_serv_processed; 839 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 840 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 841 u8 fd_en; 842 843 u16 wanted_umv_size; 844 /* max available unicast mac vlan space */ 845 u16 max_umv_size; 846 /* private unicast mac vlan space, it's same for PF and its VFs */ 847 u16 priv_umv_size; 848 /* unicast mac vlan space shared by PF and its VFs */ 849 u16 share_umv_size; 850 851 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 852 HCLGE_MAC_TNL_LOG_SIZE); 853 854 /* affinity mask and notify for misc interrupt */ 855 cpumask_t affinity_mask; 856 struct irq_affinity_notify affinity_notify; 857 }; 858 859 /* VPort level vlan tag configuration for TX direction */ 860 struct hclge_tx_vtag_cfg { 861 bool accept_tag1; /* Whether accept tag1 packet from host */ 862 bool accept_untag1; /* Whether accept untag1 packet from host */ 863 bool accept_tag2; 864 bool accept_untag2; 865 bool insert_tag1_en; /* Whether insert inner vlan tag */ 866 bool insert_tag2_en; /* Whether insert outer vlan tag */ 867 u16 default_tag1; /* The default inner vlan tag to insert */ 868 u16 default_tag2; /* The default outer vlan tag to insert */ 869 bool tag_shift_mode_en; 870 }; 871 872 /* VPort level vlan tag configuration for RX direction */ 873 struct hclge_rx_vtag_cfg { 874 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 875 bool strip_tag1_en; /* Whether strip inner vlan tag */ 876 bool strip_tag2_en; /* Whether strip outer vlan tag */ 877 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 878 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 879 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 880 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 881 }; 882 883 struct hclge_rss_tuple_cfg { 884 u8 ipv4_tcp_en; 885 u8 ipv4_udp_en; 886 u8 ipv4_sctp_en; 887 u8 ipv4_fragment_en; 888 u8 ipv6_tcp_en; 889 u8 ipv6_udp_en; 890 u8 ipv6_sctp_en; 891 u8 ipv6_fragment_en; 892 }; 893 894 enum HCLGE_VPORT_STATE { 895 HCLGE_VPORT_STATE_ALIVE, 896 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 897 HCLGE_VPORT_STATE_MAX 898 }; 899 900 struct hclge_vlan_info { 901 u16 vlan_proto; /* so far support 802.1Q only */ 902 u16 qos; 903 u16 vlan_tag; 904 }; 905 906 struct hclge_port_base_vlan_config { 907 u16 state; 908 struct hclge_vlan_info vlan_info; 909 }; 910 911 struct hclge_vf_info { 912 int link_state; 913 u8 mac[ETH_ALEN]; 914 u32 spoofchk; 915 u32 max_tx_rate; 916 u32 trusted; 917 u16 promisc_enable; 918 }; 919 920 struct hclge_vport { 921 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 922 923 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 924 /* User configured lookup table entries */ 925 u16 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE]; 926 int rss_algo; /* User configured hash algorithm */ 927 /* User configured rss tuple sets */ 928 struct hclge_rss_tuple_cfg rss_tuple_sets; 929 930 u16 alloc_rss_size; 931 932 u16 qs_offset; 933 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 934 u8 dwrr; 935 936 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 937 struct hclge_port_base_vlan_config port_base_vlan_cfg; 938 struct hclge_tx_vtag_cfg txvlan_cfg; 939 struct hclge_rx_vtag_cfg rxvlan_cfg; 940 941 u16 used_umv_num; 942 943 u16 vport_id; 944 struct hclge_dev *back; /* Back reference to associated dev */ 945 struct hnae3_handle nic; 946 struct hnae3_handle roce; 947 948 unsigned long state; 949 unsigned long last_active_jiffies; 950 u32 mps; /* Max packet size */ 951 struct hclge_vf_info vf_info; 952 953 u8 overflow_promisc_flags; 954 u8 last_promisc_flags; 955 956 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 957 struct list_head uc_mac_list; /* Store VF unicast table */ 958 struct list_head mc_mac_list; /* Store VF multicast table */ 959 struct list_head vlan_list; /* Store VF vlan table */ 960 }; 961 962 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 963 bool en_mc_pmc, bool en_bc_pmc); 964 int hclge_add_uc_addr_common(struct hclge_vport *vport, 965 const unsigned char *addr); 966 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 967 const unsigned char *addr); 968 int hclge_add_mc_addr_common(struct hclge_vport *vport, 969 const unsigned char *addr); 970 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 971 const unsigned char *addr); 972 973 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 974 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 975 int vector_id, bool en, 976 struct hnae3_ring_chain_node *ring_chain); 977 978 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 979 { 980 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 981 982 return tqp->index; 983 } 984 985 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 986 { 987 return !!hdev->reset_pending; 988 } 989 990 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 991 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 992 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 993 u16 vlan_id, bool is_kill); 994 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 995 996 int hclge_buffer_alloc(struct hclge_dev *hdev); 997 int hclge_rss_init_hw(struct hclge_dev *hdev); 998 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 999 1000 void hclge_mbx_handler(struct hclge_dev *hdev); 1001 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id); 1002 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id); 1003 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1004 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1005 int hclge_vport_start(struct hclge_vport *vport); 1006 void hclge_vport_stop(struct hclge_vport *vport); 1007 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1008 int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf); 1009 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1010 int hclge_notify_client(struct hclge_dev *hdev, 1011 enum hnae3_reset_notify_type type); 1012 int hclge_update_mac_list(struct hclge_vport *vport, 1013 enum HCLGE_MAC_NODE_STATE state, 1014 enum HCLGE_MAC_ADDR_TYPE mac_type, 1015 const unsigned char *addr); 1016 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1017 const u8 *old_addr, const u8 *new_addr); 1018 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1019 enum HCLGE_MAC_ADDR_TYPE mac_type); 1020 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1021 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1022 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1023 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1024 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1025 struct hclge_vlan_info *vlan_info); 1026 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1027 u16 state, u16 vlan_tag, u16 qos, 1028 u16 vlan_proto); 1029 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1030 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, 1031 struct hclge_desc *desc); 1032 void hclge_report_hw_error(struct hclge_dev *hdev, 1033 enum hnae3_hw_error_type type); 1034 void hclge_inform_vf_promisc_info(struct hclge_vport *vport); 1035 void hclge_dbg_dump_rst_info(struct hclge_dev *hdev); 1036 #endif 1037