1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 #include <net/devlink.h> 12 13 #include "hclge_cmd.h" 14 #include "hclge_ptp.h" 15 #include "hnae3.h" 16 #include "hclge_comm_rss.h" 17 #include "hclge_comm_tqp_stats.h" 18 19 #define HCLGE_MOD_VERSION "1.0" 20 #define HCLGE_DRIVER_NAME "hclge" 21 22 #define HCLGE_MAX_PF_NUM 8 23 24 #define HCLGE_VF_VPORT_START_NUM 1 25 26 #define HCLGE_RD_FIRST_STATS_NUM 2 27 #define HCLGE_RD_OTHER_STATS_NUM 4 28 29 #define HCLGE_INVALID_VPORT 0xffff 30 31 #define HCLGE_PF_CFG_BLOCK_SIZE 32 32 #define HCLGE_PF_CFG_DESC_NUM \ 33 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 34 35 #define HCLGE_VECTOR_REG_BASE 0x20000 36 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 37 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 38 39 #define HCLGE_VECTOR_REG_OFFSET 0x4 40 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 41 #define HCLGE_VECTOR_VF_OFFSET 0x100000 42 43 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 44 45 /* bar registers for common func */ 46 #define HCLGE_GRO_EN_REG 0x28000 47 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 48 49 /* bar registers for rcb */ 50 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 51 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 52 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 53 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 54 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 55 #define HCLGE_RING_RX_TAIL_REG 0x80018 56 #define HCLGE_RING_RX_HEAD_REG 0x8001C 57 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 58 #define HCLGE_RING_RX_OFFSET_REG 0x80024 59 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 60 #define HCLGE_RING_RX_STASH_REG 0x80030 61 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 62 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 63 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 64 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 65 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 66 #define HCLGE_RING_TX_TC_REG 0x80050 67 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 68 #define HCLGE_RING_TX_TAIL_REG 0x80058 69 #define HCLGE_RING_TX_HEAD_REG 0x8005C 70 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 71 #define HCLGE_RING_TX_OFFSET_REG 0x80064 72 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 73 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 74 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 75 #define HCLGE_RING_EN_REG 0x80090 76 77 /* bar registers for tqp interrupt */ 78 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 79 #define HCLGE_TQP_INTR_GL0_REG 0x20100 80 #define HCLGE_TQP_INTR_GL1_REG 0x20200 81 #define HCLGE_TQP_INTR_GL2_REG 0x20300 82 #define HCLGE_TQP_INTR_RL_REG 0x20900 83 84 #define HCLGE_RSS_IND_TBL_SIZE 512 85 86 #define HCLGE_RSS_TC_SIZE_0 1 87 #define HCLGE_RSS_TC_SIZE_1 2 88 #define HCLGE_RSS_TC_SIZE_2 4 89 #define HCLGE_RSS_TC_SIZE_3 8 90 #define HCLGE_RSS_TC_SIZE_4 16 91 #define HCLGE_RSS_TC_SIZE_5 32 92 #define HCLGE_RSS_TC_SIZE_6 64 93 #define HCLGE_RSS_TC_SIZE_7 128 94 95 #define HCLGE_UMV_TBL_SIZE 3072 96 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 97 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 98 99 #define HCLGE_TQP_RESET_TRY_TIMES 200 100 101 #define HCLGE_PHY_PAGE_MDIX 0 102 #define HCLGE_PHY_PAGE_COPPER 0 103 104 /* Page Selection Reg. */ 105 #define HCLGE_PHY_PAGE_REG 22 106 107 /* Copper Specific Control Register */ 108 #define HCLGE_PHY_CSC_REG 16 109 110 /* Copper Specific Status Register */ 111 #define HCLGE_PHY_CSS_REG 17 112 113 #define HCLGE_PHY_MDIX_CTRL_S 5 114 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 115 116 #define HCLGE_PHY_MDIX_STATUS_B 6 117 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 118 119 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 120 121 /* Factor used to calculate offset and bitmap of VF num */ 122 #define HCLGE_VF_NUM_PER_CMD 64 123 124 #define HCLGE_MAX_QSET_NUM 1024 125 126 #define HCLGE_DBG_RESET_INFO_LEN 1024 127 128 enum HLCGE_PORT_TYPE { 129 HOST_PORT, 130 NETWORK_PORT 131 }; 132 133 #define PF_VPORT_ID 0 134 135 #define HCLGE_PF_ID_S 0 136 #define HCLGE_PF_ID_M GENMASK(2, 0) 137 #define HCLGE_VF_ID_S 3 138 #define HCLGE_VF_ID_M GENMASK(10, 3) 139 #define HCLGE_PORT_TYPE_B 11 140 #define HCLGE_NETWORK_PORT_ID_S 0 141 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 142 143 /* Reset related Registers */ 144 #define HCLGE_PF_OTHER_INT_REG 0x20600 145 #define HCLGE_MISC_RESET_STS_REG 0x20700 146 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 147 #define HCLGE_GLOBAL_RESET_REG 0x20A00 148 #define HCLGE_GLOBAL_RESET_BIT 0 149 #define HCLGE_CORE_RESET_BIT 1 150 #define HCLGE_IMP_RESET_BIT 2 151 #define HCLGE_RESET_INT_M GENMASK(7, 5) 152 #define HCLGE_FUN_RST_ING 0x20C00 153 #define HCLGE_FUN_RST_ING_B 0 154 155 /* Vector0 register bits define */ 156 #define HCLGE_VECTOR0_REG_PTP_INT_B 0 157 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 158 #define HCLGE_VECTOR0_CORERESET_INT_B 6 159 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 160 161 /* Vector0 interrupt CMDQ event source register(RW) */ 162 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 163 /* CMDQ register bits for RX event(=MBX event) */ 164 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 165 166 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 167 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 168 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 169 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U 170 #define HCLGE_TRIGGER_IMP_RESET_B 7U 171 172 #define HCLGE_TQP_MEM_SIZE 0x10000 173 #define HCLGE_MEM_BAR 4 174 /* in the bar4, the first half is for roce, and the second half is for nic */ 175 #define HCLGE_NIC_MEM_OFFSET(hdev) \ 176 (pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1) 177 #define HCLGE_TQP_MEM_OFFSET(hdev, i) \ 178 (HCLGE_NIC_MEM_OFFSET(hdev) + HCLGE_TQP_MEM_SIZE * (i)) 179 180 #define HCLGE_MAC_DEFAULT_FRAME \ 181 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 182 #define HCLGE_MAC_MIN_FRAME 64 183 #define HCLGE_MAC_MAX_FRAME 9728 184 185 #define HCLGE_SUPPORT_1G_BIT BIT(0) 186 #define HCLGE_SUPPORT_10G_BIT BIT(1) 187 #define HCLGE_SUPPORT_25G_BIT BIT(2) 188 #define HCLGE_SUPPORT_50G_R2_BIT BIT(3) 189 #define HCLGE_SUPPORT_100G_R4_BIT BIT(4) 190 /* to be compatible with exsit board */ 191 #define HCLGE_SUPPORT_40G_BIT BIT(5) 192 #define HCLGE_SUPPORT_100M_BIT BIT(6) 193 #define HCLGE_SUPPORT_10M_BIT BIT(7) 194 #define HCLGE_SUPPORT_200G_R4_EXT_BIT BIT(8) 195 #define HCLGE_SUPPORT_50G_R1_BIT BIT(9) 196 #define HCLGE_SUPPORT_100G_R2_BIT BIT(10) 197 #define HCLGE_SUPPORT_200G_R4_BIT BIT(11) 198 199 #define HCLGE_SUPPORT_GE \ 200 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 201 #define HCLGE_SUPPORT_50G_BITS \ 202 (HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT) 203 #define HCLGE_SUPPORT_100G_BITS \ 204 (HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT) 205 #define HCLGE_SUPPORT_200G_BITS \ 206 (HCLGE_SUPPORT_200G_R4_EXT_BIT | HCLGE_SUPPORT_200G_R4_BIT) 207 208 enum HCLGE_DEV_STATE { 209 HCLGE_STATE_REINITING, 210 HCLGE_STATE_DOWN, 211 HCLGE_STATE_DISABLED, 212 HCLGE_STATE_REMOVING, 213 HCLGE_STATE_NIC_REGISTERED, 214 HCLGE_STATE_ROCE_REGISTERED, 215 HCLGE_STATE_SERVICE_INITED, 216 HCLGE_STATE_RST_SERVICE_SCHED, 217 HCLGE_STATE_RST_HANDLING, 218 HCLGE_STATE_MBX_SERVICE_SCHED, 219 HCLGE_STATE_MBX_HANDLING, 220 HCLGE_STATE_ERR_SERVICE_SCHED, 221 HCLGE_STATE_STATISTICS_UPDATING, 222 HCLGE_STATE_LINK_UPDATING, 223 HCLGE_STATE_RST_FAIL, 224 HCLGE_STATE_FD_TBL_CHANGED, 225 HCLGE_STATE_FD_CLEAR_ALL, 226 HCLGE_STATE_FD_USER_DEF_CHANGED, 227 HCLGE_STATE_PTP_EN, 228 HCLGE_STATE_PTP_TX_HANDLING, 229 HCLGE_STATE_FEC_STATS_UPDATING, 230 HCLGE_STATE_MAX 231 }; 232 233 enum hclge_evt_cause { 234 HCLGE_VECTOR0_EVENT_RST, 235 HCLGE_VECTOR0_EVENT_MBX, 236 HCLGE_VECTOR0_EVENT_ERR, 237 HCLGE_VECTOR0_EVENT_PTP, 238 HCLGE_VECTOR0_EVENT_OTHER, 239 }; 240 241 enum HCLGE_MAC_SPEED { 242 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 243 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 244 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 245 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 246 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 247 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 248 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 249 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 250 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 251 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 252 }; 253 254 enum HCLGE_MAC_DUPLEX { 255 HCLGE_MAC_HALF, 256 HCLGE_MAC_FULL 257 }; 258 259 /* hilink version */ 260 enum hclge_hilink_version { 261 HCLGE_HILINK_H32 = 0, 262 HCLGE_HILINK_H60 = 1, 263 }; 264 265 #define QUERY_SFP_SPEED 0 266 #define QUERY_ACTIVE_SPEED 1 267 268 struct hclge_wol_info { 269 u32 wol_support_mode; /* store the wake on lan info */ 270 u32 wol_current_mode; 271 u8 wol_sopass[SOPASS_MAX]; 272 u8 wol_sopass_size; 273 }; 274 275 struct hclge_mac { 276 u8 mac_id; 277 u8 phy_addr; 278 u8 flag; 279 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 280 u8 mac_addr[ETH_ALEN]; 281 u8 autoneg; 282 u8 req_autoneg; 283 u8 duplex; 284 u8 req_duplex; 285 u8 support_autoneg; 286 u8 speed_type; /* 0: sfp speed, 1: active speed */ 287 u8 lane_num; 288 u32 speed; 289 u32 req_speed; 290 u32 max_speed; 291 u32 speed_ability; /* speed ability supported by current media */ 292 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 293 u32 fec_mode; /* active fec mode */ 294 u32 user_fec_mode; 295 u32 fec_ability; 296 int link; /* store the link status of mac & phy (if phy exists) */ 297 struct hclge_wol_info wol; 298 struct phy_device *phydev; 299 struct mii_bus *mdio_bus; 300 phy_interface_t phy_if; 301 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 302 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 303 }; 304 305 struct hclge_hw { 306 struct hclge_comm_hw hw; 307 struct hclge_mac mac; 308 int num_vec; 309 }; 310 311 enum hclge_fc_mode { 312 HCLGE_FC_NONE, 313 HCLGE_FC_RX_PAUSE, 314 HCLGE_FC_TX_PAUSE, 315 HCLGE_FC_FULL, 316 HCLGE_FC_PFC, 317 HCLGE_FC_DEFAULT 318 }; 319 320 #define HCLGE_FILTER_TYPE_VF 0 321 #define HCLGE_FILTER_TYPE_PORT 1 322 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 323 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 324 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 325 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 326 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 327 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 328 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 329 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 330 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 331 332 enum hclge_vlan_fltr_cap { 333 HCLGE_VLAN_FLTR_DEF, 334 HCLGE_VLAN_FLTR_CAN_MDF, 335 }; 336 enum hclge_link_fail_code { 337 HCLGE_LF_NORMAL, 338 HCLGE_LF_REF_CLOCK_LOST, 339 HCLGE_LF_XSFP_TX_DISABLE, 340 HCLGE_LF_XSFP_ABSENT, 341 }; 342 343 #define HCLGE_LINK_STATUS_DOWN 0 344 #define HCLGE_LINK_STATUS_UP 1 345 346 #define HCLGE_PG_NUM 4 347 #define HCLGE_SCH_MODE_SP 0 348 #define HCLGE_SCH_MODE_DWRR 1 349 struct hclge_pg_info { 350 u8 pg_id; 351 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 352 u8 tc_bit_map; 353 u32 bw_limit; 354 u8 tc_dwrr[HNAE3_MAX_TC]; 355 }; 356 357 struct hclge_tc_info { 358 u8 tc_id; 359 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 360 u8 pgid; 361 u32 bw_limit; 362 }; 363 364 struct hclge_cfg { 365 u8 tc_num; 366 u8 vlan_fliter_cap; 367 u16 tqp_desc_num; 368 u16 rx_buf_len; 369 u16 vf_rss_size_max; 370 u16 pf_rss_size_max; 371 u8 phy_addr; 372 u8 media_type; 373 u8 mac_addr[ETH_ALEN]; 374 u8 default_speed; 375 u32 numa_node_map; 376 u32 tx_spare_buf_size; 377 u16 speed_ability; 378 u16 umv_space; 379 }; 380 381 struct hclge_tm_info { 382 u8 num_tc; 383 u8 num_pg; /* It must be 1 if vNET-Base schd */ 384 u8 pg_dwrr[HCLGE_PG_NUM]; 385 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 386 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 387 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 388 enum hclge_fc_mode fc_mode; 389 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 390 u8 pfc_en; /* PFC enabled or not for user priority */ 391 }; 392 393 /* max number of mac statistics on each version */ 394 #define HCLGE_MAC_STATS_MAX_NUM_V1 87 395 #define HCLGE_MAC_STATS_MAX_NUM_V2 105 396 397 struct hclge_comm_stats_str { 398 char desc[ETH_GSTRING_LEN]; 399 u32 stats_num; 400 unsigned long offset; 401 }; 402 403 /* mac stats ,opcode id: 0x0032 */ 404 struct hclge_mac_stats { 405 u64 mac_tx_mac_pause_num; 406 u64 mac_rx_mac_pause_num; 407 u64 rsv0; 408 u64 mac_tx_pfc_pri0_pkt_num; 409 u64 mac_tx_pfc_pri1_pkt_num; 410 u64 mac_tx_pfc_pri2_pkt_num; 411 u64 mac_tx_pfc_pri3_pkt_num; 412 u64 mac_tx_pfc_pri4_pkt_num; 413 u64 mac_tx_pfc_pri5_pkt_num; 414 u64 mac_tx_pfc_pri6_pkt_num; 415 u64 mac_tx_pfc_pri7_pkt_num; 416 u64 mac_rx_pfc_pri0_pkt_num; 417 u64 mac_rx_pfc_pri1_pkt_num; 418 u64 mac_rx_pfc_pri2_pkt_num; 419 u64 mac_rx_pfc_pri3_pkt_num; 420 u64 mac_rx_pfc_pri4_pkt_num; 421 u64 mac_rx_pfc_pri5_pkt_num; 422 u64 mac_rx_pfc_pri6_pkt_num; 423 u64 mac_rx_pfc_pri7_pkt_num; 424 u64 mac_tx_total_pkt_num; 425 u64 mac_tx_total_oct_num; 426 u64 mac_tx_good_pkt_num; 427 u64 mac_tx_bad_pkt_num; 428 u64 mac_tx_good_oct_num; 429 u64 mac_tx_bad_oct_num; 430 u64 mac_tx_uni_pkt_num; 431 u64 mac_tx_multi_pkt_num; 432 u64 mac_tx_broad_pkt_num; 433 u64 mac_tx_undersize_pkt_num; 434 u64 mac_tx_oversize_pkt_num; 435 u64 mac_tx_64_oct_pkt_num; 436 u64 mac_tx_65_127_oct_pkt_num; 437 u64 mac_tx_128_255_oct_pkt_num; 438 u64 mac_tx_256_511_oct_pkt_num; 439 u64 mac_tx_512_1023_oct_pkt_num; 440 u64 mac_tx_1024_1518_oct_pkt_num; 441 u64 mac_tx_1519_2047_oct_pkt_num; 442 u64 mac_tx_2048_4095_oct_pkt_num; 443 u64 mac_tx_4096_8191_oct_pkt_num; 444 u64 rsv1; 445 u64 mac_tx_8192_9216_oct_pkt_num; 446 u64 mac_tx_9217_12287_oct_pkt_num; 447 u64 mac_tx_12288_16383_oct_pkt_num; 448 u64 mac_tx_1519_max_good_oct_pkt_num; 449 u64 mac_tx_1519_max_bad_oct_pkt_num; 450 451 u64 mac_rx_total_pkt_num; 452 u64 mac_rx_total_oct_num; 453 u64 mac_rx_good_pkt_num; 454 u64 mac_rx_bad_pkt_num; 455 u64 mac_rx_good_oct_num; 456 u64 mac_rx_bad_oct_num; 457 u64 mac_rx_uni_pkt_num; 458 u64 mac_rx_multi_pkt_num; 459 u64 mac_rx_broad_pkt_num; 460 u64 mac_rx_undersize_pkt_num; 461 u64 mac_rx_oversize_pkt_num; 462 u64 mac_rx_64_oct_pkt_num; 463 u64 mac_rx_65_127_oct_pkt_num; 464 u64 mac_rx_128_255_oct_pkt_num; 465 u64 mac_rx_256_511_oct_pkt_num; 466 u64 mac_rx_512_1023_oct_pkt_num; 467 u64 mac_rx_1024_1518_oct_pkt_num; 468 u64 mac_rx_1519_2047_oct_pkt_num; 469 u64 mac_rx_2048_4095_oct_pkt_num; 470 u64 mac_rx_4096_8191_oct_pkt_num; 471 u64 rsv2; 472 u64 mac_rx_8192_9216_oct_pkt_num; 473 u64 mac_rx_9217_12287_oct_pkt_num; 474 u64 mac_rx_12288_16383_oct_pkt_num; 475 u64 mac_rx_1519_max_good_oct_pkt_num; 476 u64 mac_rx_1519_max_bad_oct_pkt_num; 477 478 u64 mac_tx_fragment_pkt_num; 479 u64 mac_tx_undermin_pkt_num; 480 u64 mac_tx_jabber_pkt_num; 481 u64 mac_tx_err_all_pkt_num; 482 u64 mac_tx_from_app_good_pkt_num; 483 u64 mac_tx_from_app_bad_pkt_num; 484 u64 mac_rx_fragment_pkt_num; 485 u64 mac_rx_undermin_pkt_num; 486 u64 mac_rx_jabber_pkt_num; 487 u64 mac_rx_fcs_err_pkt_num; 488 u64 mac_rx_send_app_good_pkt_num; 489 u64 mac_rx_send_app_bad_pkt_num; 490 u64 mac_tx_pfc_pause_pkt_num; 491 u64 mac_rx_pfc_pause_pkt_num; 492 u64 mac_tx_ctrl_pkt_num; 493 u64 mac_rx_ctrl_pkt_num; 494 495 /* duration of pfc */ 496 u64 mac_tx_pfc_pri0_xoff_time; 497 u64 mac_tx_pfc_pri1_xoff_time; 498 u64 mac_tx_pfc_pri2_xoff_time; 499 u64 mac_tx_pfc_pri3_xoff_time; 500 u64 mac_tx_pfc_pri4_xoff_time; 501 u64 mac_tx_pfc_pri5_xoff_time; 502 u64 mac_tx_pfc_pri6_xoff_time; 503 u64 mac_tx_pfc_pri7_xoff_time; 504 u64 mac_rx_pfc_pri0_xoff_time; 505 u64 mac_rx_pfc_pri1_xoff_time; 506 u64 mac_rx_pfc_pri2_xoff_time; 507 u64 mac_rx_pfc_pri3_xoff_time; 508 u64 mac_rx_pfc_pri4_xoff_time; 509 u64 mac_rx_pfc_pri5_xoff_time; 510 u64 mac_rx_pfc_pri6_xoff_time; 511 u64 mac_rx_pfc_pri7_xoff_time; 512 513 /* duration of pause */ 514 u64 mac_tx_pause_xoff_time; 515 u64 mac_rx_pause_xoff_time; 516 }; 517 518 #define HCLGE_STATS_TIMER_INTERVAL 300UL 519 520 /* fec stats ,opcode id: 0x0316 */ 521 #define HCLGE_FEC_STATS_MAX_LANES 8 522 struct hclge_fec_stats { 523 /* fec rs mode total stats */ 524 u64 rs_corr_blocks; 525 u64 rs_uncorr_blocks; 526 u64 rs_error_blocks; 527 /* fec base-r mode per lanes stats */ 528 u64 base_r_lane_num; 529 u64 base_r_corr_blocks; 530 u64 base_r_uncorr_blocks; 531 union { 532 struct { 533 u64 base_r_corr_per_lanes[HCLGE_FEC_STATS_MAX_LANES]; 534 u64 base_r_uncorr_per_lanes[HCLGE_FEC_STATS_MAX_LANES]; 535 }; 536 u64 per_lanes[HCLGE_FEC_STATS_MAX_LANES * 2]; 537 }; 538 }; 539 540 struct hclge_vlan_type_cfg { 541 u16 rx_ot_fst_vlan_type; 542 u16 rx_ot_sec_vlan_type; 543 u16 rx_in_fst_vlan_type; 544 u16 rx_in_sec_vlan_type; 545 u16 tx_ot_vlan_type; 546 u16 tx_in_vlan_type; 547 }; 548 549 enum HCLGE_FD_MODE { 550 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 551 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 552 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 553 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 554 }; 555 556 enum HCLGE_FD_KEY_TYPE { 557 HCLGE_FD_KEY_BASE_ON_PTYPE, 558 HCLGE_FD_KEY_BASE_ON_TUPLE, 559 }; 560 561 enum HCLGE_FD_STAGE { 562 HCLGE_FD_STAGE_1, 563 HCLGE_FD_STAGE_2, 564 MAX_STAGE_NUM, 565 }; 566 567 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 568 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 569 * tuples of non-tunnel packet 570 */ 571 enum HCLGE_FD_TUPLE { 572 OUTER_DST_MAC, 573 OUTER_SRC_MAC, 574 OUTER_VLAN_TAG_FST, 575 OUTER_VLAN_TAG_SEC, 576 OUTER_ETH_TYPE, 577 OUTER_L2_RSV, 578 OUTER_IP_TOS, 579 OUTER_IP_PROTO, 580 OUTER_SRC_IP, 581 OUTER_DST_IP, 582 OUTER_L3_RSV, 583 OUTER_SRC_PORT, 584 OUTER_DST_PORT, 585 OUTER_L4_RSV, 586 OUTER_TUN_VNI, 587 OUTER_TUN_FLOW_ID, 588 INNER_DST_MAC, 589 INNER_SRC_MAC, 590 INNER_VLAN_TAG_FST, 591 INNER_VLAN_TAG_SEC, 592 INNER_ETH_TYPE, 593 INNER_L2_RSV, 594 INNER_IP_TOS, 595 INNER_IP_PROTO, 596 INNER_SRC_IP, 597 INNER_DST_IP, 598 INNER_L3_RSV, 599 INNER_SRC_PORT, 600 INNER_DST_PORT, 601 INNER_L4_RSV, 602 MAX_TUPLE, 603 }; 604 605 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 606 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 607 608 enum HCLGE_FD_META_DATA { 609 PACKET_TYPE_ID, 610 IP_FRAGEMENT, 611 ROCE_TYPE, 612 NEXT_KEY, 613 VLAN_NUMBER, 614 SRC_VPORT, 615 DST_VPORT, 616 TUNNEL_PACKET, 617 MAX_META_DATA, 618 }; 619 620 enum HCLGE_FD_KEY_OPT { 621 KEY_OPT_U8, 622 KEY_OPT_LE16, 623 KEY_OPT_LE32, 624 KEY_OPT_MAC, 625 KEY_OPT_IP, 626 KEY_OPT_VNI, 627 }; 628 629 struct key_info { 630 u8 key_type; 631 u8 key_length; /* use bit as unit */ 632 enum HCLGE_FD_KEY_OPT key_opt; 633 int offset; 634 int moffset; 635 }; 636 637 #define MAX_KEY_LENGTH 400 638 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 639 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 640 #define MAX_META_DATA_LENGTH 32 641 642 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 643 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 644 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 645 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 646 647 /* assigned by firmware, the real filter number for each pf may be less */ 648 #define MAX_FD_FILTER_NUM 4096 649 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 650 651 #define hclge_read_dev(a, reg) \ 652 hclge_comm_read_reg((a)->hw.io_base, reg) 653 #define hclge_write_dev(a, reg, value) \ 654 hclge_comm_write_reg((a)->hw.io_base, reg, value) 655 656 enum HCLGE_FD_ACTIVE_RULE_TYPE { 657 HCLGE_FD_RULE_NONE, 658 HCLGE_FD_ARFS_ACTIVE, 659 HCLGE_FD_EP_ACTIVE, 660 HCLGE_FD_TC_FLOWER_ACTIVE, 661 }; 662 663 enum HCLGE_FD_PACKET_TYPE { 664 NIC_PACKET, 665 ROCE_PACKET, 666 }; 667 668 enum HCLGE_FD_ACTION { 669 HCLGE_FD_ACTION_SELECT_QUEUE, 670 HCLGE_FD_ACTION_DROP_PACKET, 671 HCLGE_FD_ACTION_SELECT_TC, 672 }; 673 674 enum HCLGE_FD_NODE_STATE { 675 HCLGE_FD_TO_ADD, 676 HCLGE_FD_TO_DEL, 677 HCLGE_FD_ACTIVE, 678 HCLGE_FD_DELETED, 679 }; 680 681 enum HCLGE_FD_USER_DEF_LAYER { 682 HCLGE_FD_USER_DEF_NONE, 683 HCLGE_FD_USER_DEF_L2, 684 HCLGE_FD_USER_DEF_L3, 685 HCLGE_FD_USER_DEF_L4, 686 }; 687 688 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 689 struct hclge_fd_user_def_cfg { 690 u16 ref_cnt; 691 u16 offset; 692 }; 693 694 struct hclge_fd_user_def_info { 695 enum HCLGE_FD_USER_DEF_LAYER layer; 696 u16 data; 697 u16 data_mask; 698 u16 offset; 699 }; 700 701 struct hclge_fd_key_cfg { 702 u8 key_sel; 703 u8 inner_sipv6_word_en; 704 u8 inner_dipv6_word_en; 705 u8 outer_sipv6_word_en; 706 u8 outer_dipv6_word_en; 707 u32 tuple_active; 708 u32 meta_data_active; 709 }; 710 711 struct hclge_fd_cfg { 712 u8 fd_mode; 713 u16 max_key_length; /* use bit as unit */ 714 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 715 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 716 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 717 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 718 }; 719 720 #define IPV4_INDEX 3 721 #define IPV6_SIZE 4 722 struct hclge_fd_rule_tuples { 723 u8 src_mac[ETH_ALEN]; 724 u8 dst_mac[ETH_ALEN]; 725 /* Be compatible for ip address of both ipv4 and ipv6. 726 * For ipv4 address, we store it in src/dst_ip[3]. 727 */ 728 u32 src_ip[IPV6_SIZE]; 729 u32 dst_ip[IPV6_SIZE]; 730 u16 src_port; 731 u16 dst_port; 732 u16 vlan_tag1; 733 u16 ether_proto; 734 u16 l2_user_def; 735 u16 l3_user_def; 736 u32 l4_user_def; 737 u8 ip_tos; 738 u8 ip_proto; 739 }; 740 741 struct hclge_fd_rule { 742 struct hlist_node rule_node; 743 struct hclge_fd_rule_tuples tuples; 744 struct hclge_fd_rule_tuples tuples_mask; 745 u32 unused_tuple; 746 u32 flow_type; 747 union { 748 struct { 749 unsigned long cookie; 750 u8 tc; 751 } cls_flower; 752 struct { 753 u16 flow_id; /* only used for arfs */ 754 } arfs; 755 struct { 756 struct hclge_fd_user_def_info user_def; 757 } ep; 758 }; 759 u16 queue_id; 760 u16 vf_id; 761 u16 location; 762 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 763 enum HCLGE_FD_NODE_STATE state; 764 u8 action; 765 }; 766 767 struct hclge_fd_ad_data { 768 u16 ad_id; 769 u8 drop_packet; 770 u8 forward_to_direct_queue; 771 u16 queue_id; 772 u8 use_counter; 773 u8 counter_id; 774 u8 use_next_stage; 775 u8 write_rule_id_to_bd; 776 u8 next_input_key; 777 u16 rule_id; 778 u16 tc_size; 779 u8 override_tc; 780 }; 781 782 enum HCLGE_MAC_NODE_STATE { 783 HCLGE_MAC_TO_ADD, 784 HCLGE_MAC_TO_DEL, 785 HCLGE_MAC_ACTIVE 786 }; 787 788 struct hclge_mac_node { 789 struct list_head node; 790 enum HCLGE_MAC_NODE_STATE state; 791 u8 mac_addr[ETH_ALEN]; 792 }; 793 794 enum HCLGE_MAC_ADDR_TYPE { 795 HCLGE_MAC_ADDR_UC, 796 HCLGE_MAC_ADDR_MC 797 }; 798 799 struct hclge_vport_vlan_cfg { 800 struct list_head node; 801 int hd_tbl_status; 802 u16 vlan_id; 803 }; 804 805 struct hclge_rst_stats { 806 u32 reset_done_cnt; /* the number of reset has completed */ 807 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 808 u32 pf_rst_cnt; /* the number of PF reset */ 809 u32 flr_rst_cnt; /* the number of FLR */ 810 u32 global_rst_cnt; /* the number of GLOBAL */ 811 u32 imp_rst_cnt; /* the number of IMP reset */ 812 u32 reset_cnt; /* the number of reset */ 813 u32 reset_fail_cnt; /* the number of reset fail */ 814 }; 815 816 /* time and register status when mac tunnel interruption occur */ 817 struct hclge_mac_tnl_stats { 818 u64 time; 819 u32 status; 820 }; 821 822 #define HCLGE_RESET_INTERVAL (10 * HZ) 823 #define HCLGE_WAIT_RESET_DONE 100 824 825 #pragma pack(1) 826 struct hclge_vf_vlan_cfg { 827 u8 mbx_cmd; 828 u8 subcode; 829 union { 830 struct { 831 u8 is_kill; 832 __le16 vlan; 833 __le16 proto; 834 }; 835 u8 enable; 836 }; 837 }; 838 839 #pragma pack() 840 841 /* For each bit of TCAM entry, it uses a pair of 'x' and 842 * 'y' to indicate which value to match, like below: 843 * ---------------------------------- 844 * | bit x | bit y | search value | 845 * ---------------------------------- 846 * | 0 | 0 | always hit | 847 * ---------------------------------- 848 * | 1 | 0 | match '0' | 849 * ---------------------------------- 850 * | 0 | 1 | match '1' | 851 * ---------------------------------- 852 * | 1 | 1 | invalid | 853 * ---------------------------------- 854 * Then for input key(k) and mask(v), we can calculate the value by 855 * the formulae: 856 * x = (~k) & v 857 * y = k & v 858 */ 859 #define calc_x(x, k, v) ((x) = ~(k) & (v)) 860 #define calc_y(y, k, v) ((y) = (k) & (v)) 861 862 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 863 #define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset))) 864 865 #define HCLGE_MAC_TNL_LOG_SIZE 8 866 #define HCLGE_VPORT_NUM 256 867 struct hclge_dev { 868 struct pci_dev *pdev; 869 struct hnae3_ae_dev *ae_dev; 870 struct hclge_hw hw; 871 struct hclge_misc_vector misc_vector; 872 struct hclge_mac_stats mac_stats; 873 struct hclge_fec_stats fec_stats; 874 unsigned long state; 875 unsigned long flr_state; 876 unsigned long last_reset_time; 877 878 enum hnae3_reset_type reset_type; 879 enum hnae3_reset_type reset_level; 880 unsigned long default_reset_request; 881 unsigned long reset_request; /* reset has been requested */ 882 unsigned long reset_pending; /* client rst is pending to be served */ 883 struct hclge_rst_stats rst_stats; 884 struct semaphore reset_sem; /* protect reset process */ 885 u32 fw_version; 886 u16 num_tqps; /* Num task queue pairs of this PF */ 887 u16 num_req_vfs; /* Num VFs requested for this PF */ 888 889 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 890 u16 alloc_rss_size; /* Allocated RSS task queue */ 891 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 892 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 893 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */ 894 895 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 896 u16 num_alloc_vport; /* Num vports this driver supports */ 897 nodemask_t numa_node_mask; 898 u16 rx_buf_len; 899 u16 num_tx_desc; /* desc num of per tx queue */ 900 u16 num_rx_desc; /* desc num of per rx queue */ 901 u8 hw_tc_map; 902 enum hclge_fc_mode fc_mode_last_time; 903 u8 support_sfp_query; 904 905 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 906 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 907 u8 tx_sch_mode; 908 u8 tc_max; 909 u8 pfc_max; 910 911 u8 default_up; 912 u8 dcbx_cap; 913 struct hclge_tm_info tm_info; 914 915 u16 num_msi; 916 u16 num_msi_left; 917 u16 num_msi_used; 918 u16 *vector_status; 919 int *vector_irq; 920 u16 num_nic_msi; /* Num of nic vectors for this PF */ 921 u16 num_roce_msi; /* Num of roce vectors for this PF */ 922 923 unsigned long service_timer_period; 924 unsigned long service_timer_previous; 925 struct timer_list reset_timer; 926 struct delayed_work service_task; 927 928 bool cur_promisc; 929 int num_alloc_vfs; /* Actual number of VFs allocated */ 930 931 struct hclge_comm_tqp *htqp; 932 struct hclge_vport *vport; 933 934 struct dentry *hclge_dbgfs; 935 936 struct hnae3_client *nic_client; 937 struct hnae3_client *roce_client; 938 939 #define HCLGE_FLAG_MAIN BIT(0) 940 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 941 u32 flag; 942 943 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 944 u32 tx_buf_size; /* Tx buffer size for each TC */ 945 u32 dv_buf_size; /* Dv buffer size for each TC */ 946 947 u32 mps; /* Max packet size */ 948 /* vport_lock protect resource shared by vports */ 949 struct mutex vport_lock; 950 951 struct hclge_vlan_type_cfg vlan_type_cfg; 952 953 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 954 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 955 956 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 957 958 struct hclge_fd_cfg fd_cfg; 959 struct hlist_head fd_rule_list; 960 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 961 u16 hclge_fd_rule_num; 962 unsigned long serv_processed_cnt; 963 unsigned long last_serv_processed; 964 unsigned long last_rst_scheduled; 965 unsigned long last_mbx_scheduled; 966 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 967 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 968 u8 fd_en; 969 bool gro_en; 970 971 u16 wanted_umv_size; 972 /* max available unicast mac vlan space */ 973 u16 max_umv_size; 974 /* private unicast mac vlan space, it's same for PF and its VFs */ 975 u16 priv_umv_size; 976 /* unicast mac vlan space shared by PF and its VFs */ 977 u16 share_umv_size; 978 /* multicast mac address number used by PF and its VFs */ 979 u16 used_mc_mac_num; 980 981 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 982 HCLGE_MAC_TNL_LOG_SIZE); 983 984 struct hclge_ptp *ptp; 985 struct devlink *devlink; 986 struct hclge_comm_rss_cfg rss_cfg; 987 }; 988 989 /* VPort level vlan tag configuration for TX direction */ 990 struct hclge_tx_vtag_cfg { 991 bool accept_tag1; /* Whether accept tag1 packet from host */ 992 bool accept_untag1; /* Whether accept untag1 packet from host */ 993 bool accept_tag2; 994 bool accept_untag2; 995 bool insert_tag1_en; /* Whether insert inner vlan tag */ 996 bool insert_tag2_en; /* Whether insert outer vlan tag */ 997 u16 default_tag1; /* The default inner vlan tag to insert */ 998 u16 default_tag2; /* The default outer vlan tag to insert */ 999 bool tag_shift_mode_en; 1000 }; 1001 1002 /* VPort level vlan tag configuration for RX direction */ 1003 struct hclge_rx_vtag_cfg { 1004 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 1005 bool strip_tag1_en; /* Whether strip inner vlan tag */ 1006 bool strip_tag2_en; /* Whether strip outer vlan tag */ 1007 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 1008 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 1009 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 1010 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 1011 }; 1012 1013 enum HCLGE_VPORT_STATE { 1014 HCLGE_VPORT_STATE_ALIVE, 1015 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 1016 HCLGE_VPORT_STATE_PROMISC_CHANGE, 1017 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 1018 HCLGE_VPORT_STATE_INITED, 1019 HCLGE_VPORT_STATE_MAX 1020 }; 1021 1022 enum HCLGE_VPORT_NEED_NOTIFY { 1023 HCLGE_VPORT_NEED_NOTIFY_RESET, 1024 HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 1025 }; 1026 1027 struct hclge_vlan_info { 1028 u16 vlan_proto; /* so far support 802.1Q only */ 1029 u16 qos; 1030 u16 vlan_tag; 1031 }; 1032 1033 struct hclge_port_base_vlan_config { 1034 u16 state; 1035 bool tbl_sta; 1036 struct hclge_vlan_info vlan_info; 1037 struct hclge_vlan_info old_vlan_info; 1038 }; 1039 1040 struct hclge_vf_info { 1041 int link_state; 1042 u8 mac[ETH_ALEN]; 1043 u32 spoofchk; 1044 u32 max_tx_rate; 1045 u32 trusted; 1046 u8 request_uc_en; 1047 u8 request_mc_en; 1048 u8 request_bc_en; 1049 }; 1050 1051 struct hclge_vport { 1052 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 1053 1054 u16 qs_offset; 1055 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 1056 u8 dwrr; 1057 1058 bool req_vlan_fltr_en; 1059 bool cur_vlan_fltr_en; 1060 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 1061 struct hclge_port_base_vlan_config port_base_vlan_cfg; 1062 struct hclge_tx_vtag_cfg txvlan_cfg; 1063 struct hclge_rx_vtag_cfg rxvlan_cfg; 1064 1065 u16 used_umv_num; 1066 1067 u16 vport_id; 1068 struct hclge_dev *back; /* Back reference to associated dev */ 1069 struct hnae3_handle nic; 1070 struct hnae3_handle roce; 1071 1072 unsigned long state; 1073 unsigned long need_notify; 1074 unsigned long last_active_jiffies; 1075 u32 mps; /* Max packet size */ 1076 struct hclge_vf_info vf_info; 1077 1078 u8 overflow_promisc_flags; 1079 u8 last_promisc_flags; 1080 1081 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1082 struct list_head uc_mac_list; /* Store VF unicast table */ 1083 struct list_head mc_mac_list; /* Store VF multicast table */ 1084 1085 struct list_head vlan_list; /* Store VF vlan table */ 1086 }; 1087 1088 struct hclge_speed_bit_map { 1089 u32 speed; 1090 u32 speed_bit; 1091 }; 1092 1093 struct hclge_mac_speed_map { 1094 u32 speed_drv; /* speed defined in driver */ 1095 u32 speed_fw; /* speed defined in firmware */ 1096 }; 1097 1098 struct hclge_link_mode_bmap { 1099 u16 support_bit; 1100 enum ethtool_link_mode_bit_indices link_mode; 1101 }; 1102 1103 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1104 bool en_mc_pmc, bool en_bc_pmc); 1105 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1106 const unsigned char *addr); 1107 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1108 const unsigned char *addr); 1109 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1110 const unsigned char *addr); 1111 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1112 const unsigned char *addr); 1113 1114 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1115 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1116 int vector_id, bool en, 1117 struct hnae3_ring_chain_node *ring_chain); 1118 1119 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1120 { 1121 struct hclge_comm_tqp *tqp = 1122 container_of(queue, struct hclge_comm_tqp, q); 1123 1124 return tqp->index; 1125 } 1126 1127 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1128 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num); 1129 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1130 u16 vlan_id, bool is_kill); 1131 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1132 1133 int hclge_buffer_alloc(struct hclge_dev *hdev); 1134 int hclge_rss_init_hw(struct hclge_dev *hdev); 1135 1136 void hclge_mbx_handler(struct hclge_dev *hdev); 1137 int hclge_reset_tqp(struct hnae3_handle *handle); 1138 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1139 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1140 int hclge_vport_start(struct hclge_vport *vport); 1141 void hclge_vport_stop(struct hclge_vport *vport); 1142 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1143 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1144 char *buf, int len); 1145 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1146 int hclge_notify_client(struct hclge_dev *hdev, 1147 enum hnae3_reset_notify_type type); 1148 int hclge_update_mac_list(struct hclge_vport *vport, 1149 enum HCLGE_MAC_NODE_STATE state, 1150 enum HCLGE_MAC_ADDR_TYPE mac_type, 1151 const unsigned char *addr); 1152 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1153 const u8 *old_addr, const u8 *new_addr); 1154 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1155 enum HCLGE_MAC_ADDR_TYPE mac_type); 1156 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1157 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1158 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1159 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev); 1160 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1161 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1162 struct hclge_vlan_info *vlan_info); 1163 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1164 u16 state, 1165 struct hclge_vlan_info *vlan_info); 1166 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1167 void hclge_report_hw_error(struct hclge_dev *hdev, 1168 enum hnae3_hw_error_type type); 1169 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1170 int hclge_push_vf_link_status(struct hclge_vport *vport); 1171 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); 1172 int hclge_mac_update_stats(struct hclge_dev *hdev); 1173 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf); 1174 int hclge_inform_vf_reset(struct hclge_vport *vport, u16 reset_type); 1175 int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version); 1176 #endif 1177