1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <net/rtnetlink.h> 16 #include "hclge_cmd.h" 17 #include "hclge_dcb.h" 18 #include "hclge_main.h" 19 #include "hclge_mbx.h" 20 #include "hclge_mdio.h" 21 #include "hclge_tm.h" 22 #include "hnae3.h" 23 24 #define HCLGE_NAME "hclge" 25 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 26 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 27 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f)) 28 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f)) 29 30 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, 31 enum hclge_mta_dmac_sel_type mta_mac_sel, 32 bool enable); 33 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); 34 static int hclge_init_vlan_config(struct hclge_dev *hdev); 35 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 36 37 static struct hnae3_ae_algo ae_algo; 38 39 static const struct pci_device_id ae_algo_pci_tbl[] = { 40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 47 /* required last entry */ 48 {0, } 49 }; 50 51 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 52 53 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 54 "Mac Loopback test", 55 "Serdes Loopback test", 56 "Phy Loopback test" 57 }; 58 59 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = { 60 {"igu_rx_oversize_pkt", 61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)}, 62 {"igu_rx_undersize_pkt", 63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)}, 64 {"igu_rx_out_all_pkt", 65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)}, 66 {"igu_rx_uni_pkt", 67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)}, 68 {"igu_rx_multi_pkt", 69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)}, 70 {"igu_rx_broad_pkt", 71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)}, 72 {"egu_tx_out_all_pkt", 73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)}, 74 {"egu_tx_uni_pkt", 75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)}, 76 {"egu_tx_multi_pkt", 77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)}, 78 {"egu_tx_broad_pkt", 79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)}, 80 {"ssu_ppp_mac_key_num", 81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)}, 82 {"ssu_ppp_host_key_num", 83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)}, 84 {"ppp_ssu_mac_rlt_num", 85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)}, 86 {"ppp_ssu_host_rlt_num", 87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)}, 88 {"ssu_tx_in_num", 89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)}, 90 {"ssu_tx_out_num", 91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)}, 92 {"ssu_rx_in_num", 93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)}, 94 {"ssu_rx_out_num", 95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)} 96 }; 97 98 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = { 99 {"igu_rx_err_pkt", 100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)}, 101 {"igu_rx_no_eof_pkt", 102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)}, 103 {"igu_rx_no_sof_pkt", 104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)}, 105 {"egu_tx_1588_pkt", 106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)}, 107 {"ssu_full_drop_num", 108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)}, 109 {"ssu_part_drop_num", 110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)}, 111 {"ppp_key_drop_num", 112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)}, 113 {"ppp_rlt_drop_num", 114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)}, 115 {"ssu_key_drop_num", 116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)}, 117 {"pkt_curr_buf_cnt", 118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)}, 119 {"qcn_fb_rcv_cnt", 120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)}, 121 {"qcn_fb_drop_cnt", 122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)}, 123 {"qcn_fb_invaild_cnt", 124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)}, 125 {"rx_packet_tc0_in_cnt", 126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)}, 127 {"rx_packet_tc1_in_cnt", 128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)}, 129 {"rx_packet_tc2_in_cnt", 130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)}, 131 {"rx_packet_tc3_in_cnt", 132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)}, 133 {"rx_packet_tc4_in_cnt", 134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)}, 135 {"rx_packet_tc5_in_cnt", 136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)}, 137 {"rx_packet_tc6_in_cnt", 138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)}, 139 {"rx_packet_tc7_in_cnt", 140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)}, 141 {"rx_packet_tc0_out_cnt", 142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)}, 143 {"rx_packet_tc1_out_cnt", 144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)}, 145 {"rx_packet_tc2_out_cnt", 146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)}, 147 {"rx_packet_tc3_out_cnt", 148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)}, 149 {"rx_packet_tc4_out_cnt", 150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)}, 151 {"rx_packet_tc5_out_cnt", 152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)}, 153 {"rx_packet_tc6_out_cnt", 154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)}, 155 {"rx_packet_tc7_out_cnt", 156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)}, 157 {"tx_packet_tc0_in_cnt", 158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)}, 159 {"tx_packet_tc1_in_cnt", 160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)}, 161 {"tx_packet_tc2_in_cnt", 162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)}, 163 {"tx_packet_tc3_in_cnt", 164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)}, 165 {"tx_packet_tc4_in_cnt", 166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)}, 167 {"tx_packet_tc5_in_cnt", 168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)}, 169 {"tx_packet_tc6_in_cnt", 170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)}, 171 {"tx_packet_tc7_in_cnt", 172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)}, 173 {"tx_packet_tc0_out_cnt", 174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)}, 175 {"tx_packet_tc1_out_cnt", 176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)}, 177 {"tx_packet_tc2_out_cnt", 178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)}, 179 {"tx_packet_tc3_out_cnt", 180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)}, 181 {"tx_packet_tc4_out_cnt", 182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)}, 183 {"tx_packet_tc5_out_cnt", 184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)}, 185 {"tx_packet_tc6_out_cnt", 186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)}, 187 {"tx_packet_tc7_out_cnt", 188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)}, 189 {"pkt_curr_buf_tc0_cnt", 190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)}, 191 {"pkt_curr_buf_tc1_cnt", 192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)}, 193 {"pkt_curr_buf_tc2_cnt", 194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)}, 195 {"pkt_curr_buf_tc3_cnt", 196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)}, 197 {"pkt_curr_buf_tc4_cnt", 198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)}, 199 {"pkt_curr_buf_tc5_cnt", 200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)}, 201 {"pkt_curr_buf_tc6_cnt", 202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)}, 203 {"pkt_curr_buf_tc7_cnt", 204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)}, 205 {"mb_uncopy_num", 206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)}, 207 {"lo_pri_unicast_rlt_drop_num", 208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)}, 209 {"hi_pri_multicast_rlt_drop_num", 210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)}, 211 {"lo_pri_multicast_rlt_drop_num", 212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)}, 213 {"rx_oq_drop_pkt_cnt", 214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)}, 215 {"tx_oq_drop_pkt_cnt", 216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)}, 217 {"nic_l2_err_drop_pkt_cnt", 218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)}, 219 {"roc_l2_err_drop_pkt_cnt", 220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)} 221 }; 222 223 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 224 {"mac_tx_mac_pause_num", 225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 226 {"mac_rx_mac_pause_num", 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 228 {"mac_tx_pfc_pri0_pkt_num", 229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 230 {"mac_tx_pfc_pri1_pkt_num", 231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 232 {"mac_tx_pfc_pri2_pkt_num", 233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 234 {"mac_tx_pfc_pri3_pkt_num", 235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 236 {"mac_tx_pfc_pri4_pkt_num", 237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 238 {"mac_tx_pfc_pri5_pkt_num", 239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 240 {"mac_tx_pfc_pri6_pkt_num", 241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 242 {"mac_tx_pfc_pri7_pkt_num", 243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 244 {"mac_rx_pfc_pri0_pkt_num", 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 246 {"mac_rx_pfc_pri1_pkt_num", 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 248 {"mac_rx_pfc_pri2_pkt_num", 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 250 {"mac_rx_pfc_pri3_pkt_num", 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 252 {"mac_rx_pfc_pri4_pkt_num", 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 254 {"mac_rx_pfc_pri5_pkt_num", 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 256 {"mac_rx_pfc_pri6_pkt_num", 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 258 {"mac_rx_pfc_pri7_pkt_num", 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 260 {"mac_tx_total_pkt_num", 261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 262 {"mac_tx_total_oct_num", 263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 264 {"mac_tx_good_pkt_num", 265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 266 {"mac_tx_bad_pkt_num", 267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 268 {"mac_tx_good_oct_num", 269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 270 {"mac_tx_bad_oct_num", 271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 272 {"mac_tx_uni_pkt_num", 273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 274 {"mac_tx_multi_pkt_num", 275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 276 {"mac_tx_broad_pkt_num", 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 278 {"mac_tx_undersize_pkt_num", 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 280 {"mac_tx_oversize_pkt_num", 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 282 {"mac_tx_64_oct_pkt_num", 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 284 {"mac_tx_65_127_oct_pkt_num", 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 286 {"mac_tx_128_255_oct_pkt_num", 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 288 {"mac_tx_256_511_oct_pkt_num", 289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 290 {"mac_tx_512_1023_oct_pkt_num", 291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 292 {"mac_tx_1024_1518_oct_pkt_num", 293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 294 {"mac_tx_1519_2047_oct_pkt_num", 295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 296 {"mac_tx_2048_4095_oct_pkt_num", 297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 298 {"mac_tx_4096_8191_oct_pkt_num", 299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 300 {"mac_tx_8192_9216_oct_pkt_num", 301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 302 {"mac_tx_9217_12287_oct_pkt_num", 303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 304 {"mac_tx_12288_16383_oct_pkt_num", 305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 306 {"mac_tx_1519_max_good_pkt_num", 307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 308 {"mac_tx_1519_max_bad_pkt_num", 309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 310 {"mac_rx_total_pkt_num", 311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 312 {"mac_rx_total_oct_num", 313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 314 {"mac_rx_good_pkt_num", 315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 316 {"mac_rx_bad_pkt_num", 317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 318 {"mac_rx_good_oct_num", 319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 320 {"mac_rx_bad_oct_num", 321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 322 {"mac_rx_uni_pkt_num", 323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 324 {"mac_rx_multi_pkt_num", 325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 326 {"mac_rx_broad_pkt_num", 327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 328 {"mac_rx_undersize_pkt_num", 329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 330 {"mac_rx_oversize_pkt_num", 331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 332 {"mac_rx_64_oct_pkt_num", 333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 334 {"mac_rx_65_127_oct_pkt_num", 335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 336 {"mac_rx_128_255_oct_pkt_num", 337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 338 {"mac_rx_256_511_oct_pkt_num", 339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 340 {"mac_rx_512_1023_oct_pkt_num", 341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 342 {"mac_rx_1024_1518_oct_pkt_num", 343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 344 {"mac_rx_1519_2047_oct_pkt_num", 345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 346 {"mac_rx_2048_4095_oct_pkt_num", 347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 348 {"mac_rx_4096_8191_oct_pkt_num", 349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 350 {"mac_rx_8192_9216_oct_pkt_num", 351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 352 {"mac_rx_9217_12287_oct_pkt_num", 353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 354 {"mac_rx_12288_16383_oct_pkt_num", 355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 356 {"mac_rx_1519_max_good_pkt_num", 357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 358 {"mac_rx_1519_max_bad_pkt_num", 359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 360 361 {"mac_tx_fragment_pkt_num", 362 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 363 {"mac_tx_undermin_pkt_num", 364 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 365 {"mac_tx_jabber_pkt_num", 366 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 367 {"mac_tx_err_all_pkt_num", 368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 369 {"mac_tx_from_app_good_pkt_num", 370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 371 {"mac_tx_from_app_bad_pkt_num", 372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 373 {"mac_rx_fragment_pkt_num", 374 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 375 {"mac_rx_undermin_pkt_num", 376 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 377 {"mac_rx_jabber_pkt_num", 378 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 379 {"mac_rx_fcs_err_pkt_num", 380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 381 {"mac_rx_send_app_good_pkt_num", 382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 383 {"mac_rx_send_app_bad_pkt_num", 384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 385 }; 386 387 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 388 { 389 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 390 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP), 391 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)), 392 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)), 393 .i_port_bitmap = 0x1, 394 }, 395 }; 396 397 static int hclge_64_bit_update_stats(struct hclge_dev *hdev) 398 { 399 #define HCLGE_64_BIT_CMD_NUM 5 400 #define HCLGE_64_BIT_RTN_DATANUM 4 401 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats); 402 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM]; 403 __le64 *desc_data; 404 int i, k, n; 405 int ret; 406 407 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true); 408 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM); 409 if (ret) { 410 dev_err(&hdev->pdev->dev, 411 "Get 64 bit pkt stats fail, status = %d.\n", ret); 412 return ret; 413 } 414 415 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) { 416 if (unlikely(i == 0)) { 417 desc_data = (__le64 *)(&desc[i].data[0]); 418 n = HCLGE_64_BIT_RTN_DATANUM - 1; 419 } else { 420 desc_data = (__le64 *)(&desc[i]); 421 n = HCLGE_64_BIT_RTN_DATANUM; 422 } 423 for (k = 0; k < n; k++) { 424 *data++ += le64_to_cpu(*desc_data); 425 desc_data++; 426 } 427 } 428 429 return 0; 430 } 431 432 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats) 433 { 434 stats->pkt_curr_buf_cnt = 0; 435 stats->pkt_curr_buf_tc0_cnt = 0; 436 stats->pkt_curr_buf_tc1_cnt = 0; 437 stats->pkt_curr_buf_tc2_cnt = 0; 438 stats->pkt_curr_buf_tc3_cnt = 0; 439 stats->pkt_curr_buf_tc4_cnt = 0; 440 stats->pkt_curr_buf_tc5_cnt = 0; 441 stats->pkt_curr_buf_tc6_cnt = 0; 442 stats->pkt_curr_buf_tc7_cnt = 0; 443 } 444 445 static int hclge_32_bit_update_stats(struct hclge_dev *hdev) 446 { 447 #define HCLGE_32_BIT_CMD_NUM 8 448 #define HCLGE_32_BIT_RTN_DATANUM 8 449 450 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM]; 451 struct hclge_32_bit_stats *all_32_bit_stats; 452 __le32 *desc_data; 453 int i, k, n; 454 u64 *data; 455 int ret; 456 457 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats; 458 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt); 459 460 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true); 461 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM); 462 if (ret) { 463 dev_err(&hdev->pdev->dev, 464 "Get 32 bit pkt stats fail, status = %d.\n", ret); 465 466 return ret; 467 } 468 469 hclge_reset_partial_32bit_counter(all_32_bit_stats); 470 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) { 471 if (unlikely(i == 0)) { 472 __le16 *desc_data_16bit; 473 474 all_32_bit_stats->igu_rx_err_pkt += 475 le32_to_cpu(desc[i].data[0]); 476 477 desc_data_16bit = (__le16 *)&desc[i].data[1]; 478 all_32_bit_stats->igu_rx_no_eof_pkt += 479 le16_to_cpu(*desc_data_16bit); 480 481 desc_data_16bit++; 482 all_32_bit_stats->igu_rx_no_sof_pkt += 483 le16_to_cpu(*desc_data_16bit); 484 485 desc_data = &desc[i].data[2]; 486 n = HCLGE_32_BIT_RTN_DATANUM - 4; 487 } else { 488 desc_data = (__le32 *)&desc[i]; 489 n = HCLGE_32_BIT_RTN_DATANUM; 490 } 491 for (k = 0; k < n; k++) { 492 *data++ += le32_to_cpu(*desc_data); 493 desc_data++; 494 } 495 } 496 497 return 0; 498 } 499 500 static int hclge_mac_update_stats(struct hclge_dev *hdev) 501 { 502 #define HCLGE_MAC_CMD_NUM 21 503 #define HCLGE_RTN_DATA_NUM 4 504 505 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats); 506 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 507 __le64 *desc_data; 508 int i, k, n; 509 int ret; 510 511 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 512 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 513 if (ret) { 514 dev_err(&hdev->pdev->dev, 515 "Get MAC pkt stats fail, status = %d.\n", ret); 516 517 return ret; 518 } 519 520 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) { 521 if (unlikely(i == 0)) { 522 desc_data = (__le64 *)(&desc[i].data[0]); 523 n = HCLGE_RTN_DATA_NUM - 2; 524 } else { 525 desc_data = (__le64 *)(&desc[i]); 526 n = HCLGE_RTN_DATA_NUM; 527 } 528 for (k = 0; k < n; k++) { 529 *data++ += le64_to_cpu(*desc_data); 530 desc_data++; 531 } 532 } 533 534 return 0; 535 } 536 537 static int hclge_tqps_update_stats(struct hnae3_handle *handle) 538 { 539 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 540 struct hclge_vport *vport = hclge_get_vport(handle); 541 struct hclge_dev *hdev = vport->back; 542 struct hnae3_queue *queue; 543 struct hclge_desc desc[1]; 544 struct hclge_tqp *tqp; 545 int ret, i; 546 547 for (i = 0; i < kinfo->num_tqps; i++) { 548 queue = handle->kinfo.tqp[i]; 549 tqp = container_of(queue, struct hclge_tqp, q); 550 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 551 hclge_cmd_setup_basic_desc(&desc[0], 552 HCLGE_OPC_QUERY_RX_STATUS, 553 true); 554 555 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 556 ret = hclge_cmd_send(&hdev->hw, desc, 1); 557 if (ret) { 558 dev_err(&hdev->pdev->dev, 559 "Query tqp stat fail, status = %d,queue = %d\n", 560 ret, i); 561 return ret; 562 } 563 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 564 le32_to_cpu(desc[0].data[1]); 565 } 566 567 for (i = 0; i < kinfo->num_tqps; i++) { 568 queue = handle->kinfo.tqp[i]; 569 tqp = container_of(queue, struct hclge_tqp, q); 570 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 571 hclge_cmd_setup_basic_desc(&desc[0], 572 HCLGE_OPC_QUERY_TX_STATUS, 573 true); 574 575 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 576 ret = hclge_cmd_send(&hdev->hw, desc, 1); 577 if (ret) { 578 dev_err(&hdev->pdev->dev, 579 "Query tqp stat fail, status = %d,queue = %d\n", 580 ret, i); 581 return ret; 582 } 583 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 584 le32_to_cpu(desc[0].data[1]); 585 } 586 587 return 0; 588 } 589 590 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 591 { 592 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 593 struct hclge_tqp *tqp; 594 u64 *buff = data; 595 int i; 596 597 for (i = 0; i < kinfo->num_tqps; i++) { 598 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 599 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 600 } 601 602 for (i = 0; i < kinfo->num_tqps; i++) { 603 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 604 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 605 } 606 607 return buff; 608 } 609 610 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset) 611 { 612 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 613 614 return kinfo->num_tqps * (2); 615 } 616 617 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 618 { 619 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 620 u8 *buff = data; 621 int i = 0; 622 623 for (i = 0; i < kinfo->num_tqps; i++) { 624 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], 625 struct hclge_tqp, q); 626 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", 627 tqp->index); 628 buff = buff + ETH_GSTRING_LEN; 629 } 630 631 for (i = 0; i < kinfo->num_tqps; i++) { 632 struct hclge_tqp *tqp = container_of(kinfo->tqp[i], 633 struct hclge_tqp, q); 634 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", 635 tqp->index); 636 buff = buff + ETH_GSTRING_LEN; 637 } 638 639 return buff; 640 } 641 642 static u64 *hclge_comm_get_stats(void *comm_stats, 643 const struct hclge_comm_stats_str strs[], 644 int size, u64 *data) 645 { 646 u64 *buf = data; 647 u32 i; 648 649 for (i = 0; i < size; i++) 650 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset); 651 652 return buf + size; 653 } 654 655 static u8 *hclge_comm_get_strings(u32 stringset, 656 const struct hclge_comm_stats_str strs[], 657 int size, u8 *data) 658 { 659 char *buff = (char *)data; 660 u32 i; 661 662 if (stringset != ETH_SS_STATS) 663 return buff; 664 665 for (i = 0; i < size; i++) { 666 snprintf(buff, ETH_GSTRING_LEN, 667 strs[i].desc); 668 buff = buff + ETH_GSTRING_LEN; 669 } 670 671 return (u8 *)buff; 672 } 673 674 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats, 675 struct net_device_stats *net_stats) 676 { 677 net_stats->tx_dropped = 0; 678 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num; 679 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num; 680 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num; 681 682 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; 683 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; 684 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt; 685 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt; 686 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 687 688 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; 689 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num; 690 691 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 692 net_stats->rx_length_errors = 693 hw_stats->mac_stats.mac_rx_undersize_pkt_num; 694 net_stats->rx_length_errors += 695 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 696 net_stats->rx_over_errors = 697 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 698 } 699 700 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 701 { 702 struct hnae3_handle *handle; 703 int status; 704 705 handle = &hdev->vport[0].nic; 706 if (handle->client) { 707 status = hclge_tqps_update_stats(handle); 708 if (status) { 709 dev_err(&hdev->pdev->dev, 710 "Update TQPS stats fail, status = %d.\n", 711 status); 712 } 713 } 714 715 status = hclge_mac_update_stats(hdev); 716 if (status) 717 dev_err(&hdev->pdev->dev, 718 "Update MAC stats fail, status = %d.\n", status); 719 720 status = hclge_32_bit_update_stats(hdev); 721 if (status) 722 dev_err(&hdev->pdev->dev, 723 "Update 32 bit stats fail, status = %d.\n", 724 status); 725 726 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); 727 } 728 729 static void hclge_update_stats(struct hnae3_handle *handle, 730 struct net_device_stats *net_stats) 731 { 732 struct hclge_vport *vport = hclge_get_vport(handle); 733 struct hclge_dev *hdev = vport->back; 734 struct hclge_hw_stats *hw_stats = &hdev->hw_stats; 735 int status; 736 737 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 738 return; 739 740 status = hclge_mac_update_stats(hdev); 741 if (status) 742 dev_err(&hdev->pdev->dev, 743 "Update MAC stats fail, status = %d.\n", 744 status); 745 746 status = hclge_32_bit_update_stats(hdev); 747 if (status) 748 dev_err(&hdev->pdev->dev, 749 "Update 32 bit stats fail, status = %d.\n", 750 status); 751 752 status = hclge_64_bit_update_stats(hdev); 753 if (status) 754 dev_err(&hdev->pdev->dev, 755 "Update 64 bit stats fail, status = %d.\n", 756 status); 757 758 status = hclge_tqps_update_stats(handle); 759 if (status) 760 dev_err(&hdev->pdev->dev, 761 "Update TQPS stats fail, status = %d.\n", 762 status); 763 764 hclge_update_netstat(hw_stats, net_stats); 765 766 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 767 } 768 769 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 770 { 771 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7 772 773 struct hclge_vport *vport = hclge_get_vport(handle); 774 struct hclge_dev *hdev = vport->back; 775 int count = 0; 776 777 /* Loopback test support rules: 778 * mac: only GE mode support 779 * serdes: all mac mode will support include GE/XGE/LGE/CGE 780 * phy: only support when phy device exist on board 781 */ 782 if (stringset == ETH_SS_TEST) { 783 /* clear loopback bit flags at first */ 784 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 785 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 786 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 787 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 788 count += 1; 789 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK; 790 } 791 792 count++; 793 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK; 794 } else if (stringset == ETH_SS_STATS) { 795 count = ARRAY_SIZE(g_mac_stats_string) + 796 ARRAY_SIZE(g_all_32bit_stats_string) + 797 ARRAY_SIZE(g_all_64bit_stats_string) + 798 hclge_tqps_get_sset_count(handle, stringset); 799 } 800 801 return count; 802 } 803 804 static void hclge_get_strings(struct hnae3_handle *handle, 805 u32 stringset, 806 u8 *data) 807 { 808 u8 *p = (char *)data; 809 int size; 810 811 if (stringset == ETH_SS_STATS) { 812 size = ARRAY_SIZE(g_mac_stats_string); 813 p = hclge_comm_get_strings(stringset, 814 g_mac_stats_string, 815 size, 816 p); 817 size = ARRAY_SIZE(g_all_32bit_stats_string); 818 p = hclge_comm_get_strings(stringset, 819 g_all_32bit_stats_string, 820 size, 821 p); 822 size = ARRAY_SIZE(g_all_64bit_stats_string); 823 p = hclge_comm_get_strings(stringset, 824 g_all_64bit_stats_string, 825 size, 826 p); 827 p = hclge_tqps_get_strings(handle, p); 828 } else if (stringset == ETH_SS_TEST) { 829 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) { 830 memcpy(p, 831 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC], 832 ETH_GSTRING_LEN); 833 p += ETH_GSTRING_LEN; 834 } 835 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) { 836 memcpy(p, 837 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES], 838 ETH_GSTRING_LEN); 839 p += ETH_GSTRING_LEN; 840 } 841 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 842 memcpy(p, 843 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY], 844 ETH_GSTRING_LEN); 845 p += ETH_GSTRING_LEN; 846 } 847 } 848 } 849 850 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 851 { 852 struct hclge_vport *vport = hclge_get_vport(handle); 853 struct hclge_dev *hdev = vport->back; 854 u64 *p; 855 856 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats, 857 g_mac_stats_string, 858 ARRAY_SIZE(g_mac_stats_string), 859 data); 860 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats, 861 g_all_32bit_stats_string, 862 ARRAY_SIZE(g_all_32bit_stats_string), 863 p); 864 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats, 865 g_all_64bit_stats_string, 866 ARRAY_SIZE(g_all_64bit_stats_string), 867 p); 868 p = hclge_tqps_get_stats(handle, p); 869 } 870 871 static int hclge_parse_func_status(struct hclge_dev *hdev, 872 struct hclge_func_status_cmd *status) 873 { 874 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 875 return -EINVAL; 876 877 /* Set the pf to main pf */ 878 if (status->pf_state & HCLGE_PF_STATE_MAIN) 879 hdev->flag |= HCLGE_FLAG_MAIN; 880 else 881 hdev->flag &= ~HCLGE_FLAG_MAIN; 882 883 return 0; 884 } 885 886 static int hclge_query_function_status(struct hclge_dev *hdev) 887 { 888 struct hclge_func_status_cmd *req; 889 struct hclge_desc desc; 890 int timeout = 0; 891 int ret; 892 893 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 894 req = (struct hclge_func_status_cmd *)desc.data; 895 896 do { 897 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 898 if (ret) { 899 dev_err(&hdev->pdev->dev, 900 "query function status failed %d.\n", 901 ret); 902 903 return ret; 904 } 905 906 /* Check pf reset is done */ 907 if (req->pf_state) 908 break; 909 usleep_range(1000, 2000); 910 } while (timeout++ < 5); 911 912 ret = hclge_parse_func_status(hdev, req); 913 914 return ret; 915 } 916 917 static int hclge_query_pf_resource(struct hclge_dev *hdev) 918 { 919 struct hclge_pf_res_cmd *req; 920 struct hclge_desc desc; 921 int ret; 922 923 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 924 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 925 if (ret) { 926 dev_err(&hdev->pdev->dev, 927 "query pf resource failed %d.\n", ret); 928 return ret; 929 } 930 931 req = (struct hclge_pf_res_cmd *)desc.data; 932 hdev->num_tqps = __le16_to_cpu(req->tqp_num); 933 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 934 935 if (hnae3_dev_roce_supported(hdev)) { 936 hdev->roce_base_msix_offset = 937 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 938 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S); 939 hdev->num_roce_msi = 940 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), 941 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 942 943 /* PF should have NIC vectors and Roce vectors, 944 * NIC vectors are queued before Roce vectors. 945 */ 946 hdev->num_msi = hdev->num_roce_msi + 947 hdev->roce_base_msix_offset; 948 } else { 949 hdev->num_msi = 950 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), 951 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 952 } 953 954 return 0; 955 } 956 957 static int hclge_parse_speed(int speed_cmd, int *speed) 958 { 959 switch (speed_cmd) { 960 case 6: 961 *speed = HCLGE_MAC_SPEED_10M; 962 break; 963 case 7: 964 *speed = HCLGE_MAC_SPEED_100M; 965 break; 966 case 0: 967 *speed = HCLGE_MAC_SPEED_1G; 968 break; 969 case 1: 970 *speed = HCLGE_MAC_SPEED_10G; 971 break; 972 case 2: 973 *speed = HCLGE_MAC_SPEED_25G; 974 break; 975 case 3: 976 *speed = HCLGE_MAC_SPEED_40G; 977 break; 978 case 4: 979 *speed = HCLGE_MAC_SPEED_50G; 980 break; 981 case 5: 982 *speed = HCLGE_MAC_SPEED_100G; 983 break; 984 default: 985 return -EINVAL; 986 } 987 988 return 0; 989 } 990 991 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 992 u8 speed_ability) 993 { 994 unsigned long *supported = hdev->hw.mac.supported; 995 996 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 997 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 998 supported); 999 1000 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1001 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1002 supported); 1003 1004 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1005 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1006 supported); 1007 1008 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1009 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1010 supported); 1011 1012 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1013 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1014 supported); 1015 1016 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 1017 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1018 } 1019 1020 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability) 1021 { 1022 u8 media_type = hdev->hw.mac.media_type; 1023 1024 if (media_type != HNAE3_MEDIA_TYPE_FIBER) 1025 return; 1026 1027 hclge_parse_fiber_link_mode(hdev, speed_ability); 1028 } 1029 1030 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1031 { 1032 struct hclge_cfg_param_cmd *req; 1033 u64 mac_addr_tmp_high; 1034 u64 mac_addr_tmp; 1035 int i; 1036 1037 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1038 1039 /* get the configuration */ 1040 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1041 HCLGE_CFG_VMDQ_M, 1042 HCLGE_CFG_VMDQ_S); 1043 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1044 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1045 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1046 HCLGE_CFG_TQP_DESC_N_M, 1047 HCLGE_CFG_TQP_DESC_N_S); 1048 1049 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1050 HCLGE_CFG_PHY_ADDR_M, 1051 HCLGE_CFG_PHY_ADDR_S); 1052 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1053 HCLGE_CFG_MEDIA_TP_M, 1054 HCLGE_CFG_MEDIA_TP_S); 1055 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1056 HCLGE_CFG_RX_BUF_LEN_M, 1057 HCLGE_CFG_RX_BUF_LEN_S); 1058 /* get mac_address */ 1059 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1060 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1061 HCLGE_CFG_MAC_ADDR_H_M, 1062 HCLGE_CFG_MAC_ADDR_H_S); 1063 1064 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1065 1066 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1067 HCLGE_CFG_DEFAULT_SPEED_M, 1068 HCLGE_CFG_DEFAULT_SPEED_S); 1069 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1070 HCLGE_CFG_RSS_SIZE_M, 1071 HCLGE_CFG_RSS_SIZE_S); 1072 1073 for (i = 0; i < ETH_ALEN; i++) 1074 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1075 1076 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1077 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1078 1079 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1080 HCLGE_CFG_SPEED_ABILITY_M, 1081 HCLGE_CFG_SPEED_ABILITY_S); 1082 } 1083 1084 /* hclge_get_cfg: query the static parameter from flash 1085 * @hdev: pointer to struct hclge_dev 1086 * @hcfg: the config structure to be getted 1087 */ 1088 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1089 { 1090 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1091 struct hclge_cfg_param_cmd *req; 1092 int i, ret; 1093 1094 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1095 u32 offset = 0; 1096 1097 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1098 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1099 true); 1100 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1101 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1102 /* Len should be united by 4 bytes when send to hardware */ 1103 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1104 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1105 req->offset = cpu_to_le32(offset); 1106 } 1107 1108 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1109 if (ret) { 1110 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1111 return ret; 1112 } 1113 1114 hclge_parse_cfg(hcfg, desc); 1115 1116 return 0; 1117 } 1118 1119 static int hclge_get_cap(struct hclge_dev *hdev) 1120 { 1121 int ret; 1122 1123 ret = hclge_query_function_status(hdev); 1124 if (ret) { 1125 dev_err(&hdev->pdev->dev, 1126 "query function status error %d.\n", ret); 1127 return ret; 1128 } 1129 1130 /* get pf resource */ 1131 ret = hclge_query_pf_resource(hdev); 1132 if (ret) 1133 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret); 1134 1135 return ret; 1136 } 1137 1138 static int hclge_configure(struct hclge_dev *hdev) 1139 { 1140 struct hclge_cfg cfg; 1141 int ret, i; 1142 1143 ret = hclge_get_cfg(hdev, &cfg); 1144 if (ret) { 1145 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret); 1146 return ret; 1147 } 1148 1149 hdev->num_vmdq_vport = cfg.vmdq_vport_num; 1150 hdev->base_tqp_pid = 0; 1151 hdev->rss_size_max = cfg.rss_size_max; 1152 hdev->rx_buf_len = cfg.rx_buf_len; 1153 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1154 hdev->hw.mac.media_type = cfg.media_type; 1155 hdev->hw.mac.phy_addr = cfg.phy_addr; 1156 hdev->num_desc = cfg.tqp_desc_num; 1157 hdev->tm_info.num_pg = 1; 1158 hdev->tc_max = cfg.tc_num; 1159 hdev->tm_info.hw_pfc_map = 0; 1160 1161 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1162 if (ret) { 1163 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret); 1164 return ret; 1165 } 1166 1167 hclge_parse_link_mode(hdev, cfg.speed_ability); 1168 1169 if ((hdev->tc_max > HNAE3_MAX_TC) || 1170 (hdev->tc_max < 1)) { 1171 dev_warn(&hdev->pdev->dev, "TC num = %d.\n", 1172 hdev->tc_max); 1173 hdev->tc_max = 1; 1174 } 1175 1176 /* Dev does not support DCB */ 1177 if (!hnae3_dev_dcb_supported(hdev)) { 1178 hdev->tc_max = 1; 1179 hdev->pfc_max = 0; 1180 } else { 1181 hdev->pfc_max = hdev->tc_max; 1182 } 1183 1184 hdev->tm_info.num_tc = hdev->tc_max; 1185 1186 /* Currently not support uncontiuous tc */ 1187 for (i = 0; i < hdev->tm_info.num_tc; i++) 1188 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1189 1190 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1191 1192 return ret; 1193 } 1194 1195 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, 1196 int tso_mss_max) 1197 { 1198 struct hclge_cfg_tso_status_cmd *req; 1199 struct hclge_desc desc; 1200 u16 tso_mss; 1201 1202 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1203 1204 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1205 1206 tso_mss = 0; 1207 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 1208 HCLGE_TSO_MSS_MIN_S, tso_mss_min); 1209 req->tso_mss_min = cpu_to_le16(tso_mss); 1210 1211 tso_mss = 0; 1212 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 1213 HCLGE_TSO_MSS_MIN_S, tso_mss_max); 1214 req->tso_mss_max = cpu_to_le16(tso_mss); 1215 1216 return hclge_cmd_send(&hdev->hw, &desc, 1); 1217 } 1218 1219 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1220 { 1221 struct hclge_tqp *tqp; 1222 int i; 1223 1224 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1225 sizeof(struct hclge_tqp), GFP_KERNEL); 1226 if (!hdev->htqp) 1227 return -ENOMEM; 1228 1229 tqp = hdev->htqp; 1230 1231 for (i = 0; i < hdev->num_tqps; i++) { 1232 tqp->dev = &hdev->pdev->dev; 1233 tqp->index = i; 1234 1235 tqp->q.ae_algo = &ae_algo; 1236 tqp->q.buf_size = hdev->rx_buf_len; 1237 tqp->q.desc_num = hdev->num_desc; 1238 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET + 1239 i * HCLGE_TQP_REG_SIZE; 1240 1241 tqp++; 1242 } 1243 1244 return 0; 1245 } 1246 1247 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1248 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1249 { 1250 struct hclge_tqp_map_cmd *req; 1251 struct hclge_desc desc; 1252 int ret; 1253 1254 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1255 1256 req = (struct hclge_tqp_map_cmd *)desc.data; 1257 req->tqp_id = cpu_to_le16(tqp_pid); 1258 req->tqp_vf = func_id; 1259 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B | 1260 1 << HCLGE_TQP_MAP_EN_B; 1261 req->tqp_vid = cpu_to_le16(tqp_vid); 1262 1263 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1264 if (ret) 1265 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1266 1267 return ret; 1268 } 1269 1270 static int hclge_assign_tqp(struct hclge_vport *vport) 1271 { 1272 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1273 struct hclge_dev *hdev = vport->back; 1274 int i, alloced; 1275 1276 for (i = 0, alloced = 0; i < hdev->num_tqps && 1277 alloced < kinfo->num_tqps; i++) { 1278 if (!hdev->htqp[i].alloced) { 1279 hdev->htqp[i].q.handle = &vport->nic; 1280 hdev->htqp[i].q.tqp_index = alloced; 1281 hdev->htqp[i].q.desc_num = kinfo->num_desc; 1282 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1283 hdev->htqp[i].alloced = true; 1284 alloced++; 1285 } 1286 } 1287 vport->alloc_tqps = kinfo->num_tqps; 1288 1289 return 0; 1290 } 1291 1292 static int hclge_knic_setup(struct hclge_vport *vport, 1293 u16 num_tqps, u16 num_desc) 1294 { 1295 struct hnae3_handle *nic = &vport->nic; 1296 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1297 struct hclge_dev *hdev = vport->back; 1298 int i, ret; 1299 1300 kinfo->num_desc = num_desc; 1301 kinfo->rx_buf_len = hdev->rx_buf_len; 1302 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); 1303 kinfo->rss_size 1304 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc); 1305 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc; 1306 1307 for (i = 0; i < HNAE3_MAX_TC; i++) { 1308 if (hdev->hw_tc_map & BIT(i)) { 1309 kinfo->tc_info[i].enable = true; 1310 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; 1311 kinfo->tc_info[i].tqp_count = kinfo->rss_size; 1312 kinfo->tc_info[i].tc = i; 1313 } else { 1314 /* Set to default queue if TC is disable */ 1315 kinfo->tc_info[i].enable = false; 1316 kinfo->tc_info[i].tqp_offset = 0; 1317 kinfo->tc_info[i].tqp_count = 1; 1318 kinfo->tc_info[i].tc = 0; 1319 } 1320 } 1321 1322 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 1323 sizeof(struct hnae3_queue *), GFP_KERNEL); 1324 if (!kinfo->tqp) 1325 return -ENOMEM; 1326 1327 ret = hclge_assign_tqp(vport); 1328 if (ret) 1329 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1330 1331 return ret; 1332 } 1333 1334 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1335 struct hclge_vport *vport) 1336 { 1337 struct hnae3_handle *nic = &vport->nic; 1338 struct hnae3_knic_private_info *kinfo; 1339 u16 i; 1340 1341 kinfo = &nic->kinfo; 1342 for (i = 0; i < kinfo->num_tqps; i++) { 1343 struct hclge_tqp *q = 1344 container_of(kinfo->tqp[i], struct hclge_tqp, q); 1345 bool is_pf; 1346 int ret; 1347 1348 is_pf = !(vport->vport_id); 1349 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1350 i, is_pf); 1351 if (ret) 1352 return ret; 1353 } 1354 1355 return 0; 1356 } 1357 1358 static int hclge_map_tqp(struct hclge_dev *hdev) 1359 { 1360 struct hclge_vport *vport = hdev->vport; 1361 u16 i, num_vport; 1362 1363 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1364 for (i = 0; i < num_vport; i++) { 1365 int ret; 1366 1367 ret = hclge_map_tqp_to_vport(hdev, vport); 1368 if (ret) 1369 return ret; 1370 1371 vport++; 1372 } 1373 1374 return 0; 1375 } 1376 1377 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps) 1378 { 1379 /* this would be initialized later */ 1380 } 1381 1382 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1383 { 1384 struct hnae3_handle *nic = &vport->nic; 1385 struct hclge_dev *hdev = vport->back; 1386 int ret; 1387 1388 nic->pdev = hdev->pdev; 1389 nic->ae_algo = &ae_algo; 1390 nic->numa_node_mask = hdev->numa_node_mask; 1391 1392 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { 1393 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc); 1394 if (ret) { 1395 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", 1396 ret); 1397 return ret; 1398 } 1399 } else { 1400 hclge_unic_setup(vport, num_tqps); 1401 } 1402 1403 return 0; 1404 } 1405 1406 static int hclge_alloc_vport(struct hclge_dev *hdev) 1407 { 1408 struct pci_dev *pdev = hdev->pdev; 1409 struct hclge_vport *vport; 1410 u32 tqp_main_vport; 1411 u32 tqp_per_vport; 1412 int num_vport, i; 1413 int ret; 1414 1415 /* We need to alloc a vport for main NIC of PF */ 1416 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1417 1418 if (hdev->num_tqps < num_vport) { 1419 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)", 1420 hdev->num_tqps, num_vport); 1421 return -EINVAL; 1422 } 1423 1424 /* Alloc the same number of TQPs for every vport */ 1425 tqp_per_vport = hdev->num_tqps / num_vport; 1426 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1427 1428 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1429 GFP_KERNEL); 1430 if (!vport) 1431 return -ENOMEM; 1432 1433 hdev->vport = vport; 1434 hdev->num_alloc_vport = num_vport; 1435 1436 if (IS_ENABLED(CONFIG_PCI_IOV)) 1437 hdev->num_alloc_vfs = hdev->num_req_vfs; 1438 1439 for (i = 0; i < num_vport; i++) { 1440 vport->back = hdev; 1441 vport->vport_id = i; 1442 1443 if (i == 0) 1444 ret = hclge_vport_setup(vport, tqp_main_vport); 1445 else 1446 ret = hclge_vport_setup(vport, tqp_per_vport); 1447 if (ret) { 1448 dev_err(&pdev->dev, 1449 "vport setup failed for vport %d, %d\n", 1450 i, ret); 1451 return ret; 1452 } 1453 1454 vport++; 1455 } 1456 1457 return 0; 1458 } 1459 1460 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1461 struct hclge_pkt_buf_alloc *buf_alloc) 1462 { 1463 /* TX buffer size is unit by 128 byte */ 1464 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1465 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1466 struct hclge_tx_buff_alloc_cmd *req; 1467 struct hclge_desc desc; 1468 int ret; 1469 u8 i; 1470 1471 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1472 1473 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1474 for (i = 0; i < HCLGE_TC_NUM; i++) { 1475 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1476 1477 req->tx_pkt_buff[i] = 1478 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1479 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1480 } 1481 1482 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1483 if (ret) 1484 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1485 ret); 1486 1487 return ret; 1488 } 1489 1490 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1491 struct hclge_pkt_buf_alloc *buf_alloc) 1492 { 1493 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1494 1495 if (ret) 1496 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1497 1498 return ret; 1499 } 1500 1501 static int hclge_get_tc_num(struct hclge_dev *hdev) 1502 { 1503 int i, cnt = 0; 1504 1505 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1506 if (hdev->hw_tc_map & BIT(i)) 1507 cnt++; 1508 return cnt; 1509 } 1510 1511 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev) 1512 { 1513 int i, cnt = 0; 1514 1515 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1516 if (hdev->hw_tc_map & BIT(i) && 1517 hdev->tm_info.hw_pfc_map & BIT(i)) 1518 cnt++; 1519 return cnt; 1520 } 1521 1522 /* Get the number of pfc enabled TCs, which have private buffer */ 1523 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1524 struct hclge_pkt_buf_alloc *buf_alloc) 1525 { 1526 struct hclge_priv_buf *priv; 1527 int i, cnt = 0; 1528 1529 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1530 priv = &buf_alloc->priv_buf[i]; 1531 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1532 priv->enable) 1533 cnt++; 1534 } 1535 1536 return cnt; 1537 } 1538 1539 /* Get the number of pfc disabled TCs, which have private buffer */ 1540 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1541 struct hclge_pkt_buf_alloc *buf_alloc) 1542 { 1543 struct hclge_priv_buf *priv; 1544 int i, cnt = 0; 1545 1546 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1547 priv = &buf_alloc->priv_buf[i]; 1548 if (hdev->hw_tc_map & BIT(i) && 1549 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1550 priv->enable) 1551 cnt++; 1552 } 1553 1554 return cnt; 1555 } 1556 1557 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1558 { 1559 struct hclge_priv_buf *priv; 1560 u32 rx_priv = 0; 1561 int i; 1562 1563 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1564 priv = &buf_alloc->priv_buf[i]; 1565 if (priv->enable) 1566 rx_priv += priv->buf_size; 1567 } 1568 return rx_priv; 1569 } 1570 1571 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1572 { 1573 u32 i, total_tx_size = 0; 1574 1575 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1576 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1577 1578 return total_tx_size; 1579 } 1580 1581 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1582 struct hclge_pkt_buf_alloc *buf_alloc, 1583 u32 rx_all) 1584 { 1585 u32 shared_buf_min, shared_buf_tc, shared_std; 1586 int tc_num, pfc_enable_num; 1587 u32 shared_buf; 1588 u32 rx_priv; 1589 int i; 1590 1591 tc_num = hclge_get_tc_num(hdev); 1592 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev); 1593 1594 if (hnae3_dev_dcb_supported(hdev)) 1595 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV; 1596 else 1597 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV; 1598 1599 shared_buf_tc = pfc_enable_num * hdev->mps + 1600 (tc_num - pfc_enable_num) * hdev->mps / 2 + 1601 hdev->mps; 1602 shared_std = max_t(u32, shared_buf_min, shared_buf_tc); 1603 1604 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1605 if (rx_all <= rx_priv + shared_std) 1606 return false; 1607 1608 shared_buf = rx_all - rx_priv; 1609 buf_alloc->s_buf.buf_size = shared_buf; 1610 buf_alloc->s_buf.self.high = shared_buf; 1611 buf_alloc->s_buf.self.low = 2 * hdev->mps; 1612 1613 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1614 if ((hdev->hw_tc_map & BIT(i)) && 1615 (hdev->tm_info.hw_pfc_map & BIT(i))) { 1616 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps; 1617 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps; 1618 } else { 1619 buf_alloc->s_buf.tc_thrd[i].low = 0; 1620 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps; 1621 } 1622 } 1623 1624 return true; 1625 } 1626 1627 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 1628 struct hclge_pkt_buf_alloc *buf_alloc) 1629 { 1630 u32 i, total_size; 1631 1632 total_size = hdev->pkt_buf_size; 1633 1634 /* alloc tx buffer for all enabled tc */ 1635 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1636 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1637 1638 if (total_size < HCLGE_DEFAULT_TX_BUF) 1639 return -ENOMEM; 1640 1641 if (hdev->hw_tc_map & BIT(i)) 1642 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 1643 else 1644 priv->tx_buf_size = 0; 1645 1646 total_size -= priv->tx_buf_size; 1647 } 1648 1649 return 0; 1650 } 1651 1652 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 1653 * @hdev: pointer to struct hclge_dev 1654 * @buf_alloc: pointer to buffer calculation data 1655 * @return: 0: calculate sucessful, negative: fail 1656 */ 1657 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 1658 struct hclge_pkt_buf_alloc *buf_alloc) 1659 { 1660 u32 rx_all = hdev->pkt_buf_size; 1661 int no_pfc_priv_num, pfc_priv_num; 1662 struct hclge_priv_buf *priv; 1663 int i; 1664 1665 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 1666 1667 /* When DCB is not supported, rx private 1668 * buffer is not allocated. 1669 */ 1670 if (!hnae3_dev_dcb_supported(hdev)) { 1671 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1672 return -ENOMEM; 1673 1674 return 0; 1675 } 1676 1677 /* step 1, try to alloc private buffer for all enabled tc */ 1678 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1679 priv = &buf_alloc->priv_buf[i]; 1680 if (hdev->hw_tc_map & BIT(i)) { 1681 priv->enable = 1; 1682 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1683 priv->wl.low = hdev->mps; 1684 priv->wl.high = priv->wl.low + hdev->mps; 1685 priv->buf_size = priv->wl.high + 1686 HCLGE_DEFAULT_DV; 1687 } else { 1688 priv->wl.low = 0; 1689 priv->wl.high = 2 * hdev->mps; 1690 priv->buf_size = priv->wl.high; 1691 } 1692 } else { 1693 priv->enable = 0; 1694 priv->wl.low = 0; 1695 priv->wl.high = 0; 1696 priv->buf_size = 0; 1697 } 1698 } 1699 1700 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1701 return 0; 1702 1703 /* step 2, try to decrease the buffer size of 1704 * no pfc TC's private buffer 1705 */ 1706 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1707 priv = &buf_alloc->priv_buf[i]; 1708 1709 priv->enable = 0; 1710 priv->wl.low = 0; 1711 priv->wl.high = 0; 1712 priv->buf_size = 0; 1713 1714 if (!(hdev->hw_tc_map & BIT(i))) 1715 continue; 1716 1717 priv->enable = 1; 1718 1719 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1720 priv->wl.low = 128; 1721 priv->wl.high = priv->wl.low + hdev->mps; 1722 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; 1723 } else { 1724 priv->wl.low = 0; 1725 priv->wl.high = hdev->mps; 1726 priv->buf_size = priv->wl.high; 1727 } 1728 } 1729 1730 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1731 return 0; 1732 1733 /* step 3, try to reduce the number of pfc disabled TCs, 1734 * which have private buffer 1735 */ 1736 /* get the total no pfc enable TC number, which have private buffer */ 1737 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 1738 1739 /* let the last to be cleared first */ 1740 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1741 priv = &buf_alloc->priv_buf[i]; 1742 1743 if (hdev->hw_tc_map & BIT(i) && 1744 !(hdev->tm_info.hw_pfc_map & BIT(i))) { 1745 /* Clear the no pfc TC private buffer */ 1746 priv->wl.low = 0; 1747 priv->wl.high = 0; 1748 priv->buf_size = 0; 1749 priv->enable = 0; 1750 no_pfc_priv_num--; 1751 } 1752 1753 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1754 no_pfc_priv_num == 0) 1755 break; 1756 } 1757 1758 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1759 return 0; 1760 1761 /* step 4, try to reduce the number of pfc enabled TCs 1762 * which have private buffer. 1763 */ 1764 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 1765 1766 /* let the last to be cleared first */ 1767 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1768 priv = &buf_alloc->priv_buf[i]; 1769 1770 if (hdev->hw_tc_map & BIT(i) && 1771 hdev->tm_info.hw_pfc_map & BIT(i)) { 1772 /* Reduce the number of pfc TC with private buffer */ 1773 priv->wl.low = 0; 1774 priv->enable = 0; 1775 priv->wl.high = 0; 1776 priv->buf_size = 0; 1777 pfc_priv_num--; 1778 } 1779 1780 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1781 pfc_priv_num == 0) 1782 break; 1783 } 1784 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1785 return 0; 1786 1787 return -ENOMEM; 1788 } 1789 1790 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 1791 struct hclge_pkt_buf_alloc *buf_alloc) 1792 { 1793 struct hclge_rx_priv_buff_cmd *req; 1794 struct hclge_desc desc; 1795 int ret; 1796 int i; 1797 1798 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 1799 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 1800 1801 /* Alloc private buffer TCs */ 1802 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1803 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1804 1805 req->buf_num[i] = 1806 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 1807 req->buf_num[i] |= 1808 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 1809 } 1810 1811 req->shared_buf = 1812 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 1813 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 1814 1815 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1816 if (ret) 1817 dev_err(&hdev->pdev->dev, 1818 "rx private buffer alloc cmd failed %d\n", ret); 1819 1820 return ret; 1821 } 1822 1823 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 1824 struct hclge_pkt_buf_alloc *buf_alloc) 1825 { 1826 struct hclge_rx_priv_wl_buf *req; 1827 struct hclge_priv_buf *priv; 1828 struct hclge_desc desc[2]; 1829 int i, j; 1830 int ret; 1831 1832 for (i = 0; i < 2; i++) { 1833 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 1834 false); 1835 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 1836 1837 /* The first descriptor set the NEXT bit to 1 */ 1838 if (i == 0) 1839 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1840 else 1841 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1842 1843 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1844 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 1845 1846 priv = &buf_alloc->priv_buf[idx]; 1847 req->tc_wl[j].high = 1848 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 1849 req->tc_wl[j].high |= 1850 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1851 req->tc_wl[j].low = 1852 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 1853 req->tc_wl[j].low |= 1854 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1855 } 1856 } 1857 1858 /* Send 2 descriptor at one time */ 1859 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1860 if (ret) 1861 dev_err(&hdev->pdev->dev, 1862 "rx private waterline config cmd failed %d\n", 1863 ret); 1864 return ret; 1865 } 1866 1867 static int hclge_common_thrd_config(struct hclge_dev *hdev, 1868 struct hclge_pkt_buf_alloc *buf_alloc) 1869 { 1870 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 1871 struct hclge_rx_com_thrd *req; 1872 struct hclge_desc desc[2]; 1873 struct hclge_tc_thrd *tc; 1874 int i, j; 1875 int ret; 1876 1877 for (i = 0; i < 2; i++) { 1878 hclge_cmd_setup_basic_desc(&desc[i], 1879 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 1880 req = (struct hclge_rx_com_thrd *)&desc[i].data; 1881 1882 /* The first descriptor set the NEXT bit to 1 */ 1883 if (i == 0) 1884 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1885 else 1886 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1887 1888 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1889 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 1890 1891 req->com_thrd[j].high = 1892 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 1893 req->com_thrd[j].high |= 1894 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1895 req->com_thrd[j].low = 1896 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 1897 req->com_thrd[j].low |= 1898 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1899 } 1900 } 1901 1902 /* Send 2 descriptors at one time */ 1903 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1904 if (ret) 1905 dev_err(&hdev->pdev->dev, 1906 "common threshold config cmd failed %d\n", ret); 1907 return ret; 1908 } 1909 1910 static int hclge_common_wl_config(struct hclge_dev *hdev, 1911 struct hclge_pkt_buf_alloc *buf_alloc) 1912 { 1913 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 1914 struct hclge_rx_com_wl *req; 1915 struct hclge_desc desc; 1916 int ret; 1917 1918 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 1919 1920 req = (struct hclge_rx_com_wl *)desc.data; 1921 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 1922 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1923 1924 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 1925 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1926 1927 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1928 if (ret) 1929 dev_err(&hdev->pdev->dev, 1930 "common waterline config cmd failed %d\n", ret); 1931 1932 return ret; 1933 } 1934 1935 int hclge_buffer_alloc(struct hclge_dev *hdev) 1936 { 1937 struct hclge_pkt_buf_alloc *pkt_buf; 1938 int ret; 1939 1940 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 1941 if (!pkt_buf) 1942 return -ENOMEM; 1943 1944 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 1945 if (ret) { 1946 dev_err(&hdev->pdev->dev, 1947 "could not calc tx buffer size for all TCs %d\n", ret); 1948 goto out; 1949 } 1950 1951 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 1952 if (ret) { 1953 dev_err(&hdev->pdev->dev, 1954 "could not alloc tx buffers %d\n", ret); 1955 goto out; 1956 } 1957 1958 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 1959 if (ret) { 1960 dev_err(&hdev->pdev->dev, 1961 "could not calc rx priv buffer size for all TCs %d\n", 1962 ret); 1963 goto out; 1964 } 1965 1966 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 1967 if (ret) { 1968 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 1969 ret); 1970 goto out; 1971 } 1972 1973 if (hnae3_dev_dcb_supported(hdev)) { 1974 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 1975 if (ret) { 1976 dev_err(&hdev->pdev->dev, 1977 "could not configure rx private waterline %d\n", 1978 ret); 1979 goto out; 1980 } 1981 1982 ret = hclge_common_thrd_config(hdev, pkt_buf); 1983 if (ret) { 1984 dev_err(&hdev->pdev->dev, 1985 "could not configure common threshold %d\n", 1986 ret); 1987 goto out; 1988 } 1989 } 1990 1991 ret = hclge_common_wl_config(hdev, pkt_buf); 1992 if (ret) 1993 dev_err(&hdev->pdev->dev, 1994 "could not configure common waterline %d\n", ret); 1995 1996 out: 1997 kfree(pkt_buf); 1998 return ret; 1999 } 2000 2001 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2002 { 2003 struct hnae3_handle *roce = &vport->roce; 2004 struct hnae3_handle *nic = &vport->nic; 2005 2006 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2007 2008 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors || 2009 vport->back->num_msi_left == 0) 2010 return -EINVAL; 2011 2012 roce->rinfo.base_vector = vport->back->roce_base_vector; 2013 2014 roce->rinfo.netdev = nic->kinfo.netdev; 2015 roce->rinfo.roce_io_base = vport->back->hw.io_base; 2016 2017 roce->pdev = nic->pdev; 2018 roce->ae_algo = nic->ae_algo; 2019 roce->numa_node_mask = nic->numa_node_mask; 2020 2021 return 0; 2022 } 2023 2024 static int hclge_init_msi(struct hclge_dev *hdev) 2025 { 2026 struct pci_dev *pdev = hdev->pdev; 2027 int vectors; 2028 int i; 2029 2030 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2031 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2032 if (vectors < 0) { 2033 dev_err(&pdev->dev, 2034 "failed(%d) to allocate MSI/MSI-X vectors\n", 2035 vectors); 2036 return vectors; 2037 } 2038 if (vectors < hdev->num_msi) 2039 dev_warn(&hdev->pdev->dev, 2040 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2041 hdev->num_msi, vectors); 2042 2043 hdev->num_msi = vectors; 2044 hdev->num_msi_left = vectors; 2045 hdev->base_msi_vector = pdev->irq; 2046 hdev->roce_base_vector = hdev->base_msi_vector + 2047 hdev->roce_base_msix_offset; 2048 2049 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2050 sizeof(u16), GFP_KERNEL); 2051 if (!hdev->vector_status) { 2052 pci_free_irq_vectors(pdev); 2053 return -ENOMEM; 2054 } 2055 2056 for (i = 0; i < hdev->num_msi; i++) 2057 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2058 2059 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2060 sizeof(int), GFP_KERNEL); 2061 if (!hdev->vector_irq) { 2062 pci_free_irq_vectors(pdev); 2063 return -ENOMEM; 2064 } 2065 2066 return 0; 2067 } 2068 2069 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2070 { 2071 2072 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2073 duplex = HCLGE_MAC_FULL; 2074 2075 return duplex; 2076 } 2077 2078 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2079 u8 duplex) 2080 { 2081 struct hclge_config_mac_speed_dup_cmd *req; 2082 struct hclge_desc desc; 2083 int ret; 2084 2085 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2086 2087 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2088 2089 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); 2090 2091 switch (speed) { 2092 case HCLGE_MAC_SPEED_10M: 2093 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2094 HCLGE_CFG_SPEED_S, 6); 2095 break; 2096 case HCLGE_MAC_SPEED_100M: 2097 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2098 HCLGE_CFG_SPEED_S, 7); 2099 break; 2100 case HCLGE_MAC_SPEED_1G: 2101 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2102 HCLGE_CFG_SPEED_S, 0); 2103 break; 2104 case HCLGE_MAC_SPEED_10G: 2105 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2106 HCLGE_CFG_SPEED_S, 1); 2107 break; 2108 case HCLGE_MAC_SPEED_25G: 2109 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2110 HCLGE_CFG_SPEED_S, 2); 2111 break; 2112 case HCLGE_MAC_SPEED_40G: 2113 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2114 HCLGE_CFG_SPEED_S, 3); 2115 break; 2116 case HCLGE_MAC_SPEED_50G: 2117 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2118 HCLGE_CFG_SPEED_S, 4); 2119 break; 2120 case HCLGE_MAC_SPEED_100G: 2121 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2122 HCLGE_CFG_SPEED_S, 5); 2123 break; 2124 default: 2125 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2126 return -EINVAL; 2127 } 2128 2129 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2130 1); 2131 2132 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2133 if (ret) { 2134 dev_err(&hdev->pdev->dev, 2135 "mac speed/duplex config cmd failed %d.\n", ret); 2136 return ret; 2137 } 2138 2139 return 0; 2140 } 2141 2142 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) 2143 { 2144 int ret; 2145 2146 duplex = hclge_check_speed_dup(duplex, speed); 2147 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex) 2148 return 0; 2149 2150 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex); 2151 if (ret) 2152 return ret; 2153 2154 hdev->hw.mac.speed = speed; 2155 hdev->hw.mac.duplex = duplex; 2156 2157 return 0; 2158 } 2159 2160 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2161 u8 duplex) 2162 { 2163 struct hclge_vport *vport = hclge_get_vport(handle); 2164 struct hclge_dev *hdev = vport->back; 2165 2166 return hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2167 } 2168 2169 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed, 2170 u8 *duplex) 2171 { 2172 struct hclge_query_an_speed_dup_cmd *req; 2173 struct hclge_desc desc; 2174 int speed_tmp; 2175 int ret; 2176 2177 req = (struct hclge_query_an_speed_dup_cmd *)desc.data; 2178 2179 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true); 2180 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2181 if (ret) { 2182 dev_err(&hdev->pdev->dev, 2183 "mac speed/autoneg/duplex query cmd failed %d\n", 2184 ret); 2185 return ret; 2186 } 2187 2188 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); 2189 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, 2190 HCLGE_QUERY_SPEED_S); 2191 2192 ret = hclge_parse_speed(speed_tmp, speed); 2193 if (ret) 2194 dev_err(&hdev->pdev->dev, 2195 "could not parse speed(=%d), %d\n", speed_tmp, ret); 2196 2197 return ret; 2198 } 2199 2200 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2201 { 2202 struct hclge_config_auto_neg_cmd *req; 2203 struct hclge_desc desc; 2204 u32 flag = 0; 2205 int ret; 2206 2207 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2208 2209 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2210 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); 2211 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2212 2213 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2214 if (ret) 2215 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2216 ret); 2217 2218 return ret; 2219 } 2220 2221 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2222 { 2223 struct hclge_vport *vport = hclge_get_vport(handle); 2224 struct hclge_dev *hdev = vport->back; 2225 2226 return hclge_set_autoneg_en(hdev, enable); 2227 } 2228 2229 static int hclge_get_autoneg(struct hnae3_handle *handle) 2230 { 2231 struct hclge_vport *vport = hclge_get_vport(handle); 2232 struct hclge_dev *hdev = vport->back; 2233 struct phy_device *phydev = hdev->hw.mac.phydev; 2234 2235 if (phydev) 2236 return phydev->autoneg; 2237 2238 return hdev->hw.mac.autoneg; 2239 } 2240 2241 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev, 2242 bool mask_vlan, 2243 u8 *mac_mask) 2244 { 2245 struct hclge_mac_vlan_mask_entry_cmd *req; 2246 struct hclge_desc desc; 2247 int status; 2248 2249 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data; 2250 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false); 2251 2252 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B, 2253 mask_vlan ? 1 : 0); 2254 ether_addr_copy(req->mac_mask, mac_mask); 2255 2256 status = hclge_cmd_send(&hdev->hw, &desc, 1); 2257 if (status) 2258 dev_err(&hdev->pdev->dev, 2259 "Config mac_vlan_mask failed for cmd_send, ret =%d\n", 2260 status); 2261 2262 return status; 2263 } 2264 2265 static int hclge_mac_init(struct hclge_dev *hdev) 2266 { 2267 struct hnae3_handle *handle = &hdev->vport[0].nic; 2268 struct net_device *netdev = handle->kinfo.netdev; 2269 struct hclge_mac *mac = &hdev->hw.mac; 2270 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 2271 struct hclge_vport *vport; 2272 int mtu; 2273 int ret; 2274 int i; 2275 2276 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2277 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2278 hdev->hw.mac.duplex); 2279 if (ret) { 2280 dev_err(&hdev->pdev->dev, 2281 "Config mac speed dup fail ret=%d\n", ret); 2282 return ret; 2283 } 2284 2285 mac->link = 0; 2286 2287 /* Initialize the MTA table work mode */ 2288 hdev->enable_mta = true; 2289 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36; 2290 2291 ret = hclge_set_mta_filter_mode(hdev, 2292 hdev->mta_mac_sel_type, 2293 hdev->enable_mta); 2294 if (ret) { 2295 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n", 2296 ret); 2297 return ret; 2298 } 2299 2300 for (i = 0; i < hdev->num_alloc_vport; i++) { 2301 vport = &hdev->vport[i]; 2302 vport->accept_mta_mc = false; 2303 2304 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow)); 2305 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false); 2306 if (ret) { 2307 dev_err(&hdev->pdev->dev, 2308 "set mta filter mode fail ret=%d\n", ret); 2309 return ret; 2310 } 2311 } 2312 2313 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask); 2314 if (ret) { 2315 dev_err(&hdev->pdev->dev, 2316 "set default mac_vlan_mask fail ret=%d\n", ret); 2317 return ret; 2318 } 2319 2320 if (netdev) 2321 mtu = netdev->mtu; 2322 else 2323 mtu = ETH_DATA_LEN; 2324 2325 ret = hclge_set_mtu(handle, mtu); 2326 if (ret) 2327 dev_err(&hdev->pdev->dev, 2328 "set mtu failed ret=%d\n", ret); 2329 2330 return ret; 2331 } 2332 2333 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2334 { 2335 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2336 schedule_work(&hdev->mbx_service_task); 2337 } 2338 2339 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2340 { 2341 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 2342 schedule_work(&hdev->rst_service_task); 2343 } 2344 2345 static void hclge_task_schedule(struct hclge_dev *hdev) 2346 { 2347 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && 2348 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2349 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)) 2350 (void)schedule_work(&hdev->service_task); 2351 } 2352 2353 static int hclge_get_mac_link_status(struct hclge_dev *hdev) 2354 { 2355 struct hclge_link_status_cmd *req; 2356 struct hclge_desc desc; 2357 int link_status; 2358 int ret; 2359 2360 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2361 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2362 if (ret) { 2363 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2364 ret); 2365 return ret; 2366 } 2367 2368 req = (struct hclge_link_status_cmd *)desc.data; 2369 link_status = req->status & HCLGE_LINK_STATUS_UP_M; 2370 2371 return !!link_status; 2372 } 2373 2374 static int hclge_get_mac_phy_link(struct hclge_dev *hdev) 2375 { 2376 int mac_state; 2377 int link_stat; 2378 2379 mac_state = hclge_get_mac_link_status(hdev); 2380 2381 if (hdev->hw.mac.phydev) { 2382 if (!genphy_read_status(hdev->hw.mac.phydev)) 2383 link_stat = mac_state & 2384 hdev->hw.mac.phydev->link; 2385 else 2386 link_stat = 0; 2387 2388 } else { 2389 link_stat = mac_state; 2390 } 2391 2392 return !!link_stat; 2393 } 2394 2395 static void hclge_update_link_status(struct hclge_dev *hdev) 2396 { 2397 struct hnae3_client *client = hdev->nic_client; 2398 struct hnae3_handle *handle; 2399 int state; 2400 int i; 2401 2402 if (!client) 2403 return; 2404 state = hclge_get_mac_phy_link(hdev); 2405 if (state != hdev->hw.mac.link) { 2406 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2407 handle = &hdev->vport[i].nic; 2408 client->ops->link_status_change(handle, state); 2409 } 2410 hdev->hw.mac.link = state; 2411 } 2412 } 2413 2414 static int hclge_update_speed_duplex(struct hclge_dev *hdev) 2415 { 2416 struct hclge_mac mac = hdev->hw.mac; 2417 u8 duplex; 2418 int speed; 2419 int ret; 2420 2421 /* get the speed and duplex as autoneg'result from mac cmd when phy 2422 * doesn't exit. 2423 */ 2424 if (mac.phydev || !mac.autoneg) 2425 return 0; 2426 2427 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex); 2428 if (ret) { 2429 dev_err(&hdev->pdev->dev, 2430 "mac autoneg/speed/duplex query failed %d\n", ret); 2431 return ret; 2432 } 2433 2434 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2435 if (ret) { 2436 dev_err(&hdev->pdev->dev, 2437 "mac speed/duplex config failed %d\n", ret); 2438 return ret; 2439 } 2440 2441 return 0; 2442 } 2443 2444 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle) 2445 { 2446 struct hclge_vport *vport = hclge_get_vport(handle); 2447 struct hclge_dev *hdev = vport->back; 2448 2449 return hclge_update_speed_duplex(hdev); 2450 } 2451 2452 static int hclge_get_status(struct hnae3_handle *handle) 2453 { 2454 struct hclge_vport *vport = hclge_get_vport(handle); 2455 struct hclge_dev *hdev = vport->back; 2456 2457 hclge_update_link_status(hdev); 2458 2459 return hdev->hw.mac.link; 2460 } 2461 2462 static void hclge_service_timer(struct timer_list *t) 2463 { 2464 struct hclge_dev *hdev = from_timer(hdev, t, service_timer); 2465 2466 mod_timer(&hdev->service_timer, jiffies + HZ); 2467 hdev->hw_stats.stats_timer++; 2468 hclge_task_schedule(hdev); 2469 } 2470 2471 static void hclge_service_complete(struct hclge_dev *hdev) 2472 { 2473 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)); 2474 2475 /* Flush memory before next watchdog */ 2476 smp_mb__before_atomic(); 2477 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); 2478 } 2479 2480 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 2481 { 2482 u32 rst_src_reg; 2483 u32 cmdq_src_reg; 2484 2485 /* fetch the events from their corresponding regs */ 2486 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 2487 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 2488 2489 /* Assumption: If by any chance reset and mailbox events are reported 2490 * together then we will only process reset event in this go and will 2491 * defer the processing of the mailbox events. Since, we would have not 2492 * cleared RX CMDQ event this time we would receive again another 2493 * interrupt from H/W just for the mailbox. 2494 */ 2495 2496 /* check for vector0 reset event sources */ 2497 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { 2498 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); 2499 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 2500 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 2501 return HCLGE_VECTOR0_EVENT_RST; 2502 } 2503 2504 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { 2505 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); 2506 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); 2507 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); 2508 return HCLGE_VECTOR0_EVENT_RST; 2509 } 2510 2511 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { 2512 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 2513 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 2514 return HCLGE_VECTOR0_EVENT_RST; 2515 } 2516 2517 /* check for vector0 mailbox(=CMDQ RX) event source */ 2518 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 2519 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 2520 *clearval = cmdq_src_reg; 2521 return HCLGE_VECTOR0_EVENT_MBX; 2522 } 2523 2524 return HCLGE_VECTOR0_EVENT_OTHER; 2525 } 2526 2527 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 2528 u32 regclr) 2529 { 2530 switch (event_type) { 2531 case HCLGE_VECTOR0_EVENT_RST: 2532 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 2533 break; 2534 case HCLGE_VECTOR0_EVENT_MBX: 2535 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 2536 break; 2537 } 2538 } 2539 2540 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 2541 { 2542 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 2543 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 2544 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 2545 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 2546 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 2547 } 2548 2549 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 2550 { 2551 writel(enable ? 1 : 0, vector->addr); 2552 } 2553 2554 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 2555 { 2556 struct hclge_dev *hdev = data; 2557 u32 event_cause; 2558 u32 clearval; 2559 2560 hclge_enable_vector(&hdev->misc_vector, false); 2561 event_cause = hclge_check_event_cause(hdev, &clearval); 2562 2563 /* vector 0 interrupt is shared with reset and mailbox source events.*/ 2564 switch (event_cause) { 2565 case HCLGE_VECTOR0_EVENT_RST: 2566 hclge_reset_task_schedule(hdev); 2567 break; 2568 case HCLGE_VECTOR0_EVENT_MBX: 2569 /* If we are here then, 2570 * 1. Either we are not handling any mbx task and we are not 2571 * scheduled as well 2572 * OR 2573 * 2. We could be handling a mbx task but nothing more is 2574 * scheduled. 2575 * In both cases, we should schedule mbx task as there are more 2576 * mbx messages reported by this interrupt. 2577 */ 2578 hclge_mbx_task_schedule(hdev); 2579 break; 2580 default: 2581 dev_warn(&hdev->pdev->dev, 2582 "received unknown or unhandled event of vector0\n"); 2583 break; 2584 } 2585 2586 /* clear the source of interrupt if it is not cause by reset */ 2587 if (event_cause != HCLGE_VECTOR0_EVENT_RST) { 2588 hclge_clear_event_cause(hdev, event_cause, clearval); 2589 hclge_enable_vector(&hdev->misc_vector, true); 2590 } 2591 2592 return IRQ_HANDLED; 2593 } 2594 2595 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 2596 { 2597 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 2598 dev_warn(&hdev->pdev->dev, 2599 "vector(vector_id %d) has been freed.\n", vector_id); 2600 return; 2601 } 2602 2603 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 2604 hdev->num_msi_left += 1; 2605 hdev->num_msi_used -= 1; 2606 } 2607 2608 static void hclge_get_misc_vector(struct hclge_dev *hdev) 2609 { 2610 struct hclge_misc_vector *vector = &hdev->misc_vector; 2611 2612 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 2613 2614 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 2615 hdev->vector_status[0] = 0; 2616 2617 hdev->num_msi_left -= 1; 2618 hdev->num_msi_used += 1; 2619 } 2620 2621 static int hclge_misc_irq_init(struct hclge_dev *hdev) 2622 { 2623 int ret; 2624 2625 hclge_get_misc_vector(hdev); 2626 2627 /* this would be explicitly freed in the end */ 2628 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 2629 0, "hclge_misc", hdev); 2630 if (ret) { 2631 hclge_free_vector(hdev, 0); 2632 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 2633 hdev->misc_vector.vector_irq); 2634 } 2635 2636 return ret; 2637 } 2638 2639 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 2640 { 2641 free_irq(hdev->misc_vector.vector_irq, hdev); 2642 hclge_free_vector(hdev, 0); 2643 } 2644 2645 static int hclge_notify_client(struct hclge_dev *hdev, 2646 enum hnae3_reset_notify_type type) 2647 { 2648 struct hnae3_client *client = hdev->nic_client; 2649 u16 i; 2650 2651 if (!client->ops->reset_notify) 2652 return -EOPNOTSUPP; 2653 2654 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2655 struct hnae3_handle *handle = &hdev->vport[i].nic; 2656 int ret; 2657 2658 ret = client->ops->reset_notify(handle, type); 2659 if (ret) 2660 return ret; 2661 } 2662 2663 return 0; 2664 } 2665 2666 static int hclge_reset_wait(struct hclge_dev *hdev) 2667 { 2668 #define HCLGE_RESET_WATI_MS 100 2669 #define HCLGE_RESET_WAIT_CNT 5 2670 u32 val, reg, reg_bit; 2671 u32 cnt = 0; 2672 2673 switch (hdev->reset_type) { 2674 case HNAE3_GLOBAL_RESET: 2675 reg = HCLGE_GLOBAL_RESET_REG; 2676 reg_bit = HCLGE_GLOBAL_RESET_BIT; 2677 break; 2678 case HNAE3_CORE_RESET: 2679 reg = HCLGE_GLOBAL_RESET_REG; 2680 reg_bit = HCLGE_CORE_RESET_BIT; 2681 break; 2682 case HNAE3_FUNC_RESET: 2683 reg = HCLGE_FUN_RST_ING; 2684 reg_bit = HCLGE_FUN_RST_ING_B; 2685 break; 2686 default: 2687 dev_err(&hdev->pdev->dev, 2688 "Wait for unsupported reset type: %d\n", 2689 hdev->reset_type); 2690 return -EINVAL; 2691 } 2692 2693 val = hclge_read_dev(&hdev->hw, reg); 2694 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 2695 msleep(HCLGE_RESET_WATI_MS); 2696 val = hclge_read_dev(&hdev->hw, reg); 2697 cnt++; 2698 } 2699 2700 if (cnt >= HCLGE_RESET_WAIT_CNT) { 2701 dev_warn(&hdev->pdev->dev, 2702 "Wait for reset timeout: %d\n", hdev->reset_type); 2703 return -EBUSY; 2704 } 2705 2706 return 0; 2707 } 2708 2709 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 2710 { 2711 struct hclge_desc desc; 2712 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 2713 int ret; 2714 2715 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 2716 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 2717 req->fun_reset_vfid = func_id; 2718 2719 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2720 if (ret) 2721 dev_err(&hdev->pdev->dev, 2722 "send function reset cmd fail, status =%d\n", ret); 2723 2724 return ret; 2725 } 2726 2727 static void hclge_do_reset(struct hclge_dev *hdev) 2728 { 2729 struct pci_dev *pdev = hdev->pdev; 2730 u32 val; 2731 2732 switch (hdev->reset_type) { 2733 case HNAE3_GLOBAL_RESET: 2734 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2735 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 2736 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2737 dev_info(&pdev->dev, "Global Reset requested\n"); 2738 break; 2739 case HNAE3_CORE_RESET: 2740 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2741 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1); 2742 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2743 dev_info(&pdev->dev, "Core Reset requested\n"); 2744 break; 2745 case HNAE3_FUNC_RESET: 2746 dev_info(&pdev->dev, "PF Reset requested\n"); 2747 hclge_func_reset_cmd(hdev, 0); 2748 /* schedule again to check later */ 2749 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 2750 hclge_reset_task_schedule(hdev); 2751 break; 2752 default: 2753 dev_warn(&pdev->dev, 2754 "Unsupported reset type: %d\n", hdev->reset_type); 2755 break; 2756 } 2757 } 2758 2759 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, 2760 unsigned long *addr) 2761 { 2762 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2763 2764 /* return the highest priority reset level amongst all */ 2765 if (test_bit(HNAE3_GLOBAL_RESET, addr)) 2766 rst_level = HNAE3_GLOBAL_RESET; 2767 else if (test_bit(HNAE3_CORE_RESET, addr)) 2768 rst_level = HNAE3_CORE_RESET; 2769 else if (test_bit(HNAE3_IMP_RESET, addr)) 2770 rst_level = HNAE3_IMP_RESET; 2771 else if (test_bit(HNAE3_FUNC_RESET, addr)) 2772 rst_level = HNAE3_FUNC_RESET; 2773 2774 /* now, clear all other resets */ 2775 clear_bit(HNAE3_GLOBAL_RESET, addr); 2776 clear_bit(HNAE3_CORE_RESET, addr); 2777 clear_bit(HNAE3_IMP_RESET, addr); 2778 clear_bit(HNAE3_FUNC_RESET, addr); 2779 2780 return rst_level; 2781 } 2782 2783 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 2784 { 2785 u32 clearval = 0; 2786 2787 switch (hdev->reset_type) { 2788 case HNAE3_IMP_RESET: 2789 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 2790 break; 2791 case HNAE3_GLOBAL_RESET: 2792 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 2793 break; 2794 case HNAE3_CORE_RESET: 2795 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); 2796 break; 2797 default: 2798 break; 2799 } 2800 2801 if (!clearval) 2802 return; 2803 2804 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval); 2805 hclge_enable_vector(&hdev->misc_vector, true); 2806 } 2807 2808 static void hclge_reset(struct hclge_dev *hdev) 2809 { 2810 struct hnae3_handle *handle; 2811 2812 /* perform reset of the stack & ae device for a client */ 2813 handle = &hdev->vport[0].nic; 2814 rtnl_lock(); 2815 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2816 2817 if (!hclge_reset_wait(hdev)) { 2818 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 2819 hclge_reset_ae_dev(hdev->ae_dev); 2820 hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 2821 2822 hclge_clear_reset_cause(hdev); 2823 } else { 2824 /* schedule again to check pending resets later */ 2825 set_bit(hdev->reset_type, &hdev->reset_pending); 2826 hclge_reset_task_schedule(hdev); 2827 } 2828 2829 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2830 handle->last_reset_time = jiffies; 2831 rtnl_unlock(); 2832 } 2833 2834 static void hclge_reset_event(struct hnae3_handle *handle) 2835 { 2836 struct hclge_vport *vport = hclge_get_vport(handle); 2837 struct hclge_dev *hdev = vport->back; 2838 2839 /* check if this is a new reset request and we are not here just because 2840 * last reset attempt did not succeed and watchdog hit us again. We will 2841 * know this if last reset request did not occur very recently (watchdog 2842 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 2843 * In case of new request we reset the "reset level" to PF reset. 2844 * And if it is a repeat reset request of the most recent one then we 2845 * want to make sure we throttle the reset request. Therefore, we will 2846 * not allow it again before 3*HZ times. 2847 */ 2848 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ))) 2849 return; 2850 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ))) 2851 handle->reset_level = HNAE3_FUNC_RESET; 2852 2853 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d", 2854 handle->reset_level); 2855 2856 /* request reset & schedule reset task */ 2857 set_bit(handle->reset_level, &hdev->reset_request); 2858 hclge_reset_task_schedule(hdev); 2859 2860 if (handle->reset_level < HNAE3_GLOBAL_RESET) 2861 handle->reset_level++; 2862 } 2863 2864 static void hclge_reset_subtask(struct hclge_dev *hdev) 2865 { 2866 /* check if there is any ongoing reset in the hardware. This status can 2867 * be checked from reset_pending. If there is then, we need to wait for 2868 * hardware to complete reset. 2869 * a. If we are able to figure out in reasonable time that hardware 2870 * has fully resetted then, we can proceed with driver, client 2871 * reset. 2872 * b. else, we can come back later to check this status so re-sched 2873 * now. 2874 */ 2875 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); 2876 if (hdev->reset_type != HNAE3_NONE_RESET) 2877 hclge_reset(hdev); 2878 2879 /* check if we got any *new* reset requests to be honored */ 2880 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); 2881 if (hdev->reset_type != HNAE3_NONE_RESET) 2882 hclge_do_reset(hdev); 2883 2884 hdev->reset_type = HNAE3_NONE_RESET; 2885 } 2886 2887 static void hclge_reset_service_task(struct work_struct *work) 2888 { 2889 struct hclge_dev *hdev = 2890 container_of(work, struct hclge_dev, rst_service_task); 2891 2892 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2893 return; 2894 2895 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 2896 2897 hclge_reset_subtask(hdev); 2898 2899 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 2900 } 2901 2902 static void hclge_mailbox_service_task(struct work_struct *work) 2903 { 2904 struct hclge_dev *hdev = 2905 container_of(work, struct hclge_dev, mbx_service_task); 2906 2907 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 2908 return; 2909 2910 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 2911 2912 hclge_mbx_handler(hdev); 2913 2914 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 2915 } 2916 2917 static void hclge_service_task(struct work_struct *work) 2918 { 2919 struct hclge_dev *hdev = 2920 container_of(work, struct hclge_dev, service_task); 2921 2922 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { 2923 hclge_update_stats_for_all(hdev); 2924 hdev->hw_stats.stats_timer = 0; 2925 } 2926 2927 hclge_update_speed_duplex(hdev); 2928 hclge_update_link_status(hdev); 2929 hclge_service_complete(hdev); 2930 } 2931 2932 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 2933 { 2934 /* VF handle has no client */ 2935 if (!handle->client) 2936 return container_of(handle, struct hclge_vport, nic); 2937 else if (handle->client->type == HNAE3_CLIENT_ROCE) 2938 return container_of(handle, struct hclge_vport, roce); 2939 else 2940 return container_of(handle, struct hclge_vport, nic); 2941 } 2942 2943 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 2944 struct hnae3_vector_info *vector_info) 2945 { 2946 struct hclge_vport *vport = hclge_get_vport(handle); 2947 struct hnae3_vector_info *vector = vector_info; 2948 struct hclge_dev *hdev = vport->back; 2949 int alloc = 0; 2950 int i, j; 2951 2952 vector_num = min(hdev->num_msi_left, vector_num); 2953 2954 for (j = 0; j < vector_num; j++) { 2955 for (i = 1; i < hdev->num_msi; i++) { 2956 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 2957 vector->vector = pci_irq_vector(hdev->pdev, i); 2958 vector->io_addr = hdev->hw.io_base + 2959 HCLGE_VECTOR_REG_BASE + 2960 (i - 1) * HCLGE_VECTOR_REG_OFFSET + 2961 vport->vport_id * 2962 HCLGE_VECTOR_VF_OFFSET; 2963 hdev->vector_status[i] = vport->vport_id; 2964 hdev->vector_irq[i] = vector->vector; 2965 2966 vector++; 2967 alloc++; 2968 2969 break; 2970 } 2971 } 2972 } 2973 hdev->num_msi_left -= alloc; 2974 hdev->num_msi_used += alloc; 2975 2976 return alloc; 2977 } 2978 2979 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 2980 { 2981 int i; 2982 2983 for (i = 0; i < hdev->num_msi; i++) 2984 if (vector == hdev->vector_irq[i]) 2985 return i; 2986 2987 return -EINVAL; 2988 } 2989 2990 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 2991 { 2992 struct hclge_vport *vport = hclge_get_vport(handle); 2993 struct hclge_dev *hdev = vport->back; 2994 int vector_id; 2995 2996 vector_id = hclge_get_vector_index(hdev, vector); 2997 if (vector_id < 0) { 2998 dev_err(&hdev->pdev->dev, 2999 "Get vector index fail. vector_id =%d\n", vector_id); 3000 return vector_id; 3001 } 3002 3003 hclge_free_vector(hdev, vector_id); 3004 3005 return 0; 3006 } 3007 3008 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle) 3009 { 3010 return HCLGE_RSS_KEY_SIZE; 3011 } 3012 3013 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle) 3014 { 3015 return HCLGE_RSS_IND_TBL_SIZE; 3016 } 3017 3018 static int hclge_set_rss_algo_key(struct hclge_dev *hdev, 3019 const u8 hfunc, const u8 *key) 3020 { 3021 struct hclge_rss_config_cmd *req; 3022 struct hclge_desc desc; 3023 int key_offset; 3024 int key_size; 3025 int ret; 3026 3027 req = (struct hclge_rss_config_cmd *)desc.data; 3028 3029 for (key_offset = 0; key_offset < 3; key_offset++) { 3030 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, 3031 false); 3032 3033 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK); 3034 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B); 3035 3036 if (key_offset == 2) 3037 key_size = 3038 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2; 3039 else 3040 key_size = HCLGE_RSS_HASH_KEY_NUM; 3041 3042 memcpy(req->hash_key, 3043 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size); 3044 3045 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3046 if (ret) { 3047 dev_err(&hdev->pdev->dev, 3048 "Configure RSS config fail, status = %d\n", 3049 ret); 3050 return ret; 3051 } 3052 } 3053 return 0; 3054 } 3055 3056 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir) 3057 { 3058 struct hclge_rss_indirection_table_cmd *req; 3059 struct hclge_desc desc; 3060 int i, j; 3061 int ret; 3062 3063 req = (struct hclge_rss_indirection_table_cmd *)desc.data; 3064 3065 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) { 3066 hclge_cmd_setup_basic_desc 3067 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false); 3068 3069 req->start_table_index = 3070 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE); 3071 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK); 3072 3073 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++) 3074 req->rss_result[j] = 3075 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j]; 3076 3077 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3078 if (ret) { 3079 dev_err(&hdev->pdev->dev, 3080 "Configure rss indir table fail,status = %d\n", 3081 ret); 3082 return ret; 3083 } 3084 } 3085 return 0; 3086 } 3087 3088 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid, 3089 u16 *tc_size, u16 *tc_offset) 3090 { 3091 struct hclge_rss_tc_mode_cmd *req; 3092 struct hclge_desc desc; 3093 int ret; 3094 int i; 3095 3096 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false); 3097 req = (struct hclge_rss_tc_mode_cmd *)desc.data; 3098 3099 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 3100 u16 mode = 0; 3101 3102 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); 3103 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M, 3104 HCLGE_RSS_TC_SIZE_S, tc_size[i]); 3105 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M, 3106 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); 3107 3108 req->rss_tc_mode[i] = cpu_to_le16(mode); 3109 } 3110 3111 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3112 if (ret) 3113 dev_err(&hdev->pdev->dev, 3114 "Configure rss tc mode fail, status = %d\n", ret); 3115 3116 return ret; 3117 } 3118 3119 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) 3120 { 3121 struct hclge_rss_input_tuple_cmd *req; 3122 struct hclge_desc desc; 3123 int ret; 3124 3125 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); 3126 3127 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 3128 3129 /* Get the tuple cfg from pf */ 3130 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en; 3131 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en; 3132 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en; 3133 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en; 3134 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en; 3135 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en; 3136 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en; 3137 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en; 3138 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3139 if (ret) 3140 dev_err(&hdev->pdev->dev, 3141 "Configure rss input fail, status = %d\n", ret); 3142 return ret; 3143 } 3144 3145 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 3146 u8 *key, u8 *hfunc) 3147 { 3148 struct hclge_vport *vport = hclge_get_vport(handle); 3149 int i; 3150 3151 /* Get hash algorithm */ 3152 if (hfunc) 3153 *hfunc = vport->rss_algo; 3154 3155 /* Get the RSS Key required by the user */ 3156 if (key) 3157 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE); 3158 3159 /* Get indirect table */ 3160 if (indir) 3161 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3162 indir[i] = vport->rss_indirection_tbl[i]; 3163 3164 return 0; 3165 } 3166 3167 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 3168 const u8 *key, const u8 hfunc) 3169 { 3170 struct hclge_vport *vport = hclge_get_vport(handle); 3171 struct hclge_dev *hdev = vport->back; 3172 u8 hash_algo; 3173 int ret, i; 3174 3175 /* Set the RSS Hash Key if specififed by the user */ 3176 if (key) { 3177 3178 if (hfunc == ETH_RSS_HASH_TOP || 3179 hfunc == ETH_RSS_HASH_NO_CHANGE) 3180 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 3181 else 3182 return -EINVAL; 3183 ret = hclge_set_rss_algo_key(hdev, hash_algo, key); 3184 if (ret) 3185 return ret; 3186 3187 /* Update the shadow RSS key with user specified qids */ 3188 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE); 3189 vport->rss_algo = hash_algo; 3190 } 3191 3192 /* Update the shadow RSS table with user specified qids */ 3193 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3194 vport->rss_indirection_tbl[i] = indir[i]; 3195 3196 /* Update the hardware */ 3197 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl); 3198 } 3199 3200 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 3201 { 3202 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0; 3203 3204 if (nfc->data & RXH_L4_B_2_3) 3205 hash_sets |= HCLGE_D_PORT_BIT; 3206 else 3207 hash_sets &= ~HCLGE_D_PORT_BIT; 3208 3209 if (nfc->data & RXH_IP_SRC) 3210 hash_sets |= HCLGE_S_IP_BIT; 3211 else 3212 hash_sets &= ~HCLGE_S_IP_BIT; 3213 3214 if (nfc->data & RXH_IP_DST) 3215 hash_sets |= HCLGE_D_IP_BIT; 3216 else 3217 hash_sets &= ~HCLGE_D_IP_BIT; 3218 3219 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 3220 hash_sets |= HCLGE_V_TAG_BIT; 3221 3222 return hash_sets; 3223 } 3224 3225 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 3226 struct ethtool_rxnfc *nfc) 3227 { 3228 struct hclge_vport *vport = hclge_get_vport(handle); 3229 struct hclge_dev *hdev = vport->back; 3230 struct hclge_rss_input_tuple_cmd *req; 3231 struct hclge_desc desc; 3232 u8 tuple_sets; 3233 int ret; 3234 3235 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 3236 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3237 return -EINVAL; 3238 3239 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 3240 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); 3241 3242 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en; 3243 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en; 3244 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en; 3245 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en; 3246 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en; 3247 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en; 3248 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en; 3249 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en; 3250 3251 tuple_sets = hclge_get_rss_hash_bits(nfc); 3252 switch (nfc->flow_type) { 3253 case TCP_V4_FLOW: 3254 req->ipv4_tcp_en = tuple_sets; 3255 break; 3256 case TCP_V6_FLOW: 3257 req->ipv6_tcp_en = tuple_sets; 3258 break; 3259 case UDP_V4_FLOW: 3260 req->ipv4_udp_en = tuple_sets; 3261 break; 3262 case UDP_V6_FLOW: 3263 req->ipv6_udp_en = tuple_sets; 3264 break; 3265 case SCTP_V4_FLOW: 3266 req->ipv4_sctp_en = tuple_sets; 3267 break; 3268 case SCTP_V6_FLOW: 3269 if ((nfc->data & RXH_L4_B_0_1) || 3270 (nfc->data & RXH_L4_B_2_3)) 3271 return -EINVAL; 3272 3273 req->ipv6_sctp_en = tuple_sets; 3274 break; 3275 case IPV4_FLOW: 3276 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3277 break; 3278 case IPV6_FLOW: 3279 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3280 break; 3281 default: 3282 return -EINVAL; 3283 } 3284 3285 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3286 if (ret) { 3287 dev_err(&hdev->pdev->dev, 3288 "Set rss tuple fail, status = %d\n", ret); 3289 return ret; 3290 } 3291 3292 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 3293 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 3294 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 3295 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 3296 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 3297 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 3298 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 3299 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 3300 return 0; 3301 } 3302 3303 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 3304 struct ethtool_rxnfc *nfc) 3305 { 3306 struct hclge_vport *vport = hclge_get_vport(handle); 3307 u8 tuple_sets; 3308 3309 nfc->data = 0; 3310 3311 switch (nfc->flow_type) { 3312 case TCP_V4_FLOW: 3313 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en; 3314 break; 3315 case UDP_V4_FLOW: 3316 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en; 3317 break; 3318 case TCP_V6_FLOW: 3319 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en; 3320 break; 3321 case UDP_V6_FLOW: 3322 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en; 3323 break; 3324 case SCTP_V4_FLOW: 3325 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en; 3326 break; 3327 case SCTP_V6_FLOW: 3328 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en; 3329 break; 3330 case IPV4_FLOW: 3331 case IPV6_FLOW: 3332 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT; 3333 break; 3334 default: 3335 return -EINVAL; 3336 } 3337 3338 if (!tuple_sets) 3339 return 0; 3340 3341 if (tuple_sets & HCLGE_D_PORT_BIT) 3342 nfc->data |= RXH_L4_B_2_3; 3343 if (tuple_sets & HCLGE_S_PORT_BIT) 3344 nfc->data |= RXH_L4_B_0_1; 3345 if (tuple_sets & HCLGE_D_IP_BIT) 3346 nfc->data |= RXH_IP_DST; 3347 if (tuple_sets & HCLGE_S_IP_BIT) 3348 nfc->data |= RXH_IP_SRC; 3349 3350 return 0; 3351 } 3352 3353 static int hclge_get_tc_size(struct hnae3_handle *handle) 3354 { 3355 struct hclge_vport *vport = hclge_get_vport(handle); 3356 struct hclge_dev *hdev = vport->back; 3357 3358 return hdev->rss_size_max; 3359 } 3360 3361 int hclge_rss_init_hw(struct hclge_dev *hdev) 3362 { 3363 struct hclge_vport *vport = hdev->vport; 3364 u8 *rss_indir = vport[0].rss_indirection_tbl; 3365 u16 rss_size = vport[0].alloc_rss_size; 3366 u8 *key = vport[0].rss_hash_key; 3367 u8 hfunc = vport[0].rss_algo; 3368 u16 tc_offset[HCLGE_MAX_TC_NUM]; 3369 u16 tc_valid[HCLGE_MAX_TC_NUM]; 3370 u16 tc_size[HCLGE_MAX_TC_NUM]; 3371 u16 roundup_size; 3372 int i, ret; 3373 3374 ret = hclge_set_rss_indir_table(hdev, rss_indir); 3375 if (ret) 3376 return ret; 3377 3378 ret = hclge_set_rss_algo_key(hdev, hfunc, key); 3379 if (ret) 3380 return ret; 3381 3382 ret = hclge_set_rss_input_tuple(hdev); 3383 if (ret) 3384 return ret; 3385 3386 /* Each TC have the same queue size, and tc_size set to hardware is 3387 * the log2 of roundup power of two of rss_size, the acutal queue 3388 * size is limited by indirection table. 3389 */ 3390 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) { 3391 dev_err(&hdev->pdev->dev, 3392 "Configure rss tc size failed, invalid TC_SIZE = %d\n", 3393 rss_size); 3394 return -EINVAL; 3395 } 3396 3397 roundup_size = roundup_pow_of_two(rss_size); 3398 roundup_size = ilog2(roundup_size); 3399 3400 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 3401 tc_valid[i] = 0; 3402 3403 if (!(hdev->hw_tc_map & BIT(i))) 3404 continue; 3405 3406 tc_valid[i] = 1; 3407 tc_size[i] = roundup_size; 3408 tc_offset[i] = rss_size * i; 3409 } 3410 3411 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 3412 } 3413 3414 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev) 3415 { 3416 struct hclge_vport *vport = hdev->vport; 3417 int i, j; 3418 3419 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) { 3420 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3421 vport[j].rss_indirection_tbl[i] = 3422 i % vport[j].alloc_rss_size; 3423 } 3424 } 3425 3426 static void hclge_rss_init_cfg(struct hclge_dev *hdev) 3427 { 3428 struct hclge_vport *vport = hdev->vport; 3429 int i; 3430 3431 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 3432 vport[i].rss_tuple_sets.ipv4_tcp_en = 3433 HCLGE_RSS_INPUT_TUPLE_OTHER; 3434 vport[i].rss_tuple_sets.ipv4_udp_en = 3435 HCLGE_RSS_INPUT_TUPLE_OTHER; 3436 vport[i].rss_tuple_sets.ipv4_sctp_en = 3437 HCLGE_RSS_INPUT_TUPLE_SCTP; 3438 vport[i].rss_tuple_sets.ipv4_fragment_en = 3439 HCLGE_RSS_INPUT_TUPLE_OTHER; 3440 vport[i].rss_tuple_sets.ipv6_tcp_en = 3441 HCLGE_RSS_INPUT_TUPLE_OTHER; 3442 vport[i].rss_tuple_sets.ipv6_udp_en = 3443 HCLGE_RSS_INPUT_TUPLE_OTHER; 3444 vport[i].rss_tuple_sets.ipv6_sctp_en = 3445 HCLGE_RSS_INPUT_TUPLE_SCTP; 3446 vport[i].rss_tuple_sets.ipv6_fragment_en = 3447 HCLGE_RSS_INPUT_TUPLE_OTHER; 3448 3449 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 3450 3451 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE); 3452 } 3453 3454 hclge_rss_indir_init_cfg(hdev); 3455 } 3456 3457 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 3458 int vector_id, bool en, 3459 struct hnae3_ring_chain_node *ring_chain) 3460 { 3461 struct hclge_dev *hdev = vport->back; 3462 struct hnae3_ring_chain_node *node; 3463 struct hclge_desc desc; 3464 struct hclge_ctrl_vector_chain_cmd *req 3465 = (struct hclge_ctrl_vector_chain_cmd *)desc.data; 3466 enum hclge_cmd_status status; 3467 enum hclge_opcode_type op; 3468 u16 tqp_type_and_id; 3469 int i; 3470 3471 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 3472 hclge_cmd_setup_basic_desc(&desc, op, false); 3473 req->int_vector_id = vector_id; 3474 3475 i = 0; 3476 for (node = ring_chain; node; node = node->next) { 3477 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 3478 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 3479 HCLGE_INT_TYPE_S, 3480 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 3481 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 3482 HCLGE_TQP_ID_S, node->tqp_index); 3483 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 3484 HCLGE_INT_GL_IDX_S, 3485 hnae3_get_field(node->int_gl_idx, 3486 HNAE3_RING_GL_IDX_M, 3487 HNAE3_RING_GL_IDX_S)); 3488 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 3489 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 3490 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 3491 req->vfid = vport->vport_id; 3492 3493 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3494 if (status) { 3495 dev_err(&hdev->pdev->dev, 3496 "Map TQP fail, status is %d.\n", 3497 status); 3498 return -EIO; 3499 } 3500 i = 0; 3501 3502 hclge_cmd_setup_basic_desc(&desc, 3503 op, 3504 false); 3505 req->int_vector_id = vector_id; 3506 } 3507 } 3508 3509 if (i > 0) { 3510 req->int_cause_num = i; 3511 req->vfid = vport->vport_id; 3512 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3513 if (status) { 3514 dev_err(&hdev->pdev->dev, 3515 "Map TQP fail, status is %d.\n", status); 3516 return -EIO; 3517 } 3518 } 3519 3520 return 0; 3521 } 3522 3523 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, 3524 int vector, 3525 struct hnae3_ring_chain_node *ring_chain) 3526 { 3527 struct hclge_vport *vport = hclge_get_vport(handle); 3528 struct hclge_dev *hdev = vport->back; 3529 int vector_id; 3530 3531 vector_id = hclge_get_vector_index(hdev, vector); 3532 if (vector_id < 0) { 3533 dev_err(&hdev->pdev->dev, 3534 "Get vector index fail. vector_id =%d\n", vector_id); 3535 return vector_id; 3536 } 3537 3538 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 3539 } 3540 3541 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, 3542 int vector, 3543 struct hnae3_ring_chain_node *ring_chain) 3544 { 3545 struct hclge_vport *vport = hclge_get_vport(handle); 3546 struct hclge_dev *hdev = vport->back; 3547 int vector_id, ret; 3548 3549 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 3550 return 0; 3551 3552 vector_id = hclge_get_vector_index(hdev, vector); 3553 if (vector_id < 0) { 3554 dev_err(&handle->pdev->dev, 3555 "Get vector index fail. ret =%d\n", vector_id); 3556 return vector_id; 3557 } 3558 3559 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 3560 if (ret) 3561 dev_err(&handle->pdev->dev, 3562 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 3563 vector_id, 3564 ret); 3565 3566 return ret; 3567 } 3568 3569 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 3570 struct hclge_promisc_param *param) 3571 { 3572 struct hclge_promisc_cfg_cmd *req; 3573 struct hclge_desc desc; 3574 int ret; 3575 3576 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 3577 3578 req = (struct hclge_promisc_cfg_cmd *)desc.data; 3579 req->vf_id = param->vf_id; 3580 3581 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on 3582 * pdev revision(0x20), new revision support them. The 3583 * value of this two fields will not return error when driver 3584 * send command to fireware in revision(0x20). 3585 */ 3586 req->flag = (param->enable << HCLGE_PROMISC_EN_B) | 3587 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B; 3588 3589 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3590 if (ret) 3591 dev_err(&hdev->pdev->dev, 3592 "Set promisc mode fail, status is %d.\n", ret); 3593 3594 return ret; 3595 } 3596 3597 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 3598 bool en_mc, bool en_bc, int vport_id) 3599 { 3600 if (!param) 3601 return; 3602 3603 memset(param, 0, sizeof(struct hclge_promisc_param)); 3604 if (en_uc) 3605 param->enable = HCLGE_PROMISC_EN_UC; 3606 if (en_mc) 3607 param->enable |= HCLGE_PROMISC_EN_MC; 3608 if (en_bc) 3609 param->enable |= HCLGE_PROMISC_EN_BC; 3610 param->vf_id = vport_id; 3611 } 3612 3613 static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 3614 bool en_mc_pmc) 3615 { 3616 struct hclge_vport *vport = hclge_get_vport(handle); 3617 struct hclge_dev *hdev = vport->back; 3618 struct hclge_promisc_param param; 3619 3620 hclge_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, true, 3621 vport->vport_id); 3622 hclge_cmd_set_promisc_mode(hdev, ¶m); 3623 } 3624 3625 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 3626 { 3627 struct hclge_desc desc; 3628 struct hclge_config_mac_mode_cmd *req = 3629 (struct hclge_config_mac_mode_cmd *)desc.data; 3630 u32 loop_en = 0; 3631 int ret; 3632 3633 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 3634 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); 3635 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); 3636 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); 3637 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); 3638 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); 3639 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); 3640 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); 3641 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); 3642 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); 3643 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); 3644 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); 3645 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); 3646 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); 3647 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); 3648 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 3649 3650 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3651 if (ret) 3652 dev_err(&hdev->pdev->dev, 3653 "mac enable fail, ret =%d.\n", ret); 3654 } 3655 3656 static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en) 3657 { 3658 struct hclge_config_mac_mode_cmd *req; 3659 struct hclge_desc desc; 3660 u32 loop_en; 3661 int ret; 3662 3663 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 3664 /* 1 Read out the MAC mode config at first */ 3665 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 3666 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3667 if (ret) { 3668 dev_err(&hdev->pdev->dev, 3669 "mac loopback get fail, ret =%d.\n", ret); 3670 return ret; 3671 } 3672 3673 /* 2 Then setup the loopback flag */ 3674 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 3675 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 3676 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0); 3677 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0); 3678 3679 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 3680 3681 /* 3 Config mac work mode with loopback flag 3682 * and its original configure parameters 3683 */ 3684 hclge_cmd_reuse_desc(&desc, false); 3685 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3686 if (ret) 3687 dev_err(&hdev->pdev->dev, 3688 "mac loopback set fail, ret =%d.\n", ret); 3689 return ret; 3690 } 3691 3692 static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en) 3693 { 3694 #define HCLGE_SERDES_RETRY_MS 10 3695 #define HCLGE_SERDES_RETRY_NUM 100 3696 struct hclge_serdes_lb_cmd *req; 3697 struct hclge_desc desc; 3698 int ret, i = 0; 3699 3700 req = (struct hclge_serdes_lb_cmd *)&desc.data[0]; 3701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false); 3702 3703 if (en) { 3704 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 3705 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 3706 } else { 3707 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 3708 } 3709 3710 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3711 if (ret) { 3712 dev_err(&hdev->pdev->dev, 3713 "serdes loopback set fail, ret = %d\n", ret); 3714 return ret; 3715 } 3716 3717 do { 3718 msleep(HCLGE_SERDES_RETRY_MS); 3719 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, 3720 true); 3721 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3722 if (ret) { 3723 dev_err(&hdev->pdev->dev, 3724 "serdes loopback get, ret = %d\n", ret); 3725 return ret; 3726 } 3727 } while (++i < HCLGE_SERDES_RETRY_NUM && 3728 !(req->result & HCLGE_CMD_SERDES_DONE_B)); 3729 3730 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) { 3731 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n"); 3732 return -EBUSY; 3733 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) { 3734 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n"); 3735 return -EIO; 3736 } 3737 3738 hclge_cfg_mac_mode(hdev, en); 3739 return 0; 3740 } 3741 3742 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, 3743 int stream_id, bool enable) 3744 { 3745 struct hclge_desc desc; 3746 struct hclge_cfg_com_tqp_queue_cmd *req = 3747 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 3748 int ret; 3749 3750 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 3751 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK); 3752 req->stream_id = cpu_to_le16(stream_id); 3753 req->enable |= enable << HCLGE_TQP_ENABLE_B; 3754 3755 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3756 if (ret) 3757 dev_err(&hdev->pdev->dev, 3758 "Tqp enable fail, status =%d.\n", ret); 3759 return ret; 3760 } 3761 3762 static int hclge_set_loopback(struct hnae3_handle *handle, 3763 enum hnae3_loop loop_mode, bool en) 3764 { 3765 struct hclge_vport *vport = hclge_get_vport(handle); 3766 struct hclge_dev *hdev = vport->back; 3767 int i, ret; 3768 3769 switch (loop_mode) { 3770 case HNAE3_MAC_INTER_LOOP_MAC: 3771 ret = hclge_set_mac_loopback(hdev, en); 3772 break; 3773 case HNAE3_MAC_INTER_LOOP_SERDES: 3774 ret = hclge_set_serdes_loopback(hdev, en); 3775 break; 3776 default: 3777 ret = -ENOTSUPP; 3778 dev_err(&hdev->pdev->dev, 3779 "loop_mode %d is not supported\n", loop_mode); 3780 break; 3781 } 3782 3783 for (i = 0; i < vport->alloc_tqps; i++) { 3784 ret = hclge_tqp_enable(hdev, i, 0, en); 3785 if (ret) 3786 return ret; 3787 } 3788 3789 return 0; 3790 } 3791 3792 static void hclge_reset_tqp_stats(struct hnae3_handle *handle) 3793 { 3794 struct hclge_vport *vport = hclge_get_vport(handle); 3795 struct hnae3_queue *queue; 3796 struct hclge_tqp *tqp; 3797 int i; 3798 3799 for (i = 0; i < vport->alloc_tqps; i++) { 3800 queue = handle->kinfo.tqp[i]; 3801 tqp = container_of(queue, struct hclge_tqp, q); 3802 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 3803 } 3804 } 3805 3806 static int hclge_ae_start(struct hnae3_handle *handle) 3807 { 3808 struct hclge_vport *vport = hclge_get_vport(handle); 3809 struct hclge_dev *hdev = vport->back; 3810 int i; 3811 3812 for (i = 0; i < vport->alloc_tqps; i++) 3813 hclge_tqp_enable(hdev, i, 0, true); 3814 3815 /* mac enable */ 3816 hclge_cfg_mac_mode(hdev, true); 3817 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 3818 mod_timer(&hdev->service_timer, jiffies + HZ); 3819 hdev->hw.mac.link = 0; 3820 3821 /* reset tqp stats */ 3822 hclge_reset_tqp_stats(handle); 3823 3824 hclge_mac_start_phy(hdev); 3825 3826 return 0; 3827 } 3828 3829 static void hclge_ae_stop(struct hnae3_handle *handle) 3830 { 3831 struct hclge_vport *vport = hclge_get_vport(handle); 3832 struct hclge_dev *hdev = vport->back; 3833 int i; 3834 3835 del_timer_sync(&hdev->service_timer); 3836 cancel_work_sync(&hdev->service_task); 3837 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); 3838 3839 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 3840 hclge_mac_stop_phy(hdev); 3841 return; 3842 } 3843 3844 for (i = 0; i < vport->alloc_tqps; i++) 3845 hclge_tqp_enable(hdev, i, 0, false); 3846 3847 /* Mac disable */ 3848 hclge_cfg_mac_mode(hdev, false); 3849 3850 hclge_mac_stop_phy(hdev); 3851 3852 /* reset tqp stats */ 3853 hclge_reset_tqp_stats(handle); 3854 del_timer_sync(&hdev->service_timer); 3855 cancel_work_sync(&hdev->service_task); 3856 hclge_update_link_status(hdev); 3857 } 3858 3859 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 3860 u16 cmdq_resp, u8 resp_code, 3861 enum hclge_mac_vlan_tbl_opcode op) 3862 { 3863 struct hclge_dev *hdev = vport->back; 3864 int return_status = -EIO; 3865 3866 if (cmdq_resp) { 3867 dev_err(&hdev->pdev->dev, 3868 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n", 3869 cmdq_resp); 3870 return -EIO; 3871 } 3872 3873 if (op == HCLGE_MAC_VLAN_ADD) { 3874 if ((!resp_code) || (resp_code == 1)) { 3875 return_status = 0; 3876 } else if (resp_code == 2) { 3877 return_status = -ENOSPC; 3878 dev_err(&hdev->pdev->dev, 3879 "add mac addr failed for uc_overflow.\n"); 3880 } else if (resp_code == 3) { 3881 return_status = -ENOSPC; 3882 dev_err(&hdev->pdev->dev, 3883 "add mac addr failed for mc_overflow.\n"); 3884 } else { 3885 dev_err(&hdev->pdev->dev, 3886 "add mac addr failed for undefined, code=%d.\n", 3887 resp_code); 3888 } 3889 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 3890 if (!resp_code) { 3891 return_status = 0; 3892 } else if (resp_code == 1) { 3893 return_status = -ENOENT; 3894 dev_dbg(&hdev->pdev->dev, 3895 "remove mac addr failed for miss.\n"); 3896 } else { 3897 dev_err(&hdev->pdev->dev, 3898 "remove mac addr failed for undefined, code=%d.\n", 3899 resp_code); 3900 } 3901 } else if (op == HCLGE_MAC_VLAN_LKUP) { 3902 if (!resp_code) { 3903 return_status = 0; 3904 } else if (resp_code == 1) { 3905 return_status = -ENOENT; 3906 dev_dbg(&hdev->pdev->dev, 3907 "lookup mac addr failed for miss.\n"); 3908 } else { 3909 dev_err(&hdev->pdev->dev, 3910 "lookup mac addr failed for undefined, code=%d.\n", 3911 resp_code); 3912 } 3913 } else { 3914 return_status = -EINVAL; 3915 dev_err(&hdev->pdev->dev, 3916 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n", 3917 op); 3918 } 3919 3920 return return_status; 3921 } 3922 3923 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 3924 { 3925 int word_num; 3926 int bit_num; 3927 3928 if (vfid > 255 || vfid < 0) 3929 return -EIO; 3930 3931 if (vfid >= 0 && vfid <= 191) { 3932 word_num = vfid / 32; 3933 bit_num = vfid % 32; 3934 if (clr) 3935 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 3936 else 3937 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 3938 } else { 3939 word_num = (vfid - 192) / 32; 3940 bit_num = vfid % 32; 3941 if (clr) 3942 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 3943 else 3944 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 3945 } 3946 3947 return 0; 3948 } 3949 3950 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 3951 { 3952 #define HCLGE_DESC_NUMBER 3 3953 #define HCLGE_FUNC_NUMBER_PER_DESC 6 3954 int i, j; 3955 3956 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 3957 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 3958 if (desc[i].data[j]) 3959 return false; 3960 3961 return true; 3962 } 3963 3964 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 3965 const u8 *addr) 3966 { 3967 const unsigned char *mac_addr = addr; 3968 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 3969 (mac_addr[0]) | (mac_addr[1] << 8); 3970 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 3971 3972 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 3973 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 3974 } 3975 3976 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport, 3977 const u8 *addr) 3978 { 3979 u16 high_val = addr[1] | (addr[0] << 8); 3980 struct hclge_dev *hdev = vport->back; 3981 u32 rsh = 4 - hdev->mta_mac_sel_type; 3982 u16 ret_val = (high_val >> rsh) & 0xfff; 3983 3984 return ret_val; 3985 } 3986 3987 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, 3988 enum hclge_mta_dmac_sel_type mta_mac_sel, 3989 bool enable) 3990 { 3991 struct hclge_mta_filter_mode_cmd *req; 3992 struct hclge_desc desc; 3993 int ret; 3994 3995 req = (struct hclge_mta_filter_mode_cmd *)desc.data; 3996 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false); 3997 3998 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B, 3999 enable); 4000 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M, 4001 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel); 4002 4003 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4004 if (ret) 4005 dev_err(&hdev->pdev->dev, 4006 "Config mat filter mode failed for cmd_send, ret =%d.\n", 4007 ret); 4008 4009 return ret; 4010 } 4011 4012 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, 4013 u8 func_id, 4014 bool enable) 4015 { 4016 struct hclge_cfg_func_mta_filter_cmd *req; 4017 struct hclge_desc desc; 4018 int ret; 4019 4020 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data; 4021 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false); 4022 4023 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B, 4024 enable); 4025 req->function_id = func_id; 4026 4027 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4028 if (ret) 4029 dev_err(&hdev->pdev->dev, 4030 "Config func_id enable failed for cmd_send, ret =%d.\n", 4031 ret); 4032 4033 return ret; 4034 } 4035 4036 static int hclge_set_mta_table_item(struct hclge_vport *vport, 4037 u16 idx, 4038 bool enable) 4039 { 4040 struct hclge_dev *hdev = vport->back; 4041 struct hclge_cfg_func_mta_item_cmd *req; 4042 struct hclge_desc desc; 4043 u16 item_idx = 0; 4044 int ret; 4045 4046 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data; 4047 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false); 4048 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable); 4049 4050 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M, 4051 HCLGE_CFG_MTA_ITEM_IDX_S, idx); 4052 req->item_idx = cpu_to_le16(item_idx); 4053 4054 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4055 if (ret) { 4056 dev_err(&hdev->pdev->dev, 4057 "Config mta table item failed for cmd_send, ret =%d.\n", 4058 ret); 4059 return ret; 4060 } 4061 4062 if (enable) 4063 set_bit(idx, vport->mta_shadow); 4064 else 4065 clear_bit(idx, vport->mta_shadow); 4066 4067 return 0; 4068 } 4069 4070 static int hclge_update_mta_status(struct hnae3_handle *handle) 4071 { 4072 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)]; 4073 struct hclge_vport *vport = hclge_get_vport(handle); 4074 struct net_device *netdev = handle->kinfo.netdev; 4075 struct netdev_hw_addr *ha; 4076 u16 tbl_idx; 4077 4078 memset(mta_status, 0, sizeof(mta_status)); 4079 4080 /* update mta_status from mc addr list */ 4081 netdev_for_each_mc_addr(ha, netdev) { 4082 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr); 4083 set_bit(tbl_idx, mta_status); 4084 } 4085 4086 return hclge_update_mta_status_common(vport, mta_status, 4087 0, HCLGE_MTA_TBL_SIZE, true); 4088 } 4089 4090 int hclge_update_mta_status_common(struct hclge_vport *vport, 4091 unsigned long *status, 4092 u16 idx, 4093 u16 count, 4094 bool update_filter) 4095 { 4096 struct hclge_dev *hdev = vport->back; 4097 u16 update_max = idx + count; 4098 u16 check_max; 4099 int ret = 0; 4100 bool used; 4101 u16 i; 4102 4103 /* setup mta check range */ 4104 if (update_filter) { 4105 i = 0; 4106 check_max = HCLGE_MTA_TBL_SIZE; 4107 } else { 4108 i = idx; 4109 check_max = update_max; 4110 } 4111 4112 used = false; 4113 /* check and update all mta item */ 4114 for (; i < check_max; i++) { 4115 /* ignore unused item */ 4116 if (!test_bit(i, vport->mta_shadow)) 4117 continue; 4118 4119 /* if i in update range then update it */ 4120 if (i >= idx && i < update_max) 4121 if (!test_bit(i - idx, status)) 4122 hclge_set_mta_table_item(vport, i, false); 4123 4124 if (!used && test_bit(i, vport->mta_shadow)) 4125 used = true; 4126 } 4127 4128 /* no longer use mta, disable it */ 4129 if (vport->accept_mta_mc && update_filter && !used) { 4130 ret = hclge_cfg_func_mta_filter(hdev, 4131 vport->vport_id, 4132 false); 4133 if (ret) 4134 dev_err(&hdev->pdev->dev, 4135 "disable func mta filter fail ret=%d\n", 4136 ret); 4137 else 4138 vport->accept_mta_mc = false; 4139 } 4140 4141 return ret; 4142 } 4143 4144 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 4145 struct hclge_mac_vlan_tbl_entry_cmd *req) 4146 { 4147 struct hclge_dev *hdev = vport->back; 4148 struct hclge_desc desc; 4149 u8 resp_code; 4150 u16 retval; 4151 int ret; 4152 4153 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 4154 4155 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4156 4157 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4158 if (ret) { 4159 dev_err(&hdev->pdev->dev, 4160 "del mac addr failed for cmd_send, ret =%d.\n", 4161 ret); 4162 return ret; 4163 } 4164 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4165 retval = le16_to_cpu(desc.retval); 4166 4167 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 4168 HCLGE_MAC_VLAN_REMOVE); 4169 } 4170 4171 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 4172 struct hclge_mac_vlan_tbl_entry_cmd *req, 4173 struct hclge_desc *desc, 4174 bool is_mc) 4175 { 4176 struct hclge_dev *hdev = vport->back; 4177 u8 resp_code; 4178 u16 retval; 4179 int ret; 4180 4181 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 4182 if (is_mc) { 4183 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4184 memcpy(desc[0].data, 4185 req, 4186 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4187 hclge_cmd_setup_basic_desc(&desc[1], 4188 HCLGE_OPC_MAC_VLAN_ADD, 4189 true); 4190 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4191 hclge_cmd_setup_basic_desc(&desc[2], 4192 HCLGE_OPC_MAC_VLAN_ADD, 4193 true); 4194 ret = hclge_cmd_send(&hdev->hw, desc, 3); 4195 } else { 4196 memcpy(desc[0].data, 4197 req, 4198 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4199 ret = hclge_cmd_send(&hdev->hw, desc, 1); 4200 } 4201 if (ret) { 4202 dev_err(&hdev->pdev->dev, 4203 "lookup mac addr failed for cmd_send, ret =%d.\n", 4204 ret); 4205 return ret; 4206 } 4207 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 4208 retval = le16_to_cpu(desc[0].retval); 4209 4210 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 4211 HCLGE_MAC_VLAN_LKUP); 4212 } 4213 4214 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 4215 struct hclge_mac_vlan_tbl_entry_cmd *req, 4216 struct hclge_desc *mc_desc) 4217 { 4218 struct hclge_dev *hdev = vport->back; 4219 int cfg_status; 4220 u8 resp_code; 4221 u16 retval; 4222 int ret; 4223 4224 if (!mc_desc) { 4225 struct hclge_desc desc; 4226 4227 hclge_cmd_setup_basic_desc(&desc, 4228 HCLGE_OPC_MAC_VLAN_ADD, 4229 false); 4230 memcpy(desc.data, req, 4231 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4232 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4233 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4234 retval = le16_to_cpu(desc.retval); 4235 4236 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 4237 resp_code, 4238 HCLGE_MAC_VLAN_ADD); 4239 } else { 4240 hclge_cmd_reuse_desc(&mc_desc[0], false); 4241 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4242 hclge_cmd_reuse_desc(&mc_desc[1], false); 4243 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4244 hclge_cmd_reuse_desc(&mc_desc[2], false); 4245 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT); 4246 memcpy(mc_desc[0].data, req, 4247 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4248 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 4249 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 4250 retval = le16_to_cpu(mc_desc[0].retval); 4251 4252 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 4253 resp_code, 4254 HCLGE_MAC_VLAN_ADD); 4255 } 4256 4257 if (ret) { 4258 dev_err(&hdev->pdev->dev, 4259 "add mac addr failed for cmd_send, ret =%d.\n", 4260 ret); 4261 return ret; 4262 } 4263 4264 return cfg_status; 4265 } 4266 4267 static int hclge_add_uc_addr(struct hnae3_handle *handle, 4268 const unsigned char *addr) 4269 { 4270 struct hclge_vport *vport = hclge_get_vport(handle); 4271 4272 return hclge_add_uc_addr_common(vport, addr); 4273 } 4274 4275 int hclge_add_uc_addr_common(struct hclge_vport *vport, 4276 const unsigned char *addr) 4277 { 4278 struct hclge_dev *hdev = vport->back; 4279 struct hclge_mac_vlan_tbl_entry_cmd req; 4280 struct hclge_desc desc; 4281 u16 egress_port = 0; 4282 int ret; 4283 4284 /* mac addr check */ 4285 if (is_zero_ether_addr(addr) || 4286 is_broadcast_ether_addr(addr) || 4287 is_multicast_ether_addr(addr)) { 4288 dev_err(&hdev->pdev->dev, 4289 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n", 4290 addr, 4291 is_zero_ether_addr(addr), 4292 is_broadcast_ether_addr(addr), 4293 is_multicast_ether_addr(addr)); 4294 return -EINVAL; 4295 } 4296 4297 memset(&req, 0, sizeof(req)); 4298 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4299 4300 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 4301 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 4302 4303 req.egress_port = cpu_to_le16(egress_port); 4304 4305 hclge_prepare_mac_addr(&req, addr); 4306 4307 /* Lookup the mac address in the mac_vlan table, and add 4308 * it if the entry is inexistent. Repeated unicast entry 4309 * is not allowed in the mac vlan table. 4310 */ 4311 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 4312 if (ret == -ENOENT) 4313 return hclge_add_mac_vlan_tbl(vport, &req, NULL); 4314 4315 /* check if we just hit the duplicate */ 4316 if (!ret) 4317 ret = -EINVAL; 4318 4319 dev_err(&hdev->pdev->dev, 4320 "PF failed to add unicast entry(%pM) in the MAC table\n", 4321 addr); 4322 4323 return ret; 4324 } 4325 4326 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 4327 const unsigned char *addr) 4328 { 4329 struct hclge_vport *vport = hclge_get_vport(handle); 4330 4331 return hclge_rm_uc_addr_common(vport, addr); 4332 } 4333 4334 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 4335 const unsigned char *addr) 4336 { 4337 struct hclge_dev *hdev = vport->back; 4338 struct hclge_mac_vlan_tbl_entry_cmd req; 4339 int ret; 4340 4341 /* mac addr check */ 4342 if (is_zero_ether_addr(addr) || 4343 is_broadcast_ether_addr(addr) || 4344 is_multicast_ether_addr(addr)) { 4345 dev_dbg(&hdev->pdev->dev, 4346 "Remove mac err! invalid mac:%pM.\n", 4347 addr); 4348 return -EINVAL; 4349 } 4350 4351 memset(&req, 0, sizeof(req)); 4352 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4353 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4354 hclge_prepare_mac_addr(&req, addr); 4355 ret = hclge_remove_mac_vlan_tbl(vport, &req); 4356 4357 return ret; 4358 } 4359 4360 static int hclge_add_mc_addr(struct hnae3_handle *handle, 4361 const unsigned char *addr) 4362 { 4363 struct hclge_vport *vport = hclge_get_vport(handle); 4364 4365 return hclge_add_mc_addr_common(vport, addr); 4366 } 4367 4368 int hclge_add_mc_addr_common(struct hclge_vport *vport, 4369 const unsigned char *addr) 4370 { 4371 struct hclge_dev *hdev = vport->back; 4372 struct hclge_mac_vlan_tbl_entry_cmd req; 4373 struct hclge_desc desc[3]; 4374 u16 tbl_idx; 4375 int status; 4376 4377 /* mac addr check */ 4378 if (!is_multicast_ether_addr(addr)) { 4379 dev_err(&hdev->pdev->dev, 4380 "Add mc mac err! invalid mac:%pM.\n", 4381 addr); 4382 return -EINVAL; 4383 } 4384 memset(&req, 0, sizeof(req)); 4385 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4386 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4387 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 4388 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4389 hclge_prepare_mac_addr(&req, addr); 4390 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 4391 if (!status) { 4392 /* This mac addr exist, update VFID for it */ 4393 hclge_update_desc_vfid(desc, vport->vport_id, false); 4394 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4395 } else { 4396 /* This mac addr do not exist, add new entry for it */ 4397 memset(desc[0].data, 0, sizeof(desc[0].data)); 4398 memset(desc[1].data, 0, sizeof(desc[0].data)); 4399 memset(desc[2].data, 0, sizeof(desc[0].data)); 4400 hclge_update_desc_vfid(desc, vport->vport_id, false); 4401 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4402 } 4403 4404 /* If mc mac vlan table is full, use MTA table */ 4405 if (status == -ENOSPC) { 4406 if (!vport->accept_mta_mc) { 4407 status = hclge_cfg_func_mta_filter(hdev, 4408 vport->vport_id, 4409 true); 4410 if (status) { 4411 dev_err(&hdev->pdev->dev, 4412 "set mta filter mode fail ret=%d\n", 4413 status); 4414 return status; 4415 } 4416 vport->accept_mta_mc = true; 4417 } 4418 4419 /* Set MTA table for this MAC address */ 4420 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); 4421 status = hclge_set_mta_table_item(vport, tbl_idx, true); 4422 } 4423 4424 return status; 4425 } 4426 4427 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 4428 const unsigned char *addr) 4429 { 4430 struct hclge_vport *vport = hclge_get_vport(handle); 4431 4432 return hclge_rm_mc_addr_common(vport, addr); 4433 } 4434 4435 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 4436 const unsigned char *addr) 4437 { 4438 struct hclge_dev *hdev = vport->back; 4439 struct hclge_mac_vlan_tbl_entry_cmd req; 4440 enum hclge_cmd_status status; 4441 struct hclge_desc desc[3]; 4442 4443 /* mac addr check */ 4444 if (!is_multicast_ether_addr(addr)) { 4445 dev_dbg(&hdev->pdev->dev, 4446 "Remove mc mac err! invalid mac:%pM.\n", 4447 addr); 4448 return -EINVAL; 4449 } 4450 4451 memset(&req, 0, sizeof(req)); 4452 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4453 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4454 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 4455 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4456 hclge_prepare_mac_addr(&req, addr); 4457 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 4458 if (!status) { 4459 /* This mac addr exist, remove this handle's VFID for it */ 4460 hclge_update_desc_vfid(desc, vport->vport_id, true); 4461 4462 if (hclge_is_all_function_id_zero(desc)) 4463 /* All the vfid is zero, so need to delete this entry */ 4464 status = hclge_remove_mac_vlan_tbl(vport, &req); 4465 else 4466 /* Not all the vfid is zero, update the vfid */ 4467 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4468 4469 } else { 4470 /* Maybe this mac address is in mta table, but it cannot be 4471 * deleted here because an entry of mta represents an address 4472 * range rather than a specific address. the delete action to 4473 * all entries will take effect in update_mta_status called by 4474 * hns3_nic_set_rx_mode. 4475 */ 4476 status = 0; 4477 } 4478 4479 return status; 4480 } 4481 4482 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 4483 u16 cmdq_resp, u8 resp_code) 4484 { 4485 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 4486 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 4487 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 4488 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 4489 4490 int return_status; 4491 4492 if (cmdq_resp) { 4493 dev_err(&hdev->pdev->dev, 4494 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 4495 cmdq_resp); 4496 return -EIO; 4497 } 4498 4499 switch (resp_code) { 4500 case HCLGE_ETHERTYPE_SUCCESS_ADD: 4501 case HCLGE_ETHERTYPE_ALREADY_ADD: 4502 return_status = 0; 4503 break; 4504 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 4505 dev_err(&hdev->pdev->dev, 4506 "add mac ethertype failed for manager table overflow.\n"); 4507 return_status = -EIO; 4508 break; 4509 case HCLGE_ETHERTYPE_KEY_CONFLICT: 4510 dev_err(&hdev->pdev->dev, 4511 "add mac ethertype failed for key conflict.\n"); 4512 return_status = -EIO; 4513 break; 4514 default: 4515 dev_err(&hdev->pdev->dev, 4516 "add mac ethertype failed for undefined, code=%d.\n", 4517 resp_code); 4518 return_status = -EIO; 4519 } 4520 4521 return return_status; 4522 } 4523 4524 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 4525 const struct hclge_mac_mgr_tbl_entry_cmd *req) 4526 { 4527 struct hclge_desc desc; 4528 u8 resp_code; 4529 u16 retval; 4530 int ret; 4531 4532 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 4533 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 4534 4535 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4536 if (ret) { 4537 dev_err(&hdev->pdev->dev, 4538 "add mac ethertype failed for cmd_send, ret =%d.\n", 4539 ret); 4540 return ret; 4541 } 4542 4543 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4544 retval = le16_to_cpu(desc.retval); 4545 4546 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 4547 } 4548 4549 static int init_mgr_tbl(struct hclge_dev *hdev) 4550 { 4551 int ret; 4552 int i; 4553 4554 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 4555 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 4556 if (ret) { 4557 dev_err(&hdev->pdev->dev, 4558 "add mac ethertype failed, ret =%d.\n", 4559 ret); 4560 return ret; 4561 } 4562 } 4563 4564 return 0; 4565 } 4566 4567 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 4568 { 4569 struct hclge_vport *vport = hclge_get_vport(handle); 4570 struct hclge_dev *hdev = vport->back; 4571 4572 ether_addr_copy(p, hdev->hw.mac.mac_addr); 4573 } 4574 4575 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p, 4576 bool is_first) 4577 { 4578 const unsigned char *new_addr = (const unsigned char *)p; 4579 struct hclge_vport *vport = hclge_get_vport(handle); 4580 struct hclge_dev *hdev = vport->back; 4581 int ret; 4582 4583 /* mac addr check */ 4584 if (is_zero_ether_addr(new_addr) || 4585 is_broadcast_ether_addr(new_addr) || 4586 is_multicast_ether_addr(new_addr)) { 4587 dev_err(&hdev->pdev->dev, 4588 "Change uc mac err! invalid mac:%p.\n", 4589 new_addr); 4590 return -EINVAL; 4591 } 4592 4593 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr)) 4594 dev_warn(&hdev->pdev->dev, 4595 "remove old uc mac address fail.\n"); 4596 4597 ret = hclge_add_uc_addr(handle, new_addr); 4598 if (ret) { 4599 dev_err(&hdev->pdev->dev, 4600 "add uc mac address fail, ret =%d.\n", 4601 ret); 4602 4603 if (!is_first && 4604 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr)) 4605 dev_err(&hdev->pdev->dev, 4606 "restore uc mac address fail.\n"); 4607 4608 return -EIO; 4609 } 4610 4611 ret = hclge_pause_addr_cfg(hdev, new_addr); 4612 if (ret) { 4613 dev_err(&hdev->pdev->dev, 4614 "configure mac pause address fail, ret =%d.\n", 4615 ret); 4616 return -EIO; 4617 } 4618 4619 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 4620 4621 return 0; 4622 } 4623 4624 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 4625 bool filter_en) 4626 { 4627 struct hclge_vlan_filter_ctrl_cmd *req; 4628 struct hclge_desc desc; 4629 int ret; 4630 4631 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false); 4632 4633 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 4634 req->vlan_type = vlan_type; 4635 req->vlan_fe = filter_en; 4636 4637 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4638 if (ret) 4639 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", 4640 ret); 4641 4642 return ret; 4643 } 4644 4645 #define HCLGE_FILTER_TYPE_VF 0 4646 #define HCLGE_FILTER_TYPE_PORT 1 4647 4648 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 4649 { 4650 struct hclge_vport *vport = hclge_get_vport(handle); 4651 struct hclge_dev *hdev = vport->back; 4652 4653 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable); 4654 } 4655 4656 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, 4657 bool is_kill, u16 vlan, u8 qos, 4658 __be16 proto) 4659 { 4660 #define HCLGE_MAX_VF_BYTES 16 4661 struct hclge_vlan_filter_vf_cfg_cmd *req0; 4662 struct hclge_vlan_filter_vf_cfg_cmd *req1; 4663 struct hclge_desc desc[2]; 4664 u8 vf_byte_val; 4665 u8 vf_byte_off; 4666 int ret; 4667 4668 hclge_cmd_setup_basic_desc(&desc[0], 4669 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 4670 hclge_cmd_setup_basic_desc(&desc[1], 4671 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 4672 4673 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4674 4675 vf_byte_off = vfid / 8; 4676 vf_byte_val = 1 << (vfid % 8); 4677 4678 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 4679 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 4680 4681 req0->vlan_id = cpu_to_le16(vlan); 4682 req0->vlan_cfg = is_kill; 4683 4684 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 4685 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 4686 else 4687 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 4688 4689 ret = hclge_cmd_send(&hdev->hw, desc, 2); 4690 if (ret) { 4691 dev_err(&hdev->pdev->dev, 4692 "Send vf vlan command fail, ret =%d.\n", 4693 ret); 4694 return ret; 4695 } 4696 4697 if (!is_kill) { 4698 #define HCLGE_VF_VLAN_NO_ENTRY 2 4699 if (!req0->resp_code || req0->resp_code == 1) 4700 return 0; 4701 4702 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 4703 dev_warn(&hdev->pdev->dev, 4704 "vf vlan table is full, vf vlan filter is disabled\n"); 4705 return 0; 4706 } 4707 4708 dev_err(&hdev->pdev->dev, 4709 "Add vf vlan filter fail, ret =%d.\n", 4710 req0->resp_code); 4711 } else { 4712 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 4713 if (!req0->resp_code) 4714 return 0; 4715 4716 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) { 4717 dev_warn(&hdev->pdev->dev, 4718 "vlan %d filter is not in vf vlan table\n", 4719 vlan); 4720 return 0; 4721 } 4722 4723 dev_err(&hdev->pdev->dev, 4724 "Kill vf vlan filter fail, ret =%d.\n", 4725 req0->resp_code); 4726 } 4727 4728 return -EIO; 4729 } 4730 4731 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 4732 u16 vlan_id, bool is_kill) 4733 { 4734 struct hclge_vlan_filter_pf_cfg_cmd *req; 4735 struct hclge_desc desc; 4736 u8 vlan_offset_byte_val; 4737 u8 vlan_offset_byte; 4738 u8 vlan_offset_160; 4739 int ret; 4740 4741 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 4742 4743 vlan_offset_160 = vlan_id / 160; 4744 vlan_offset_byte = (vlan_id % 160) / 8; 4745 vlan_offset_byte_val = 1 << (vlan_id % 8); 4746 4747 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 4748 req->vlan_offset = vlan_offset_160; 4749 req->vlan_cfg = is_kill; 4750 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 4751 4752 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4753 if (ret) 4754 dev_err(&hdev->pdev->dev, 4755 "port vlan command, send fail, ret =%d.\n", ret); 4756 return ret; 4757 } 4758 4759 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 4760 u16 vport_id, u16 vlan_id, u8 qos, 4761 bool is_kill) 4762 { 4763 u16 vport_idx, vport_num = 0; 4764 int ret; 4765 4766 if (is_kill && !vlan_id) 4767 return 0; 4768 4769 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id, 4770 0, proto); 4771 if (ret) { 4772 dev_err(&hdev->pdev->dev, 4773 "Set %d vport vlan filter config fail, ret =%d.\n", 4774 vport_id, ret); 4775 return ret; 4776 } 4777 4778 /* vlan 0 may be added twice when 8021q module is enabled */ 4779 if (!is_kill && !vlan_id && 4780 test_bit(vport_id, hdev->vlan_table[vlan_id])) 4781 return 0; 4782 4783 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 4784 dev_err(&hdev->pdev->dev, 4785 "Add port vlan failed, vport %d is already in vlan %d\n", 4786 vport_id, vlan_id); 4787 return -EINVAL; 4788 } 4789 4790 if (is_kill && 4791 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 4792 dev_err(&hdev->pdev->dev, 4793 "Delete port vlan failed, vport %d is not in vlan %d\n", 4794 vport_id, vlan_id); 4795 return -EINVAL; 4796 } 4797 4798 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 4799 vport_num++; 4800 4801 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 4802 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 4803 is_kill); 4804 4805 return ret; 4806 } 4807 4808 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 4809 u16 vlan_id, bool is_kill) 4810 { 4811 struct hclge_vport *vport = hclge_get_vport(handle); 4812 struct hclge_dev *hdev = vport->back; 4813 4814 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id, 4815 0, is_kill); 4816 } 4817 4818 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 4819 u16 vlan, u8 qos, __be16 proto) 4820 { 4821 struct hclge_vport *vport = hclge_get_vport(handle); 4822 struct hclge_dev *hdev = vport->back; 4823 4824 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7)) 4825 return -EINVAL; 4826 if (proto != htons(ETH_P_8021Q)) 4827 return -EPROTONOSUPPORT; 4828 4829 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false); 4830 } 4831 4832 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 4833 { 4834 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 4835 struct hclge_vport_vtag_tx_cfg_cmd *req; 4836 struct hclge_dev *hdev = vport->back; 4837 struct hclge_desc desc; 4838 int status; 4839 4840 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 4841 4842 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 4843 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 4844 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 4845 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 4846 vcfg->accept_tag1 ? 1 : 0); 4847 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 4848 vcfg->accept_untag1 ? 1 : 0); 4849 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 4850 vcfg->accept_tag2 ? 1 : 0); 4851 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 4852 vcfg->accept_untag2 ? 1 : 0); 4853 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 4854 vcfg->insert_tag1_en ? 1 : 0); 4855 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 4856 vcfg->insert_tag2_en ? 1 : 0); 4857 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 4858 4859 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 4860 req->vf_bitmap[req->vf_offset] = 4861 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 4862 4863 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4864 if (status) 4865 dev_err(&hdev->pdev->dev, 4866 "Send port txvlan cfg command fail, ret =%d\n", 4867 status); 4868 4869 return status; 4870 } 4871 4872 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 4873 { 4874 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 4875 struct hclge_vport_vtag_rx_cfg_cmd *req; 4876 struct hclge_dev *hdev = vport->back; 4877 struct hclge_desc desc; 4878 int status; 4879 4880 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 4881 4882 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 4883 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 4884 vcfg->strip_tag1_en ? 1 : 0); 4885 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 4886 vcfg->strip_tag2_en ? 1 : 0); 4887 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 4888 vcfg->vlan1_vlan_prionly ? 1 : 0); 4889 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 4890 vcfg->vlan2_vlan_prionly ? 1 : 0); 4891 4892 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 4893 req->vf_bitmap[req->vf_offset] = 4894 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 4895 4896 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4897 if (status) 4898 dev_err(&hdev->pdev->dev, 4899 "Send port rxvlan cfg command fail, ret =%d\n", 4900 status); 4901 4902 return status; 4903 } 4904 4905 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 4906 { 4907 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 4908 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 4909 struct hclge_desc desc; 4910 int status; 4911 4912 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 4913 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 4914 rx_req->ot_fst_vlan_type = 4915 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 4916 rx_req->ot_sec_vlan_type = 4917 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 4918 rx_req->in_fst_vlan_type = 4919 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 4920 rx_req->in_sec_vlan_type = 4921 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 4922 4923 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4924 if (status) { 4925 dev_err(&hdev->pdev->dev, 4926 "Send rxvlan protocol type command fail, ret =%d\n", 4927 status); 4928 return status; 4929 } 4930 4931 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 4932 4933 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data; 4934 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 4935 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 4936 4937 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4938 if (status) 4939 dev_err(&hdev->pdev->dev, 4940 "Send txvlan protocol type command fail, ret =%d\n", 4941 status); 4942 4943 return status; 4944 } 4945 4946 static int hclge_init_vlan_config(struct hclge_dev *hdev) 4947 { 4948 #define HCLGE_DEF_VLAN_TYPE 0x8100 4949 4950 struct hnae3_handle *handle; 4951 struct hclge_vport *vport; 4952 int ret; 4953 int i; 4954 4955 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true); 4956 if (ret) 4957 return ret; 4958 4959 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true); 4960 if (ret) 4961 return ret; 4962 4963 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 4964 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 4965 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 4966 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 4967 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE; 4968 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE; 4969 4970 ret = hclge_set_vlan_protocol_type(hdev); 4971 if (ret) 4972 return ret; 4973 4974 for (i = 0; i < hdev->num_alloc_vport; i++) { 4975 vport = &hdev->vport[i]; 4976 vport->txvlan_cfg.accept_tag1 = true; 4977 vport->txvlan_cfg.accept_untag1 = true; 4978 4979 /* accept_tag2 and accept_untag2 are not supported on 4980 * pdev revision(0x20), new revision support them. The 4981 * value of this two fields will not return error when driver 4982 * send command to fireware in revision(0x20). 4983 * This two fields can not configured by user. 4984 */ 4985 vport->txvlan_cfg.accept_tag2 = true; 4986 vport->txvlan_cfg.accept_untag2 = true; 4987 4988 vport->txvlan_cfg.insert_tag1_en = false; 4989 vport->txvlan_cfg.insert_tag2_en = false; 4990 vport->txvlan_cfg.default_tag1 = 0; 4991 vport->txvlan_cfg.default_tag2 = 0; 4992 4993 ret = hclge_set_vlan_tx_offload_cfg(vport); 4994 if (ret) 4995 return ret; 4996 4997 vport->rxvlan_cfg.strip_tag1_en = false; 4998 vport->rxvlan_cfg.strip_tag2_en = true; 4999 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 5000 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 5001 5002 ret = hclge_set_vlan_rx_offload_cfg(vport); 5003 if (ret) 5004 return ret; 5005 } 5006 5007 handle = &hdev->vport[0].nic; 5008 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 5009 } 5010 5011 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 5012 { 5013 struct hclge_vport *vport = hclge_get_vport(handle); 5014 5015 vport->rxvlan_cfg.strip_tag1_en = false; 5016 vport->rxvlan_cfg.strip_tag2_en = enable; 5017 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 5018 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 5019 5020 return hclge_set_vlan_rx_offload_cfg(vport); 5021 } 5022 5023 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu) 5024 { 5025 struct hclge_config_max_frm_size_cmd *req; 5026 struct hclge_desc desc; 5027 int max_frm_size; 5028 int ret; 5029 5030 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5031 5032 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 5033 max_frm_size > HCLGE_MAC_MAX_FRAME) 5034 return -EINVAL; 5035 5036 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 5037 5038 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 5039 5040 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 5041 req->max_frm_size = cpu_to_le16(max_frm_size); 5042 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 5043 5044 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5045 if (ret) 5046 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); 5047 else 5048 hdev->mps = max_frm_size; 5049 5050 return ret; 5051 } 5052 5053 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 5054 { 5055 struct hclge_vport *vport = hclge_get_vport(handle); 5056 struct hclge_dev *hdev = vport->back; 5057 int ret; 5058 5059 ret = hclge_set_mac_mtu(hdev, new_mtu); 5060 if (ret) { 5061 dev_err(&hdev->pdev->dev, 5062 "Change mtu fail, ret =%d\n", ret); 5063 return ret; 5064 } 5065 5066 ret = hclge_buffer_alloc(hdev); 5067 if (ret) 5068 dev_err(&hdev->pdev->dev, 5069 "Allocate buffer fail, ret =%d\n", ret); 5070 5071 return ret; 5072 } 5073 5074 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id, 5075 bool enable) 5076 { 5077 struct hclge_reset_tqp_queue_cmd *req; 5078 struct hclge_desc desc; 5079 int ret; 5080 5081 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 5082 5083 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 5084 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 5085 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); 5086 5087 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5088 if (ret) { 5089 dev_err(&hdev->pdev->dev, 5090 "Send tqp reset cmd error, status =%d\n", ret); 5091 return ret; 5092 } 5093 5094 return 0; 5095 } 5096 5097 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id) 5098 { 5099 struct hclge_reset_tqp_queue_cmd *req; 5100 struct hclge_desc desc; 5101 int ret; 5102 5103 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 5104 5105 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 5106 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 5107 5108 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5109 if (ret) { 5110 dev_err(&hdev->pdev->dev, 5111 "Get reset status error, status =%d\n", ret); 5112 return ret; 5113 } 5114 5115 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 5116 } 5117 5118 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, 5119 u16 queue_id) 5120 { 5121 struct hnae3_queue *queue; 5122 struct hclge_tqp *tqp; 5123 5124 queue = handle->kinfo.tqp[queue_id]; 5125 tqp = container_of(queue, struct hclge_tqp, q); 5126 5127 return tqp->index; 5128 } 5129 5130 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 5131 { 5132 struct hclge_vport *vport = hclge_get_vport(handle); 5133 struct hclge_dev *hdev = vport->back; 5134 int reset_try_times = 0; 5135 int reset_status; 5136 u16 queue_gid; 5137 int ret; 5138 5139 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5140 return; 5141 5142 queue_gid = hclge_covert_handle_qid_global(handle, queue_id); 5143 5144 ret = hclge_tqp_enable(hdev, queue_id, 0, false); 5145 if (ret) { 5146 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); 5147 return; 5148 } 5149 5150 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); 5151 if (ret) { 5152 dev_warn(&hdev->pdev->dev, 5153 "Send reset tqp cmd fail, ret = %d\n", ret); 5154 return; 5155 } 5156 5157 reset_try_times = 0; 5158 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 5159 /* Wait for tqp hw reset */ 5160 msleep(20); 5161 reset_status = hclge_get_reset_status(hdev, queue_gid); 5162 if (reset_status) 5163 break; 5164 } 5165 5166 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 5167 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); 5168 return; 5169 } 5170 5171 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); 5172 if (ret) { 5173 dev_warn(&hdev->pdev->dev, 5174 "Deassert the soft reset fail, ret = %d\n", ret); 5175 return; 5176 } 5177 } 5178 5179 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id) 5180 { 5181 struct hclge_dev *hdev = vport->back; 5182 int reset_try_times = 0; 5183 int reset_status; 5184 u16 queue_gid; 5185 int ret; 5186 5187 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id); 5188 5189 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); 5190 if (ret) { 5191 dev_warn(&hdev->pdev->dev, 5192 "Send reset tqp cmd fail, ret = %d\n", ret); 5193 return; 5194 } 5195 5196 reset_try_times = 0; 5197 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 5198 /* Wait for tqp hw reset */ 5199 msleep(20); 5200 reset_status = hclge_get_reset_status(hdev, queue_gid); 5201 if (reset_status) 5202 break; 5203 } 5204 5205 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 5206 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); 5207 return; 5208 } 5209 5210 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); 5211 if (ret) 5212 dev_warn(&hdev->pdev->dev, 5213 "Deassert the soft reset fail, ret = %d\n", ret); 5214 } 5215 5216 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 5217 { 5218 struct hclge_vport *vport = hclge_get_vport(handle); 5219 struct hclge_dev *hdev = vport->back; 5220 5221 return hdev->fw_version; 5222 } 5223 5224 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 5225 { 5226 struct phy_device *phydev = hdev->hw.mac.phydev; 5227 5228 if (!phydev) 5229 return; 5230 5231 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); 5232 5233 if (rx_en) 5234 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 5235 5236 if (tx_en) 5237 phydev->advertising ^= ADVERTISED_Asym_Pause; 5238 } 5239 5240 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 5241 { 5242 int ret; 5243 5244 if (rx_en && tx_en) 5245 hdev->fc_mode_last_time = HCLGE_FC_FULL; 5246 else if (rx_en && !tx_en) 5247 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 5248 else if (!rx_en && tx_en) 5249 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 5250 else 5251 hdev->fc_mode_last_time = HCLGE_FC_NONE; 5252 5253 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 5254 return 0; 5255 5256 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 5257 if (ret) { 5258 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n", 5259 ret); 5260 return ret; 5261 } 5262 5263 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 5264 5265 return 0; 5266 } 5267 5268 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 5269 { 5270 struct phy_device *phydev = hdev->hw.mac.phydev; 5271 u16 remote_advertising = 0; 5272 u16 local_advertising = 0; 5273 u32 rx_pause, tx_pause; 5274 u8 flowctl; 5275 5276 if (!phydev->link || !phydev->autoneg) 5277 return 0; 5278 5279 if (phydev->advertising & ADVERTISED_Pause) 5280 local_advertising = ADVERTISE_PAUSE_CAP; 5281 5282 if (phydev->advertising & ADVERTISED_Asym_Pause) 5283 local_advertising |= ADVERTISE_PAUSE_ASYM; 5284 5285 if (phydev->pause) 5286 remote_advertising = LPA_PAUSE_CAP; 5287 5288 if (phydev->asym_pause) 5289 remote_advertising |= LPA_PAUSE_ASYM; 5290 5291 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 5292 remote_advertising); 5293 tx_pause = flowctl & FLOW_CTRL_TX; 5294 rx_pause = flowctl & FLOW_CTRL_RX; 5295 5296 if (phydev->duplex == HCLGE_MAC_HALF) { 5297 tx_pause = 0; 5298 rx_pause = 0; 5299 } 5300 5301 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 5302 } 5303 5304 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 5305 u32 *rx_en, u32 *tx_en) 5306 { 5307 struct hclge_vport *vport = hclge_get_vport(handle); 5308 struct hclge_dev *hdev = vport->back; 5309 5310 *auto_neg = hclge_get_autoneg(handle); 5311 5312 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 5313 *rx_en = 0; 5314 *tx_en = 0; 5315 return; 5316 } 5317 5318 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 5319 *rx_en = 1; 5320 *tx_en = 0; 5321 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 5322 *tx_en = 1; 5323 *rx_en = 0; 5324 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 5325 *rx_en = 1; 5326 *tx_en = 1; 5327 } else { 5328 *rx_en = 0; 5329 *tx_en = 0; 5330 } 5331 } 5332 5333 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 5334 u32 rx_en, u32 tx_en) 5335 { 5336 struct hclge_vport *vport = hclge_get_vport(handle); 5337 struct hclge_dev *hdev = vport->back; 5338 struct phy_device *phydev = hdev->hw.mac.phydev; 5339 u32 fc_autoneg; 5340 5341 fc_autoneg = hclge_get_autoneg(handle); 5342 if (auto_neg != fc_autoneg) { 5343 dev_info(&hdev->pdev->dev, 5344 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 5345 return -EOPNOTSUPP; 5346 } 5347 5348 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 5349 dev_info(&hdev->pdev->dev, 5350 "Priority flow control enabled. Cannot set link flow control.\n"); 5351 return -EOPNOTSUPP; 5352 } 5353 5354 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 5355 5356 if (!fc_autoneg) 5357 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 5358 5359 /* Only support flow control negotiation for netdev with 5360 * phy attached for now. 5361 */ 5362 if (!phydev) 5363 return -EOPNOTSUPP; 5364 5365 return phy_start_aneg(phydev); 5366 } 5367 5368 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 5369 u8 *auto_neg, u32 *speed, u8 *duplex) 5370 { 5371 struct hclge_vport *vport = hclge_get_vport(handle); 5372 struct hclge_dev *hdev = vport->back; 5373 5374 if (speed) 5375 *speed = hdev->hw.mac.speed; 5376 if (duplex) 5377 *duplex = hdev->hw.mac.duplex; 5378 if (auto_neg) 5379 *auto_neg = hdev->hw.mac.autoneg; 5380 } 5381 5382 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type) 5383 { 5384 struct hclge_vport *vport = hclge_get_vport(handle); 5385 struct hclge_dev *hdev = vport->back; 5386 5387 if (media_type) 5388 *media_type = hdev->hw.mac.media_type; 5389 } 5390 5391 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 5392 u8 *tp_mdix_ctrl, u8 *tp_mdix) 5393 { 5394 struct hclge_vport *vport = hclge_get_vport(handle); 5395 struct hclge_dev *hdev = vport->back; 5396 struct phy_device *phydev = hdev->hw.mac.phydev; 5397 int mdix_ctrl, mdix, retval, is_resolved; 5398 5399 if (!phydev) { 5400 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 5401 *tp_mdix = ETH_TP_MDI_INVALID; 5402 return; 5403 } 5404 5405 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 5406 5407 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 5408 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 5409 HCLGE_PHY_MDIX_CTRL_S); 5410 5411 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 5412 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 5413 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 5414 5415 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 5416 5417 switch (mdix_ctrl) { 5418 case 0x0: 5419 *tp_mdix_ctrl = ETH_TP_MDI; 5420 break; 5421 case 0x1: 5422 *tp_mdix_ctrl = ETH_TP_MDI_X; 5423 break; 5424 case 0x3: 5425 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 5426 break; 5427 default: 5428 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 5429 break; 5430 } 5431 5432 if (!is_resolved) 5433 *tp_mdix = ETH_TP_MDI_INVALID; 5434 else if (mdix) 5435 *tp_mdix = ETH_TP_MDI_X; 5436 else 5437 *tp_mdix = ETH_TP_MDI; 5438 } 5439 5440 static int hclge_init_instance_hw(struct hclge_dev *hdev) 5441 { 5442 return hclge_mac_connect_phy(hdev); 5443 } 5444 5445 static void hclge_uninit_instance_hw(struct hclge_dev *hdev) 5446 { 5447 hclge_mac_disconnect_phy(hdev); 5448 } 5449 5450 static int hclge_init_client_instance(struct hnae3_client *client, 5451 struct hnae3_ae_dev *ae_dev) 5452 { 5453 struct hclge_dev *hdev = ae_dev->priv; 5454 struct hclge_vport *vport; 5455 int i, ret; 5456 5457 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 5458 vport = &hdev->vport[i]; 5459 5460 switch (client->type) { 5461 case HNAE3_CLIENT_KNIC: 5462 5463 hdev->nic_client = client; 5464 vport->nic.client = client; 5465 ret = client->ops->init_instance(&vport->nic); 5466 if (ret) 5467 return ret; 5468 5469 ret = hclge_init_instance_hw(hdev); 5470 if (ret) { 5471 client->ops->uninit_instance(&vport->nic, 5472 0); 5473 return ret; 5474 } 5475 5476 if (hdev->roce_client && 5477 hnae3_dev_roce_supported(hdev)) { 5478 struct hnae3_client *rc = hdev->roce_client; 5479 5480 ret = hclge_init_roce_base_info(vport); 5481 if (ret) 5482 return ret; 5483 5484 ret = rc->ops->init_instance(&vport->roce); 5485 if (ret) 5486 return ret; 5487 } 5488 5489 break; 5490 case HNAE3_CLIENT_UNIC: 5491 hdev->nic_client = client; 5492 vport->nic.client = client; 5493 5494 ret = client->ops->init_instance(&vport->nic); 5495 if (ret) 5496 return ret; 5497 5498 break; 5499 case HNAE3_CLIENT_ROCE: 5500 if (hnae3_dev_roce_supported(hdev)) { 5501 hdev->roce_client = client; 5502 vport->roce.client = client; 5503 } 5504 5505 if (hdev->roce_client && hdev->nic_client) { 5506 ret = hclge_init_roce_base_info(vport); 5507 if (ret) 5508 return ret; 5509 5510 ret = client->ops->init_instance(&vport->roce); 5511 if (ret) 5512 return ret; 5513 } 5514 } 5515 } 5516 5517 return 0; 5518 } 5519 5520 static void hclge_uninit_client_instance(struct hnae3_client *client, 5521 struct hnae3_ae_dev *ae_dev) 5522 { 5523 struct hclge_dev *hdev = ae_dev->priv; 5524 struct hclge_vport *vport; 5525 int i; 5526 5527 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 5528 vport = &hdev->vport[i]; 5529 if (hdev->roce_client) { 5530 hdev->roce_client->ops->uninit_instance(&vport->roce, 5531 0); 5532 hdev->roce_client = NULL; 5533 vport->roce.client = NULL; 5534 } 5535 if (client->type == HNAE3_CLIENT_ROCE) 5536 return; 5537 if (client->ops->uninit_instance) { 5538 hclge_uninit_instance_hw(hdev); 5539 client->ops->uninit_instance(&vport->nic, 0); 5540 hdev->nic_client = NULL; 5541 vport->nic.client = NULL; 5542 } 5543 } 5544 } 5545 5546 static int hclge_pci_init(struct hclge_dev *hdev) 5547 { 5548 struct pci_dev *pdev = hdev->pdev; 5549 struct hclge_hw *hw; 5550 int ret; 5551 5552 ret = pci_enable_device(pdev); 5553 if (ret) { 5554 dev_err(&pdev->dev, "failed to enable PCI device\n"); 5555 return ret; 5556 } 5557 5558 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 5559 if (ret) { 5560 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 5561 if (ret) { 5562 dev_err(&pdev->dev, 5563 "can't set consistent PCI DMA"); 5564 goto err_disable_device; 5565 } 5566 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 5567 } 5568 5569 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 5570 if (ret) { 5571 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 5572 goto err_disable_device; 5573 } 5574 5575 pci_set_master(pdev); 5576 hw = &hdev->hw; 5577 hw->io_base = pcim_iomap(pdev, 2, 0); 5578 if (!hw->io_base) { 5579 dev_err(&pdev->dev, "Can't map configuration register space\n"); 5580 ret = -ENOMEM; 5581 goto err_clr_master; 5582 } 5583 5584 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 5585 5586 return 0; 5587 err_clr_master: 5588 pci_clear_master(pdev); 5589 pci_release_regions(pdev); 5590 err_disable_device: 5591 pci_disable_device(pdev); 5592 5593 return ret; 5594 } 5595 5596 static void hclge_pci_uninit(struct hclge_dev *hdev) 5597 { 5598 struct pci_dev *pdev = hdev->pdev; 5599 5600 pcim_iounmap(pdev, hdev->hw.io_base); 5601 pci_free_irq_vectors(pdev); 5602 pci_clear_master(pdev); 5603 pci_release_mem_regions(pdev); 5604 pci_disable_device(pdev); 5605 } 5606 5607 static void hclge_state_init(struct hclge_dev *hdev) 5608 { 5609 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 5610 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5611 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 5612 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 5613 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 5614 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 5615 } 5616 5617 static void hclge_state_uninit(struct hclge_dev *hdev) 5618 { 5619 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5620 5621 if (hdev->service_timer.function) 5622 del_timer_sync(&hdev->service_timer); 5623 if (hdev->service_task.func) 5624 cancel_work_sync(&hdev->service_task); 5625 if (hdev->rst_service_task.func) 5626 cancel_work_sync(&hdev->rst_service_task); 5627 if (hdev->mbx_service_task.func) 5628 cancel_work_sync(&hdev->mbx_service_task); 5629 } 5630 5631 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 5632 { 5633 struct pci_dev *pdev = ae_dev->pdev; 5634 struct hclge_dev *hdev; 5635 int ret; 5636 5637 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 5638 if (!hdev) { 5639 ret = -ENOMEM; 5640 goto out; 5641 } 5642 5643 hdev->pdev = pdev; 5644 hdev->ae_dev = ae_dev; 5645 hdev->reset_type = HNAE3_NONE_RESET; 5646 ae_dev->priv = hdev; 5647 5648 ret = hclge_pci_init(hdev); 5649 if (ret) { 5650 dev_err(&pdev->dev, "PCI init failed\n"); 5651 goto out; 5652 } 5653 5654 /* Firmware command queue initialize */ 5655 ret = hclge_cmd_queue_init(hdev); 5656 if (ret) { 5657 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); 5658 goto err_pci_uninit; 5659 } 5660 5661 /* Firmware command initialize */ 5662 ret = hclge_cmd_init(hdev); 5663 if (ret) 5664 goto err_cmd_uninit; 5665 5666 ret = hclge_get_cap(hdev); 5667 if (ret) { 5668 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 5669 ret); 5670 goto err_cmd_uninit; 5671 } 5672 5673 ret = hclge_configure(hdev); 5674 if (ret) { 5675 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 5676 goto err_cmd_uninit; 5677 } 5678 5679 ret = hclge_init_msi(hdev); 5680 if (ret) { 5681 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 5682 goto err_cmd_uninit; 5683 } 5684 5685 ret = hclge_misc_irq_init(hdev); 5686 if (ret) { 5687 dev_err(&pdev->dev, 5688 "Misc IRQ(vector0) init error, ret = %d.\n", 5689 ret); 5690 goto err_msi_uninit; 5691 } 5692 5693 ret = hclge_alloc_tqps(hdev); 5694 if (ret) { 5695 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 5696 goto err_msi_irq_uninit; 5697 } 5698 5699 ret = hclge_alloc_vport(hdev); 5700 if (ret) { 5701 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); 5702 goto err_msi_irq_uninit; 5703 } 5704 5705 ret = hclge_map_tqp(hdev); 5706 if (ret) { 5707 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 5708 goto err_msi_irq_uninit; 5709 } 5710 5711 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 5712 ret = hclge_mac_mdio_config(hdev); 5713 if (ret) { 5714 dev_err(&hdev->pdev->dev, 5715 "mdio config fail ret=%d\n", ret); 5716 goto err_msi_irq_uninit; 5717 } 5718 } 5719 5720 ret = hclge_mac_init(hdev); 5721 if (ret) { 5722 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 5723 goto err_mdiobus_unreg; 5724 } 5725 5726 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 5727 if (ret) { 5728 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 5729 goto err_mdiobus_unreg; 5730 } 5731 5732 ret = hclge_init_vlan_config(hdev); 5733 if (ret) { 5734 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 5735 goto err_mdiobus_unreg; 5736 } 5737 5738 ret = hclge_tm_schd_init(hdev); 5739 if (ret) { 5740 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 5741 goto err_mdiobus_unreg; 5742 } 5743 5744 hclge_rss_init_cfg(hdev); 5745 ret = hclge_rss_init_hw(hdev); 5746 if (ret) { 5747 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 5748 goto err_mdiobus_unreg; 5749 } 5750 5751 ret = init_mgr_tbl(hdev); 5752 if (ret) { 5753 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 5754 goto err_mdiobus_unreg; 5755 } 5756 5757 hclge_dcb_ops_set(hdev); 5758 5759 timer_setup(&hdev->service_timer, hclge_service_timer, 0); 5760 INIT_WORK(&hdev->service_task, hclge_service_task); 5761 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); 5762 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); 5763 5764 hclge_clear_all_event_cause(hdev); 5765 5766 /* Enable MISC vector(vector0) */ 5767 hclge_enable_vector(&hdev->misc_vector, true); 5768 5769 hclge_state_init(hdev); 5770 5771 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); 5772 return 0; 5773 5774 err_mdiobus_unreg: 5775 if (hdev->hw.mac.phydev) 5776 mdiobus_unregister(hdev->hw.mac.mdio_bus); 5777 err_msi_irq_uninit: 5778 hclge_misc_irq_uninit(hdev); 5779 err_msi_uninit: 5780 pci_free_irq_vectors(pdev); 5781 err_cmd_uninit: 5782 hclge_destroy_cmd_queue(&hdev->hw); 5783 err_pci_uninit: 5784 pcim_iounmap(pdev, hdev->hw.io_base); 5785 pci_clear_master(pdev); 5786 pci_release_regions(pdev); 5787 pci_disable_device(pdev); 5788 out: 5789 return ret; 5790 } 5791 5792 static void hclge_stats_clear(struct hclge_dev *hdev) 5793 { 5794 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats)); 5795 } 5796 5797 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 5798 { 5799 struct hclge_dev *hdev = ae_dev->priv; 5800 struct pci_dev *pdev = ae_dev->pdev; 5801 int ret; 5802 5803 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5804 5805 hclge_stats_clear(hdev); 5806 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 5807 5808 ret = hclge_cmd_init(hdev); 5809 if (ret) { 5810 dev_err(&pdev->dev, "Cmd queue init failed\n"); 5811 return ret; 5812 } 5813 5814 ret = hclge_get_cap(hdev); 5815 if (ret) { 5816 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 5817 ret); 5818 return ret; 5819 } 5820 5821 ret = hclge_configure(hdev); 5822 if (ret) { 5823 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 5824 return ret; 5825 } 5826 5827 ret = hclge_map_tqp(hdev); 5828 if (ret) { 5829 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 5830 return ret; 5831 } 5832 5833 ret = hclge_mac_init(hdev); 5834 if (ret) { 5835 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 5836 return ret; 5837 } 5838 5839 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 5840 if (ret) { 5841 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 5842 return ret; 5843 } 5844 5845 ret = hclge_init_vlan_config(hdev); 5846 if (ret) { 5847 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 5848 return ret; 5849 } 5850 5851 ret = hclge_tm_init_hw(hdev); 5852 if (ret) { 5853 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 5854 return ret; 5855 } 5856 5857 ret = hclge_rss_init_hw(hdev); 5858 if (ret) { 5859 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 5860 return ret; 5861 } 5862 5863 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 5864 HCLGE_DRIVER_NAME); 5865 5866 return 0; 5867 } 5868 5869 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 5870 { 5871 struct hclge_dev *hdev = ae_dev->priv; 5872 struct hclge_mac *mac = &hdev->hw.mac; 5873 5874 hclge_state_uninit(hdev); 5875 5876 if (mac->phydev) 5877 mdiobus_unregister(mac->mdio_bus); 5878 5879 /* Disable MISC vector(vector0) */ 5880 hclge_enable_vector(&hdev->misc_vector, false); 5881 synchronize_irq(hdev->misc_vector.vector_irq); 5882 5883 hclge_destroy_cmd_queue(&hdev->hw); 5884 hclge_misc_irq_uninit(hdev); 5885 hclge_pci_uninit(hdev); 5886 ae_dev->priv = NULL; 5887 } 5888 5889 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 5890 { 5891 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5892 struct hclge_vport *vport = hclge_get_vport(handle); 5893 struct hclge_dev *hdev = vport->back; 5894 5895 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 5896 } 5897 5898 static void hclge_get_channels(struct hnae3_handle *handle, 5899 struct ethtool_channels *ch) 5900 { 5901 struct hclge_vport *vport = hclge_get_vport(handle); 5902 5903 ch->max_combined = hclge_get_max_channels(handle); 5904 ch->other_count = 1; 5905 ch->max_other = 1; 5906 ch->combined_count = vport->alloc_tqps; 5907 } 5908 5909 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 5910 u16 *free_tqps, u16 *max_rss_size) 5911 { 5912 struct hclge_vport *vport = hclge_get_vport(handle); 5913 struct hclge_dev *hdev = vport->back; 5914 u16 temp_tqps = 0; 5915 int i; 5916 5917 for (i = 0; i < hdev->num_tqps; i++) { 5918 if (!hdev->htqp[i].alloced) 5919 temp_tqps++; 5920 } 5921 *free_tqps = temp_tqps; 5922 *max_rss_size = hdev->rss_size_max; 5923 } 5924 5925 static void hclge_release_tqp(struct hclge_vport *vport) 5926 { 5927 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5928 struct hclge_dev *hdev = vport->back; 5929 int i; 5930 5931 for (i = 0; i < kinfo->num_tqps; i++) { 5932 struct hclge_tqp *tqp = 5933 container_of(kinfo->tqp[i], struct hclge_tqp, q); 5934 5935 tqp->q.handle = NULL; 5936 tqp->q.tqp_index = 0; 5937 tqp->alloced = false; 5938 } 5939 5940 devm_kfree(&hdev->pdev->dev, kinfo->tqp); 5941 kinfo->tqp = NULL; 5942 } 5943 5944 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num) 5945 { 5946 struct hclge_vport *vport = hclge_get_vport(handle); 5947 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5948 struct hclge_dev *hdev = vport->back; 5949 int cur_rss_size = kinfo->rss_size; 5950 int cur_tqps = kinfo->num_tqps; 5951 u16 tc_offset[HCLGE_MAX_TC_NUM]; 5952 u16 tc_valid[HCLGE_MAX_TC_NUM]; 5953 u16 tc_size[HCLGE_MAX_TC_NUM]; 5954 u16 roundup_size; 5955 u32 *rss_indir; 5956 int ret, i; 5957 5958 /* Free old tqps, and reallocate with new tqp number when nic setup */ 5959 hclge_release_tqp(vport); 5960 5961 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc); 5962 if (ret) { 5963 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); 5964 return ret; 5965 } 5966 5967 ret = hclge_map_tqp_to_vport(hdev, vport); 5968 if (ret) { 5969 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret); 5970 return ret; 5971 } 5972 5973 ret = hclge_tm_schd_init(hdev); 5974 if (ret) { 5975 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret); 5976 return ret; 5977 } 5978 5979 roundup_size = roundup_pow_of_two(kinfo->rss_size); 5980 roundup_size = ilog2(roundup_size); 5981 /* Set the RSS TC mode according to the new RSS size */ 5982 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 5983 tc_valid[i] = 0; 5984 5985 if (!(hdev->hw_tc_map & BIT(i))) 5986 continue; 5987 5988 tc_valid[i] = 1; 5989 tc_size[i] = roundup_size; 5990 tc_offset[i] = kinfo->rss_size * i; 5991 } 5992 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 5993 if (ret) 5994 return ret; 5995 5996 /* Reinitializes the rss indirect table according to the new RSS size */ 5997 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 5998 if (!rss_indir) 5999 return -ENOMEM; 6000 6001 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 6002 rss_indir[i] = i % kinfo->rss_size; 6003 6004 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 6005 if (ret) 6006 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 6007 ret); 6008 6009 kfree(rss_indir); 6010 6011 if (!ret) 6012 dev_info(&hdev->pdev->dev, 6013 "Channels changed, rss_size from %d to %d, tqps from %d to %d", 6014 cur_rss_size, kinfo->rss_size, 6015 cur_tqps, kinfo->rss_size * kinfo->num_tc); 6016 6017 return ret; 6018 } 6019 6020 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 6021 u32 *regs_num_64_bit) 6022 { 6023 struct hclge_desc desc; 6024 u32 total_num; 6025 int ret; 6026 6027 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 6028 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6029 if (ret) { 6030 dev_err(&hdev->pdev->dev, 6031 "Query register number cmd failed, ret = %d.\n", ret); 6032 return ret; 6033 } 6034 6035 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 6036 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 6037 6038 total_num = *regs_num_32_bit + *regs_num_64_bit; 6039 if (!total_num) 6040 return -EINVAL; 6041 6042 return 0; 6043 } 6044 6045 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 6046 void *data) 6047 { 6048 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 6049 6050 struct hclge_desc *desc; 6051 u32 *reg_val = data; 6052 __le32 *desc_data; 6053 int cmd_num; 6054 int i, k, n; 6055 int ret; 6056 6057 if (regs_num == 0) 6058 return 0; 6059 6060 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM); 6061 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 6062 if (!desc) 6063 return -ENOMEM; 6064 6065 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 6066 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 6067 if (ret) { 6068 dev_err(&hdev->pdev->dev, 6069 "Query 32 bit register cmd failed, ret = %d.\n", ret); 6070 kfree(desc); 6071 return ret; 6072 } 6073 6074 for (i = 0; i < cmd_num; i++) { 6075 if (i == 0) { 6076 desc_data = (__le32 *)(&desc[i].data[0]); 6077 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2; 6078 } else { 6079 desc_data = (__le32 *)(&desc[i]); 6080 n = HCLGE_32_BIT_REG_RTN_DATANUM; 6081 } 6082 for (k = 0; k < n; k++) { 6083 *reg_val++ = le32_to_cpu(*desc_data++); 6084 6085 regs_num--; 6086 if (!regs_num) 6087 break; 6088 } 6089 } 6090 6091 kfree(desc); 6092 return 0; 6093 } 6094 6095 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 6096 void *data) 6097 { 6098 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 6099 6100 struct hclge_desc *desc; 6101 u64 *reg_val = data; 6102 __le64 *desc_data; 6103 int cmd_num; 6104 int i, k, n; 6105 int ret; 6106 6107 if (regs_num == 0) 6108 return 0; 6109 6110 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM); 6111 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 6112 if (!desc) 6113 return -ENOMEM; 6114 6115 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 6116 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 6117 if (ret) { 6118 dev_err(&hdev->pdev->dev, 6119 "Query 64 bit register cmd failed, ret = %d.\n", ret); 6120 kfree(desc); 6121 return ret; 6122 } 6123 6124 for (i = 0; i < cmd_num; i++) { 6125 if (i == 0) { 6126 desc_data = (__le64 *)(&desc[i].data[0]); 6127 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1; 6128 } else { 6129 desc_data = (__le64 *)(&desc[i]); 6130 n = HCLGE_64_BIT_REG_RTN_DATANUM; 6131 } 6132 for (k = 0; k < n; k++) { 6133 *reg_val++ = le64_to_cpu(*desc_data++); 6134 6135 regs_num--; 6136 if (!regs_num) 6137 break; 6138 } 6139 } 6140 6141 kfree(desc); 6142 return 0; 6143 } 6144 6145 static int hclge_get_regs_len(struct hnae3_handle *handle) 6146 { 6147 struct hclge_vport *vport = hclge_get_vport(handle); 6148 struct hclge_dev *hdev = vport->back; 6149 u32 regs_num_32_bit, regs_num_64_bit; 6150 int ret; 6151 6152 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 6153 if (ret) { 6154 dev_err(&hdev->pdev->dev, 6155 "Get register number failed, ret = %d.\n", ret); 6156 return -EOPNOTSUPP; 6157 } 6158 6159 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64); 6160 } 6161 6162 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 6163 void *data) 6164 { 6165 struct hclge_vport *vport = hclge_get_vport(handle); 6166 struct hclge_dev *hdev = vport->back; 6167 u32 regs_num_32_bit, regs_num_64_bit; 6168 int ret; 6169 6170 *version = hdev->fw_version; 6171 6172 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 6173 if (ret) { 6174 dev_err(&hdev->pdev->dev, 6175 "Get register number failed, ret = %d.\n", ret); 6176 return; 6177 } 6178 6179 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data); 6180 if (ret) { 6181 dev_err(&hdev->pdev->dev, 6182 "Get 32 bit register failed, ret = %d.\n", ret); 6183 return; 6184 } 6185 6186 data = (u32 *)data + regs_num_32_bit; 6187 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, 6188 data); 6189 if (ret) 6190 dev_err(&hdev->pdev->dev, 6191 "Get 64 bit register failed, ret = %d.\n", ret); 6192 } 6193 6194 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 6195 { 6196 struct hclge_set_led_state_cmd *req; 6197 struct hclge_desc desc; 6198 int ret; 6199 6200 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 6201 6202 req = (struct hclge_set_led_state_cmd *)desc.data; 6203 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 6204 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 6205 6206 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6207 if (ret) 6208 dev_err(&hdev->pdev->dev, 6209 "Send set led state cmd error, ret =%d\n", ret); 6210 6211 return ret; 6212 } 6213 6214 enum hclge_led_status { 6215 HCLGE_LED_OFF, 6216 HCLGE_LED_ON, 6217 HCLGE_LED_NO_CHANGE = 0xFF, 6218 }; 6219 6220 static int hclge_set_led_id(struct hnae3_handle *handle, 6221 enum ethtool_phys_id_state status) 6222 { 6223 struct hclge_vport *vport = hclge_get_vport(handle); 6224 struct hclge_dev *hdev = vport->back; 6225 6226 switch (status) { 6227 case ETHTOOL_ID_ACTIVE: 6228 return hclge_set_led_status(hdev, HCLGE_LED_ON); 6229 case ETHTOOL_ID_INACTIVE: 6230 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 6231 default: 6232 return -EINVAL; 6233 } 6234 } 6235 6236 static void hclge_get_link_mode(struct hnae3_handle *handle, 6237 unsigned long *supported, 6238 unsigned long *advertising) 6239 { 6240 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 6241 struct hclge_vport *vport = hclge_get_vport(handle); 6242 struct hclge_dev *hdev = vport->back; 6243 unsigned int idx = 0; 6244 6245 for (; idx < size; idx++) { 6246 supported[idx] = hdev->hw.mac.supported[idx]; 6247 advertising[idx] = hdev->hw.mac.advertising[idx]; 6248 } 6249 } 6250 6251 static void hclge_get_port_type(struct hnae3_handle *handle, 6252 u8 *port_type) 6253 { 6254 struct hclge_vport *vport = hclge_get_vport(handle); 6255 struct hclge_dev *hdev = vport->back; 6256 u8 media_type = hdev->hw.mac.media_type; 6257 6258 switch (media_type) { 6259 case HNAE3_MEDIA_TYPE_FIBER: 6260 *port_type = PORT_FIBRE; 6261 break; 6262 case HNAE3_MEDIA_TYPE_COPPER: 6263 *port_type = PORT_TP; 6264 break; 6265 case HNAE3_MEDIA_TYPE_UNKNOWN: 6266 default: 6267 *port_type = PORT_OTHER; 6268 break; 6269 } 6270 } 6271 6272 static const struct hnae3_ae_ops hclge_ops = { 6273 .init_ae_dev = hclge_init_ae_dev, 6274 .uninit_ae_dev = hclge_uninit_ae_dev, 6275 .init_client_instance = hclge_init_client_instance, 6276 .uninit_client_instance = hclge_uninit_client_instance, 6277 .map_ring_to_vector = hclge_map_ring_to_vector, 6278 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 6279 .get_vector = hclge_get_vector, 6280 .put_vector = hclge_put_vector, 6281 .set_promisc_mode = hclge_set_promisc_mode, 6282 .set_loopback = hclge_set_loopback, 6283 .start = hclge_ae_start, 6284 .stop = hclge_ae_stop, 6285 .get_status = hclge_get_status, 6286 .get_ksettings_an_result = hclge_get_ksettings_an_result, 6287 .update_speed_duplex_h = hclge_update_speed_duplex_h, 6288 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 6289 .get_media_type = hclge_get_media_type, 6290 .get_rss_key_size = hclge_get_rss_key_size, 6291 .get_rss_indir_size = hclge_get_rss_indir_size, 6292 .get_rss = hclge_get_rss, 6293 .set_rss = hclge_set_rss, 6294 .set_rss_tuple = hclge_set_rss_tuple, 6295 .get_rss_tuple = hclge_get_rss_tuple, 6296 .get_tc_size = hclge_get_tc_size, 6297 .get_mac_addr = hclge_get_mac_addr, 6298 .set_mac_addr = hclge_set_mac_addr, 6299 .add_uc_addr = hclge_add_uc_addr, 6300 .rm_uc_addr = hclge_rm_uc_addr, 6301 .add_mc_addr = hclge_add_mc_addr, 6302 .rm_mc_addr = hclge_rm_mc_addr, 6303 .update_mta_status = hclge_update_mta_status, 6304 .set_autoneg = hclge_set_autoneg, 6305 .get_autoneg = hclge_get_autoneg, 6306 .get_pauseparam = hclge_get_pauseparam, 6307 .set_pauseparam = hclge_set_pauseparam, 6308 .set_mtu = hclge_set_mtu, 6309 .reset_queue = hclge_reset_tqp, 6310 .get_stats = hclge_get_stats, 6311 .update_stats = hclge_update_stats, 6312 .get_strings = hclge_get_strings, 6313 .get_sset_count = hclge_get_sset_count, 6314 .get_fw_version = hclge_get_fw_version, 6315 .get_mdix_mode = hclge_get_mdix_mode, 6316 .enable_vlan_filter = hclge_enable_vlan_filter, 6317 .set_vlan_filter = hclge_set_vlan_filter, 6318 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 6319 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 6320 .reset_event = hclge_reset_event, 6321 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 6322 .set_channels = hclge_set_channels, 6323 .get_channels = hclge_get_channels, 6324 .get_regs_len = hclge_get_regs_len, 6325 .get_regs = hclge_get_regs, 6326 .set_led_id = hclge_set_led_id, 6327 .get_link_mode = hclge_get_link_mode, 6328 .get_port_type = hclge_get_port_type, 6329 }; 6330 6331 static struct hnae3_ae_algo ae_algo = { 6332 .ops = &hclge_ops, 6333 .pdev_id_table = ae_algo_pci_tbl, 6334 }; 6335 6336 static int hclge_init(void) 6337 { 6338 pr_info("%s is initializing\n", HCLGE_NAME); 6339 6340 hnae3_register_ae_algo(&ae_algo); 6341 6342 return 0; 6343 } 6344 6345 static void hclge_exit(void) 6346 { 6347 hnae3_unregister_ae_algo(&ae_algo); 6348 } 6349 module_init(hclge_init); 6350 module_exit(hclge_exit); 6351 6352 MODULE_LICENSE("GPL"); 6353 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 6354 MODULE_DESCRIPTION("HCLGE Driver"); 6355 MODULE_VERSION(HCLGE_MOD_VERSION); 6356