1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_regs.h" 24 #include "hclge_tm.h" 25 #include "hclge_err.h" 26 #include "hnae3.h" 27 #include "hclge_devlink.h" 28 #include "hclge_comm_cmd.h" 29 30 #define HCLGE_NAME "hclge" 31 32 #define HCLGE_BUF_SIZE_UNIT 256U 33 #define HCLGE_BUF_MUL_BY 2 34 #define HCLGE_BUF_DIV_BY 2 35 #define NEED_RESERVE_TC_NUM 2 36 #define BUF_MAX_PERCENT 100 37 #define BUF_RESERVE_PERCENT 90 38 39 #define HCLGE_RESET_MAX_FAIL_CNT 5 40 #define HCLGE_RESET_SYNC_TIME 100 41 #define HCLGE_PF_RESET_SYNC_TIME 20 42 #define HCLGE_PF_RESET_SYNC_CNT 1500 43 44 #define HCLGE_LINK_STATUS_MS 10 45 46 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 47 static int hclge_init_vlan_config(struct hclge_dev *hdev); 48 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 49 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 50 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 51 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 52 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 53 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 54 unsigned long *addr); 55 static int hclge_set_default_loopback(struct hclge_dev *hdev); 56 57 static void hclge_sync_mac_table(struct hclge_dev *hdev); 58 static void hclge_restore_hw_table(struct hclge_dev *hdev); 59 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 60 static void hclge_sync_fd_table(struct hclge_dev *hdev); 61 static void hclge_update_fec_stats(struct hclge_dev *hdev); 62 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 63 int wait_cnt); 64 static int hclge_update_port_info(struct hclge_dev *hdev); 65 66 static struct hnae3_ae_algo ae_algo; 67 68 static struct workqueue_struct *hclge_wq; 69 70 static const struct pci_device_id ae_algo_pci_tbl[] = { 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 79 /* required last entry */ 80 {0, } 81 }; 82 83 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 84 85 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 86 "External Loopback test", 87 "App Loopback test", 88 "Serdes serial Loopback test", 89 "Serdes parallel Loopback test", 90 "Phy Loopback test" 91 }; 92 93 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 94 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 95 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 96 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 97 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 98 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 100 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 101 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 102 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 104 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 105 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 106 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 108 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 109 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 110 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 112 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 114 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 116 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 118 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 120 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 122 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 124 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 126 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 128 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 130 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 132 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 134 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 136 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 138 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 140 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 141 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 142 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 143 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 144 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 146 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 148 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 150 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 152 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 154 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 156 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 158 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 160 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 162 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 164 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 166 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 168 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 170 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 172 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 174 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 176 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 178 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 180 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 182 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 184 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 186 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 188 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 190 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 192 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 194 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 196 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 198 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 200 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 202 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 204 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 206 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 208 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 210 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 212 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 214 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 216 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 218 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 220 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 222 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 224 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 226 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 228 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 230 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 232 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 234 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 236 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 238 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 240 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 242 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 244 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 246 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 248 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 250 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 252 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 254 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 256 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 258 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 260 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 262 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 264 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 266 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 268 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 270 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 272 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 274 275 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 277 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 279 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 281 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 283 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 285 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 287 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 288 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 289 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 290 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 291 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 293 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 295 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 297 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 299 }; 300 301 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 302 { 303 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 304 .ethter_type = cpu_to_le16(ETH_P_LLDP), 305 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 306 .i_port_bitmap = 0x1, 307 }, 308 }; 309 310 static const struct key_info meta_data_key_info[] = { 311 { PACKET_TYPE_ID, 6 }, 312 { IP_FRAGEMENT, 1 }, 313 { ROCE_TYPE, 1 }, 314 { NEXT_KEY, 5 }, 315 { VLAN_NUMBER, 2 }, 316 { SRC_VPORT, 12 }, 317 { DST_VPORT, 12 }, 318 { TUNNEL_PACKET, 1 }, 319 }; 320 321 static const struct key_info tuple_key_info[] = { 322 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 323 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 324 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 325 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 326 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 327 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 328 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 329 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 330 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 331 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 332 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 333 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 334 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 335 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 336 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 337 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 338 { INNER_DST_MAC, 48, KEY_OPT_MAC, 339 offsetof(struct hclge_fd_rule, tuples.dst_mac), 340 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 341 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 342 offsetof(struct hclge_fd_rule, tuples.src_mac), 343 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 344 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 345 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 346 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 347 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 348 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 349 offsetof(struct hclge_fd_rule, tuples.ether_proto), 350 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 351 { INNER_L2_RSV, 16, KEY_OPT_LE16, 352 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 353 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 354 { INNER_IP_TOS, 8, KEY_OPT_U8, 355 offsetof(struct hclge_fd_rule, tuples.ip_tos), 356 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 357 { INNER_IP_PROTO, 8, KEY_OPT_U8, 358 offsetof(struct hclge_fd_rule, tuples.ip_proto), 359 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 360 { INNER_SRC_IP, 32, KEY_OPT_IP, 361 offsetof(struct hclge_fd_rule, tuples.src_ip), 362 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 363 { INNER_DST_IP, 32, KEY_OPT_IP, 364 offsetof(struct hclge_fd_rule, tuples.dst_ip), 365 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 366 { INNER_L3_RSV, 16, KEY_OPT_LE16, 367 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 368 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 369 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 370 offsetof(struct hclge_fd_rule, tuples.src_port), 371 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 372 { INNER_DST_PORT, 16, KEY_OPT_LE16, 373 offsetof(struct hclge_fd_rule, tuples.dst_port), 374 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 375 { INNER_L4_RSV, 32, KEY_OPT_LE32, 376 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 377 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 378 }; 379 380 /** 381 * hclge_cmd_send - send command to command queue 382 * @hw: pointer to the hw struct 383 * @desc: prefilled descriptor for describing the command 384 * @num : the number of descriptors to be sent 385 * 386 * This is the main send command for command queue, it 387 * sends the queue, cleans the queue, etc 388 **/ 389 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 390 { 391 return hclge_comm_cmd_send(&hw->hw, desc, num); 392 } 393 394 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 395 { 396 #define HCLGE_MAC_CMD_NUM 21 397 398 u64 *data = (u64 *)(&hdev->mac_stats); 399 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 400 __le64 *desc_data; 401 u32 data_size; 402 int ret; 403 u32 i; 404 405 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 406 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 407 if (ret) { 408 dev_err(&hdev->pdev->dev, 409 "Get MAC pkt stats fail, status = %d.\n", ret); 410 411 return ret; 412 } 413 414 /* The first desc has a 64-bit header, so data size need to minus 1 */ 415 data_size = sizeof(desc) / (sizeof(u64)) - 1; 416 417 desc_data = (__le64 *)(&desc[0].data[0]); 418 for (i = 0; i < data_size; i++) { 419 /* data memory is continuous becase only the first desc has a 420 * header in this command 421 */ 422 *data += le64_to_cpu(*desc_data); 423 data++; 424 desc_data++; 425 } 426 427 return 0; 428 } 429 430 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 431 { 432 #define HCLGE_REG_NUM_PER_DESC 4 433 434 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 435 u64 *data = (u64 *)(&hdev->mac_stats); 436 struct hclge_desc *desc; 437 __le64 *desc_data; 438 u32 data_size; 439 u32 desc_num; 440 int ret; 441 u32 i; 442 443 /* The first desc has a 64-bit header, so need to consider it */ 444 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 445 446 /* This may be called inside atomic sections, 447 * so GFP_ATOMIC is more suitalbe here 448 */ 449 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 450 if (!desc) 451 return -ENOMEM; 452 453 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 454 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 455 if (ret) { 456 kfree(desc); 457 return ret; 458 } 459 460 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 461 462 desc_data = (__le64 *)(&desc[0].data[0]); 463 for (i = 0; i < data_size; i++) { 464 /* data memory is continuous becase only the first desc has a 465 * header in this command 466 */ 467 *data += le64_to_cpu(*desc_data); 468 data++; 469 desc_data++; 470 } 471 472 kfree(desc); 473 474 return 0; 475 } 476 477 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 478 { 479 struct hclge_desc desc; 480 int ret; 481 482 /* Driver needs total register number of both valid registers and 483 * reserved registers, but the old firmware only returns number 484 * of valid registers in device V2. To be compatible with these 485 * devices, driver uses a fixed value. 486 */ 487 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 488 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 489 return 0; 490 } 491 492 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 493 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 494 if (ret) { 495 dev_err(&hdev->pdev->dev, 496 "failed to query mac statistic reg number, ret = %d\n", 497 ret); 498 return ret; 499 } 500 501 *reg_num = le32_to_cpu(desc.data[0]); 502 if (*reg_num == 0) { 503 dev_err(&hdev->pdev->dev, 504 "mac statistic reg number is invalid!\n"); 505 return -ENODATA; 506 } 507 508 return 0; 509 } 510 511 int hclge_mac_update_stats(struct hclge_dev *hdev) 512 { 513 /* The firmware supports the new statistics acquisition method */ 514 if (hdev->ae_dev->dev_specs.mac_stats_num) 515 return hclge_mac_update_stats_complete(hdev); 516 else 517 return hclge_mac_update_stats_defective(hdev); 518 } 519 520 static int hclge_comm_get_count(struct hclge_dev *hdev, 521 const struct hclge_comm_stats_str strs[], 522 u32 size) 523 { 524 int count = 0; 525 u32 i; 526 527 for (i = 0; i < size; i++) 528 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 529 count++; 530 531 return count; 532 } 533 534 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 535 const struct hclge_comm_stats_str strs[], 536 int size, u64 *data) 537 { 538 u64 *buf = data; 539 u32 i; 540 541 for (i = 0; i < size; i++) { 542 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 543 continue; 544 545 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 546 buf++; 547 } 548 549 return buf; 550 } 551 552 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 553 const struct hclge_comm_stats_str strs[], 554 int size, u8 *data) 555 { 556 char *buff = (char *)data; 557 u32 i; 558 559 if (stringset != ETH_SS_STATS) 560 return buff; 561 562 for (i = 0; i < size; i++) { 563 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 564 continue; 565 566 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 567 buff = buff + ETH_GSTRING_LEN; 568 } 569 570 return (u8 *)buff; 571 } 572 573 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 574 { 575 struct hnae3_handle *handle; 576 int status; 577 578 handle = &hdev->vport[0].nic; 579 if (handle->client) { 580 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 581 if (status) { 582 dev_err(&hdev->pdev->dev, 583 "Update TQPS stats fail, status = %d.\n", 584 status); 585 } 586 } 587 588 hclge_update_fec_stats(hdev); 589 590 status = hclge_mac_update_stats(hdev); 591 if (status) 592 dev_err(&hdev->pdev->dev, 593 "Update MAC stats fail, status = %d.\n", status); 594 } 595 596 static void hclge_update_stats(struct hnae3_handle *handle) 597 { 598 struct hclge_vport *vport = hclge_get_vport(handle); 599 struct hclge_dev *hdev = vport->back; 600 int status; 601 602 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 603 return; 604 605 status = hclge_mac_update_stats(hdev); 606 if (status) 607 dev_err(&hdev->pdev->dev, 608 "Update MAC stats fail, status = %d.\n", 609 status); 610 611 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 612 if (status) 613 dev_err(&hdev->pdev->dev, 614 "Update TQPS stats fail, status = %d.\n", 615 status); 616 617 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 618 } 619 620 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 621 { 622 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 623 HNAE3_SUPPORT_PHY_LOOPBACK | \ 624 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 625 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 626 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 627 628 struct hclge_vport *vport = hclge_get_vport(handle); 629 struct hclge_dev *hdev = vport->back; 630 int count = 0; 631 632 /* Loopback test support rules: 633 * mac: only GE mode support 634 * serdes: all mac mode will support include GE/XGE/LGE/CGE 635 * phy: only support when phy device exist on board 636 */ 637 if (stringset == ETH_SS_TEST) { 638 /* clear loopback bit flags at first */ 639 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 640 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 641 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 642 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 643 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 644 count += 1; 645 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 646 } 647 648 if (hdev->ae_dev->dev_specs.hilink_version != 649 HCLGE_HILINK_H60) { 650 count += 1; 651 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 652 } 653 654 count += 1; 655 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 656 count += 1; 657 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 658 659 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 660 hdev->hw.mac.phydev->drv->set_loopback) || 661 hnae3_dev_phy_imp_supported(hdev)) { 662 count += 1; 663 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 664 } 665 } else if (stringset == ETH_SS_STATS) { 666 count = hclge_comm_get_count(hdev, g_mac_stats_string, 667 ARRAY_SIZE(g_mac_stats_string)) + 668 hclge_comm_tqps_get_sset_count(handle); 669 } 670 671 return count; 672 } 673 674 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 675 u8 *data) 676 { 677 struct hclge_vport *vport = hclge_get_vport(handle); 678 struct hclge_dev *hdev = vport->back; 679 u8 *p = (char *)data; 680 int size; 681 682 if (stringset == ETH_SS_STATS) { 683 size = ARRAY_SIZE(g_mac_stats_string); 684 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 685 size, p); 686 p = hclge_comm_tqps_get_strings(handle, p); 687 } else if (stringset == ETH_SS_TEST) { 688 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 689 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 690 ETH_GSTRING_LEN); 691 p += ETH_GSTRING_LEN; 692 } 693 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 694 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 695 ETH_GSTRING_LEN); 696 p += ETH_GSTRING_LEN; 697 } 698 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 699 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 700 ETH_GSTRING_LEN); 701 p += ETH_GSTRING_LEN; 702 } 703 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 704 memcpy(p, 705 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 706 ETH_GSTRING_LEN); 707 p += ETH_GSTRING_LEN; 708 } 709 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 710 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 711 ETH_GSTRING_LEN); 712 p += ETH_GSTRING_LEN; 713 } 714 } 715 } 716 717 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 718 { 719 struct hclge_vport *vport = hclge_get_vport(handle); 720 struct hclge_dev *hdev = vport->back; 721 u64 *p; 722 723 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 724 ARRAY_SIZE(g_mac_stats_string), data); 725 p = hclge_comm_tqps_get_stats(handle, p); 726 } 727 728 static void hclge_get_mac_stat(struct hnae3_handle *handle, 729 struct hns3_mac_stats *mac_stats) 730 { 731 struct hclge_vport *vport = hclge_get_vport(handle); 732 struct hclge_dev *hdev = vport->back; 733 734 hclge_update_stats(handle); 735 736 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 737 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 738 } 739 740 static int hclge_parse_func_status(struct hclge_dev *hdev, 741 struct hclge_func_status_cmd *status) 742 { 743 #define HCLGE_MAC_ID_MASK 0xF 744 745 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 746 return -EINVAL; 747 748 /* Set the pf to main pf */ 749 if (status->pf_state & HCLGE_PF_STATE_MAIN) 750 hdev->flag |= HCLGE_FLAG_MAIN; 751 else 752 hdev->flag &= ~HCLGE_FLAG_MAIN; 753 754 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 755 return 0; 756 } 757 758 static int hclge_query_function_status(struct hclge_dev *hdev) 759 { 760 #define HCLGE_QUERY_MAX_CNT 5 761 762 struct hclge_func_status_cmd *req; 763 struct hclge_desc desc; 764 int timeout = 0; 765 int ret; 766 767 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 768 req = (struct hclge_func_status_cmd *)desc.data; 769 770 do { 771 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 772 if (ret) { 773 dev_err(&hdev->pdev->dev, 774 "query function status failed %d.\n", ret); 775 return ret; 776 } 777 778 /* Check pf reset is done */ 779 if (req->pf_state) 780 break; 781 usleep_range(1000, 2000); 782 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 783 784 return hclge_parse_func_status(hdev, req); 785 } 786 787 static int hclge_query_pf_resource(struct hclge_dev *hdev) 788 { 789 struct hclge_pf_res_cmd *req; 790 struct hclge_desc desc; 791 int ret; 792 793 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 794 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 795 if (ret) { 796 dev_err(&hdev->pdev->dev, 797 "query pf resource failed %d.\n", ret); 798 return ret; 799 } 800 801 req = (struct hclge_pf_res_cmd *)desc.data; 802 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 803 le16_to_cpu(req->ext_tqp_num); 804 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 805 806 if (req->tx_buf_size) 807 hdev->tx_buf_size = 808 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 809 else 810 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 811 812 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 813 814 if (req->dv_buf_size) 815 hdev->dv_buf_size = 816 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 817 else 818 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 819 820 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 821 822 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 823 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 824 dev_err(&hdev->pdev->dev, 825 "only %u msi resources available, not enough for pf(min:2).\n", 826 hdev->num_nic_msi); 827 return -EINVAL; 828 } 829 830 if (hnae3_dev_roce_supported(hdev)) { 831 hdev->num_roce_msi = 832 le16_to_cpu(req->pf_intr_vector_number_roce); 833 834 /* PF should have NIC vectors and Roce vectors, 835 * NIC vectors are queued before Roce vectors. 836 */ 837 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 838 } else { 839 hdev->num_msi = hdev->num_nic_msi; 840 } 841 842 return 0; 843 } 844 845 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 846 { 847 switch (speed_cmd) { 848 case HCLGE_FW_MAC_SPEED_10M: 849 *speed = HCLGE_MAC_SPEED_10M; 850 break; 851 case HCLGE_FW_MAC_SPEED_100M: 852 *speed = HCLGE_MAC_SPEED_100M; 853 break; 854 case HCLGE_FW_MAC_SPEED_1G: 855 *speed = HCLGE_MAC_SPEED_1G; 856 break; 857 case HCLGE_FW_MAC_SPEED_10G: 858 *speed = HCLGE_MAC_SPEED_10G; 859 break; 860 case HCLGE_FW_MAC_SPEED_25G: 861 *speed = HCLGE_MAC_SPEED_25G; 862 break; 863 case HCLGE_FW_MAC_SPEED_40G: 864 *speed = HCLGE_MAC_SPEED_40G; 865 break; 866 case HCLGE_FW_MAC_SPEED_50G: 867 *speed = HCLGE_MAC_SPEED_50G; 868 break; 869 case HCLGE_FW_MAC_SPEED_100G: 870 *speed = HCLGE_MAC_SPEED_100G; 871 break; 872 case HCLGE_FW_MAC_SPEED_200G: 873 *speed = HCLGE_MAC_SPEED_200G; 874 break; 875 default: 876 return -EINVAL; 877 } 878 879 return 0; 880 } 881 882 static const struct hclge_speed_bit_map speed_bit_map[] = { 883 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 884 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 885 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 886 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 887 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 888 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 889 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS}, 890 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS}, 891 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS}, 892 }; 893 894 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 895 { 896 u16 i; 897 898 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 899 if (speed == speed_bit_map[i].speed) { 900 *speed_bit = speed_bit_map[i].speed_bit; 901 return 0; 902 } 903 } 904 905 return -EINVAL; 906 } 907 908 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 909 { 910 struct hclge_vport *vport = hclge_get_vport(handle); 911 struct hclge_dev *hdev = vport->back; 912 u32 speed_ability = hdev->hw.mac.speed_ability; 913 u32 speed_bit = 0; 914 int ret; 915 916 ret = hclge_get_speed_bit(speed, &speed_bit); 917 if (ret) 918 return ret; 919 920 if (speed_bit & speed_ability) 921 return 0; 922 923 return -EINVAL; 924 } 925 926 static void hclge_update_fec_support(struct hclge_mac *mac) 927 { 928 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 929 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 930 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 931 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 932 933 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 934 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 935 mac->supported); 936 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 937 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 938 mac->supported); 939 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 940 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 941 mac->supported); 942 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 943 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 944 mac->supported); 945 } 946 947 static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = { 948 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT}, 949 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT}, 950 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT}, 951 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT}, 952 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT}, 953 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT}, 954 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT}, 955 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 956 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 957 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 958 }; 959 960 static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = { 961 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT}, 962 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT}, 963 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT}, 964 {HCLGE_SUPPORT_100G_R4_BIT, 965 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT}, 966 {HCLGE_SUPPORT_100G_R2_BIT, 967 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT}, 968 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 969 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 970 {HCLGE_SUPPORT_200G_R4_BIT, 971 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 972 }; 973 974 static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = { 975 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT}, 976 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT}, 977 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT}, 978 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT}, 979 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT}, 980 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT}, 981 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT}, 982 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 983 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 984 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 985 }; 986 987 static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = { 988 {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, 989 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, 990 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT}, 991 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT}, 992 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT}, 993 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT}, 994 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT}, 995 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT}, 996 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 997 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 998 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 999 }; 1000 1001 static void hclge_convert_setting_sr(u16 speed_ability, 1002 unsigned long *link_mode) 1003 { 1004 int i; 1005 1006 for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) { 1007 if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit) 1008 linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode, 1009 link_mode); 1010 } 1011 } 1012 1013 static void hclge_convert_setting_lr(u16 speed_ability, 1014 unsigned long *link_mode) 1015 { 1016 int i; 1017 1018 for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) { 1019 if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit) 1020 linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode, 1021 link_mode); 1022 } 1023 } 1024 1025 static void hclge_convert_setting_cr(u16 speed_ability, 1026 unsigned long *link_mode) 1027 { 1028 int i; 1029 1030 for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) { 1031 if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit) 1032 linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode, 1033 link_mode); 1034 } 1035 } 1036 1037 static void hclge_convert_setting_kr(u16 speed_ability, 1038 unsigned long *link_mode) 1039 { 1040 int i; 1041 1042 for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) { 1043 if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit) 1044 linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode, 1045 link_mode); 1046 } 1047 } 1048 1049 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1050 { 1051 /* If firmware has reported fec_ability, don't need to convert by speed */ 1052 if (mac->fec_ability) 1053 goto out; 1054 1055 switch (mac->speed) { 1056 case HCLGE_MAC_SPEED_10G: 1057 case HCLGE_MAC_SPEED_40G: 1058 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1059 BIT(HNAE3_FEC_NONE); 1060 break; 1061 case HCLGE_MAC_SPEED_25G: 1062 case HCLGE_MAC_SPEED_50G: 1063 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1064 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1065 break; 1066 case HCLGE_MAC_SPEED_100G: 1067 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1068 BIT(HNAE3_FEC_NONE); 1069 break; 1070 case HCLGE_MAC_SPEED_200G: 1071 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1072 BIT(HNAE3_FEC_LLRS); 1073 break; 1074 default: 1075 mac->fec_ability = 0; 1076 break; 1077 } 1078 1079 out: 1080 hclge_update_fec_support(mac); 1081 } 1082 1083 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1084 u16 speed_ability) 1085 { 1086 struct hclge_mac *mac = &hdev->hw.mac; 1087 1088 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1089 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1090 mac->supported); 1091 1092 hclge_convert_setting_sr(speed_ability, mac->supported); 1093 hclge_convert_setting_lr(speed_ability, mac->supported); 1094 hclge_convert_setting_cr(speed_ability, mac->supported); 1095 if (hnae3_dev_fec_supported(hdev)) 1096 hclge_convert_setting_fec(mac); 1097 1098 if (hnae3_dev_pause_supported(hdev)) 1099 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1100 1101 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1102 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1103 } 1104 1105 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1106 u16 speed_ability) 1107 { 1108 struct hclge_mac *mac = &hdev->hw.mac; 1109 1110 hclge_convert_setting_kr(speed_ability, mac->supported); 1111 if (hnae3_dev_fec_supported(hdev)) 1112 hclge_convert_setting_fec(mac); 1113 1114 if (hnae3_dev_pause_supported(hdev)) 1115 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1116 1117 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1118 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1119 } 1120 1121 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1122 u16 speed_ability) 1123 { 1124 unsigned long *supported = hdev->hw.mac.supported; 1125 1126 /* default to support all speed for GE port */ 1127 if (!speed_ability) 1128 speed_ability = HCLGE_SUPPORT_GE; 1129 1130 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1131 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1132 supported); 1133 1134 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1135 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1136 supported); 1137 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1138 supported); 1139 } 1140 1141 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1142 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1143 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1144 } 1145 1146 if (hnae3_dev_pause_supported(hdev)) { 1147 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1148 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1149 } 1150 1151 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1152 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1153 } 1154 1155 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1156 { 1157 u8 media_type = hdev->hw.mac.media_type; 1158 1159 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1160 hclge_parse_fiber_link_mode(hdev, speed_ability); 1161 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1162 hclge_parse_copper_link_mode(hdev, speed_ability); 1163 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1164 hclge_parse_backplane_link_mode(hdev, speed_ability); 1165 } 1166 1167 static u32 hclge_get_max_speed(u16 speed_ability) 1168 { 1169 if (speed_ability & HCLGE_SUPPORT_200G_BITS) 1170 return HCLGE_MAC_SPEED_200G; 1171 1172 if (speed_ability & HCLGE_SUPPORT_100G_BITS) 1173 return HCLGE_MAC_SPEED_100G; 1174 1175 if (speed_ability & HCLGE_SUPPORT_50G_BITS) 1176 return HCLGE_MAC_SPEED_50G; 1177 1178 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1179 return HCLGE_MAC_SPEED_40G; 1180 1181 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1182 return HCLGE_MAC_SPEED_25G; 1183 1184 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1185 return HCLGE_MAC_SPEED_10G; 1186 1187 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1188 return HCLGE_MAC_SPEED_1G; 1189 1190 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1191 return HCLGE_MAC_SPEED_100M; 1192 1193 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1194 return HCLGE_MAC_SPEED_10M; 1195 1196 return HCLGE_MAC_SPEED_1G; 1197 } 1198 1199 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1200 { 1201 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1202 #define SPEED_ABILITY_EXT_SHIFT 8 1203 1204 struct hclge_cfg_param_cmd *req; 1205 u64 mac_addr_tmp_high; 1206 u16 speed_ability_ext; 1207 u64 mac_addr_tmp; 1208 unsigned int i; 1209 1210 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1211 1212 /* get the configuration */ 1213 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1214 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1215 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1216 HCLGE_CFG_TQP_DESC_N_M, 1217 HCLGE_CFG_TQP_DESC_N_S); 1218 1219 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1220 HCLGE_CFG_PHY_ADDR_M, 1221 HCLGE_CFG_PHY_ADDR_S); 1222 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1223 HCLGE_CFG_MEDIA_TP_M, 1224 HCLGE_CFG_MEDIA_TP_S); 1225 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1226 HCLGE_CFG_RX_BUF_LEN_M, 1227 HCLGE_CFG_RX_BUF_LEN_S); 1228 /* get mac_address */ 1229 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1230 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1231 HCLGE_CFG_MAC_ADDR_H_M, 1232 HCLGE_CFG_MAC_ADDR_H_S); 1233 1234 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1235 1236 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1237 HCLGE_CFG_DEFAULT_SPEED_M, 1238 HCLGE_CFG_DEFAULT_SPEED_S); 1239 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1240 HCLGE_CFG_RSS_SIZE_M, 1241 HCLGE_CFG_RSS_SIZE_S); 1242 1243 for (i = 0; i < ETH_ALEN; i++) 1244 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1245 1246 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1247 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1248 1249 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1250 HCLGE_CFG_SPEED_ABILITY_M, 1251 HCLGE_CFG_SPEED_ABILITY_S); 1252 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1253 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1254 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1255 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1256 1257 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1258 HCLGE_CFG_VLAN_FLTR_CAP_M, 1259 HCLGE_CFG_VLAN_FLTR_CAP_S); 1260 1261 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1262 HCLGE_CFG_UMV_TBL_SPACE_M, 1263 HCLGE_CFG_UMV_TBL_SPACE_S); 1264 1265 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1266 HCLGE_CFG_PF_RSS_SIZE_M, 1267 HCLGE_CFG_PF_RSS_SIZE_S); 1268 1269 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1270 * power of 2, instead of reading out directly. This would 1271 * be more flexible for future changes and expansions. 1272 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1273 * it does not make sense if PF's field is 0. In this case, PF and VF 1274 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1275 */ 1276 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1277 1U << cfg->pf_rss_size_max : 1278 cfg->vf_rss_size_max; 1279 1280 /* The unit of the tx spare buffer size queried from configuration 1281 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1282 * needed here. 1283 */ 1284 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1285 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1286 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1287 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1288 } 1289 1290 /* hclge_get_cfg: query the static parameter from flash 1291 * @hdev: pointer to struct hclge_dev 1292 * @hcfg: the config structure to be getted 1293 */ 1294 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1295 { 1296 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1297 struct hclge_cfg_param_cmd *req; 1298 unsigned int i; 1299 int ret; 1300 1301 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1302 u32 offset = 0; 1303 1304 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1305 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1306 true); 1307 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1308 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1309 /* Len should be united by 4 bytes when send to hardware */ 1310 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1311 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1312 req->offset = cpu_to_le32(offset); 1313 } 1314 1315 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1316 if (ret) { 1317 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1318 return ret; 1319 } 1320 1321 hclge_parse_cfg(hcfg, desc); 1322 1323 return 0; 1324 } 1325 1326 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1327 { 1328 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1329 1330 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1331 1332 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1333 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1334 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1335 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1336 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1337 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1338 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1339 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1340 ae_dev->dev_specs.tnl_num = 0; 1341 } 1342 1343 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1344 struct hclge_desc *desc) 1345 { 1346 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1347 struct hclge_dev_specs_0_cmd *req0; 1348 struct hclge_dev_specs_1_cmd *req1; 1349 1350 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1351 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1352 1353 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1354 ae_dev->dev_specs.rss_ind_tbl_size = 1355 le16_to_cpu(req0->rss_ind_tbl_size); 1356 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1357 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1358 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1359 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1360 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1361 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1362 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1363 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1364 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1365 ae_dev->dev_specs.hilink_version = req1->hilink_version; 1366 } 1367 1368 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1369 { 1370 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1371 1372 if (!dev_specs->max_non_tso_bd_num) 1373 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1374 if (!dev_specs->rss_ind_tbl_size) 1375 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1376 if (!dev_specs->rss_key_size) 1377 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1378 if (!dev_specs->max_tm_rate) 1379 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1380 if (!dev_specs->max_qset_num) 1381 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1382 if (!dev_specs->max_int_gl) 1383 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1384 if (!dev_specs->max_frm_size) 1385 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1386 if (!dev_specs->umv_size) 1387 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1388 } 1389 1390 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1391 { 1392 u32 reg_num = 0; 1393 int ret; 1394 1395 ret = hclge_mac_query_reg_num(hdev, ®_num); 1396 if (ret && ret != -EOPNOTSUPP) 1397 return ret; 1398 1399 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1400 return 0; 1401 } 1402 1403 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1404 { 1405 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1406 int ret; 1407 int i; 1408 1409 ret = hclge_query_mac_stats_num(hdev); 1410 if (ret) 1411 return ret; 1412 1413 /* set default specifications as devices lower than version V3 do not 1414 * support querying specifications from firmware. 1415 */ 1416 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1417 hclge_set_default_dev_specs(hdev); 1418 return 0; 1419 } 1420 1421 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1422 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1423 true); 1424 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1425 } 1426 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1427 1428 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1429 if (ret) 1430 return ret; 1431 1432 hclge_parse_dev_specs(hdev, desc); 1433 hclge_check_dev_specs(hdev); 1434 1435 return 0; 1436 } 1437 1438 static int hclge_get_cap(struct hclge_dev *hdev) 1439 { 1440 int ret; 1441 1442 ret = hclge_query_function_status(hdev); 1443 if (ret) { 1444 dev_err(&hdev->pdev->dev, 1445 "query function status error %d.\n", ret); 1446 return ret; 1447 } 1448 1449 /* get pf resource */ 1450 return hclge_query_pf_resource(hdev); 1451 } 1452 1453 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1454 { 1455 #define HCLGE_MIN_TX_DESC 64 1456 #define HCLGE_MIN_RX_DESC 64 1457 1458 if (!is_kdump_kernel()) 1459 return; 1460 1461 dev_info(&hdev->pdev->dev, 1462 "Running kdump kernel. Using minimal resources\n"); 1463 1464 /* minimal queue pairs equals to the number of vports */ 1465 hdev->num_tqps = hdev->num_req_vfs + 1; 1466 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1467 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1468 } 1469 1470 static void hclge_init_tc_config(struct hclge_dev *hdev) 1471 { 1472 unsigned int i; 1473 1474 if (hdev->tc_max > HNAE3_MAX_TC || 1475 hdev->tc_max < 1) { 1476 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1477 hdev->tc_max); 1478 hdev->tc_max = 1; 1479 } 1480 1481 /* Dev does not support DCB */ 1482 if (!hnae3_dev_dcb_supported(hdev)) { 1483 hdev->tc_max = 1; 1484 hdev->pfc_max = 0; 1485 } else { 1486 hdev->pfc_max = hdev->tc_max; 1487 } 1488 1489 hdev->tm_info.num_tc = 1; 1490 1491 /* Currently not support uncontiuous tc */ 1492 for (i = 0; i < hdev->tm_info.num_tc; i++) 1493 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1494 1495 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1496 } 1497 1498 static int hclge_configure(struct hclge_dev *hdev) 1499 { 1500 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1501 struct hclge_cfg cfg; 1502 int ret; 1503 1504 ret = hclge_get_cfg(hdev, &cfg); 1505 if (ret) 1506 return ret; 1507 1508 hdev->base_tqp_pid = 0; 1509 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1510 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1511 hdev->rx_buf_len = cfg.rx_buf_len; 1512 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1513 hdev->hw.mac.media_type = cfg.media_type; 1514 hdev->hw.mac.phy_addr = cfg.phy_addr; 1515 hdev->num_tx_desc = cfg.tqp_desc_num; 1516 hdev->num_rx_desc = cfg.tqp_desc_num; 1517 hdev->tm_info.num_pg = 1; 1518 hdev->tc_max = cfg.tc_num; 1519 hdev->tm_info.hw_pfc_map = 0; 1520 if (cfg.umv_space) 1521 hdev->wanted_umv_size = cfg.umv_space; 1522 else 1523 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1524 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1525 hdev->gro_en = true; 1526 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1527 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1528 1529 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1530 hdev->fd_en = true; 1531 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1532 } 1533 1534 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1535 if (ret) { 1536 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1537 cfg.default_speed, ret); 1538 return ret; 1539 } 1540 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1541 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1542 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1543 1544 hclge_parse_link_mode(hdev, cfg.speed_ability); 1545 1546 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1547 1548 hclge_init_tc_config(hdev); 1549 hclge_init_kdump_kernel_config(hdev); 1550 1551 return ret; 1552 } 1553 1554 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1555 u16 tso_mss_max) 1556 { 1557 struct hclge_cfg_tso_status_cmd *req; 1558 struct hclge_desc desc; 1559 1560 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1561 1562 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1563 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1564 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1565 1566 return hclge_cmd_send(&hdev->hw, &desc, 1); 1567 } 1568 1569 static int hclge_config_gro(struct hclge_dev *hdev) 1570 { 1571 struct hclge_cfg_gro_status_cmd *req; 1572 struct hclge_desc desc; 1573 int ret; 1574 1575 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1576 return 0; 1577 1578 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1579 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1580 1581 req->gro_en = hdev->gro_en ? 1 : 0; 1582 1583 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1584 if (ret) 1585 dev_err(&hdev->pdev->dev, 1586 "GRO hardware config cmd failed, ret = %d\n", ret); 1587 1588 return ret; 1589 } 1590 1591 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1592 { 1593 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1594 struct hclge_comm_tqp *tqp; 1595 int i; 1596 1597 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1598 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1599 if (!hdev->htqp) 1600 return -ENOMEM; 1601 1602 tqp = hdev->htqp; 1603 1604 for (i = 0; i < hdev->num_tqps; i++) { 1605 tqp->dev = &hdev->pdev->dev; 1606 tqp->index = i; 1607 1608 tqp->q.ae_algo = &ae_algo; 1609 tqp->q.buf_size = hdev->rx_buf_len; 1610 tqp->q.tx_desc_num = hdev->num_tx_desc; 1611 tqp->q.rx_desc_num = hdev->num_rx_desc; 1612 1613 /* need an extended offset to configure queues >= 1614 * HCLGE_TQP_MAX_SIZE_DEV_V2 1615 */ 1616 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1617 tqp->q.io_base = hdev->hw.hw.io_base + 1618 HCLGE_TQP_REG_OFFSET + 1619 i * HCLGE_TQP_REG_SIZE; 1620 else 1621 tqp->q.io_base = hdev->hw.hw.io_base + 1622 HCLGE_TQP_REG_OFFSET + 1623 HCLGE_TQP_EXT_REG_OFFSET + 1624 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1625 HCLGE_TQP_REG_SIZE; 1626 1627 /* when device supports tx push and has device memory, 1628 * the queue can execute push mode or doorbell mode on 1629 * device memory. 1630 */ 1631 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1632 tqp->q.mem_base = hdev->hw.hw.mem_base + 1633 HCLGE_TQP_MEM_OFFSET(hdev, i); 1634 1635 tqp++; 1636 } 1637 1638 return 0; 1639 } 1640 1641 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1642 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1643 { 1644 struct hclge_tqp_map_cmd *req; 1645 struct hclge_desc desc; 1646 int ret; 1647 1648 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1649 1650 req = (struct hclge_tqp_map_cmd *)desc.data; 1651 req->tqp_id = cpu_to_le16(tqp_pid); 1652 req->tqp_vf = func_id; 1653 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1654 if (!is_pf) 1655 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1656 req->tqp_vid = cpu_to_le16(tqp_vid); 1657 1658 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1659 if (ret) 1660 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1661 1662 return ret; 1663 } 1664 1665 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1666 { 1667 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1668 struct hclge_dev *hdev = vport->back; 1669 int i, alloced; 1670 1671 for (i = 0, alloced = 0; i < hdev->num_tqps && 1672 alloced < num_tqps; i++) { 1673 if (!hdev->htqp[i].alloced) { 1674 hdev->htqp[i].q.handle = &vport->nic; 1675 hdev->htqp[i].q.tqp_index = alloced; 1676 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1677 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1678 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1679 hdev->htqp[i].alloced = true; 1680 alloced++; 1681 } 1682 } 1683 vport->alloc_tqps = alloced; 1684 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1685 vport->alloc_tqps / hdev->tm_info.num_tc); 1686 1687 /* ensure one to one mapping between irq and queue at default */ 1688 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1689 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1690 1691 return 0; 1692 } 1693 1694 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1695 u16 num_tx_desc, u16 num_rx_desc) 1696 1697 { 1698 struct hnae3_handle *nic = &vport->nic; 1699 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1700 struct hclge_dev *hdev = vport->back; 1701 int ret; 1702 1703 kinfo->num_tx_desc = num_tx_desc; 1704 kinfo->num_rx_desc = num_rx_desc; 1705 1706 kinfo->rx_buf_len = hdev->rx_buf_len; 1707 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1708 1709 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1710 sizeof(struct hnae3_queue *), GFP_KERNEL); 1711 if (!kinfo->tqp) 1712 return -ENOMEM; 1713 1714 ret = hclge_assign_tqp(vport, num_tqps); 1715 if (ret) 1716 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1717 1718 return ret; 1719 } 1720 1721 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1722 struct hclge_vport *vport) 1723 { 1724 struct hnae3_handle *nic = &vport->nic; 1725 struct hnae3_knic_private_info *kinfo; 1726 u16 i; 1727 1728 kinfo = &nic->kinfo; 1729 for (i = 0; i < vport->alloc_tqps; i++) { 1730 struct hclge_comm_tqp *q = 1731 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1732 bool is_pf; 1733 int ret; 1734 1735 is_pf = !(vport->vport_id); 1736 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1737 i, is_pf); 1738 if (ret) 1739 return ret; 1740 } 1741 1742 return 0; 1743 } 1744 1745 static int hclge_map_tqp(struct hclge_dev *hdev) 1746 { 1747 struct hclge_vport *vport = hdev->vport; 1748 u16 i, num_vport; 1749 1750 num_vport = hdev->num_req_vfs + 1; 1751 for (i = 0; i < num_vport; i++) { 1752 int ret; 1753 1754 ret = hclge_map_tqp_to_vport(hdev, vport); 1755 if (ret) 1756 return ret; 1757 1758 vport++; 1759 } 1760 1761 return 0; 1762 } 1763 1764 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1765 { 1766 struct hnae3_handle *nic = &vport->nic; 1767 struct hclge_dev *hdev = vport->back; 1768 int ret; 1769 1770 nic->pdev = hdev->pdev; 1771 nic->ae_algo = &ae_algo; 1772 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1773 MAX_NUMNODES); 1774 nic->kinfo.io_base = hdev->hw.hw.io_base; 1775 1776 ret = hclge_knic_setup(vport, num_tqps, 1777 hdev->num_tx_desc, hdev->num_rx_desc); 1778 if (ret) 1779 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1780 1781 return ret; 1782 } 1783 1784 static int hclge_alloc_vport(struct hclge_dev *hdev) 1785 { 1786 struct pci_dev *pdev = hdev->pdev; 1787 struct hclge_vport *vport; 1788 u32 tqp_main_vport; 1789 u32 tqp_per_vport; 1790 int num_vport, i; 1791 int ret; 1792 1793 /* We need to alloc a vport for main NIC of PF */ 1794 num_vport = hdev->num_req_vfs + 1; 1795 1796 if (hdev->num_tqps < num_vport) { 1797 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1798 hdev->num_tqps, num_vport); 1799 return -EINVAL; 1800 } 1801 1802 /* Alloc the same number of TQPs for every vport */ 1803 tqp_per_vport = hdev->num_tqps / num_vport; 1804 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1805 1806 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1807 GFP_KERNEL); 1808 if (!vport) 1809 return -ENOMEM; 1810 1811 hdev->vport = vport; 1812 hdev->num_alloc_vport = num_vport; 1813 1814 if (IS_ENABLED(CONFIG_PCI_IOV)) 1815 hdev->num_alloc_vfs = hdev->num_req_vfs; 1816 1817 for (i = 0; i < num_vport; i++) { 1818 vport->back = hdev; 1819 vport->vport_id = i; 1820 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1821 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1822 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1823 vport->port_base_vlan_cfg.tbl_sta = true; 1824 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1825 vport->req_vlan_fltr_en = true; 1826 INIT_LIST_HEAD(&vport->vlan_list); 1827 INIT_LIST_HEAD(&vport->uc_mac_list); 1828 INIT_LIST_HEAD(&vport->mc_mac_list); 1829 spin_lock_init(&vport->mac_list_lock); 1830 1831 if (i == 0) 1832 ret = hclge_vport_setup(vport, tqp_main_vport); 1833 else 1834 ret = hclge_vport_setup(vport, tqp_per_vport); 1835 if (ret) { 1836 dev_err(&pdev->dev, 1837 "vport setup failed for vport %d, %d\n", 1838 i, ret); 1839 return ret; 1840 } 1841 1842 vport++; 1843 } 1844 1845 return 0; 1846 } 1847 1848 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1849 struct hclge_pkt_buf_alloc *buf_alloc) 1850 { 1851 /* TX buffer size is unit by 128 byte */ 1852 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1853 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1854 struct hclge_tx_buff_alloc_cmd *req; 1855 struct hclge_desc desc; 1856 int ret; 1857 u8 i; 1858 1859 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1860 1861 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1862 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1863 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1864 1865 req->tx_pkt_buff[i] = 1866 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1867 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1868 } 1869 1870 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1871 if (ret) 1872 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1873 ret); 1874 1875 return ret; 1876 } 1877 1878 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1879 struct hclge_pkt_buf_alloc *buf_alloc) 1880 { 1881 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1882 1883 if (ret) 1884 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1885 1886 return ret; 1887 } 1888 1889 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1890 { 1891 unsigned int i; 1892 u32 cnt = 0; 1893 1894 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1895 if (hdev->hw_tc_map & BIT(i)) 1896 cnt++; 1897 return cnt; 1898 } 1899 1900 /* Get the number of pfc enabled TCs, which have private buffer */ 1901 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1902 struct hclge_pkt_buf_alloc *buf_alloc) 1903 { 1904 struct hclge_priv_buf *priv; 1905 unsigned int i; 1906 int cnt = 0; 1907 1908 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1909 priv = &buf_alloc->priv_buf[i]; 1910 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1911 priv->enable) 1912 cnt++; 1913 } 1914 1915 return cnt; 1916 } 1917 1918 /* Get the number of pfc disabled TCs, which have private buffer */ 1919 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1920 struct hclge_pkt_buf_alloc *buf_alloc) 1921 { 1922 struct hclge_priv_buf *priv; 1923 unsigned int i; 1924 int cnt = 0; 1925 1926 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1927 priv = &buf_alloc->priv_buf[i]; 1928 if (hdev->hw_tc_map & BIT(i) && 1929 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1930 priv->enable) 1931 cnt++; 1932 } 1933 1934 return cnt; 1935 } 1936 1937 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1938 { 1939 struct hclge_priv_buf *priv; 1940 u32 rx_priv = 0; 1941 int i; 1942 1943 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1944 priv = &buf_alloc->priv_buf[i]; 1945 if (priv->enable) 1946 rx_priv += priv->buf_size; 1947 } 1948 return rx_priv; 1949 } 1950 1951 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1952 { 1953 u32 i, total_tx_size = 0; 1954 1955 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1956 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1957 1958 return total_tx_size; 1959 } 1960 1961 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1962 struct hclge_pkt_buf_alloc *buf_alloc, 1963 u32 rx_all) 1964 { 1965 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 1966 u32 tc_num = hclge_get_tc_num(hdev); 1967 u32 shared_buf, aligned_mps; 1968 u32 rx_priv; 1969 int i; 1970 1971 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 1972 1973 if (hnae3_dev_dcb_supported(hdev)) 1974 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 1975 hdev->dv_buf_size; 1976 else 1977 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 1978 + hdev->dv_buf_size; 1979 1980 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 1981 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 1982 HCLGE_BUF_SIZE_UNIT); 1983 1984 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1985 if (rx_all < rx_priv + shared_std) 1986 return false; 1987 1988 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 1989 buf_alloc->s_buf.buf_size = shared_buf; 1990 if (hnae3_dev_dcb_supported(hdev)) { 1991 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 1992 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 1993 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 1994 HCLGE_BUF_SIZE_UNIT); 1995 } else { 1996 buf_alloc->s_buf.self.high = aligned_mps + 1997 HCLGE_NON_DCB_ADDITIONAL_BUF; 1998 buf_alloc->s_buf.self.low = aligned_mps; 1999 } 2000 2001 if (hnae3_dev_dcb_supported(hdev)) { 2002 hi_thrd = shared_buf - hdev->dv_buf_size; 2003 2004 if (tc_num <= NEED_RESERVE_TC_NUM) 2005 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2006 / BUF_MAX_PERCENT; 2007 2008 if (tc_num) 2009 hi_thrd = hi_thrd / tc_num; 2010 2011 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2012 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2013 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2014 } else { 2015 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2016 lo_thrd = aligned_mps; 2017 } 2018 2019 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2020 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2021 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2022 } 2023 2024 return true; 2025 } 2026 2027 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2028 struct hclge_pkt_buf_alloc *buf_alloc) 2029 { 2030 u32 i, total_size; 2031 2032 total_size = hdev->pkt_buf_size; 2033 2034 /* alloc tx buffer for all enabled tc */ 2035 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2036 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2037 2038 if (hdev->hw_tc_map & BIT(i)) { 2039 if (total_size < hdev->tx_buf_size) 2040 return -ENOMEM; 2041 2042 priv->tx_buf_size = hdev->tx_buf_size; 2043 } else { 2044 priv->tx_buf_size = 0; 2045 } 2046 2047 total_size -= priv->tx_buf_size; 2048 } 2049 2050 return 0; 2051 } 2052 2053 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2054 struct hclge_pkt_buf_alloc *buf_alloc) 2055 { 2056 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2057 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2058 unsigned int i; 2059 2060 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2061 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2062 2063 priv->enable = 0; 2064 priv->wl.low = 0; 2065 priv->wl.high = 0; 2066 priv->buf_size = 0; 2067 2068 if (!(hdev->hw_tc_map & BIT(i))) 2069 continue; 2070 2071 priv->enable = 1; 2072 2073 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2074 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2075 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2076 HCLGE_BUF_SIZE_UNIT); 2077 } else { 2078 priv->wl.low = 0; 2079 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2080 aligned_mps; 2081 } 2082 2083 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2084 } 2085 2086 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2087 } 2088 2089 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2090 struct hclge_pkt_buf_alloc *buf_alloc) 2091 { 2092 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2093 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2094 int i; 2095 2096 /* let the last to be cleared first */ 2097 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2098 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2099 unsigned int mask = BIT((unsigned int)i); 2100 2101 if (hdev->hw_tc_map & mask && 2102 !(hdev->tm_info.hw_pfc_map & mask)) { 2103 /* Clear the no pfc TC private buffer */ 2104 priv->wl.low = 0; 2105 priv->wl.high = 0; 2106 priv->buf_size = 0; 2107 priv->enable = 0; 2108 no_pfc_priv_num--; 2109 } 2110 2111 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2112 no_pfc_priv_num == 0) 2113 break; 2114 } 2115 2116 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2117 } 2118 2119 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2120 struct hclge_pkt_buf_alloc *buf_alloc) 2121 { 2122 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2123 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2124 int i; 2125 2126 /* let the last to be cleared first */ 2127 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2128 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2129 unsigned int mask = BIT((unsigned int)i); 2130 2131 if (hdev->hw_tc_map & mask && 2132 hdev->tm_info.hw_pfc_map & mask) { 2133 /* Reduce the number of pfc TC with private buffer */ 2134 priv->wl.low = 0; 2135 priv->enable = 0; 2136 priv->wl.high = 0; 2137 priv->buf_size = 0; 2138 pfc_priv_num--; 2139 } 2140 2141 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2142 pfc_priv_num == 0) 2143 break; 2144 } 2145 2146 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2147 } 2148 2149 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2150 struct hclge_pkt_buf_alloc *buf_alloc) 2151 { 2152 #define COMPENSATE_BUFFER 0x3C00 2153 #define COMPENSATE_HALF_MPS_NUM 5 2154 #define PRIV_WL_GAP 0x1800 2155 2156 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2157 u32 tc_num = hclge_get_tc_num(hdev); 2158 u32 half_mps = hdev->mps >> 1; 2159 u32 min_rx_priv; 2160 unsigned int i; 2161 2162 if (tc_num) 2163 rx_priv = rx_priv / tc_num; 2164 2165 if (tc_num <= NEED_RESERVE_TC_NUM) 2166 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2167 2168 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2169 COMPENSATE_HALF_MPS_NUM * half_mps; 2170 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2171 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2172 if (rx_priv < min_rx_priv) 2173 return false; 2174 2175 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2176 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2177 2178 priv->enable = 0; 2179 priv->wl.low = 0; 2180 priv->wl.high = 0; 2181 priv->buf_size = 0; 2182 2183 if (!(hdev->hw_tc_map & BIT(i))) 2184 continue; 2185 2186 priv->enable = 1; 2187 priv->buf_size = rx_priv; 2188 priv->wl.high = rx_priv - hdev->dv_buf_size; 2189 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2190 } 2191 2192 buf_alloc->s_buf.buf_size = 0; 2193 2194 return true; 2195 } 2196 2197 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2198 * @hdev: pointer to struct hclge_dev 2199 * @buf_alloc: pointer to buffer calculation data 2200 * @return: 0: calculate successful, negative: fail 2201 */ 2202 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2203 struct hclge_pkt_buf_alloc *buf_alloc) 2204 { 2205 /* When DCB is not supported, rx private buffer is not allocated. */ 2206 if (!hnae3_dev_dcb_supported(hdev)) { 2207 u32 rx_all = hdev->pkt_buf_size; 2208 2209 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2210 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2211 return -ENOMEM; 2212 2213 return 0; 2214 } 2215 2216 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2217 return 0; 2218 2219 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2220 return 0; 2221 2222 /* try to decrease the buffer size */ 2223 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2224 return 0; 2225 2226 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2227 return 0; 2228 2229 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2230 return 0; 2231 2232 return -ENOMEM; 2233 } 2234 2235 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2236 struct hclge_pkt_buf_alloc *buf_alloc) 2237 { 2238 struct hclge_rx_priv_buff_cmd *req; 2239 struct hclge_desc desc; 2240 int ret; 2241 int i; 2242 2243 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2244 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2245 2246 /* Alloc private buffer TCs */ 2247 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2248 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2249 2250 req->buf_num[i] = 2251 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2252 req->buf_num[i] |= 2253 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2254 } 2255 2256 req->shared_buf = 2257 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2258 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2259 2260 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2261 if (ret) 2262 dev_err(&hdev->pdev->dev, 2263 "rx private buffer alloc cmd failed %d\n", ret); 2264 2265 return ret; 2266 } 2267 2268 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2269 struct hclge_pkt_buf_alloc *buf_alloc) 2270 { 2271 struct hclge_rx_priv_wl_buf *req; 2272 struct hclge_priv_buf *priv; 2273 struct hclge_desc desc[2]; 2274 int i, j; 2275 int ret; 2276 2277 for (i = 0; i < 2; i++) { 2278 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2279 false); 2280 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2281 2282 /* The first descriptor set the NEXT bit to 1 */ 2283 if (i == 0) 2284 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2285 else 2286 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2287 2288 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2289 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2290 2291 priv = &buf_alloc->priv_buf[idx]; 2292 req->tc_wl[j].high = 2293 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2294 req->tc_wl[j].high |= 2295 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2296 req->tc_wl[j].low = 2297 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2298 req->tc_wl[j].low |= 2299 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2300 } 2301 } 2302 2303 /* Send 2 descriptor at one time */ 2304 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2305 if (ret) 2306 dev_err(&hdev->pdev->dev, 2307 "rx private waterline config cmd failed %d\n", 2308 ret); 2309 return ret; 2310 } 2311 2312 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2313 struct hclge_pkt_buf_alloc *buf_alloc) 2314 { 2315 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2316 struct hclge_rx_com_thrd *req; 2317 struct hclge_desc desc[2]; 2318 struct hclge_tc_thrd *tc; 2319 int i, j; 2320 int ret; 2321 2322 for (i = 0; i < 2; i++) { 2323 hclge_cmd_setup_basic_desc(&desc[i], 2324 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2325 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2326 2327 /* The first descriptor set the NEXT bit to 1 */ 2328 if (i == 0) 2329 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2330 else 2331 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2332 2333 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2334 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2335 2336 req->com_thrd[j].high = 2337 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2338 req->com_thrd[j].high |= 2339 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2340 req->com_thrd[j].low = 2341 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2342 req->com_thrd[j].low |= 2343 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2344 } 2345 } 2346 2347 /* Send 2 descriptors at one time */ 2348 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2349 if (ret) 2350 dev_err(&hdev->pdev->dev, 2351 "common threshold config cmd failed %d\n", ret); 2352 return ret; 2353 } 2354 2355 static int hclge_common_wl_config(struct hclge_dev *hdev, 2356 struct hclge_pkt_buf_alloc *buf_alloc) 2357 { 2358 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2359 struct hclge_rx_com_wl *req; 2360 struct hclge_desc desc; 2361 int ret; 2362 2363 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2364 2365 req = (struct hclge_rx_com_wl *)desc.data; 2366 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2367 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2368 2369 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2370 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2371 2372 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2373 if (ret) 2374 dev_err(&hdev->pdev->dev, 2375 "common waterline config cmd failed %d\n", ret); 2376 2377 return ret; 2378 } 2379 2380 int hclge_buffer_alloc(struct hclge_dev *hdev) 2381 { 2382 struct hclge_pkt_buf_alloc *pkt_buf; 2383 int ret; 2384 2385 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2386 if (!pkt_buf) 2387 return -ENOMEM; 2388 2389 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2390 if (ret) { 2391 dev_err(&hdev->pdev->dev, 2392 "could not calc tx buffer size for all TCs %d\n", ret); 2393 goto out; 2394 } 2395 2396 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2397 if (ret) { 2398 dev_err(&hdev->pdev->dev, 2399 "could not alloc tx buffers %d\n", ret); 2400 goto out; 2401 } 2402 2403 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2404 if (ret) { 2405 dev_err(&hdev->pdev->dev, 2406 "could not calc rx priv buffer size for all TCs %d\n", 2407 ret); 2408 goto out; 2409 } 2410 2411 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2412 if (ret) { 2413 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2414 ret); 2415 goto out; 2416 } 2417 2418 if (hnae3_dev_dcb_supported(hdev)) { 2419 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2420 if (ret) { 2421 dev_err(&hdev->pdev->dev, 2422 "could not configure rx private waterline %d\n", 2423 ret); 2424 goto out; 2425 } 2426 2427 ret = hclge_common_thrd_config(hdev, pkt_buf); 2428 if (ret) { 2429 dev_err(&hdev->pdev->dev, 2430 "could not configure common threshold %d\n", 2431 ret); 2432 goto out; 2433 } 2434 } 2435 2436 ret = hclge_common_wl_config(hdev, pkt_buf); 2437 if (ret) 2438 dev_err(&hdev->pdev->dev, 2439 "could not configure common waterline %d\n", ret); 2440 2441 out: 2442 kfree(pkt_buf); 2443 return ret; 2444 } 2445 2446 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2447 { 2448 struct hnae3_handle *roce = &vport->roce; 2449 struct hnae3_handle *nic = &vport->nic; 2450 struct hclge_dev *hdev = vport->back; 2451 2452 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2453 2454 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2455 return -EINVAL; 2456 2457 roce->rinfo.base_vector = hdev->num_nic_msi; 2458 2459 roce->rinfo.netdev = nic->kinfo.netdev; 2460 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2461 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2462 2463 roce->pdev = nic->pdev; 2464 roce->ae_algo = nic->ae_algo; 2465 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2466 MAX_NUMNODES); 2467 2468 return 0; 2469 } 2470 2471 static int hclge_init_msi(struct hclge_dev *hdev) 2472 { 2473 struct pci_dev *pdev = hdev->pdev; 2474 int vectors; 2475 int i; 2476 2477 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2478 hdev->num_msi, 2479 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2480 if (vectors < 0) { 2481 dev_err(&pdev->dev, 2482 "failed(%d) to allocate MSI/MSI-X vectors\n", 2483 vectors); 2484 return vectors; 2485 } 2486 if (vectors < hdev->num_msi) 2487 dev_warn(&hdev->pdev->dev, 2488 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2489 hdev->num_msi, vectors); 2490 2491 hdev->num_msi = vectors; 2492 hdev->num_msi_left = vectors; 2493 2494 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2495 sizeof(u16), GFP_KERNEL); 2496 if (!hdev->vector_status) { 2497 pci_free_irq_vectors(pdev); 2498 return -ENOMEM; 2499 } 2500 2501 for (i = 0; i < hdev->num_msi; i++) 2502 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2503 2504 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2505 sizeof(int), GFP_KERNEL); 2506 if (!hdev->vector_irq) { 2507 pci_free_irq_vectors(pdev); 2508 return -ENOMEM; 2509 } 2510 2511 return 0; 2512 } 2513 2514 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2515 { 2516 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2517 duplex = HCLGE_MAC_FULL; 2518 2519 return duplex; 2520 } 2521 2522 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2523 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2524 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2525 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2526 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2527 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2528 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2529 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2530 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2531 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2532 }; 2533 2534 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2535 { 2536 u16 i; 2537 2538 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2539 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2540 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2541 return 0; 2542 } 2543 } 2544 2545 return -EINVAL; 2546 } 2547 2548 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2549 u8 duplex, u8 lane_num) 2550 { 2551 struct hclge_config_mac_speed_dup_cmd *req; 2552 struct hclge_desc desc; 2553 u32 speed_fw; 2554 int ret; 2555 2556 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2557 2558 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2559 2560 if (duplex) 2561 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2562 2563 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2564 if (ret) { 2565 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2566 return ret; 2567 } 2568 2569 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2570 speed_fw); 2571 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2572 1); 2573 req->lane_num = lane_num; 2574 2575 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2576 if (ret) { 2577 dev_err(&hdev->pdev->dev, 2578 "mac speed/duplex config cmd failed %d.\n", ret); 2579 return ret; 2580 } 2581 2582 return 0; 2583 } 2584 2585 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2586 { 2587 struct hclge_mac *mac = &hdev->hw.mac; 2588 int ret; 2589 2590 duplex = hclge_check_speed_dup(duplex, speed); 2591 if (!mac->support_autoneg && mac->speed == speed && 2592 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2593 return 0; 2594 2595 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2596 if (ret) 2597 return ret; 2598 2599 hdev->hw.mac.speed = speed; 2600 hdev->hw.mac.duplex = duplex; 2601 if (!lane_num) 2602 hdev->hw.mac.lane_num = lane_num; 2603 2604 return 0; 2605 } 2606 2607 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2608 u8 duplex, u8 lane_num) 2609 { 2610 struct hclge_vport *vport = hclge_get_vport(handle); 2611 struct hclge_dev *hdev = vport->back; 2612 2613 return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2614 } 2615 2616 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2617 { 2618 struct hclge_config_auto_neg_cmd *req; 2619 struct hclge_desc desc; 2620 u32 flag = 0; 2621 int ret; 2622 2623 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2624 2625 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2626 if (enable) 2627 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2628 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2629 2630 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2631 if (ret) 2632 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2633 ret); 2634 2635 return ret; 2636 } 2637 2638 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2639 { 2640 struct hclge_vport *vport = hclge_get_vport(handle); 2641 struct hclge_dev *hdev = vport->back; 2642 2643 if (!hdev->hw.mac.support_autoneg) { 2644 if (enable) { 2645 dev_err(&hdev->pdev->dev, 2646 "autoneg is not supported by current port\n"); 2647 return -EOPNOTSUPP; 2648 } else { 2649 return 0; 2650 } 2651 } 2652 2653 return hclge_set_autoneg_en(hdev, enable); 2654 } 2655 2656 static int hclge_get_autoneg(struct hnae3_handle *handle) 2657 { 2658 struct hclge_vport *vport = hclge_get_vport(handle); 2659 struct hclge_dev *hdev = vport->back; 2660 struct phy_device *phydev = hdev->hw.mac.phydev; 2661 2662 if (phydev) 2663 return phydev->autoneg; 2664 2665 return hdev->hw.mac.autoneg; 2666 } 2667 2668 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2669 { 2670 struct hclge_vport *vport = hclge_get_vport(handle); 2671 struct hclge_dev *hdev = vport->back; 2672 int ret; 2673 2674 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2675 2676 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2677 if (ret) 2678 return ret; 2679 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2680 } 2681 2682 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2683 { 2684 struct hclge_vport *vport = hclge_get_vport(handle); 2685 struct hclge_dev *hdev = vport->back; 2686 2687 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2688 return hclge_set_autoneg_en(hdev, !halt); 2689 2690 return 0; 2691 } 2692 2693 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2694 struct hclge_desc *desc, u32 desc_len) 2695 { 2696 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2697 u32 desc_index = 0; 2698 u32 data_index = 0; 2699 u32 i; 2700 2701 for (i = 0; i < lane_size; i++) { 2702 if (data_index >= HCLGE_DESC_DATA_LEN) { 2703 desc_index++; 2704 data_index = 0; 2705 } 2706 2707 if (desc_index >= desc_len) 2708 return; 2709 2710 hdev->fec_stats.per_lanes[i] += 2711 le32_to_cpu(desc[desc_index].data[data_index]); 2712 data_index++; 2713 } 2714 } 2715 2716 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2717 struct hclge_desc *desc, u32 desc_len) 2718 { 2719 struct hclge_query_fec_stats_cmd *req; 2720 2721 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2722 2723 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2724 hdev->fec_stats.rs_corr_blocks += 2725 le32_to_cpu(req->rs_fec_corr_blocks); 2726 hdev->fec_stats.rs_uncorr_blocks += 2727 le32_to_cpu(req->rs_fec_uncorr_blocks); 2728 hdev->fec_stats.rs_error_blocks += 2729 le32_to_cpu(req->rs_fec_error_blocks); 2730 hdev->fec_stats.base_r_corr_blocks += 2731 le32_to_cpu(req->base_r_fec_corr_blocks); 2732 hdev->fec_stats.base_r_uncorr_blocks += 2733 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2734 2735 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2736 } 2737 2738 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2739 { 2740 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2741 int ret; 2742 u32 i; 2743 2744 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2745 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2746 true); 2747 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2748 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2749 } 2750 2751 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2752 if (ret) 2753 return ret; 2754 2755 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2756 2757 return 0; 2758 } 2759 2760 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2761 { 2762 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2763 int ret; 2764 2765 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2766 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2767 return; 2768 2769 ret = hclge_update_fec_stats_hw(hdev); 2770 if (ret) 2771 dev_err(&hdev->pdev->dev, 2772 "failed to update fec stats, ret = %d\n", ret); 2773 2774 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2775 } 2776 2777 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2778 struct ethtool_fec_stats *fec_stats) 2779 { 2780 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2781 fec_stats->uncorrectable_blocks.total = 2782 hdev->fec_stats.rs_uncorr_blocks; 2783 } 2784 2785 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2786 struct ethtool_fec_stats *fec_stats) 2787 { 2788 u32 i; 2789 2790 if (hdev->fec_stats.base_r_lane_num == 0 || 2791 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2792 dev_err(&hdev->pdev->dev, 2793 "fec stats lane number(%llu) is invalid\n", 2794 hdev->fec_stats.base_r_lane_num); 2795 return; 2796 } 2797 2798 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2799 fec_stats->corrected_blocks.lanes[i] = 2800 hdev->fec_stats.base_r_corr_per_lanes[i]; 2801 fec_stats->uncorrectable_blocks.lanes[i] = 2802 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2803 } 2804 } 2805 2806 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2807 struct ethtool_fec_stats *fec_stats) 2808 { 2809 u32 fec_mode = hdev->hw.mac.fec_mode; 2810 2811 switch (fec_mode) { 2812 case BIT(HNAE3_FEC_RS): 2813 case BIT(HNAE3_FEC_LLRS): 2814 hclge_get_fec_stats_total(hdev, fec_stats); 2815 break; 2816 case BIT(HNAE3_FEC_BASER): 2817 hclge_get_fec_stats_lanes(hdev, fec_stats); 2818 break; 2819 default: 2820 dev_err(&hdev->pdev->dev, 2821 "fec stats is not supported by current fec mode(0x%x)\n", 2822 fec_mode); 2823 break; 2824 } 2825 } 2826 2827 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2828 struct ethtool_fec_stats *fec_stats) 2829 { 2830 struct hclge_vport *vport = hclge_get_vport(handle); 2831 struct hclge_dev *hdev = vport->back; 2832 u32 fec_mode = hdev->hw.mac.fec_mode; 2833 2834 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2835 fec_mode == BIT(HNAE3_FEC_AUTO) || 2836 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2837 return; 2838 2839 hclge_update_fec_stats(hdev); 2840 2841 hclge_comm_get_fec_stats(hdev, fec_stats); 2842 } 2843 2844 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2845 { 2846 struct hclge_config_fec_cmd *req; 2847 struct hclge_desc desc; 2848 int ret; 2849 2850 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2851 2852 req = (struct hclge_config_fec_cmd *)desc.data; 2853 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2854 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2855 if (fec_mode & BIT(HNAE3_FEC_RS)) 2856 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2857 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2858 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2859 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2860 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2861 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2862 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2863 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2864 2865 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2866 if (ret) 2867 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2868 2869 return ret; 2870 } 2871 2872 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2873 { 2874 struct hclge_vport *vport = hclge_get_vport(handle); 2875 struct hclge_dev *hdev = vport->back; 2876 struct hclge_mac *mac = &hdev->hw.mac; 2877 int ret; 2878 2879 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2880 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2881 return -EINVAL; 2882 } 2883 2884 ret = hclge_set_fec_hw(hdev, fec_mode); 2885 if (ret) 2886 return ret; 2887 2888 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2889 return 0; 2890 } 2891 2892 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2893 u8 *fec_mode) 2894 { 2895 struct hclge_vport *vport = hclge_get_vport(handle); 2896 struct hclge_dev *hdev = vport->back; 2897 struct hclge_mac *mac = &hdev->hw.mac; 2898 2899 if (fec_ability) 2900 *fec_ability = mac->fec_ability; 2901 if (fec_mode) 2902 *fec_mode = mac->fec_mode; 2903 } 2904 2905 static int hclge_mac_init(struct hclge_dev *hdev) 2906 { 2907 struct hclge_mac *mac = &hdev->hw.mac; 2908 int ret; 2909 2910 hdev->support_sfp_query = true; 2911 2912 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2913 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2914 2915 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2916 hdev->hw.mac.duplex, hdev->hw.mac.lane_num); 2917 if (ret) 2918 return ret; 2919 2920 if (hdev->hw.mac.support_autoneg) { 2921 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2922 if (ret) 2923 return ret; 2924 } 2925 2926 mac->link = 0; 2927 2928 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2929 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2930 if (ret) 2931 return ret; 2932 } 2933 2934 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2935 if (ret) { 2936 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2937 return ret; 2938 } 2939 2940 ret = hclge_set_default_loopback(hdev); 2941 if (ret) 2942 return ret; 2943 2944 ret = hclge_buffer_alloc(hdev); 2945 if (ret) 2946 dev_err(&hdev->pdev->dev, 2947 "allocate buffer fail, ret=%d\n", ret); 2948 2949 return ret; 2950 } 2951 2952 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2953 { 2954 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2955 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 2956 hdev->last_mbx_scheduled = jiffies; 2957 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2958 } 2959 } 2960 2961 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2962 { 2963 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2964 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 2965 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 2966 hdev->last_rst_scheduled = jiffies; 2967 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2968 } 2969 } 2970 2971 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 2972 { 2973 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2974 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 2975 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2976 } 2977 2978 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 2979 { 2980 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2981 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 2982 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 2983 } 2984 2985 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 2986 { 2987 struct hclge_link_status_cmd *req; 2988 struct hclge_desc desc; 2989 int ret; 2990 2991 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2992 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2993 if (ret) { 2994 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2995 ret); 2996 return ret; 2997 } 2998 2999 req = (struct hclge_link_status_cmd *)desc.data; 3000 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3001 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3002 3003 return 0; 3004 } 3005 3006 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3007 { 3008 struct phy_device *phydev = hdev->hw.mac.phydev; 3009 3010 *link_status = HCLGE_LINK_STATUS_DOWN; 3011 3012 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3013 return 0; 3014 3015 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3016 return 0; 3017 3018 return hclge_get_mac_link_status(hdev, link_status); 3019 } 3020 3021 static void hclge_push_link_status(struct hclge_dev *hdev) 3022 { 3023 struct hclge_vport *vport; 3024 int ret; 3025 u16 i; 3026 3027 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3028 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3029 3030 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3031 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3032 continue; 3033 3034 ret = hclge_push_vf_link_status(vport); 3035 if (ret) { 3036 dev_err(&hdev->pdev->dev, 3037 "failed to push link status to vf%u, ret = %d\n", 3038 i, ret); 3039 } 3040 } 3041 } 3042 3043 static void hclge_update_link_status(struct hclge_dev *hdev) 3044 { 3045 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3046 struct hnae3_handle *handle = &hdev->vport[0].nic; 3047 struct hnae3_client *rclient = hdev->roce_client; 3048 struct hnae3_client *client = hdev->nic_client; 3049 int state; 3050 int ret; 3051 3052 if (!client) 3053 return; 3054 3055 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3056 return; 3057 3058 ret = hclge_get_mac_phy_link(hdev, &state); 3059 if (ret) { 3060 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3061 return; 3062 } 3063 3064 if (state != hdev->hw.mac.link) { 3065 hdev->hw.mac.link = state; 3066 if (state == HCLGE_LINK_STATUS_UP) 3067 hclge_update_port_info(hdev); 3068 3069 client->ops->link_status_change(handle, state); 3070 hclge_config_mac_tnl_int(hdev, state); 3071 if (rclient && rclient->ops->link_status_change) 3072 rclient->ops->link_status_change(rhandle, state); 3073 3074 hclge_push_link_status(hdev); 3075 } 3076 3077 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3078 } 3079 3080 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3081 { 3082 u32 speed_ability; 3083 3084 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3085 return; 3086 3087 switch (mac->module_type) { 3088 case HNAE3_MODULE_TYPE_FIBRE_LR: 3089 hclge_convert_setting_lr(speed_ability, mac->advertising); 3090 break; 3091 case HNAE3_MODULE_TYPE_FIBRE_SR: 3092 case HNAE3_MODULE_TYPE_AOC: 3093 hclge_convert_setting_sr(speed_ability, mac->advertising); 3094 break; 3095 case HNAE3_MODULE_TYPE_CR: 3096 hclge_convert_setting_cr(speed_ability, mac->advertising); 3097 break; 3098 case HNAE3_MODULE_TYPE_KR: 3099 hclge_convert_setting_kr(speed_ability, mac->advertising); 3100 break; 3101 default: 3102 break; 3103 } 3104 } 3105 3106 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3107 { 3108 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3109 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3110 mac->advertising); 3111 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3112 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3113 mac->advertising); 3114 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3115 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3116 mac->advertising); 3117 else 3118 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3119 mac->advertising); 3120 } 3121 3122 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3123 { 3124 struct hclge_mac *mac = &hdev->hw.mac; 3125 bool rx_en, tx_en; 3126 3127 switch (hdev->fc_mode_last_time) { 3128 case HCLGE_FC_RX_PAUSE: 3129 rx_en = true; 3130 tx_en = false; 3131 break; 3132 case HCLGE_FC_TX_PAUSE: 3133 rx_en = false; 3134 tx_en = true; 3135 break; 3136 case HCLGE_FC_FULL: 3137 rx_en = true; 3138 tx_en = true; 3139 break; 3140 default: 3141 rx_en = false; 3142 tx_en = false; 3143 break; 3144 } 3145 3146 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3147 } 3148 3149 static void hclge_update_advertising(struct hclge_dev *hdev) 3150 { 3151 struct hclge_mac *mac = &hdev->hw.mac; 3152 3153 linkmode_zero(mac->advertising); 3154 hclge_update_speed_advertising(mac); 3155 hclge_update_fec_advertising(mac); 3156 hclge_update_pause_advertising(hdev); 3157 } 3158 3159 static void hclge_update_port_capability(struct hclge_dev *hdev, 3160 struct hclge_mac *mac) 3161 { 3162 if (hnae3_dev_fec_supported(hdev)) 3163 hclge_convert_setting_fec(mac); 3164 3165 /* firmware can not identify back plane type, the media type 3166 * read from configuration can help deal it 3167 */ 3168 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3169 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3170 mac->module_type = HNAE3_MODULE_TYPE_KR; 3171 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3172 mac->module_type = HNAE3_MODULE_TYPE_TP; 3173 3174 if (mac->support_autoneg) { 3175 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3176 linkmode_copy(mac->advertising, mac->supported); 3177 } else { 3178 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3179 mac->supported); 3180 hclge_update_advertising(hdev); 3181 } 3182 } 3183 3184 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3185 { 3186 struct hclge_sfp_info_cmd *resp; 3187 struct hclge_desc desc; 3188 int ret; 3189 3190 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3191 resp = (struct hclge_sfp_info_cmd *)desc.data; 3192 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3193 if (ret == -EOPNOTSUPP) { 3194 dev_warn(&hdev->pdev->dev, 3195 "IMP do not support get SFP speed %d\n", ret); 3196 return ret; 3197 } else if (ret) { 3198 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3199 return ret; 3200 } 3201 3202 *speed = le32_to_cpu(resp->speed); 3203 3204 return 0; 3205 } 3206 3207 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3208 { 3209 struct hclge_sfp_info_cmd *resp; 3210 struct hclge_desc desc; 3211 int ret; 3212 3213 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3214 resp = (struct hclge_sfp_info_cmd *)desc.data; 3215 3216 resp->query_type = QUERY_ACTIVE_SPEED; 3217 3218 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3219 if (ret == -EOPNOTSUPP) { 3220 dev_warn(&hdev->pdev->dev, 3221 "IMP does not support get SFP info %d\n", ret); 3222 return ret; 3223 } else if (ret) { 3224 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3225 return ret; 3226 } 3227 3228 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3229 * set to mac->speed. 3230 */ 3231 if (!le32_to_cpu(resp->speed)) 3232 return 0; 3233 3234 mac->speed = le32_to_cpu(resp->speed); 3235 /* if resp->speed_ability is 0, it means it's an old version 3236 * firmware, do not update these params 3237 */ 3238 if (resp->speed_ability) { 3239 mac->module_type = le32_to_cpu(resp->module_type); 3240 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3241 mac->autoneg = resp->autoneg; 3242 mac->support_autoneg = resp->autoneg_ability; 3243 mac->speed_type = QUERY_ACTIVE_SPEED; 3244 mac->lane_num = resp->lane_num; 3245 if (!resp->active_fec) 3246 mac->fec_mode = 0; 3247 else 3248 mac->fec_mode = BIT(resp->active_fec); 3249 mac->fec_ability = resp->fec_ability; 3250 } else { 3251 mac->speed_type = QUERY_SFP_SPEED; 3252 } 3253 3254 return 0; 3255 } 3256 3257 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3258 struct ethtool_link_ksettings *cmd) 3259 { 3260 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3261 struct hclge_vport *vport = hclge_get_vport(handle); 3262 struct hclge_phy_link_ksetting_0_cmd *req0; 3263 struct hclge_phy_link_ksetting_1_cmd *req1; 3264 u32 supported, advertising, lp_advertising; 3265 struct hclge_dev *hdev = vport->back; 3266 int ret; 3267 3268 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3269 true); 3270 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3271 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3272 true); 3273 3274 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3275 if (ret) { 3276 dev_err(&hdev->pdev->dev, 3277 "failed to get phy link ksetting, ret = %d.\n", ret); 3278 return ret; 3279 } 3280 3281 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3282 cmd->base.autoneg = req0->autoneg; 3283 cmd->base.speed = le32_to_cpu(req0->speed); 3284 cmd->base.duplex = req0->duplex; 3285 cmd->base.port = req0->port; 3286 cmd->base.transceiver = req0->transceiver; 3287 cmd->base.phy_address = req0->phy_address; 3288 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3289 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3290 supported = le32_to_cpu(req0->supported); 3291 advertising = le32_to_cpu(req0->advertising); 3292 lp_advertising = le32_to_cpu(req0->lp_advertising); 3293 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3294 supported); 3295 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3296 advertising); 3297 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3298 lp_advertising); 3299 3300 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3301 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3302 cmd->base.master_slave_state = req1->master_slave_state; 3303 3304 return 0; 3305 } 3306 3307 static int 3308 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3309 const struct ethtool_link_ksettings *cmd) 3310 { 3311 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3312 struct hclge_vport *vport = hclge_get_vport(handle); 3313 struct hclge_phy_link_ksetting_0_cmd *req0; 3314 struct hclge_phy_link_ksetting_1_cmd *req1; 3315 struct hclge_dev *hdev = vport->back; 3316 u32 advertising; 3317 int ret; 3318 3319 if (cmd->base.autoneg == AUTONEG_DISABLE && 3320 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3321 (cmd->base.duplex != DUPLEX_HALF && 3322 cmd->base.duplex != DUPLEX_FULL))) 3323 return -EINVAL; 3324 3325 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3326 false); 3327 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3328 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3329 false); 3330 3331 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3332 req0->autoneg = cmd->base.autoneg; 3333 req0->speed = cpu_to_le32(cmd->base.speed); 3334 req0->duplex = cmd->base.duplex; 3335 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3336 cmd->link_modes.advertising); 3337 req0->advertising = cpu_to_le32(advertising); 3338 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3339 3340 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3341 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3342 3343 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3344 if (ret) { 3345 dev_err(&hdev->pdev->dev, 3346 "failed to set phy link ksettings, ret = %d.\n", ret); 3347 return ret; 3348 } 3349 3350 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3351 hdev->hw.mac.req_speed = cmd->base.speed; 3352 hdev->hw.mac.req_duplex = cmd->base.duplex; 3353 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3354 3355 return 0; 3356 } 3357 3358 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3359 { 3360 struct ethtool_link_ksettings cmd; 3361 int ret; 3362 3363 if (!hnae3_dev_phy_imp_supported(hdev)) 3364 return 0; 3365 3366 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3367 if (ret) 3368 return ret; 3369 3370 hdev->hw.mac.autoneg = cmd.base.autoneg; 3371 hdev->hw.mac.speed = cmd.base.speed; 3372 hdev->hw.mac.duplex = cmd.base.duplex; 3373 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3374 3375 return 0; 3376 } 3377 3378 static int hclge_tp_port_init(struct hclge_dev *hdev) 3379 { 3380 struct ethtool_link_ksettings cmd; 3381 3382 if (!hnae3_dev_phy_imp_supported(hdev)) 3383 return 0; 3384 3385 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3386 cmd.base.speed = hdev->hw.mac.req_speed; 3387 cmd.base.duplex = hdev->hw.mac.req_duplex; 3388 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3389 3390 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3391 } 3392 3393 static int hclge_update_port_info(struct hclge_dev *hdev) 3394 { 3395 struct hclge_mac *mac = &hdev->hw.mac; 3396 int speed; 3397 int ret; 3398 3399 /* get the port info from SFP cmd if not copper port */ 3400 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3401 return hclge_update_tp_port_info(hdev); 3402 3403 /* if IMP does not support get SFP/qSFP info, return directly */ 3404 if (!hdev->support_sfp_query) 3405 return 0; 3406 3407 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3408 speed = mac->speed; 3409 ret = hclge_get_sfp_info(hdev, mac); 3410 } else { 3411 speed = HCLGE_MAC_SPEED_UNKNOWN; 3412 ret = hclge_get_sfp_speed(hdev, &speed); 3413 } 3414 3415 if (ret == -EOPNOTSUPP) { 3416 hdev->support_sfp_query = false; 3417 return ret; 3418 } else if (ret) { 3419 return ret; 3420 } 3421 3422 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3423 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3424 hclge_update_port_capability(hdev, mac); 3425 if (mac->speed != speed) 3426 (void)hclge_tm_port_shaper_cfg(hdev); 3427 return 0; 3428 } 3429 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3430 HCLGE_MAC_FULL, mac->lane_num); 3431 } else { 3432 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3433 return 0; /* do nothing if no SFP */ 3434 3435 /* must config full duplex for SFP */ 3436 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3437 } 3438 } 3439 3440 static int hclge_get_status(struct hnae3_handle *handle) 3441 { 3442 struct hclge_vport *vport = hclge_get_vport(handle); 3443 struct hclge_dev *hdev = vport->back; 3444 3445 hclge_update_link_status(hdev); 3446 3447 return hdev->hw.mac.link; 3448 } 3449 3450 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3451 { 3452 if (!pci_num_vf(hdev->pdev)) { 3453 dev_err(&hdev->pdev->dev, 3454 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3455 return NULL; 3456 } 3457 3458 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3459 dev_err(&hdev->pdev->dev, 3460 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3461 vf, pci_num_vf(hdev->pdev)); 3462 return NULL; 3463 } 3464 3465 /* VF start from 1 in vport */ 3466 vf += HCLGE_VF_VPORT_START_NUM; 3467 return &hdev->vport[vf]; 3468 } 3469 3470 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3471 struct ifla_vf_info *ivf) 3472 { 3473 struct hclge_vport *vport = hclge_get_vport(handle); 3474 struct hclge_dev *hdev = vport->back; 3475 3476 vport = hclge_get_vf_vport(hdev, vf); 3477 if (!vport) 3478 return -EINVAL; 3479 3480 ivf->vf = vf; 3481 ivf->linkstate = vport->vf_info.link_state; 3482 ivf->spoofchk = vport->vf_info.spoofchk; 3483 ivf->trusted = vport->vf_info.trusted; 3484 ivf->min_tx_rate = 0; 3485 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3486 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3487 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3488 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3489 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3490 3491 return 0; 3492 } 3493 3494 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3495 int link_state) 3496 { 3497 struct hclge_vport *vport = hclge_get_vport(handle); 3498 struct hclge_dev *hdev = vport->back; 3499 int link_state_old; 3500 int ret; 3501 3502 vport = hclge_get_vf_vport(hdev, vf); 3503 if (!vport) 3504 return -EINVAL; 3505 3506 link_state_old = vport->vf_info.link_state; 3507 vport->vf_info.link_state = link_state; 3508 3509 /* return success directly if the VF is unalive, VF will 3510 * query link state itself when it starts work. 3511 */ 3512 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3513 return 0; 3514 3515 ret = hclge_push_vf_link_status(vport); 3516 if (ret) { 3517 vport->vf_info.link_state = link_state_old; 3518 dev_err(&hdev->pdev->dev, 3519 "failed to push vf%d link status, ret = %d\n", vf, ret); 3520 } 3521 3522 return ret; 3523 } 3524 3525 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3526 { 3527 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3528 3529 /* fetch the events from their corresponding regs */ 3530 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3531 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3532 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3533 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3534 3535 /* Assumption: If by any chance reset and mailbox events are reported 3536 * together then we will only process reset event in this go and will 3537 * defer the processing of the mailbox events. Since, we would have not 3538 * cleared RX CMDQ event this time we would receive again another 3539 * interrupt from H/W just for the mailbox. 3540 * 3541 * check for vector0 reset event sources 3542 */ 3543 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3544 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3545 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3546 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3547 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3548 hdev->rst_stats.imp_rst_cnt++; 3549 return HCLGE_VECTOR0_EVENT_RST; 3550 } 3551 3552 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3553 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3554 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3555 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3556 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3557 hdev->rst_stats.global_rst_cnt++; 3558 return HCLGE_VECTOR0_EVENT_RST; 3559 } 3560 3561 /* check for vector0 msix event and hardware error event source */ 3562 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3563 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3564 return HCLGE_VECTOR0_EVENT_ERR; 3565 3566 /* check for vector0 ptp event source */ 3567 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3568 *clearval = msix_src_reg; 3569 return HCLGE_VECTOR0_EVENT_PTP; 3570 } 3571 3572 /* check for vector0 mailbox(=CMDQ RX) event source */ 3573 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3574 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3575 *clearval = cmdq_src_reg; 3576 return HCLGE_VECTOR0_EVENT_MBX; 3577 } 3578 3579 /* print other vector0 event source */ 3580 dev_info(&hdev->pdev->dev, 3581 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3582 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3583 3584 return HCLGE_VECTOR0_EVENT_OTHER; 3585 } 3586 3587 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3588 u32 regclr) 3589 { 3590 #define HCLGE_IMP_RESET_DELAY 5 3591 3592 switch (event_type) { 3593 case HCLGE_VECTOR0_EVENT_PTP: 3594 case HCLGE_VECTOR0_EVENT_RST: 3595 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3596 mdelay(HCLGE_IMP_RESET_DELAY); 3597 3598 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3599 break; 3600 case HCLGE_VECTOR0_EVENT_MBX: 3601 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3602 break; 3603 default: 3604 break; 3605 } 3606 } 3607 3608 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3609 { 3610 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3611 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3612 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3613 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3614 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3615 } 3616 3617 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3618 { 3619 writel(enable ? 1 : 0, vector->addr); 3620 } 3621 3622 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3623 { 3624 struct hclge_dev *hdev = data; 3625 unsigned long flags; 3626 u32 clearval = 0; 3627 u32 event_cause; 3628 3629 hclge_enable_vector(&hdev->misc_vector, false); 3630 event_cause = hclge_check_event_cause(hdev, &clearval); 3631 3632 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3633 switch (event_cause) { 3634 case HCLGE_VECTOR0_EVENT_ERR: 3635 hclge_errhand_task_schedule(hdev); 3636 break; 3637 case HCLGE_VECTOR0_EVENT_RST: 3638 hclge_reset_task_schedule(hdev); 3639 break; 3640 case HCLGE_VECTOR0_EVENT_PTP: 3641 spin_lock_irqsave(&hdev->ptp->lock, flags); 3642 hclge_ptp_clean_tx_hwts(hdev); 3643 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3644 break; 3645 case HCLGE_VECTOR0_EVENT_MBX: 3646 /* If we are here then, 3647 * 1. Either we are not handling any mbx task and we are not 3648 * scheduled as well 3649 * OR 3650 * 2. We could be handling a mbx task but nothing more is 3651 * scheduled. 3652 * In both cases, we should schedule mbx task as there are more 3653 * mbx messages reported by this interrupt. 3654 */ 3655 hclge_mbx_task_schedule(hdev); 3656 break; 3657 default: 3658 dev_warn(&hdev->pdev->dev, 3659 "received unknown or unhandled event of vector0\n"); 3660 break; 3661 } 3662 3663 hclge_clear_event_cause(hdev, event_cause, clearval); 3664 3665 /* Enable interrupt if it is not caused by reset event or error event */ 3666 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3667 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3668 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3669 hclge_enable_vector(&hdev->misc_vector, true); 3670 3671 return IRQ_HANDLED; 3672 } 3673 3674 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3675 { 3676 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3677 dev_warn(&hdev->pdev->dev, 3678 "vector(vector_id %d) has been freed.\n", vector_id); 3679 return; 3680 } 3681 3682 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3683 hdev->num_msi_left += 1; 3684 hdev->num_msi_used -= 1; 3685 } 3686 3687 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3688 { 3689 struct hclge_misc_vector *vector = &hdev->misc_vector; 3690 3691 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3692 3693 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3694 hdev->vector_status[0] = 0; 3695 3696 hdev->num_msi_left -= 1; 3697 hdev->num_msi_used += 1; 3698 } 3699 3700 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3701 { 3702 int ret; 3703 3704 hclge_get_misc_vector(hdev); 3705 3706 /* this would be explicitly freed in the end */ 3707 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3708 HCLGE_NAME, pci_name(hdev->pdev)); 3709 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3710 0, hdev->misc_vector.name, hdev); 3711 if (ret) { 3712 hclge_free_vector(hdev, 0); 3713 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3714 hdev->misc_vector.vector_irq); 3715 } 3716 3717 return ret; 3718 } 3719 3720 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3721 { 3722 free_irq(hdev->misc_vector.vector_irq, hdev); 3723 hclge_free_vector(hdev, 0); 3724 } 3725 3726 int hclge_notify_client(struct hclge_dev *hdev, 3727 enum hnae3_reset_notify_type type) 3728 { 3729 struct hnae3_handle *handle = &hdev->vport[0].nic; 3730 struct hnae3_client *client = hdev->nic_client; 3731 int ret; 3732 3733 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3734 return 0; 3735 3736 if (!client->ops->reset_notify) 3737 return -EOPNOTSUPP; 3738 3739 ret = client->ops->reset_notify(handle, type); 3740 if (ret) 3741 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3742 type, ret); 3743 3744 return ret; 3745 } 3746 3747 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3748 enum hnae3_reset_notify_type type) 3749 { 3750 struct hnae3_handle *handle = &hdev->vport[0].roce; 3751 struct hnae3_client *client = hdev->roce_client; 3752 int ret; 3753 3754 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3755 return 0; 3756 3757 if (!client->ops->reset_notify) 3758 return -EOPNOTSUPP; 3759 3760 ret = client->ops->reset_notify(handle, type); 3761 if (ret) 3762 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3763 type, ret); 3764 3765 return ret; 3766 } 3767 3768 static int hclge_reset_wait(struct hclge_dev *hdev) 3769 { 3770 #define HCLGE_RESET_WATI_MS 100 3771 #define HCLGE_RESET_WAIT_CNT 350 3772 3773 u32 val, reg, reg_bit; 3774 u32 cnt = 0; 3775 3776 switch (hdev->reset_type) { 3777 case HNAE3_IMP_RESET: 3778 reg = HCLGE_GLOBAL_RESET_REG; 3779 reg_bit = HCLGE_IMP_RESET_BIT; 3780 break; 3781 case HNAE3_GLOBAL_RESET: 3782 reg = HCLGE_GLOBAL_RESET_REG; 3783 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3784 break; 3785 case HNAE3_FUNC_RESET: 3786 reg = HCLGE_FUN_RST_ING; 3787 reg_bit = HCLGE_FUN_RST_ING_B; 3788 break; 3789 default: 3790 dev_err(&hdev->pdev->dev, 3791 "Wait for unsupported reset type: %d\n", 3792 hdev->reset_type); 3793 return -EINVAL; 3794 } 3795 3796 val = hclge_read_dev(&hdev->hw, reg); 3797 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3798 msleep(HCLGE_RESET_WATI_MS); 3799 val = hclge_read_dev(&hdev->hw, reg); 3800 cnt++; 3801 } 3802 3803 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3804 dev_warn(&hdev->pdev->dev, 3805 "Wait for reset timeout: %d\n", hdev->reset_type); 3806 return -EBUSY; 3807 } 3808 3809 return 0; 3810 } 3811 3812 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3813 { 3814 struct hclge_vf_rst_cmd *req; 3815 struct hclge_desc desc; 3816 3817 req = (struct hclge_vf_rst_cmd *)desc.data; 3818 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3819 req->dest_vfid = func_id; 3820 3821 if (reset) 3822 req->vf_rst = 0x1; 3823 3824 return hclge_cmd_send(&hdev->hw, &desc, 1); 3825 } 3826 3827 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3828 { 3829 int i; 3830 3831 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3832 struct hclge_vport *vport = &hdev->vport[i]; 3833 int ret; 3834 3835 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3836 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3837 if (ret) { 3838 dev_err(&hdev->pdev->dev, 3839 "set vf(%u) rst failed %d!\n", 3840 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3841 ret); 3842 return ret; 3843 } 3844 3845 if (!reset || 3846 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3847 continue; 3848 3849 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3850 hdev->reset_type == HNAE3_FUNC_RESET) { 3851 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3852 &vport->need_notify); 3853 continue; 3854 } 3855 3856 /* Inform VF to process the reset. 3857 * hclge_inform_reset_assert_to_vf may fail if VF 3858 * driver is not loaded. 3859 */ 3860 ret = hclge_inform_reset_assert_to_vf(vport); 3861 if (ret) 3862 dev_warn(&hdev->pdev->dev, 3863 "inform reset to vf(%u) failed %d!\n", 3864 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3865 ret); 3866 } 3867 3868 return 0; 3869 } 3870 3871 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3872 { 3873 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3874 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3875 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3876 return; 3877 3878 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3879 HCLGE_MBX_SCHED_TIMEOUT)) 3880 dev_warn(&hdev->pdev->dev, 3881 "mbx service task is scheduled after %ums on cpu%u!\n", 3882 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3883 smp_processor_id()); 3884 3885 hclge_mbx_handler(hdev); 3886 3887 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3888 } 3889 3890 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3891 { 3892 struct hclge_pf_rst_sync_cmd *req; 3893 struct hclge_desc desc; 3894 int cnt = 0; 3895 int ret; 3896 3897 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3898 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3899 3900 do { 3901 /* vf need to down netdev by mbx during PF or FLR reset */ 3902 hclge_mailbox_service_task(hdev); 3903 3904 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3905 /* for compatible with old firmware, wait 3906 * 100 ms for VF to stop IO 3907 */ 3908 if (ret == -EOPNOTSUPP) { 3909 msleep(HCLGE_RESET_SYNC_TIME); 3910 return; 3911 } else if (ret) { 3912 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3913 ret); 3914 return; 3915 } else if (req->all_vf_ready) { 3916 return; 3917 } 3918 msleep(HCLGE_PF_RESET_SYNC_TIME); 3919 hclge_comm_cmd_reuse_desc(&desc, true); 3920 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3921 3922 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3923 } 3924 3925 void hclge_report_hw_error(struct hclge_dev *hdev, 3926 enum hnae3_hw_error_type type) 3927 { 3928 struct hnae3_client *client = hdev->nic_client; 3929 3930 if (!client || !client->ops->process_hw_error || 3931 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3932 return; 3933 3934 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3935 } 3936 3937 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3938 { 3939 u32 reg_val; 3940 3941 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3942 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3943 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3944 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3945 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3946 } 3947 3948 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 3949 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 3950 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 3951 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3952 } 3953 } 3954 3955 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 3956 { 3957 struct hclge_desc desc; 3958 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 3959 int ret; 3960 3961 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 3962 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 3963 req->fun_reset_vfid = func_id; 3964 3965 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3966 if (ret) 3967 dev_err(&hdev->pdev->dev, 3968 "send function reset cmd fail, status =%d\n", ret); 3969 3970 return ret; 3971 } 3972 3973 static void hclge_do_reset(struct hclge_dev *hdev) 3974 { 3975 struct hnae3_handle *handle = &hdev->vport[0].nic; 3976 struct pci_dev *pdev = hdev->pdev; 3977 u32 val; 3978 3979 if (hclge_get_hw_reset_stat(handle)) { 3980 dev_info(&pdev->dev, "hardware reset not finish\n"); 3981 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 3982 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 3983 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 3984 return; 3985 } 3986 3987 switch (hdev->reset_type) { 3988 case HNAE3_IMP_RESET: 3989 dev_info(&pdev->dev, "IMP reset requested\n"); 3990 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3991 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 3992 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 3993 break; 3994 case HNAE3_GLOBAL_RESET: 3995 dev_info(&pdev->dev, "global reset requested\n"); 3996 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 3997 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 3998 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 3999 break; 4000 case HNAE3_FUNC_RESET: 4001 dev_info(&pdev->dev, "PF reset requested\n"); 4002 /* schedule again to check later */ 4003 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4004 hclge_reset_task_schedule(hdev); 4005 break; 4006 default: 4007 dev_warn(&pdev->dev, 4008 "unsupported reset type: %d\n", hdev->reset_type); 4009 break; 4010 } 4011 } 4012 4013 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4014 unsigned long *addr) 4015 { 4016 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4017 struct hclge_dev *hdev = ae_dev->priv; 4018 4019 /* return the highest priority reset level amongst all */ 4020 if (test_bit(HNAE3_IMP_RESET, addr)) { 4021 rst_level = HNAE3_IMP_RESET; 4022 clear_bit(HNAE3_IMP_RESET, addr); 4023 clear_bit(HNAE3_GLOBAL_RESET, addr); 4024 clear_bit(HNAE3_FUNC_RESET, addr); 4025 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4026 rst_level = HNAE3_GLOBAL_RESET; 4027 clear_bit(HNAE3_GLOBAL_RESET, addr); 4028 clear_bit(HNAE3_FUNC_RESET, addr); 4029 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4030 rst_level = HNAE3_FUNC_RESET; 4031 clear_bit(HNAE3_FUNC_RESET, addr); 4032 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4033 rst_level = HNAE3_FLR_RESET; 4034 clear_bit(HNAE3_FLR_RESET, addr); 4035 } 4036 4037 if (hdev->reset_type != HNAE3_NONE_RESET && 4038 rst_level < hdev->reset_type) 4039 return HNAE3_NONE_RESET; 4040 4041 return rst_level; 4042 } 4043 4044 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4045 { 4046 u32 clearval = 0; 4047 4048 switch (hdev->reset_type) { 4049 case HNAE3_IMP_RESET: 4050 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4051 break; 4052 case HNAE3_GLOBAL_RESET: 4053 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4054 break; 4055 default: 4056 break; 4057 } 4058 4059 if (!clearval) 4060 return; 4061 4062 /* For revision 0x20, the reset interrupt source 4063 * can only be cleared after hardware reset done 4064 */ 4065 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4066 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4067 clearval); 4068 4069 hclge_enable_vector(&hdev->misc_vector, true); 4070 } 4071 4072 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4073 { 4074 u32 reg_val; 4075 4076 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4077 if (enable) 4078 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4079 else 4080 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4081 4082 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4083 } 4084 4085 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4086 { 4087 int ret; 4088 4089 ret = hclge_set_all_vf_rst(hdev, true); 4090 if (ret) 4091 return ret; 4092 4093 hclge_func_reset_sync_vf(hdev); 4094 4095 return 0; 4096 } 4097 4098 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4099 { 4100 u32 reg_val; 4101 int ret = 0; 4102 4103 switch (hdev->reset_type) { 4104 case HNAE3_FUNC_RESET: 4105 ret = hclge_func_reset_notify_vf(hdev); 4106 if (ret) 4107 return ret; 4108 4109 ret = hclge_func_reset_cmd(hdev, 0); 4110 if (ret) { 4111 dev_err(&hdev->pdev->dev, 4112 "asserting function reset fail %d!\n", ret); 4113 return ret; 4114 } 4115 4116 /* After performaning pf reset, it is not necessary to do the 4117 * mailbox handling or send any command to firmware, because 4118 * any mailbox handling or command to firmware is only valid 4119 * after hclge_comm_cmd_init is called. 4120 */ 4121 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4122 hdev->rst_stats.pf_rst_cnt++; 4123 break; 4124 case HNAE3_FLR_RESET: 4125 ret = hclge_func_reset_notify_vf(hdev); 4126 if (ret) 4127 return ret; 4128 break; 4129 case HNAE3_IMP_RESET: 4130 hclge_handle_imp_error(hdev); 4131 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4132 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4133 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4134 break; 4135 default: 4136 break; 4137 } 4138 4139 /* inform hardware that preparatory work is done */ 4140 msleep(HCLGE_RESET_SYNC_TIME); 4141 hclge_reset_handshake(hdev, true); 4142 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4143 4144 return ret; 4145 } 4146 4147 static void hclge_show_rst_info(struct hclge_dev *hdev) 4148 { 4149 char *buf; 4150 4151 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4152 if (!buf) 4153 return; 4154 4155 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4156 4157 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4158 4159 kfree(buf); 4160 } 4161 4162 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4163 { 4164 #define MAX_RESET_FAIL_CNT 5 4165 4166 if (hdev->reset_pending) { 4167 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4168 hdev->reset_pending); 4169 return true; 4170 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4171 HCLGE_RESET_INT_M) { 4172 dev_info(&hdev->pdev->dev, 4173 "reset failed because new reset interrupt\n"); 4174 hclge_clear_reset_cause(hdev); 4175 return false; 4176 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4177 hdev->rst_stats.reset_fail_cnt++; 4178 set_bit(hdev->reset_type, &hdev->reset_pending); 4179 dev_info(&hdev->pdev->dev, 4180 "re-schedule reset task(%u)\n", 4181 hdev->rst_stats.reset_fail_cnt); 4182 return true; 4183 } 4184 4185 hclge_clear_reset_cause(hdev); 4186 4187 /* recover the handshake status when reset fail */ 4188 hclge_reset_handshake(hdev, true); 4189 4190 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4191 4192 hclge_show_rst_info(hdev); 4193 4194 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4195 4196 return false; 4197 } 4198 4199 static void hclge_update_reset_level(struct hclge_dev *hdev) 4200 { 4201 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4202 enum hnae3_reset_type reset_level; 4203 4204 /* reset request will not be set during reset, so clear 4205 * pending reset request to avoid unnecessary reset 4206 * caused by the same reason. 4207 */ 4208 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4209 4210 /* if default_reset_request has a higher level reset request, 4211 * it should be handled as soon as possible. since some errors 4212 * need this kind of reset to fix. 4213 */ 4214 reset_level = hclge_get_reset_level(ae_dev, 4215 &hdev->default_reset_request); 4216 if (reset_level != HNAE3_NONE_RESET) 4217 set_bit(reset_level, &hdev->reset_request); 4218 } 4219 4220 static int hclge_set_rst_done(struct hclge_dev *hdev) 4221 { 4222 struct hclge_pf_rst_done_cmd *req; 4223 struct hclge_desc desc; 4224 int ret; 4225 4226 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4227 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4228 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4229 4230 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4231 /* To be compatible with the old firmware, which does not support 4232 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4233 * return success 4234 */ 4235 if (ret == -EOPNOTSUPP) { 4236 dev_warn(&hdev->pdev->dev, 4237 "current firmware does not support command(0x%x)!\n", 4238 HCLGE_OPC_PF_RST_DONE); 4239 return 0; 4240 } else if (ret) { 4241 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4242 ret); 4243 } 4244 4245 return ret; 4246 } 4247 4248 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4249 { 4250 int ret = 0; 4251 4252 switch (hdev->reset_type) { 4253 case HNAE3_FUNC_RESET: 4254 case HNAE3_FLR_RESET: 4255 ret = hclge_set_all_vf_rst(hdev, false); 4256 break; 4257 case HNAE3_GLOBAL_RESET: 4258 case HNAE3_IMP_RESET: 4259 ret = hclge_set_rst_done(hdev); 4260 break; 4261 default: 4262 break; 4263 } 4264 4265 /* clear up the handshake status after re-initialize done */ 4266 hclge_reset_handshake(hdev, false); 4267 4268 return ret; 4269 } 4270 4271 static int hclge_reset_stack(struct hclge_dev *hdev) 4272 { 4273 int ret; 4274 4275 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4276 if (ret) 4277 return ret; 4278 4279 ret = hclge_reset_ae_dev(hdev->ae_dev); 4280 if (ret) 4281 return ret; 4282 4283 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4284 } 4285 4286 static int hclge_reset_prepare(struct hclge_dev *hdev) 4287 { 4288 int ret; 4289 4290 hdev->rst_stats.reset_cnt++; 4291 /* perform reset of the stack & ae device for a client */ 4292 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4293 if (ret) 4294 return ret; 4295 4296 rtnl_lock(); 4297 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4298 rtnl_unlock(); 4299 if (ret) 4300 return ret; 4301 4302 return hclge_reset_prepare_wait(hdev); 4303 } 4304 4305 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4306 { 4307 int ret; 4308 4309 hdev->rst_stats.hw_reset_done_cnt++; 4310 4311 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4312 if (ret) 4313 return ret; 4314 4315 rtnl_lock(); 4316 ret = hclge_reset_stack(hdev); 4317 rtnl_unlock(); 4318 if (ret) 4319 return ret; 4320 4321 hclge_clear_reset_cause(hdev); 4322 4323 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4324 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4325 * times 4326 */ 4327 if (ret && 4328 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4329 return ret; 4330 4331 ret = hclge_reset_prepare_up(hdev); 4332 if (ret) 4333 return ret; 4334 4335 rtnl_lock(); 4336 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4337 rtnl_unlock(); 4338 if (ret) 4339 return ret; 4340 4341 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4342 if (ret) 4343 return ret; 4344 4345 hdev->last_reset_time = jiffies; 4346 hdev->rst_stats.reset_fail_cnt = 0; 4347 hdev->rst_stats.reset_done_cnt++; 4348 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4349 4350 hclge_update_reset_level(hdev); 4351 4352 return 0; 4353 } 4354 4355 static void hclge_reset(struct hclge_dev *hdev) 4356 { 4357 if (hclge_reset_prepare(hdev)) 4358 goto err_reset; 4359 4360 if (hclge_reset_wait(hdev)) 4361 goto err_reset; 4362 4363 if (hclge_reset_rebuild(hdev)) 4364 goto err_reset; 4365 4366 return; 4367 4368 err_reset: 4369 if (hclge_reset_err_handle(hdev)) 4370 hclge_reset_task_schedule(hdev); 4371 } 4372 4373 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4374 { 4375 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4376 struct hclge_dev *hdev = ae_dev->priv; 4377 4378 /* We might end up getting called broadly because of 2 below cases: 4379 * 1. Recoverable error was conveyed through APEI and only way to bring 4380 * normalcy is to reset. 4381 * 2. A new reset request from the stack due to timeout 4382 * 4383 * check if this is a new reset request and we are not here just because 4384 * last reset attempt did not succeed and watchdog hit us again. We will 4385 * know this if last reset request did not occur very recently (watchdog 4386 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4387 * In case of new request we reset the "reset level" to PF reset. 4388 * And if it is a repeat reset request of the most recent one then we 4389 * want to make sure we throttle the reset request. Therefore, we will 4390 * not allow it again before 3*HZ times. 4391 */ 4392 4393 if (time_before(jiffies, (hdev->last_reset_time + 4394 HCLGE_RESET_INTERVAL))) { 4395 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4396 return; 4397 } 4398 4399 if (hdev->default_reset_request) { 4400 hdev->reset_level = 4401 hclge_get_reset_level(ae_dev, 4402 &hdev->default_reset_request); 4403 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4404 hdev->reset_level = HNAE3_FUNC_RESET; 4405 } 4406 4407 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4408 hdev->reset_level); 4409 4410 /* request reset & schedule reset task */ 4411 set_bit(hdev->reset_level, &hdev->reset_request); 4412 hclge_reset_task_schedule(hdev); 4413 4414 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4415 hdev->reset_level++; 4416 } 4417 4418 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4419 enum hnae3_reset_type rst_type) 4420 { 4421 struct hclge_dev *hdev = ae_dev->priv; 4422 4423 set_bit(rst_type, &hdev->default_reset_request); 4424 } 4425 4426 static void hclge_reset_timer(struct timer_list *t) 4427 { 4428 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4429 4430 /* if default_reset_request has no value, it means that this reset 4431 * request has already be handled, so just return here 4432 */ 4433 if (!hdev->default_reset_request) 4434 return; 4435 4436 dev_info(&hdev->pdev->dev, 4437 "triggering reset in reset timer\n"); 4438 hclge_reset_event(hdev->pdev, NULL); 4439 } 4440 4441 static void hclge_reset_subtask(struct hclge_dev *hdev) 4442 { 4443 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4444 4445 /* check if there is any ongoing reset in the hardware. This status can 4446 * be checked from reset_pending. If there is then, we need to wait for 4447 * hardware to complete reset. 4448 * a. If we are able to figure out in reasonable time that hardware 4449 * has fully resetted then, we can proceed with driver, client 4450 * reset. 4451 * b. else, we can come back later to check this status so re-sched 4452 * now. 4453 */ 4454 hdev->last_reset_time = jiffies; 4455 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4456 if (hdev->reset_type != HNAE3_NONE_RESET) 4457 hclge_reset(hdev); 4458 4459 /* check if we got any *new* reset requests to be honored */ 4460 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4461 if (hdev->reset_type != HNAE3_NONE_RESET) 4462 hclge_do_reset(hdev); 4463 4464 hdev->reset_type = HNAE3_NONE_RESET; 4465 } 4466 4467 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4468 { 4469 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4470 enum hnae3_reset_type reset_type; 4471 4472 if (ae_dev->hw_err_reset_req) { 4473 reset_type = hclge_get_reset_level(ae_dev, 4474 &ae_dev->hw_err_reset_req); 4475 hclge_set_def_reset_request(ae_dev, reset_type); 4476 } 4477 4478 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4479 ae_dev->ops->reset_event(hdev->pdev, NULL); 4480 4481 /* enable interrupt after error handling complete */ 4482 hclge_enable_vector(&hdev->misc_vector, true); 4483 } 4484 4485 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4486 { 4487 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4488 4489 ae_dev->hw_err_reset_req = 0; 4490 4491 if (hclge_find_error_source(hdev)) { 4492 hclge_handle_error_info_log(ae_dev); 4493 hclge_handle_mac_tnl(hdev); 4494 hclge_handle_vf_queue_err_ras(hdev); 4495 } 4496 4497 hclge_handle_err_reset_request(hdev); 4498 } 4499 4500 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4501 { 4502 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4503 struct device *dev = &hdev->pdev->dev; 4504 u32 msix_sts_reg; 4505 4506 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4507 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4508 if (hclge_handle_hw_msix_error 4509 (hdev, &hdev->default_reset_request)) 4510 dev_info(dev, "received msix interrupt 0x%x\n", 4511 msix_sts_reg); 4512 } 4513 4514 hclge_handle_hw_ras_error(ae_dev); 4515 4516 hclge_handle_err_reset_request(hdev); 4517 } 4518 4519 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4520 { 4521 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4522 return; 4523 4524 if (hnae3_dev_ras_imp_supported(hdev)) 4525 hclge_handle_err_recovery(hdev); 4526 else 4527 hclge_misc_err_recovery(hdev); 4528 } 4529 4530 static void hclge_reset_service_task(struct hclge_dev *hdev) 4531 { 4532 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4533 return; 4534 4535 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4536 HCLGE_RESET_SCHED_TIMEOUT)) 4537 dev_warn(&hdev->pdev->dev, 4538 "reset service task is scheduled after %ums on cpu%u!\n", 4539 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4540 smp_processor_id()); 4541 4542 down(&hdev->reset_sem); 4543 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4544 4545 hclge_reset_subtask(hdev); 4546 4547 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4548 up(&hdev->reset_sem); 4549 } 4550 4551 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4552 { 4553 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4554 4555 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4556 int i; 4557 4558 /* start from vport 1 for PF is always alive */ 4559 for (i = 1; i < hdev->num_alloc_vport; i++) { 4560 struct hclge_vport *vport = &hdev->vport[i]; 4561 4562 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4563 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4564 continue; 4565 if (time_after(jiffies, vport->last_active_jiffies + 4566 alive_time)) { 4567 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4568 dev_warn(&hdev->pdev->dev, 4569 "VF %u heartbeat timeout\n", 4570 i - HCLGE_VF_VPORT_START_NUM); 4571 } 4572 } 4573 } 4574 4575 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4576 { 4577 unsigned long delta = round_jiffies_relative(HZ); 4578 4579 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4580 return; 4581 4582 /* Always handle the link updating to make sure link state is 4583 * updated when it is triggered by mbx. 4584 */ 4585 hclge_update_link_status(hdev); 4586 hclge_sync_mac_table(hdev); 4587 hclge_sync_promisc_mode(hdev); 4588 hclge_sync_fd_table(hdev); 4589 4590 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4591 delta = jiffies - hdev->last_serv_processed; 4592 4593 if (delta < round_jiffies_relative(HZ)) { 4594 delta = round_jiffies_relative(HZ) - delta; 4595 goto out; 4596 } 4597 } 4598 4599 hdev->serv_processed_cnt++; 4600 hclge_update_vport_alive(hdev); 4601 4602 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4603 hdev->last_serv_processed = jiffies; 4604 goto out; 4605 } 4606 4607 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4608 hclge_update_stats_for_all(hdev); 4609 4610 hclge_update_port_info(hdev); 4611 hclge_sync_vlan_filter(hdev); 4612 4613 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4614 hclge_rfs_filter_expire(hdev); 4615 4616 hdev->last_serv_processed = jiffies; 4617 4618 out: 4619 hclge_task_schedule(hdev, delta); 4620 } 4621 4622 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4623 { 4624 unsigned long flags; 4625 4626 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4627 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4628 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4629 return; 4630 4631 /* to prevent concurrence with the irq handler */ 4632 spin_lock_irqsave(&hdev->ptp->lock, flags); 4633 4634 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4635 * handler may handle it just before spin_lock_irqsave(). 4636 */ 4637 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4638 hclge_ptp_clean_tx_hwts(hdev); 4639 4640 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4641 } 4642 4643 static void hclge_service_task(struct work_struct *work) 4644 { 4645 struct hclge_dev *hdev = 4646 container_of(work, struct hclge_dev, service_task.work); 4647 4648 hclge_errhand_service_task(hdev); 4649 hclge_reset_service_task(hdev); 4650 hclge_ptp_service_task(hdev); 4651 hclge_mailbox_service_task(hdev); 4652 hclge_periodic_service_task(hdev); 4653 4654 /* Handle error recovery, reset and mbx again in case periodical task 4655 * delays the handling by calling hclge_task_schedule() in 4656 * hclge_periodic_service_task(). 4657 */ 4658 hclge_errhand_service_task(hdev); 4659 hclge_reset_service_task(hdev); 4660 hclge_mailbox_service_task(hdev); 4661 } 4662 4663 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4664 { 4665 /* VF handle has no client */ 4666 if (!handle->client) 4667 return container_of(handle, struct hclge_vport, nic); 4668 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4669 return container_of(handle, struct hclge_vport, roce); 4670 else 4671 return container_of(handle, struct hclge_vport, nic); 4672 } 4673 4674 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4675 struct hnae3_vector_info *vector_info) 4676 { 4677 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4678 4679 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4680 4681 /* need an extend offset to config vector >= 64 */ 4682 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4683 vector_info->io_addr = hdev->hw.hw.io_base + 4684 HCLGE_VECTOR_REG_BASE + 4685 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4686 else 4687 vector_info->io_addr = hdev->hw.hw.io_base + 4688 HCLGE_VECTOR_EXT_REG_BASE + 4689 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4690 HCLGE_VECTOR_REG_OFFSET_H + 4691 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4692 HCLGE_VECTOR_REG_OFFSET; 4693 4694 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4695 hdev->vector_irq[idx] = vector_info->vector; 4696 } 4697 4698 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4699 struct hnae3_vector_info *vector_info) 4700 { 4701 struct hclge_vport *vport = hclge_get_vport(handle); 4702 struct hnae3_vector_info *vector = vector_info; 4703 struct hclge_dev *hdev = vport->back; 4704 int alloc = 0; 4705 u16 i = 0; 4706 u16 j; 4707 4708 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4709 vector_num = min(hdev->num_msi_left, vector_num); 4710 4711 for (j = 0; j < vector_num; j++) { 4712 while (++i < hdev->num_nic_msi) { 4713 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4714 hclge_get_vector_info(hdev, i, vector); 4715 vector++; 4716 alloc++; 4717 4718 break; 4719 } 4720 } 4721 } 4722 hdev->num_msi_left -= alloc; 4723 hdev->num_msi_used += alloc; 4724 4725 return alloc; 4726 } 4727 4728 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4729 { 4730 int i; 4731 4732 for (i = 0; i < hdev->num_msi; i++) 4733 if (vector == hdev->vector_irq[i]) 4734 return i; 4735 4736 return -EINVAL; 4737 } 4738 4739 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4740 { 4741 struct hclge_vport *vport = hclge_get_vport(handle); 4742 struct hclge_dev *hdev = vport->back; 4743 int vector_id; 4744 4745 vector_id = hclge_get_vector_index(hdev, vector); 4746 if (vector_id < 0) { 4747 dev_err(&hdev->pdev->dev, 4748 "Get vector index fail. vector = %d\n", vector); 4749 return vector_id; 4750 } 4751 4752 hclge_free_vector(hdev, vector_id); 4753 4754 return 0; 4755 } 4756 4757 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4758 u8 *key, u8 *hfunc) 4759 { 4760 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4761 struct hclge_vport *vport = hclge_get_vport(handle); 4762 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4763 4764 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4765 4766 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4767 ae_dev->dev_specs.rss_ind_tbl_size); 4768 4769 return 0; 4770 } 4771 4772 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4773 const u8 *key, const u8 hfunc) 4774 { 4775 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4776 struct hclge_vport *vport = hclge_get_vport(handle); 4777 struct hclge_dev *hdev = vport->back; 4778 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4779 int ret, i; 4780 4781 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4782 if (ret) { 4783 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4784 return ret; 4785 } 4786 4787 /* Update the shadow RSS table with user specified qids */ 4788 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4789 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4790 4791 /* Update the hardware */ 4792 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4793 rss_cfg->rss_indirection_tbl); 4794 } 4795 4796 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4797 struct ethtool_rxnfc *nfc) 4798 { 4799 struct hclge_vport *vport = hclge_get_vport(handle); 4800 struct hclge_dev *hdev = vport->back; 4801 int ret; 4802 4803 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4804 &hdev->rss_cfg, nfc); 4805 if (ret) { 4806 dev_err(&hdev->pdev->dev, 4807 "failed to set rss tuple, ret = %d.\n", ret); 4808 return ret; 4809 } 4810 4811 return 0; 4812 } 4813 4814 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4815 struct ethtool_rxnfc *nfc) 4816 { 4817 struct hclge_vport *vport = hclge_get_vport(handle); 4818 u8 tuple_sets; 4819 int ret; 4820 4821 nfc->data = 0; 4822 4823 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4824 &tuple_sets); 4825 if (ret || !tuple_sets) 4826 return ret; 4827 4828 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4829 4830 return 0; 4831 } 4832 4833 static int hclge_get_tc_size(struct hnae3_handle *handle) 4834 { 4835 struct hclge_vport *vport = hclge_get_vport(handle); 4836 struct hclge_dev *hdev = vport->back; 4837 4838 return hdev->pf_rss_size_max; 4839 } 4840 4841 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4842 { 4843 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4844 struct hclge_vport *vport = hdev->vport; 4845 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4846 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4847 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4848 struct hnae3_tc_info *tc_info; 4849 u16 roundup_size; 4850 u16 rss_size; 4851 int i; 4852 4853 tc_info = &vport->nic.kinfo.tc_info; 4854 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4855 rss_size = tc_info->tqp_count[i]; 4856 tc_valid[i] = 0; 4857 4858 if (!(hdev->hw_tc_map & BIT(i))) 4859 continue; 4860 4861 /* tc_size set to hardware is the log2 of roundup power of two 4862 * of rss_size, the acutal queue size is limited by indirection 4863 * table. 4864 */ 4865 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4866 rss_size == 0) { 4867 dev_err(&hdev->pdev->dev, 4868 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4869 rss_size); 4870 return -EINVAL; 4871 } 4872 4873 roundup_size = roundup_pow_of_two(rss_size); 4874 roundup_size = ilog2(roundup_size); 4875 4876 tc_valid[i] = 1; 4877 tc_size[i] = roundup_size; 4878 tc_offset[i] = tc_info->tqp_offset[i]; 4879 } 4880 4881 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4882 tc_size); 4883 } 4884 4885 int hclge_rss_init_hw(struct hclge_dev *hdev) 4886 { 4887 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4888 u8 *key = hdev->rss_cfg.rss_hash_key; 4889 u8 hfunc = hdev->rss_cfg.rss_algo; 4890 int ret; 4891 4892 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4893 rss_indir); 4894 if (ret) 4895 return ret; 4896 4897 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4898 if (ret) 4899 return ret; 4900 4901 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4902 if (ret) 4903 return ret; 4904 4905 return hclge_init_rss_tc_mode(hdev); 4906 } 4907 4908 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4909 int vector_id, bool en, 4910 struct hnae3_ring_chain_node *ring_chain) 4911 { 4912 struct hclge_dev *hdev = vport->back; 4913 struct hnae3_ring_chain_node *node; 4914 struct hclge_desc desc; 4915 struct hclge_ctrl_vector_chain_cmd *req = 4916 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4917 enum hclge_comm_cmd_status status; 4918 enum hclge_opcode_type op; 4919 u16 tqp_type_and_id; 4920 int i; 4921 4922 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4923 hclge_cmd_setup_basic_desc(&desc, op, false); 4924 req->int_vector_id_l = hnae3_get_field(vector_id, 4925 HCLGE_VECTOR_ID_L_M, 4926 HCLGE_VECTOR_ID_L_S); 4927 req->int_vector_id_h = hnae3_get_field(vector_id, 4928 HCLGE_VECTOR_ID_H_M, 4929 HCLGE_VECTOR_ID_H_S); 4930 4931 i = 0; 4932 for (node = ring_chain; node; node = node->next) { 4933 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4934 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4935 HCLGE_INT_TYPE_S, 4936 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4937 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4938 HCLGE_TQP_ID_S, node->tqp_index); 4939 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4940 HCLGE_INT_GL_IDX_S, 4941 hnae3_get_field(node->int_gl_idx, 4942 HNAE3_RING_GL_IDX_M, 4943 HNAE3_RING_GL_IDX_S)); 4944 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4945 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4946 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4947 req->vfid = vport->vport_id; 4948 4949 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4950 if (status) { 4951 dev_err(&hdev->pdev->dev, 4952 "Map TQP fail, status is %d.\n", 4953 status); 4954 return -EIO; 4955 } 4956 i = 0; 4957 4958 hclge_cmd_setup_basic_desc(&desc, 4959 op, 4960 false); 4961 req->int_vector_id_l = 4962 hnae3_get_field(vector_id, 4963 HCLGE_VECTOR_ID_L_M, 4964 HCLGE_VECTOR_ID_L_S); 4965 req->int_vector_id_h = 4966 hnae3_get_field(vector_id, 4967 HCLGE_VECTOR_ID_H_M, 4968 HCLGE_VECTOR_ID_H_S); 4969 } 4970 } 4971 4972 if (i > 0) { 4973 req->int_cause_num = i; 4974 req->vfid = vport->vport_id; 4975 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4976 if (status) { 4977 dev_err(&hdev->pdev->dev, 4978 "Map TQP fail, status is %d.\n", status); 4979 return -EIO; 4980 } 4981 } 4982 4983 return 0; 4984 } 4985 4986 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 4987 struct hnae3_ring_chain_node *ring_chain) 4988 { 4989 struct hclge_vport *vport = hclge_get_vport(handle); 4990 struct hclge_dev *hdev = vport->back; 4991 int vector_id; 4992 4993 vector_id = hclge_get_vector_index(hdev, vector); 4994 if (vector_id < 0) { 4995 dev_err(&hdev->pdev->dev, 4996 "failed to get vector index. vector=%d\n", vector); 4997 return vector_id; 4998 } 4999 5000 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5001 } 5002 5003 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5004 struct hnae3_ring_chain_node *ring_chain) 5005 { 5006 struct hclge_vport *vport = hclge_get_vport(handle); 5007 struct hclge_dev *hdev = vport->back; 5008 int vector_id, ret; 5009 5010 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5011 return 0; 5012 5013 vector_id = hclge_get_vector_index(hdev, vector); 5014 if (vector_id < 0) { 5015 dev_err(&handle->pdev->dev, 5016 "Get vector index fail. ret =%d\n", vector_id); 5017 return vector_id; 5018 } 5019 5020 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5021 if (ret) 5022 dev_err(&handle->pdev->dev, 5023 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5024 vector_id, ret); 5025 5026 return ret; 5027 } 5028 5029 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5030 bool en_uc, bool en_mc, bool en_bc) 5031 { 5032 struct hclge_vport *vport = &hdev->vport[vf_id]; 5033 struct hnae3_handle *handle = &vport->nic; 5034 struct hclge_promisc_cfg_cmd *req; 5035 struct hclge_desc desc; 5036 bool uc_tx_en = en_uc; 5037 u8 promisc_cfg = 0; 5038 int ret; 5039 5040 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5041 5042 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5043 req->vf_id = vf_id; 5044 5045 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5046 uc_tx_en = false; 5047 5048 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5049 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5050 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5051 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5052 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5053 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5054 req->extend_promisc = promisc_cfg; 5055 5056 /* to be compatible with DEVICE_VERSION_V1/2 */ 5057 promisc_cfg = 0; 5058 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5059 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5060 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5061 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5062 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5063 req->promisc = promisc_cfg; 5064 5065 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5066 if (ret) 5067 dev_err(&hdev->pdev->dev, 5068 "failed to set vport %u promisc mode, ret = %d.\n", 5069 vf_id, ret); 5070 5071 return ret; 5072 } 5073 5074 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5075 bool en_mc_pmc, bool en_bc_pmc) 5076 { 5077 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5078 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5079 } 5080 5081 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5082 bool en_mc_pmc) 5083 { 5084 struct hclge_vport *vport = hclge_get_vport(handle); 5085 struct hclge_dev *hdev = vport->back; 5086 bool en_bc_pmc = true; 5087 5088 /* For device whose version below V2, if broadcast promisc enabled, 5089 * vlan filter is always bypassed. So broadcast promisc should be 5090 * disabled until user enable promisc mode 5091 */ 5092 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5093 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5094 5095 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5096 en_bc_pmc); 5097 } 5098 5099 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5100 { 5101 struct hclge_vport *vport = hclge_get_vport(handle); 5102 5103 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5104 } 5105 5106 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5107 { 5108 if (hlist_empty(&hdev->fd_rule_list)) 5109 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5110 } 5111 5112 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5113 { 5114 if (!test_bit(location, hdev->fd_bmap)) { 5115 set_bit(location, hdev->fd_bmap); 5116 hdev->hclge_fd_rule_num++; 5117 } 5118 } 5119 5120 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5121 { 5122 if (test_bit(location, hdev->fd_bmap)) { 5123 clear_bit(location, hdev->fd_bmap); 5124 hdev->hclge_fd_rule_num--; 5125 } 5126 } 5127 5128 static void hclge_fd_free_node(struct hclge_dev *hdev, 5129 struct hclge_fd_rule *rule) 5130 { 5131 hlist_del(&rule->rule_node); 5132 kfree(rule); 5133 hclge_sync_fd_state(hdev); 5134 } 5135 5136 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5137 struct hclge_fd_rule *old_rule, 5138 struct hclge_fd_rule *new_rule, 5139 enum HCLGE_FD_NODE_STATE state) 5140 { 5141 switch (state) { 5142 case HCLGE_FD_TO_ADD: 5143 case HCLGE_FD_ACTIVE: 5144 /* 1) if the new state is TO_ADD, just replace the old rule 5145 * with the same location, no matter its state, because the 5146 * new rule will be configured to the hardware. 5147 * 2) if the new state is ACTIVE, it means the new rule 5148 * has been configured to the hardware, so just replace 5149 * the old rule node with the same location. 5150 * 3) for it doesn't add a new node to the list, so it's 5151 * unnecessary to update the rule number and fd_bmap. 5152 */ 5153 new_rule->rule_node.next = old_rule->rule_node.next; 5154 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5155 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5156 kfree(new_rule); 5157 break; 5158 case HCLGE_FD_DELETED: 5159 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5160 hclge_fd_free_node(hdev, old_rule); 5161 break; 5162 case HCLGE_FD_TO_DEL: 5163 /* if new request is TO_DEL, and old rule is existent 5164 * 1) the state of old rule is TO_DEL, we need do nothing, 5165 * because we delete rule by location, other rule content 5166 * is unncessary. 5167 * 2) the state of old rule is ACTIVE, we need to change its 5168 * state to TO_DEL, so the rule will be deleted when periodic 5169 * task being scheduled. 5170 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5171 * been added to hardware, so we just delete the rule node from 5172 * fd_rule_list directly. 5173 */ 5174 if (old_rule->state == HCLGE_FD_TO_ADD) { 5175 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5176 hclge_fd_free_node(hdev, old_rule); 5177 return; 5178 } 5179 old_rule->state = HCLGE_FD_TO_DEL; 5180 break; 5181 } 5182 } 5183 5184 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5185 u16 location, 5186 struct hclge_fd_rule **parent) 5187 { 5188 struct hclge_fd_rule *rule; 5189 struct hlist_node *node; 5190 5191 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5192 if (rule->location == location) 5193 return rule; 5194 else if (rule->location > location) 5195 return NULL; 5196 /* record the parent node, use to keep the nodes in fd_rule_list 5197 * in ascend order. 5198 */ 5199 *parent = rule; 5200 } 5201 5202 return NULL; 5203 } 5204 5205 /* insert fd rule node in ascend order according to rule->location */ 5206 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5207 struct hclge_fd_rule *rule, 5208 struct hclge_fd_rule *parent) 5209 { 5210 INIT_HLIST_NODE(&rule->rule_node); 5211 5212 if (parent) 5213 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5214 else 5215 hlist_add_head(&rule->rule_node, hlist); 5216 } 5217 5218 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5219 struct hclge_fd_user_def_cfg *cfg) 5220 { 5221 struct hclge_fd_user_def_cfg_cmd *req; 5222 struct hclge_desc desc; 5223 u16 data = 0; 5224 int ret; 5225 5226 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5227 5228 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5229 5230 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5231 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5232 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5233 req->ol2_cfg = cpu_to_le16(data); 5234 5235 data = 0; 5236 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5237 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5238 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5239 req->ol3_cfg = cpu_to_le16(data); 5240 5241 data = 0; 5242 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5243 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5244 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5245 req->ol4_cfg = cpu_to_le16(data); 5246 5247 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5248 if (ret) 5249 dev_err(&hdev->pdev->dev, 5250 "failed to set fd user def data, ret= %d\n", ret); 5251 return ret; 5252 } 5253 5254 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5255 { 5256 int ret; 5257 5258 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5259 return; 5260 5261 if (!locked) 5262 spin_lock_bh(&hdev->fd_rule_lock); 5263 5264 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5265 if (ret) 5266 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5267 5268 if (!locked) 5269 spin_unlock_bh(&hdev->fd_rule_lock); 5270 } 5271 5272 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5273 struct hclge_fd_rule *rule) 5274 { 5275 struct hlist_head *hlist = &hdev->fd_rule_list; 5276 struct hclge_fd_rule *fd_rule, *parent = NULL; 5277 struct hclge_fd_user_def_info *info, *old_info; 5278 struct hclge_fd_user_def_cfg *cfg; 5279 5280 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5281 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5282 return 0; 5283 5284 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5285 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5286 info = &rule->ep.user_def; 5287 5288 if (!cfg->ref_cnt || cfg->offset == info->offset) 5289 return 0; 5290 5291 if (cfg->ref_cnt > 1) 5292 goto error; 5293 5294 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5295 if (fd_rule) { 5296 old_info = &fd_rule->ep.user_def; 5297 if (info->layer == old_info->layer) 5298 return 0; 5299 } 5300 5301 error: 5302 dev_err(&hdev->pdev->dev, 5303 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5304 info->layer + 1); 5305 return -ENOSPC; 5306 } 5307 5308 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5309 struct hclge_fd_rule *rule) 5310 { 5311 struct hclge_fd_user_def_cfg *cfg; 5312 5313 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5314 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5315 return; 5316 5317 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5318 if (!cfg->ref_cnt) { 5319 cfg->offset = rule->ep.user_def.offset; 5320 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5321 } 5322 cfg->ref_cnt++; 5323 } 5324 5325 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5326 struct hclge_fd_rule *rule) 5327 { 5328 struct hclge_fd_user_def_cfg *cfg; 5329 5330 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5331 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5332 return; 5333 5334 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5335 if (!cfg->ref_cnt) 5336 return; 5337 5338 cfg->ref_cnt--; 5339 if (!cfg->ref_cnt) { 5340 cfg->offset = 0; 5341 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5342 } 5343 } 5344 5345 static void hclge_update_fd_list(struct hclge_dev *hdev, 5346 enum HCLGE_FD_NODE_STATE state, u16 location, 5347 struct hclge_fd_rule *new_rule) 5348 { 5349 struct hlist_head *hlist = &hdev->fd_rule_list; 5350 struct hclge_fd_rule *fd_rule, *parent = NULL; 5351 5352 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5353 if (fd_rule) { 5354 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5355 if (state == HCLGE_FD_ACTIVE) 5356 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5357 hclge_sync_fd_user_def_cfg(hdev, true); 5358 5359 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5360 return; 5361 } 5362 5363 /* it's unlikely to fail here, because we have checked the rule 5364 * exist before. 5365 */ 5366 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5367 dev_warn(&hdev->pdev->dev, 5368 "failed to delete fd rule %u, it's inexistent\n", 5369 location); 5370 return; 5371 } 5372 5373 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5374 hclge_sync_fd_user_def_cfg(hdev, true); 5375 5376 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5377 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5378 5379 if (state == HCLGE_FD_TO_ADD) { 5380 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5381 hclge_task_schedule(hdev, 0); 5382 } 5383 } 5384 5385 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5386 { 5387 struct hclge_get_fd_mode_cmd *req; 5388 struct hclge_desc desc; 5389 int ret; 5390 5391 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5392 5393 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5394 5395 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5396 if (ret) { 5397 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5398 return ret; 5399 } 5400 5401 *fd_mode = req->mode; 5402 5403 return ret; 5404 } 5405 5406 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5407 u32 *stage1_entry_num, 5408 u32 *stage2_entry_num, 5409 u16 *stage1_counter_num, 5410 u16 *stage2_counter_num) 5411 { 5412 struct hclge_get_fd_allocation_cmd *req; 5413 struct hclge_desc desc; 5414 int ret; 5415 5416 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5417 5418 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5419 5420 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5421 if (ret) { 5422 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5423 ret); 5424 return ret; 5425 } 5426 5427 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5428 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5429 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5430 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5431 5432 return ret; 5433 } 5434 5435 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5436 enum HCLGE_FD_STAGE stage_num) 5437 { 5438 struct hclge_set_fd_key_config_cmd *req; 5439 struct hclge_fd_key_cfg *stage; 5440 struct hclge_desc desc; 5441 int ret; 5442 5443 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5444 5445 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5446 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5447 req->stage = stage_num; 5448 req->key_select = stage->key_sel; 5449 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5450 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5451 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5452 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5453 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5454 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5455 5456 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5457 if (ret) 5458 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5459 5460 return ret; 5461 } 5462 5463 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5464 { 5465 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5466 5467 spin_lock_bh(&hdev->fd_rule_lock); 5468 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5469 spin_unlock_bh(&hdev->fd_rule_lock); 5470 5471 hclge_fd_set_user_def_cmd(hdev, cfg); 5472 } 5473 5474 static int hclge_init_fd_config(struct hclge_dev *hdev) 5475 { 5476 #define LOW_2_WORDS 0x03 5477 struct hclge_fd_key_cfg *key_cfg; 5478 int ret; 5479 5480 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5481 return 0; 5482 5483 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5484 if (ret) 5485 return ret; 5486 5487 switch (hdev->fd_cfg.fd_mode) { 5488 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5489 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5490 break; 5491 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5492 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5493 break; 5494 default: 5495 dev_err(&hdev->pdev->dev, 5496 "Unsupported flow director mode %u\n", 5497 hdev->fd_cfg.fd_mode); 5498 return -EOPNOTSUPP; 5499 } 5500 5501 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5502 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5503 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5504 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5505 key_cfg->outer_sipv6_word_en = 0; 5506 key_cfg->outer_dipv6_word_en = 0; 5507 5508 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5509 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5510 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5511 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5512 5513 /* If use max 400bit key, we can support tuples for ether type */ 5514 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5515 key_cfg->tuple_active |= 5516 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5517 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5518 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5519 } 5520 5521 /* roce_type is used to filter roce frames 5522 * dst_vport is used to specify the rule 5523 */ 5524 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5525 5526 ret = hclge_get_fd_allocation(hdev, 5527 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5528 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5529 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5530 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5531 if (ret) 5532 return ret; 5533 5534 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5535 } 5536 5537 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5538 int loc, u8 *key, bool is_add) 5539 { 5540 struct hclge_fd_tcam_config_1_cmd *req1; 5541 struct hclge_fd_tcam_config_2_cmd *req2; 5542 struct hclge_fd_tcam_config_3_cmd *req3; 5543 struct hclge_desc desc[3]; 5544 int ret; 5545 5546 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5547 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5548 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5549 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5550 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5551 5552 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5553 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5554 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5555 5556 req1->stage = stage; 5557 req1->xy_sel = sel_x ? 1 : 0; 5558 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5559 req1->index = cpu_to_le32(loc); 5560 req1->entry_vld = sel_x ? is_add : 0; 5561 5562 if (key) { 5563 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5564 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5565 sizeof(req2->tcam_data)); 5566 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5567 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5568 } 5569 5570 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5571 if (ret) 5572 dev_err(&hdev->pdev->dev, 5573 "config tcam key fail, ret=%d\n", 5574 ret); 5575 5576 return ret; 5577 } 5578 5579 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5580 struct hclge_fd_ad_data *action) 5581 { 5582 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5583 struct hclge_fd_ad_config_cmd *req; 5584 struct hclge_desc desc; 5585 u64 ad_data = 0; 5586 int ret; 5587 5588 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5589 5590 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5591 req->index = cpu_to_le32(loc); 5592 req->stage = stage; 5593 5594 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5595 action->write_rule_id_to_bd); 5596 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5597 action->rule_id); 5598 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5599 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5600 action->override_tc); 5601 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5602 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5603 } 5604 ad_data <<= 32; 5605 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5606 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5607 action->forward_to_direct_queue); 5608 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5609 action->queue_id); 5610 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5611 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5612 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5613 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5614 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5615 action->counter_id); 5616 5617 req->ad_data = cpu_to_le64(ad_data); 5618 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5619 if (ret) 5620 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5621 5622 return ret; 5623 } 5624 5625 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5626 struct hclge_fd_rule *rule) 5627 { 5628 int offset, moffset, ip_offset; 5629 enum HCLGE_FD_KEY_OPT key_opt; 5630 u16 tmp_x_s, tmp_y_s; 5631 u32 tmp_x_l, tmp_y_l; 5632 u8 *p = (u8 *)rule; 5633 int i; 5634 5635 if (rule->unused_tuple & BIT(tuple_bit)) 5636 return true; 5637 5638 key_opt = tuple_key_info[tuple_bit].key_opt; 5639 offset = tuple_key_info[tuple_bit].offset; 5640 moffset = tuple_key_info[tuple_bit].moffset; 5641 5642 switch (key_opt) { 5643 case KEY_OPT_U8: 5644 calc_x(*key_x, p[offset], p[moffset]); 5645 calc_y(*key_y, p[offset], p[moffset]); 5646 5647 return true; 5648 case KEY_OPT_LE16: 5649 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5650 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5651 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5652 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5653 5654 return true; 5655 case KEY_OPT_LE32: 5656 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5657 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5658 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5659 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5660 5661 return true; 5662 case KEY_OPT_MAC: 5663 for (i = 0; i < ETH_ALEN; i++) { 5664 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5665 p[moffset + i]); 5666 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5667 p[moffset + i]); 5668 } 5669 5670 return true; 5671 case KEY_OPT_IP: 5672 ip_offset = IPV4_INDEX * sizeof(u32); 5673 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5674 *(u32 *)(&p[moffset + ip_offset])); 5675 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5676 *(u32 *)(&p[moffset + ip_offset])); 5677 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5678 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5679 5680 return true; 5681 default: 5682 return false; 5683 } 5684 } 5685 5686 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5687 u8 vf_id, u8 network_port_id) 5688 { 5689 u32 port_number = 0; 5690 5691 if (port_type == HOST_PORT) { 5692 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5693 pf_id); 5694 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5695 vf_id); 5696 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5697 } else { 5698 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5699 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5700 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5701 } 5702 5703 return port_number; 5704 } 5705 5706 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5707 __le32 *key_x, __le32 *key_y, 5708 struct hclge_fd_rule *rule) 5709 { 5710 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5711 u8 cur_pos = 0, tuple_size, shift_bits; 5712 unsigned int i; 5713 5714 for (i = 0; i < MAX_META_DATA; i++) { 5715 tuple_size = meta_data_key_info[i].key_length; 5716 tuple_bit = key_cfg->meta_data_active & BIT(i); 5717 5718 switch (tuple_bit) { 5719 case BIT(ROCE_TYPE): 5720 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5721 cur_pos += tuple_size; 5722 break; 5723 case BIT(DST_VPORT): 5724 port_number = hclge_get_port_number(HOST_PORT, 0, 5725 rule->vf_id, 0); 5726 hnae3_set_field(meta_data, 5727 GENMASK(cur_pos + tuple_size, cur_pos), 5728 cur_pos, port_number); 5729 cur_pos += tuple_size; 5730 break; 5731 default: 5732 break; 5733 } 5734 } 5735 5736 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5737 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5738 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5739 5740 *key_x = cpu_to_le32(tmp_x << shift_bits); 5741 *key_y = cpu_to_le32(tmp_y << shift_bits); 5742 } 5743 5744 /* A complete key is combined with meta data key and tuple key. 5745 * Meta data key is stored at the MSB region, and tuple key is stored at 5746 * the LSB region, unused bits will be filled 0. 5747 */ 5748 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5749 struct hclge_fd_rule *rule) 5750 { 5751 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5752 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5753 u8 *cur_key_x, *cur_key_y; 5754 u8 meta_data_region; 5755 u8 tuple_size; 5756 int ret; 5757 u32 i; 5758 5759 memset(key_x, 0, sizeof(key_x)); 5760 memset(key_y, 0, sizeof(key_y)); 5761 cur_key_x = key_x; 5762 cur_key_y = key_y; 5763 5764 for (i = 0; i < MAX_TUPLE; i++) { 5765 bool tuple_valid; 5766 5767 tuple_size = tuple_key_info[i].key_length / 8; 5768 if (!(key_cfg->tuple_active & BIT(i))) 5769 continue; 5770 5771 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5772 cur_key_y, rule); 5773 if (tuple_valid) { 5774 cur_key_x += tuple_size; 5775 cur_key_y += tuple_size; 5776 } 5777 } 5778 5779 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5780 MAX_META_DATA_LENGTH / 8; 5781 5782 hclge_fd_convert_meta_data(key_cfg, 5783 (__le32 *)(key_x + meta_data_region), 5784 (__le32 *)(key_y + meta_data_region), 5785 rule); 5786 5787 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5788 true); 5789 if (ret) { 5790 dev_err(&hdev->pdev->dev, 5791 "fd key_y config fail, loc=%u, ret=%d\n", 5792 rule->queue_id, ret); 5793 return ret; 5794 } 5795 5796 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5797 true); 5798 if (ret) 5799 dev_err(&hdev->pdev->dev, 5800 "fd key_x config fail, loc=%u, ret=%d\n", 5801 rule->queue_id, ret); 5802 return ret; 5803 } 5804 5805 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5806 struct hclge_fd_rule *rule) 5807 { 5808 struct hclge_vport *vport = hdev->vport; 5809 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5810 struct hclge_fd_ad_data ad_data; 5811 5812 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5813 ad_data.ad_id = rule->location; 5814 5815 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5816 ad_data.drop_packet = true; 5817 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5818 ad_data.override_tc = true; 5819 ad_data.queue_id = 5820 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5821 ad_data.tc_size = 5822 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5823 } else { 5824 ad_data.forward_to_direct_queue = true; 5825 ad_data.queue_id = rule->queue_id; 5826 } 5827 5828 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5829 ad_data.use_counter = true; 5830 ad_data.counter_id = rule->vf_id % 5831 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5832 } else { 5833 ad_data.use_counter = false; 5834 ad_data.counter_id = 0; 5835 } 5836 5837 ad_data.use_next_stage = false; 5838 ad_data.next_input_key = 0; 5839 5840 ad_data.write_rule_id_to_bd = true; 5841 ad_data.rule_id = rule->location; 5842 5843 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5844 } 5845 5846 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5847 u32 *unused_tuple) 5848 { 5849 if (!spec || !unused_tuple) 5850 return -EINVAL; 5851 5852 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5853 5854 if (!spec->ip4src) 5855 *unused_tuple |= BIT(INNER_SRC_IP); 5856 5857 if (!spec->ip4dst) 5858 *unused_tuple |= BIT(INNER_DST_IP); 5859 5860 if (!spec->psrc) 5861 *unused_tuple |= BIT(INNER_SRC_PORT); 5862 5863 if (!spec->pdst) 5864 *unused_tuple |= BIT(INNER_DST_PORT); 5865 5866 if (!spec->tos) 5867 *unused_tuple |= BIT(INNER_IP_TOS); 5868 5869 return 0; 5870 } 5871 5872 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5873 u32 *unused_tuple) 5874 { 5875 if (!spec || !unused_tuple) 5876 return -EINVAL; 5877 5878 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5879 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5880 5881 if (!spec->ip4src) 5882 *unused_tuple |= BIT(INNER_SRC_IP); 5883 5884 if (!spec->ip4dst) 5885 *unused_tuple |= BIT(INNER_DST_IP); 5886 5887 if (!spec->tos) 5888 *unused_tuple |= BIT(INNER_IP_TOS); 5889 5890 if (!spec->proto) 5891 *unused_tuple |= BIT(INNER_IP_PROTO); 5892 5893 if (spec->l4_4_bytes) 5894 return -EOPNOTSUPP; 5895 5896 if (spec->ip_ver != ETH_RX_NFC_IP4) 5897 return -EOPNOTSUPP; 5898 5899 return 0; 5900 } 5901 5902 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5903 u32 *unused_tuple) 5904 { 5905 if (!spec || !unused_tuple) 5906 return -EINVAL; 5907 5908 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5909 5910 /* check whether src/dst ip address used */ 5911 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5912 *unused_tuple |= BIT(INNER_SRC_IP); 5913 5914 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5915 *unused_tuple |= BIT(INNER_DST_IP); 5916 5917 if (!spec->psrc) 5918 *unused_tuple |= BIT(INNER_SRC_PORT); 5919 5920 if (!spec->pdst) 5921 *unused_tuple |= BIT(INNER_DST_PORT); 5922 5923 if (!spec->tclass) 5924 *unused_tuple |= BIT(INNER_IP_TOS); 5925 5926 return 0; 5927 } 5928 5929 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5930 u32 *unused_tuple) 5931 { 5932 if (!spec || !unused_tuple) 5933 return -EINVAL; 5934 5935 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5936 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5937 5938 /* check whether src/dst ip address used */ 5939 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5940 *unused_tuple |= BIT(INNER_SRC_IP); 5941 5942 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5943 *unused_tuple |= BIT(INNER_DST_IP); 5944 5945 if (!spec->l4_proto) 5946 *unused_tuple |= BIT(INNER_IP_PROTO); 5947 5948 if (!spec->tclass) 5949 *unused_tuple |= BIT(INNER_IP_TOS); 5950 5951 if (spec->l4_4_bytes) 5952 return -EOPNOTSUPP; 5953 5954 return 0; 5955 } 5956 5957 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 5958 { 5959 if (!spec || !unused_tuple) 5960 return -EINVAL; 5961 5962 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5963 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 5964 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 5965 5966 if (is_zero_ether_addr(spec->h_source)) 5967 *unused_tuple |= BIT(INNER_SRC_MAC); 5968 5969 if (is_zero_ether_addr(spec->h_dest)) 5970 *unused_tuple |= BIT(INNER_DST_MAC); 5971 5972 if (!spec->h_proto) 5973 *unused_tuple |= BIT(INNER_ETH_TYPE); 5974 5975 return 0; 5976 } 5977 5978 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 5979 struct ethtool_rx_flow_spec *fs, 5980 u32 *unused_tuple) 5981 { 5982 if (fs->flow_type & FLOW_EXT) { 5983 if (fs->h_ext.vlan_etype) { 5984 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 5985 return -EOPNOTSUPP; 5986 } 5987 5988 if (!fs->h_ext.vlan_tci) 5989 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5990 5991 if (fs->m_ext.vlan_tci && 5992 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 5993 dev_err(&hdev->pdev->dev, 5994 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 5995 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 5996 return -EINVAL; 5997 } 5998 } else { 5999 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6000 } 6001 6002 if (fs->flow_type & FLOW_MAC_EXT) { 6003 if (hdev->fd_cfg.fd_mode != 6004 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6005 dev_err(&hdev->pdev->dev, 6006 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6007 return -EOPNOTSUPP; 6008 } 6009 6010 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6011 *unused_tuple |= BIT(INNER_DST_MAC); 6012 else 6013 *unused_tuple &= ~BIT(INNER_DST_MAC); 6014 } 6015 6016 return 0; 6017 } 6018 6019 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6020 struct hclge_fd_user_def_info *info) 6021 { 6022 switch (flow_type) { 6023 case ETHER_FLOW: 6024 info->layer = HCLGE_FD_USER_DEF_L2; 6025 *unused_tuple &= ~BIT(INNER_L2_RSV); 6026 break; 6027 case IP_USER_FLOW: 6028 case IPV6_USER_FLOW: 6029 info->layer = HCLGE_FD_USER_DEF_L3; 6030 *unused_tuple &= ~BIT(INNER_L3_RSV); 6031 break; 6032 case TCP_V4_FLOW: 6033 case UDP_V4_FLOW: 6034 case TCP_V6_FLOW: 6035 case UDP_V6_FLOW: 6036 info->layer = HCLGE_FD_USER_DEF_L4; 6037 *unused_tuple &= ~BIT(INNER_L4_RSV); 6038 break; 6039 default: 6040 return -EOPNOTSUPP; 6041 } 6042 6043 return 0; 6044 } 6045 6046 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6047 { 6048 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6049 } 6050 6051 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6052 struct ethtool_rx_flow_spec *fs, 6053 u32 *unused_tuple, 6054 struct hclge_fd_user_def_info *info) 6055 { 6056 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6057 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6058 u16 data, offset, data_mask, offset_mask; 6059 int ret; 6060 6061 info->layer = HCLGE_FD_USER_DEF_NONE; 6062 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6063 6064 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6065 return 0; 6066 6067 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6068 * for data, and bit32~47 is used for offset. 6069 */ 6070 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6071 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6072 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6073 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6074 6075 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6076 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6077 return -EOPNOTSUPP; 6078 } 6079 6080 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6081 dev_err(&hdev->pdev->dev, 6082 "user-def offset[%u] should be no more than %u\n", 6083 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6084 return -EINVAL; 6085 } 6086 6087 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6088 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6089 return -EINVAL; 6090 } 6091 6092 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6093 if (ret) { 6094 dev_err(&hdev->pdev->dev, 6095 "unsupported flow type for user-def bytes, ret = %d\n", 6096 ret); 6097 return ret; 6098 } 6099 6100 info->data = data; 6101 info->data_mask = data_mask; 6102 info->offset = offset; 6103 6104 return 0; 6105 } 6106 6107 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6108 struct ethtool_rx_flow_spec *fs, 6109 u32 *unused_tuple, 6110 struct hclge_fd_user_def_info *info) 6111 { 6112 u32 flow_type; 6113 int ret; 6114 6115 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6116 dev_err(&hdev->pdev->dev, 6117 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6118 fs->location, 6119 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6120 return -EINVAL; 6121 } 6122 6123 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6124 if (ret) 6125 return ret; 6126 6127 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6128 switch (flow_type) { 6129 case SCTP_V4_FLOW: 6130 case TCP_V4_FLOW: 6131 case UDP_V4_FLOW: 6132 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6133 unused_tuple); 6134 break; 6135 case IP_USER_FLOW: 6136 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6137 unused_tuple); 6138 break; 6139 case SCTP_V6_FLOW: 6140 case TCP_V6_FLOW: 6141 case UDP_V6_FLOW: 6142 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6143 unused_tuple); 6144 break; 6145 case IPV6_USER_FLOW: 6146 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6147 unused_tuple); 6148 break; 6149 case ETHER_FLOW: 6150 if (hdev->fd_cfg.fd_mode != 6151 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6152 dev_err(&hdev->pdev->dev, 6153 "ETHER_FLOW is not supported in current fd mode!\n"); 6154 return -EOPNOTSUPP; 6155 } 6156 6157 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6158 unused_tuple); 6159 break; 6160 default: 6161 dev_err(&hdev->pdev->dev, 6162 "unsupported protocol type, protocol type = %#x\n", 6163 flow_type); 6164 return -EOPNOTSUPP; 6165 } 6166 6167 if (ret) { 6168 dev_err(&hdev->pdev->dev, 6169 "failed to check flow union tuple, ret = %d\n", 6170 ret); 6171 return ret; 6172 } 6173 6174 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6175 } 6176 6177 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6178 struct hclge_fd_rule *rule, u8 ip_proto) 6179 { 6180 rule->tuples.src_ip[IPV4_INDEX] = 6181 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6182 rule->tuples_mask.src_ip[IPV4_INDEX] = 6183 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6184 6185 rule->tuples.dst_ip[IPV4_INDEX] = 6186 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6187 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6188 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6189 6190 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6191 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6192 6193 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6194 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6195 6196 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6197 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6198 6199 rule->tuples.ether_proto = ETH_P_IP; 6200 rule->tuples_mask.ether_proto = 0xFFFF; 6201 6202 rule->tuples.ip_proto = ip_proto; 6203 rule->tuples_mask.ip_proto = 0xFF; 6204 } 6205 6206 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6207 struct hclge_fd_rule *rule) 6208 { 6209 rule->tuples.src_ip[IPV4_INDEX] = 6210 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6211 rule->tuples_mask.src_ip[IPV4_INDEX] = 6212 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6213 6214 rule->tuples.dst_ip[IPV4_INDEX] = 6215 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6216 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6217 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6218 6219 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6220 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6221 6222 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6223 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6224 6225 rule->tuples.ether_proto = ETH_P_IP; 6226 rule->tuples_mask.ether_proto = 0xFFFF; 6227 } 6228 6229 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6230 struct hclge_fd_rule *rule, u8 ip_proto) 6231 { 6232 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6233 IPV6_SIZE); 6234 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6235 IPV6_SIZE); 6236 6237 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6238 IPV6_SIZE); 6239 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6240 IPV6_SIZE); 6241 6242 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6243 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6244 6245 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6246 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6247 6248 rule->tuples.ether_proto = ETH_P_IPV6; 6249 rule->tuples_mask.ether_proto = 0xFFFF; 6250 6251 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6252 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6253 6254 rule->tuples.ip_proto = ip_proto; 6255 rule->tuples_mask.ip_proto = 0xFF; 6256 } 6257 6258 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6259 struct hclge_fd_rule *rule) 6260 { 6261 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6262 IPV6_SIZE); 6263 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6264 IPV6_SIZE); 6265 6266 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6267 IPV6_SIZE); 6268 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6269 IPV6_SIZE); 6270 6271 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6272 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6273 6274 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6275 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6276 6277 rule->tuples.ether_proto = ETH_P_IPV6; 6278 rule->tuples_mask.ether_proto = 0xFFFF; 6279 } 6280 6281 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6282 struct hclge_fd_rule *rule) 6283 { 6284 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6285 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6286 6287 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6288 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6289 6290 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6291 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6292 } 6293 6294 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6295 struct hclge_fd_rule *rule) 6296 { 6297 switch (info->layer) { 6298 case HCLGE_FD_USER_DEF_L2: 6299 rule->tuples.l2_user_def = info->data; 6300 rule->tuples_mask.l2_user_def = info->data_mask; 6301 break; 6302 case HCLGE_FD_USER_DEF_L3: 6303 rule->tuples.l3_user_def = info->data; 6304 rule->tuples_mask.l3_user_def = info->data_mask; 6305 break; 6306 case HCLGE_FD_USER_DEF_L4: 6307 rule->tuples.l4_user_def = (u32)info->data << 16; 6308 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6309 break; 6310 default: 6311 break; 6312 } 6313 6314 rule->ep.user_def = *info; 6315 } 6316 6317 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6318 struct hclge_fd_rule *rule, 6319 struct hclge_fd_user_def_info *info) 6320 { 6321 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6322 6323 switch (flow_type) { 6324 case SCTP_V4_FLOW: 6325 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6326 break; 6327 case TCP_V4_FLOW: 6328 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6329 break; 6330 case UDP_V4_FLOW: 6331 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6332 break; 6333 case IP_USER_FLOW: 6334 hclge_fd_get_ip4_tuple(fs, rule); 6335 break; 6336 case SCTP_V6_FLOW: 6337 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6338 break; 6339 case TCP_V6_FLOW: 6340 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6341 break; 6342 case UDP_V6_FLOW: 6343 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6344 break; 6345 case IPV6_USER_FLOW: 6346 hclge_fd_get_ip6_tuple(fs, rule); 6347 break; 6348 case ETHER_FLOW: 6349 hclge_fd_get_ether_tuple(fs, rule); 6350 break; 6351 default: 6352 return -EOPNOTSUPP; 6353 } 6354 6355 if (fs->flow_type & FLOW_EXT) { 6356 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6357 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6358 hclge_fd_get_user_def_tuple(info, rule); 6359 } 6360 6361 if (fs->flow_type & FLOW_MAC_EXT) { 6362 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6363 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6364 } 6365 6366 return 0; 6367 } 6368 6369 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6370 struct hclge_fd_rule *rule) 6371 { 6372 int ret; 6373 6374 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6375 if (ret) 6376 return ret; 6377 6378 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6379 } 6380 6381 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6382 struct hclge_fd_rule *rule) 6383 { 6384 int ret; 6385 6386 spin_lock_bh(&hdev->fd_rule_lock); 6387 6388 if (hdev->fd_active_type != rule->rule_type && 6389 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6390 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6391 dev_err(&hdev->pdev->dev, 6392 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6393 rule->rule_type, hdev->fd_active_type); 6394 spin_unlock_bh(&hdev->fd_rule_lock); 6395 return -EINVAL; 6396 } 6397 6398 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6399 if (ret) 6400 goto out; 6401 6402 ret = hclge_clear_arfs_rules(hdev); 6403 if (ret) 6404 goto out; 6405 6406 ret = hclge_fd_config_rule(hdev, rule); 6407 if (ret) 6408 goto out; 6409 6410 rule->state = HCLGE_FD_ACTIVE; 6411 hdev->fd_active_type = rule->rule_type; 6412 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6413 6414 out: 6415 spin_unlock_bh(&hdev->fd_rule_lock); 6416 return ret; 6417 } 6418 6419 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6420 { 6421 struct hclge_vport *vport = hclge_get_vport(handle); 6422 struct hclge_dev *hdev = vport->back; 6423 6424 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6425 } 6426 6427 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6428 u16 *vport_id, u8 *action, u16 *queue_id) 6429 { 6430 struct hclge_vport *vport = hdev->vport; 6431 6432 if (ring_cookie == RX_CLS_FLOW_DISC) { 6433 *action = HCLGE_FD_ACTION_DROP_PACKET; 6434 } else { 6435 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6436 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6437 u16 tqps; 6438 6439 /* To keep consistent with user's configuration, minus 1 when 6440 * printing 'vf', because vf id from ethtool is added 1 for vf. 6441 */ 6442 if (vf > hdev->num_req_vfs) { 6443 dev_err(&hdev->pdev->dev, 6444 "Error: vf id (%u) should be less than %u\n", 6445 vf - 1U, hdev->num_req_vfs); 6446 return -EINVAL; 6447 } 6448 6449 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6450 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6451 6452 if (ring >= tqps) { 6453 dev_err(&hdev->pdev->dev, 6454 "Error: queue id (%u) > max tqp num (%u)\n", 6455 ring, tqps - 1U); 6456 return -EINVAL; 6457 } 6458 6459 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6460 *queue_id = ring; 6461 } 6462 6463 return 0; 6464 } 6465 6466 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6467 struct ethtool_rxnfc *cmd) 6468 { 6469 struct hclge_vport *vport = hclge_get_vport(handle); 6470 struct hclge_dev *hdev = vport->back; 6471 struct hclge_fd_user_def_info info; 6472 u16 dst_vport_id = 0, q_index = 0; 6473 struct ethtool_rx_flow_spec *fs; 6474 struct hclge_fd_rule *rule; 6475 u32 unused = 0; 6476 u8 action; 6477 int ret; 6478 6479 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6480 dev_err(&hdev->pdev->dev, 6481 "flow table director is not supported\n"); 6482 return -EOPNOTSUPP; 6483 } 6484 6485 if (!hdev->fd_en) { 6486 dev_err(&hdev->pdev->dev, 6487 "please enable flow director first\n"); 6488 return -EOPNOTSUPP; 6489 } 6490 6491 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6492 6493 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6494 if (ret) 6495 return ret; 6496 6497 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6498 &action, &q_index); 6499 if (ret) 6500 return ret; 6501 6502 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6503 if (!rule) 6504 return -ENOMEM; 6505 6506 ret = hclge_fd_get_tuple(fs, rule, &info); 6507 if (ret) { 6508 kfree(rule); 6509 return ret; 6510 } 6511 6512 rule->flow_type = fs->flow_type; 6513 rule->location = fs->location; 6514 rule->unused_tuple = unused; 6515 rule->vf_id = dst_vport_id; 6516 rule->queue_id = q_index; 6517 rule->action = action; 6518 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6519 6520 ret = hclge_add_fd_entry_common(hdev, rule); 6521 if (ret) 6522 kfree(rule); 6523 6524 return ret; 6525 } 6526 6527 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6528 struct ethtool_rxnfc *cmd) 6529 { 6530 struct hclge_vport *vport = hclge_get_vport(handle); 6531 struct hclge_dev *hdev = vport->back; 6532 struct ethtool_rx_flow_spec *fs; 6533 int ret; 6534 6535 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6536 return -EOPNOTSUPP; 6537 6538 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6539 6540 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6541 return -EINVAL; 6542 6543 spin_lock_bh(&hdev->fd_rule_lock); 6544 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6545 !test_bit(fs->location, hdev->fd_bmap)) { 6546 dev_err(&hdev->pdev->dev, 6547 "Delete fail, rule %u is inexistent\n", fs->location); 6548 spin_unlock_bh(&hdev->fd_rule_lock); 6549 return -ENOENT; 6550 } 6551 6552 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6553 NULL, false); 6554 if (ret) 6555 goto out; 6556 6557 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6558 6559 out: 6560 spin_unlock_bh(&hdev->fd_rule_lock); 6561 return ret; 6562 } 6563 6564 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6565 bool clear_list) 6566 { 6567 struct hclge_fd_rule *rule; 6568 struct hlist_node *node; 6569 u16 location; 6570 6571 spin_lock_bh(&hdev->fd_rule_lock); 6572 6573 for_each_set_bit(location, hdev->fd_bmap, 6574 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6575 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6576 NULL, false); 6577 6578 if (clear_list) { 6579 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6580 rule_node) { 6581 hlist_del(&rule->rule_node); 6582 kfree(rule); 6583 } 6584 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6585 hdev->hclge_fd_rule_num = 0; 6586 bitmap_zero(hdev->fd_bmap, 6587 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6588 } 6589 6590 spin_unlock_bh(&hdev->fd_rule_lock); 6591 } 6592 6593 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6594 { 6595 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6596 return; 6597 6598 hclge_clear_fd_rules_in_list(hdev, true); 6599 hclge_fd_disable_user_def(hdev); 6600 } 6601 6602 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6603 { 6604 struct hclge_vport *vport = hclge_get_vport(handle); 6605 struct hclge_dev *hdev = vport->back; 6606 struct hclge_fd_rule *rule; 6607 struct hlist_node *node; 6608 6609 /* Return ok here, because reset error handling will check this 6610 * return value. If error is returned here, the reset process will 6611 * fail. 6612 */ 6613 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6614 return 0; 6615 6616 /* if fd is disabled, should not restore it when reset */ 6617 if (!hdev->fd_en) 6618 return 0; 6619 6620 spin_lock_bh(&hdev->fd_rule_lock); 6621 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6622 if (rule->state == HCLGE_FD_ACTIVE) 6623 rule->state = HCLGE_FD_TO_ADD; 6624 } 6625 spin_unlock_bh(&hdev->fd_rule_lock); 6626 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6627 6628 return 0; 6629 } 6630 6631 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6632 struct ethtool_rxnfc *cmd) 6633 { 6634 struct hclge_vport *vport = hclge_get_vport(handle); 6635 struct hclge_dev *hdev = vport->back; 6636 6637 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6638 return -EOPNOTSUPP; 6639 6640 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6641 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6642 6643 return 0; 6644 } 6645 6646 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6647 struct ethtool_tcpip4_spec *spec, 6648 struct ethtool_tcpip4_spec *spec_mask) 6649 { 6650 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6651 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6652 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6653 6654 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6655 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6656 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6657 6658 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6659 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6660 0 : cpu_to_be16(rule->tuples_mask.src_port); 6661 6662 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6663 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6664 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6665 6666 spec->tos = rule->tuples.ip_tos; 6667 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6668 0 : rule->tuples_mask.ip_tos; 6669 } 6670 6671 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6672 struct ethtool_usrip4_spec *spec, 6673 struct ethtool_usrip4_spec *spec_mask) 6674 { 6675 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6676 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6677 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6678 6679 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6680 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6681 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6682 6683 spec->tos = rule->tuples.ip_tos; 6684 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6685 0 : rule->tuples_mask.ip_tos; 6686 6687 spec->proto = rule->tuples.ip_proto; 6688 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6689 0 : rule->tuples_mask.ip_proto; 6690 6691 spec->ip_ver = ETH_RX_NFC_IP4; 6692 } 6693 6694 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6695 struct ethtool_tcpip6_spec *spec, 6696 struct ethtool_tcpip6_spec *spec_mask) 6697 { 6698 cpu_to_be32_array(spec->ip6src, 6699 rule->tuples.src_ip, IPV6_SIZE); 6700 cpu_to_be32_array(spec->ip6dst, 6701 rule->tuples.dst_ip, IPV6_SIZE); 6702 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6703 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6704 else 6705 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6706 IPV6_SIZE); 6707 6708 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6709 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6710 else 6711 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6712 IPV6_SIZE); 6713 6714 spec->tclass = rule->tuples.ip_tos; 6715 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6716 0 : rule->tuples_mask.ip_tos; 6717 6718 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6719 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6720 0 : cpu_to_be16(rule->tuples_mask.src_port); 6721 6722 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6723 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6724 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6725 } 6726 6727 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6728 struct ethtool_usrip6_spec *spec, 6729 struct ethtool_usrip6_spec *spec_mask) 6730 { 6731 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6732 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6733 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6734 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6735 else 6736 cpu_to_be32_array(spec_mask->ip6src, 6737 rule->tuples_mask.src_ip, IPV6_SIZE); 6738 6739 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6740 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6741 else 6742 cpu_to_be32_array(spec_mask->ip6dst, 6743 rule->tuples_mask.dst_ip, IPV6_SIZE); 6744 6745 spec->tclass = rule->tuples.ip_tos; 6746 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6747 0 : rule->tuples_mask.ip_tos; 6748 6749 spec->l4_proto = rule->tuples.ip_proto; 6750 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6751 0 : rule->tuples_mask.ip_proto; 6752 } 6753 6754 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6755 struct ethhdr *spec, 6756 struct ethhdr *spec_mask) 6757 { 6758 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6759 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6760 6761 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6762 eth_zero_addr(spec_mask->h_source); 6763 else 6764 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6765 6766 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6767 eth_zero_addr(spec_mask->h_dest); 6768 else 6769 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6770 6771 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6772 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6773 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6774 } 6775 6776 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6777 struct hclge_fd_rule *rule) 6778 { 6779 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6780 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6781 fs->h_ext.data[0] = 0; 6782 fs->h_ext.data[1] = 0; 6783 fs->m_ext.data[0] = 0; 6784 fs->m_ext.data[1] = 0; 6785 } else { 6786 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6787 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6788 fs->m_ext.data[0] = 6789 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6790 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6791 } 6792 } 6793 6794 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6795 struct hclge_fd_rule *rule) 6796 { 6797 if (fs->flow_type & FLOW_EXT) { 6798 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6799 fs->m_ext.vlan_tci = 6800 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6801 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6802 6803 hclge_fd_get_user_def_info(fs, rule); 6804 } 6805 6806 if (fs->flow_type & FLOW_MAC_EXT) { 6807 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6808 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6809 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6810 else 6811 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6812 rule->tuples_mask.dst_mac); 6813 } 6814 } 6815 6816 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6817 u16 location) 6818 { 6819 struct hclge_fd_rule *rule = NULL; 6820 struct hlist_node *node2; 6821 6822 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6823 if (rule->location == location) 6824 return rule; 6825 else if (rule->location > location) 6826 return NULL; 6827 } 6828 6829 return NULL; 6830 } 6831 6832 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6833 struct hclge_fd_rule *rule) 6834 { 6835 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6836 fs->ring_cookie = RX_CLS_FLOW_DISC; 6837 } else { 6838 u64 vf_id; 6839 6840 fs->ring_cookie = rule->queue_id; 6841 vf_id = rule->vf_id; 6842 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6843 fs->ring_cookie |= vf_id; 6844 } 6845 } 6846 6847 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6848 struct ethtool_rxnfc *cmd) 6849 { 6850 struct hclge_vport *vport = hclge_get_vport(handle); 6851 struct hclge_fd_rule *rule = NULL; 6852 struct hclge_dev *hdev = vport->back; 6853 struct ethtool_rx_flow_spec *fs; 6854 6855 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6856 return -EOPNOTSUPP; 6857 6858 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6859 6860 spin_lock_bh(&hdev->fd_rule_lock); 6861 6862 rule = hclge_get_fd_rule(hdev, fs->location); 6863 if (!rule) { 6864 spin_unlock_bh(&hdev->fd_rule_lock); 6865 return -ENOENT; 6866 } 6867 6868 fs->flow_type = rule->flow_type; 6869 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6870 case SCTP_V4_FLOW: 6871 case TCP_V4_FLOW: 6872 case UDP_V4_FLOW: 6873 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6874 &fs->m_u.tcp_ip4_spec); 6875 break; 6876 case IP_USER_FLOW: 6877 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6878 &fs->m_u.usr_ip4_spec); 6879 break; 6880 case SCTP_V6_FLOW: 6881 case TCP_V6_FLOW: 6882 case UDP_V6_FLOW: 6883 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6884 &fs->m_u.tcp_ip6_spec); 6885 break; 6886 case IPV6_USER_FLOW: 6887 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6888 &fs->m_u.usr_ip6_spec); 6889 break; 6890 /* The flow type of fd rule has been checked before adding in to rule 6891 * list. As other flow types have been handled, it must be ETHER_FLOW 6892 * for the default case 6893 */ 6894 default: 6895 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6896 &fs->m_u.ether_spec); 6897 break; 6898 } 6899 6900 hclge_fd_get_ext_info(fs, rule); 6901 6902 hclge_fd_get_ring_cookie(fs, rule); 6903 6904 spin_unlock_bh(&hdev->fd_rule_lock); 6905 6906 return 0; 6907 } 6908 6909 static int hclge_get_all_rules(struct hnae3_handle *handle, 6910 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6911 { 6912 struct hclge_vport *vport = hclge_get_vport(handle); 6913 struct hclge_dev *hdev = vport->back; 6914 struct hclge_fd_rule *rule; 6915 struct hlist_node *node2; 6916 int cnt = 0; 6917 6918 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6919 return -EOPNOTSUPP; 6920 6921 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6922 6923 spin_lock_bh(&hdev->fd_rule_lock); 6924 hlist_for_each_entry_safe(rule, node2, 6925 &hdev->fd_rule_list, rule_node) { 6926 if (cnt == cmd->rule_cnt) { 6927 spin_unlock_bh(&hdev->fd_rule_lock); 6928 return -EMSGSIZE; 6929 } 6930 6931 if (rule->state == HCLGE_FD_TO_DEL) 6932 continue; 6933 6934 rule_locs[cnt] = rule->location; 6935 cnt++; 6936 } 6937 6938 spin_unlock_bh(&hdev->fd_rule_lock); 6939 6940 cmd->rule_cnt = cnt; 6941 6942 return 0; 6943 } 6944 6945 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 6946 struct hclge_fd_rule_tuples *tuples) 6947 { 6948 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 6949 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 6950 6951 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 6952 tuples->ip_proto = fkeys->basic.ip_proto; 6953 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 6954 6955 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 6956 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 6957 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 6958 } else { 6959 int i; 6960 6961 for (i = 0; i < IPV6_SIZE; i++) { 6962 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 6963 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 6964 } 6965 } 6966 } 6967 6968 /* traverse all rules, check whether an existed rule has the same tuples */ 6969 static struct hclge_fd_rule * 6970 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 6971 const struct hclge_fd_rule_tuples *tuples) 6972 { 6973 struct hclge_fd_rule *rule = NULL; 6974 struct hlist_node *node; 6975 6976 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6977 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 6978 return rule; 6979 } 6980 6981 return NULL; 6982 } 6983 6984 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 6985 struct hclge_fd_rule *rule) 6986 { 6987 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6988 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 6989 BIT(INNER_SRC_PORT); 6990 rule->action = 0; 6991 rule->vf_id = 0; 6992 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 6993 rule->state = HCLGE_FD_TO_ADD; 6994 if (tuples->ether_proto == ETH_P_IP) { 6995 if (tuples->ip_proto == IPPROTO_TCP) 6996 rule->flow_type = TCP_V4_FLOW; 6997 else 6998 rule->flow_type = UDP_V4_FLOW; 6999 } else { 7000 if (tuples->ip_proto == IPPROTO_TCP) 7001 rule->flow_type = TCP_V6_FLOW; 7002 else 7003 rule->flow_type = UDP_V6_FLOW; 7004 } 7005 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7006 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7007 } 7008 7009 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7010 u16 flow_id, struct flow_keys *fkeys) 7011 { 7012 struct hclge_vport *vport = hclge_get_vport(handle); 7013 struct hclge_fd_rule_tuples new_tuples = {}; 7014 struct hclge_dev *hdev = vport->back; 7015 struct hclge_fd_rule *rule; 7016 u16 bit_id; 7017 7018 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7019 return -EOPNOTSUPP; 7020 7021 /* when there is already fd rule existed add by user, 7022 * arfs should not work 7023 */ 7024 spin_lock_bh(&hdev->fd_rule_lock); 7025 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7026 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7027 spin_unlock_bh(&hdev->fd_rule_lock); 7028 return -EOPNOTSUPP; 7029 } 7030 7031 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7032 7033 /* check is there flow director filter existed for this flow, 7034 * if not, create a new filter for it; 7035 * if filter exist with different queue id, modify the filter; 7036 * if filter exist with same queue id, do nothing 7037 */ 7038 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7039 if (!rule) { 7040 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7041 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7042 spin_unlock_bh(&hdev->fd_rule_lock); 7043 return -ENOSPC; 7044 } 7045 7046 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7047 if (!rule) { 7048 spin_unlock_bh(&hdev->fd_rule_lock); 7049 return -ENOMEM; 7050 } 7051 7052 rule->location = bit_id; 7053 rule->arfs.flow_id = flow_id; 7054 rule->queue_id = queue_id; 7055 hclge_fd_build_arfs_rule(&new_tuples, rule); 7056 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7057 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7058 } else if (rule->queue_id != queue_id) { 7059 rule->queue_id = queue_id; 7060 rule->state = HCLGE_FD_TO_ADD; 7061 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7062 hclge_task_schedule(hdev, 0); 7063 } 7064 spin_unlock_bh(&hdev->fd_rule_lock); 7065 return rule->location; 7066 } 7067 7068 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7069 { 7070 #ifdef CONFIG_RFS_ACCEL 7071 struct hnae3_handle *handle = &hdev->vport[0].nic; 7072 struct hclge_fd_rule *rule; 7073 struct hlist_node *node; 7074 7075 spin_lock_bh(&hdev->fd_rule_lock); 7076 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7077 spin_unlock_bh(&hdev->fd_rule_lock); 7078 return; 7079 } 7080 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7081 if (rule->state != HCLGE_FD_ACTIVE) 7082 continue; 7083 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7084 rule->arfs.flow_id, rule->location)) { 7085 rule->state = HCLGE_FD_TO_DEL; 7086 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7087 } 7088 } 7089 spin_unlock_bh(&hdev->fd_rule_lock); 7090 #endif 7091 } 7092 7093 /* make sure being called after lock up with fd_rule_lock */ 7094 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7095 { 7096 #ifdef CONFIG_RFS_ACCEL 7097 struct hclge_fd_rule *rule; 7098 struct hlist_node *node; 7099 int ret; 7100 7101 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7102 return 0; 7103 7104 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7105 switch (rule->state) { 7106 case HCLGE_FD_TO_DEL: 7107 case HCLGE_FD_ACTIVE: 7108 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7109 rule->location, NULL, false); 7110 if (ret) 7111 return ret; 7112 fallthrough; 7113 case HCLGE_FD_TO_ADD: 7114 hclge_fd_dec_rule_cnt(hdev, rule->location); 7115 hlist_del(&rule->rule_node); 7116 kfree(rule); 7117 break; 7118 default: 7119 break; 7120 } 7121 } 7122 hclge_sync_fd_state(hdev); 7123 7124 #endif 7125 return 0; 7126 } 7127 7128 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7129 struct hclge_fd_rule *rule) 7130 { 7131 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7132 struct flow_match_basic match; 7133 u16 ethtype_key, ethtype_mask; 7134 7135 flow_rule_match_basic(flow, &match); 7136 ethtype_key = ntohs(match.key->n_proto); 7137 ethtype_mask = ntohs(match.mask->n_proto); 7138 7139 if (ethtype_key == ETH_P_ALL) { 7140 ethtype_key = 0; 7141 ethtype_mask = 0; 7142 } 7143 rule->tuples.ether_proto = ethtype_key; 7144 rule->tuples_mask.ether_proto = ethtype_mask; 7145 rule->tuples.ip_proto = match.key->ip_proto; 7146 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7147 } else { 7148 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7149 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7150 } 7151 } 7152 7153 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7154 struct hclge_fd_rule *rule) 7155 { 7156 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7157 struct flow_match_eth_addrs match; 7158 7159 flow_rule_match_eth_addrs(flow, &match); 7160 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7161 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7162 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7163 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7164 } else { 7165 rule->unused_tuple |= BIT(INNER_DST_MAC); 7166 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7167 } 7168 } 7169 7170 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7171 struct hclge_fd_rule *rule) 7172 { 7173 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7174 struct flow_match_vlan match; 7175 7176 flow_rule_match_vlan(flow, &match); 7177 rule->tuples.vlan_tag1 = match.key->vlan_id | 7178 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7179 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7180 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7181 } else { 7182 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7183 } 7184 } 7185 7186 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7187 struct hclge_fd_rule *rule) 7188 { 7189 u16 addr_type = 0; 7190 7191 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7192 struct flow_match_control match; 7193 7194 flow_rule_match_control(flow, &match); 7195 addr_type = match.key->addr_type; 7196 } 7197 7198 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7199 struct flow_match_ipv4_addrs match; 7200 7201 flow_rule_match_ipv4_addrs(flow, &match); 7202 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7203 rule->tuples_mask.src_ip[IPV4_INDEX] = 7204 be32_to_cpu(match.mask->src); 7205 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7206 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7207 be32_to_cpu(match.mask->dst); 7208 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7209 struct flow_match_ipv6_addrs match; 7210 7211 flow_rule_match_ipv6_addrs(flow, &match); 7212 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7213 IPV6_SIZE); 7214 be32_to_cpu_array(rule->tuples_mask.src_ip, 7215 match.mask->src.s6_addr32, IPV6_SIZE); 7216 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7217 IPV6_SIZE); 7218 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7219 match.mask->dst.s6_addr32, IPV6_SIZE); 7220 } else { 7221 rule->unused_tuple |= BIT(INNER_SRC_IP); 7222 rule->unused_tuple |= BIT(INNER_DST_IP); 7223 } 7224 } 7225 7226 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7227 struct hclge_fd_rule *rule) 7228 { 7229 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7230 struct flow_match_ports match; 7231 7232 flow_rule_match_ports(flow, &match); 7233 7234 rule->tuples.src_port = be16_to_cpu(match.key->src); 7235 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7236 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7237 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7238 } else { 7239 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7240 rule->unused_tuple |= BIT(INNER_DST_PORT); 7241 } 7242 } 7243 7244 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7245 struct flow_cls_offload *cls_flower, 7246 struct hclge_fd_rule *rule) 7247 { 7248 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7249 struct flow_dissector *dissector = flow->match.dissector; 7250 7251 if (dissector->used_keys & 7252 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 7253 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 7254 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7255 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 7256 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7257 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7258 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) { 7259 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n", 7260 dissector->used_keys); 7261 return -EOPNOTSUPP; 7262 } 7263 7264 hclge_get_cls_key_basic(flow, rule); 7265 hclge_get_cls_key_mac(flow, rule); 7266 hclge_get_cls_key_vlan(flow, rule); 7267 hclge_get_cls_key_ip(flow, rule); 7268 hclge_get_cls_key_port(flow, rule); 7269 7270 return 0; 7271 } 7272 7273 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7274 struct flow_cls_offload *cls_flower, int tc) 7275 { 7276 u32 prio = cls_flower->common.prio; 7277 7278 if (tc < 0 || tc > hdev->tc_max) { 7279 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7280 return -EINVAL; 7281 } 7282 7283 if (prio == 0 || 7284 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7285 dev_err(&hdev->pdev->dev, 7286 "prio %u should be in range[1, %u]\n", 7287 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7288 return -EINVAL; 7289 } 7290 7291 if (test_bit(prio - 1, hdev->fd_bmap)) { 7292 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7293 return -EINVAL; 7294 } 7295 return 0; 7296 } 7297 7298 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7299 struct flow_cls_offload *cls_flower, 7300 int tc) 7301 { 7302 struct hclge_vport *vport = hclge_get_vport(handle); 7303 struct hclge_dev *hdev = vport->back; 7304 struct hclge_fd_rule *rule; 7305 int ret; 7306 7307 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7308 dev_err(&hdev->pdev->dev, 7309 "cls flower is not supported\n"); 7310 return -EOPNOTSUPP; 7311 } 7312 7313 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7314 if (ret) { 7315 dev_err(&hdev->pdev->dev, 7316 "failed to check cls flower params, ret = %d\n", ret); 7317 return ret; 7318 } 7319 7320 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7321 if (!rule) 7322 return -ENOMEM; 7323 7324 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7325 if (ret) { 7326 kfree(rule); 7327 return ret; 7328 } 7329 7330 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7331 rule->cls_flower.tc = tc; 7332 rule->location = cls_flower->common.prio - 1; 7333 rule->vf_id = 0; 7334 rule->cls_flower.cookie = cls_flower->cookie; 7335 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7336 7337 ret = hclge_add_fd_entry_common(hdev, rule); 7338 if (ret) 7339 kfree(rule); 7340 7341 return ret; 7342 } 7343 7344 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7345 unsigned long cookie) 7346 { 7347 struct hclge_fd_rule *rule; 7348 struct hlist_node *node; 7349 7350 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7351 if (rule->cls_flower.cookie == cookie) 7352 return rule; 7353 } 7354 7355 return NULL; 7356 } 7357 7358 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7359 struct flow_cls_offload *cls_flower) 7360 { 7361 struct hclge_vport *vport = hclge_get_vport(handle); 7362 struct hclge_dev *hdev = vport->back; 7363 struct hclge_fd_rule *rule; 7364 int ret; 7365 7366 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7367 return -EOPNOTSUPP; 7368 7369 spin_lock_bh(&hdev->fd_rule_lock); 7370 7371 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7372 if (!rule) { 7373 spin_unlock_bh(&hdev->fd_rule_lock); 7374 return -EINVAL; 7375 } 7376 7377 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7378 NULL, false); 7379 if (ret) { 7380 /* if tcam config fail, set rule state to TO_DEL, 7381 * so the rule will be deleted when periodic 7382 * task being scheduled. 7383 */ 7384 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL); 7385 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7386 spin_unlock_bh(&hdev->fd_rule_lock); 7387 return ret; 7388 } 7389 7390 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7391 spin_unlock_bh(&hdev->fd_rule_lock); 7392 7393 return 0; 7394 } 7395 7396 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7397 { 7398 struct hclge_fd_rule *rule; 7399 struct hlist_node *node; 7400 int ret = 0; 7401 7402 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7403 return; 7404 7405 spin_lock_bh(&hdev->fd_rule_lock); 7406 7407 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7408 switch (rule->state) { 7409 case HCLGE_FD_TO_ADD: 7410 ret = hclge_fd_config_rule(hdev, rule); 7411 if (ret) 7412 goto out; 7413 rule->state = HCLGE_FD_ACTIVE; 7414 break; 7415 case HCLGE_FD_TO_DEL: 7416 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7417 rule->location, NULL, false); 7418 if (ret) 7419 goto out; 7420 hclge_fd_dec_rule_cnt(hdev, rule->location); 7421 hclge_fd_free_node(hdev, rule); 7422 break; 7423 default: 7424 break; 7425 } 7426 } 7427 7428 out: 7429 if (ret) 7430 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7431 7432 spin_unlock_bh(&hdev->fd_rule_lock); 7433 } 7434 7435 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7436 { 7437 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7438 return; 7439 7440 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7441 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7442 7443 hclge_clear_fd_rules_in_list(hdev, clear_list); 7444 } 7445 7446 hclge_sync_fd_user_def_cfg(hdev, false); 7447 7448 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7449 } 7450 7451 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7452 { 7453 struct hclge_vport *vport = hclge_get_vport(handle); 7454 struct hclge_dev *hdev = vport->back; 7455 7456 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7457 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7458 } 7459 7460 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7461 { 7462 struct hclge_vport *vport = hclge_get_vport(handle); 7463 struct hclge_dev *hdev = vport->back; 7464 7465 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7466 } 7467 7468 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7469 { 7470 struct hclge_vport *vport = hclge_get_vport(handle); 7471 struct hclge_dev *hdev = vport->back; 7472 7473 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7474 } 7475 7476 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7477 { 7478 struct hclge_vport *vport = hclge_get_vport(handle); 7479 struct hclge_dev *hdev = vport->back; 7480 7481 return hdev->rst_stats.hw_reset_done_cnt; 7482 } 7483 7484 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7485 { 7486 struct hclge_vport *vport = hclge_get_vport(handle); 7487 struct hclge_dev *hdev = vport->back; 7488 7489 hdev->fd_en = enable; 7490 7491 if (!enable) 7492 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7493 else 7494 hclge_restore_fd_entries(handle); 7495 7496 hclge_task_schedule(hdev, 0); 7497 } 7498 7499 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7500 { 7501 #define HCLGE_LINK_STATUS_WAIT_CNT 3 7502 7503 struct hclge_desc desc; 7504 struct hclge_config_mac_mode_cmd *req = 7505 (struct hclge_config_mac_mode_cmd *)desc.data; 7506 u32 loop_en = 0; 7507 int ret; 7508 7509 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7510 7511 if (enable) { 7512 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7513 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7514 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7515 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7516 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7517 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7518 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7519 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7520 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7521 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7522 } 7523 7524 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7525 7526 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7527 if (ret) { 7528 dev_err(&hdev->pdev->dev, 7529 "mac enable fail, ret =%d.\n", ret); 7530 return; 7531 } 7532 7533 if (!enable) 7534 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7535 HCLGE_LINK_STATUS_WAIT_CNT); 7536 } 7537 7538 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7539 u8 switch_param, u8 param_mask) 7540 { 7541 struct hclge_mac_vlan_switch_cmd *req; 7542 struct hclge_desc desc; 7543 u32 func_id; 7544 int ret; 7545 7546 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7547 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7548 7549 /* read current config parameter */ 7550 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7551 true); 7552 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7553 req->func_id = cpu_to_le32(func_id); 7554 7555 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7556 if (ret) { 7557 dev_err(&hdev->pdev->dev, 7558 "read mac vlan switch parameter fail, ret = %d\n", ret); 7559 return ret; 7560 } 7561 7562 /* modify and write new config parameter */ 7563 hclge_comm_cmd_reuse_desc(&desc, false); 7564 req->switch_param = (req->switch_param & param_mask) | switch_param; 7565 req->param_mask = param_mask; 7566 7567 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7568 if (ret) 7569 dev_err(&hdev->pdev->dev, 7570 "set mac vlan switch parameter fail, ret = %d\n", ret); 7571 return ret; 7572 } 7573 7574 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7575 int link_ret) 7576 { 7577 #define HCLGE_PHY_LINK_STATUS_NUM 200 7578 7579 struct phy_device *phydev = hdev->hw.mac.phydev; 7580 int i = 0; 7581 int ret; 7582 7583 do { 7584 ret = phy_read_status(phydev); 7585 if (ret) { 7586 dev_err(&hdev->pdev->dev, 7587 "phy update link status fail, ret = %d\n", ret); 7588 return; 7589 } 7590 7591 if (phydev->link == link_ret) 7592 break; 7593 7594 msleep(HCLGE_LINK_STATUS_MS); 7595 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7596 } 7597 7598 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7599 int wait_cnt) 7600 { 7601 int link_status; 7602 int i = 0; 7603 int ret; 7604 7605 do { 7606 ret = hclge_get_mac_link_status(hdev, &link_status); 7607 if (ret) 7608 return ret; 7609 if (link_status == link_ret) 7610 return 0; 7611 7612 msleep(HCLGE_LINK_STATUS_MS); 7613 } while (++i < wait_cnt); 7614 return -EBUSY; 7615 } 7616 7617 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7618 bool is_phy) 7619 { 7620 #define HCLGE_MAC_LINK_STATUS_NUM 100 7621 7622 int link_ret; 7623 7624 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7625 7626 if (is_phy) 7627 hclge_phy_link_status_wait(hdev, link_ret); 7628 7629 return hclge_mac_link_status_wait(hdev, link_ret, 7630 HCLGE_MAC_LINK_STATUS_NUM); 7631 } 7632 7633 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7634 { 7635 struct hclge_config_mac_mode_cmd *req; 7636 struct hclge_desc desc; 7637 u32 loop_en; 7638 int ret; 7639 7640 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7641 /* 1 Read out the MAC mode config at first */ 7642 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7643 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7644 if (ret) { 7645 dev_err(&hdev->pdev->dev, 7646 "mac loopback get fail, ret =%d.\n", ret); 7647 return ret; 7648 } 7649 7650 /* 2 Then setup the loopback flag */ 7651 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7652 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7653 7654 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7655 7656 /* 3 Config mac work mode with loopback flag 7657 * and its original configure parameters 7658 */ 7659 hclge_comm_cmd_reuse_desc(&desc, false); 7660 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7661 if (ret) 7662 dev_err(&hdev->pdev->dev, 7663 "mac loopback set fail, ret =%d.\n", ret); 7664 return ret; 7665 } 7666 7667 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7668 enum hnae3_loop loop_mode) 7669 { 7670 struct hclge_common_lb_cmd *req; 7671 struct hclge_desc desc; 7672 u8 loop_mode_b; 7673 int ret; 7674 7675 req = (struct hclge_common_lb_cmd *)desc.data; 7676 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7677 7678 switch (loop_mode) { 7679 case HNAE3_LOOP_SERIAL_SERDES: 7680 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7681 break; 7682 case HNAE3_LOOP_PARALLEL_SERDES: 7683 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7684 break; 7685 case HNAE3_LOOP_PHY: 7686 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7687 break; 7688 default: 7689 dev_err(&hdev->pdev->dev, 7690 "unsupported loopback mode %d\n", loop_mode); 7691 return -ENOTSUPP; 7692 } 7693 7694 req->mask = loop_mode_b; 7695 if (en) 7696 req->enable = loop_mode_b; 7697 7698 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7699 if (ret) 7700 dev_err(&hdev->pdev->dev, 7701 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7702 loop_mode, ret); 7703 7704 return ret; 7705 } 7706 7707 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7708 { 7709 #define HCLGE_COMMON_LB_RETRY_MS 10 7710 #define HCLGE_COMMON_LB_RETRY_NUM 100 7711 7712 struct hclge_common_lb_cmd *req; 7713 struct hclge_desc desc; 7714 u32 i = 0; 7715 int ret; 7716 7717 req = (struct hclge_common_lb_cmd *)desc.data; 7718 7719 do { 7720 msleep(HCLGE_COMMON_LB_RETRY_MS); 7721 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7722 true); 7723 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7724 if (ret) { 7725 dev_err(&hdev->pdev->dev, 7726 "failed to get loopback done status, ret = %d\n", 7727 ret); 7728 return ret; 7729 } 7730 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7731 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7732 7733 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7734 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7735 return -EBUSY; 7736 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7737 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7738 return -EIO; 7739 } 7740 7741 return 0; 7742 } 7743 7744 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7745 enum hnae3_loop loop_mode) 7746 { 7747 int ret; 7748 7749 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7750 if (ret) 7751 return ret; 7752 7753 return hclge_cfg_common_loopback_wait(hdev); 7754 } 7755 7756 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7757 enum hnae3_loop loop_mode) 7758 { 7759 int ret; 7760 7761 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7762 if (ret) 7763 return ret; 7764 7765 hclge_cfg_mac_mode(hdev, en); 7766 7767 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7768 if (ret) 7769 dev_err(&hdev->pdev->dev, 7770 "serdes loopback config mac mode timeout\n"); 7771 7772 return ret; 7773 } 7774 7775 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7776 struct phy_device *phydev) 7777 { 7778 int ret; 7779 7780 if (!phydev->suspended) { 7781 ret = phy_suspend(phydev); 7782 if (ret) 7783 return ret; 7784 } 7785 7786 ret = phy_resume(phydev); 7787 if (ret) 7788 return ret; 7789 7790 return phy_loopback(phydev, true); 7791 } 7792 7793 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7794 struct phy_device *phydev) 7795 { 7796 int ret; 7797 7798 ret = phy_loopback(phydev, false); 7799 if (ret) 7800 return ret; 7801 7802 return phy_suspend(phydev); 7803 } 7804 7805 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7806 { 7807 struct phy_device *phydev = hdev->hw.mac.phydev; 7808 int ret; 7809 7810 if (!phydev) { 7811 if (hnae3_dev_phy_imp_supported(hdev)) 7812 return hclge_set_common_loopback(hdev, en, 7813 HNAE3_LOOP_PHY); 7814 return -ENOTSUPP; 7815 } 7816 7817 if (en) 7818 ret = hclge_enable_phy_loopback(hdev, phydev); 7819 else 7820 ret = hclge_disable_phy_loopback(hdev, phydev); 7821 if (ret) { 7822 dev_err(&hdev->pdev->dev, 7823 "set phy loopback fail, ret = %d\n", ret); 7824 return ret; 7825 } 7826 7827 hclge_cfg_mac_mode(hdev, en); 7828 7829 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7830 if (ret) 7831 dev_err(&hdev->pdev->dev, 7832 "phy loopback config mac mode timeout\n"); 7833 7834 return ret; 7835 } 7836 7837 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7838 u16 stream_id, bool enable) 7839 { 7840 struct hclge_desc desc; 7841 struct hclge_cfg_com_tqp_queue_cmd *req = 7842 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7843 7844 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7845 req->tqp_id = cpu_to_le16(tqp_id); 7846 req->stream_id = cpu_to_le16(stream_id); 7847 if (enable) 7848 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7849 7850 return hclge_cmd_send(&hdev->hw, &desc, 1); 7851 } 7852 7853 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7854 { 7855 struct hclge_vport *vport = hclge_get_vport(handle); 7856 struct hclge_dev *hdev = vport->back; 7857 int ret; 7858 u16 i; 7859 7860 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7861 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7862 if (ret) 7863 return ret; 7864 } 7865 return 0; 7866 } 7867 7868 static int hclge_set_loopback(struct hnae3_handle *handle, 7869 enum hnae3_loop loop_mode, bool en) 7870 { 7871 struct hclge_vport *vport = hclge_get_vport(handle); 7872 struct hclge_dev *hdev = vport->back; 7873 int ret = 0; 7874 7875 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7876 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7877 * the same, the packets are looped back in the SSU. If SSU loopback 7878 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7879 */ 7880 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7881 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7882 7883 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7884 HCLGE_SWITCH_ALW_LPBK_MASK); 7885 if (ret) 7886 return ret; 7887 } 7888 7889 switch (loop_mode) { 7890 case HNAE3_LOOP_APP: 7891 ret = hclge_set_app_loopback(hdev, en); 7892 break; 7893 case HNAE3_LOOP_SERIAL_SERDES: 7894 case HNAE3_LOOP_PARALLEL_SERDES: 7895 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7896 break; 7897 case HNAE3_LOOP_PHY: 7898 ret = hclge_set_phy_loopback(hdev, en); 7899 break; 7900 case HNAE3_LOOP_EXTERNAL: 7901 break; 7902 default: 7903 ret = -ENOTSUPP; 7904 dev_err(&hdev->pdev->dev, 7905 "loop_mode %d is not supported\n", loop_mode); 7906 break; 7907 } 7908 7909 if (ret) 7910 return ret; 7911 7912 ret = hclge_tqp_enable(handle, en); 7913 if (ret) 7914 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7915 en ? "enable" : "disable", ret); 7916 7917 return ret; 7918 } 7919 7920 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7921 { 7922 int ret; 7923 7924 ret = hclge_set_app_loopback(hdev, false); 7925 if (ret) 7926 return ret; 7927 7928 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7929 if (ret) 7930 return ret; 7931 7932 return hclge_cfg_common_loopback(hdev, false, 7933 HNAE3_LOOP_PARALLEL_SERDES); 7934 } 7935 7936 static void hclge_flush_link_update(struct hclge_dev *hdev) 7937 { 7938 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7939 7940 unsigned long last = hdev->serv_processed_cnt; 7941 int i = 0; 7942 7943 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 7944 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 7945 last == hdev->serv_processed_cnt) 7946 usleep_range(1, 1); 7947 } 7948 7949 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 7950 { 7951 struct hclge_vport *vport = hclge_get_vport(handle); 7952 struct hclge_dev *hdev = vport->back; 7953 7954 if (enable) { 7955 hclge_task_schedule(hdev, 0); 7956 } else { 7957 /* Set the DOWN flag here to disable link updating */ 7958 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7959 7960 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 7961 hclge_flush_link_update(hdev); 7962 } 7963 } 7964 7965 static int hclge_ae_start(struct hnae3_handle *handle) 7966 { 7967 struct hclge_vport *vport = hclge_get_vport(handle); 7968 struct hclge_dev *hdev = vport->back; 7969 7970 /* mac enable */ 7971 hclge_cfg_mac_mode(hdev, true); 7972 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 7973 hdev->hw.mac.link = 0; 7974 7975 /* reset tqp stats */ 7976 hclge_comm_reset_tqp_stats(handle); 7977 7978 hclge_mac_start_phy(hdev); 7979 7980 return 0; 7981 } 7982 7983 static void hclge_ae_stop(struct hnae3_handle *handle) 7984 { 7985 struct hclge_vport *vport = hclge_get_vport(handle); 7986 struct hclge_dev *hdev = vport->back; 7987 7988 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7989 spin_lock_bh(&hdev->fd_rule_lock); 7990 hclge_clear_arfs_rules(hdev); 7991 spin_unlock_bh(&hdev->fd_rule_lock); 7992 7993 /* If it is not PF reset or FLR, the firmware will disable the MAC, 7994 * so it only need to stop phy here. 7995 */ 7996 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 7997 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 7998 HCLGE_PFC_DISABLE); 7999 if (hdev->reset_type != HNAE3_FUNC_RESET && 8000 hdev->reset_type != HNAE3_FLR_RESET) { 8001 hclge_mac_stop_phy(hdev); 8002 hclge_update_link_status(hdev); 8003 return; 8004 } 8005 } 8006 8007 hclge_reset_tqp(handle); 8008 8009 hclge_config_mac_tnl_int(hdev, false); 8010 8011 /* Mac disable */ 8012 hclge_cfg_mac_mode(hdev, false); 8013 8014 hclge_mac_stop_phy(hdev); 8015 8016 /* reset tqp stats */ 8017 hclge_comm_reset_tqp_stats(handle); 8018 hclge_update_link_status(hdev); 8019 } 8020 8021 int hclge_vport_start(struct hclge_vport *vport) 8022 { 8023 struct hclge_dev *hdev = vport->back; 8024 8025 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8026 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8027 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8028 vport->last_active_jiffies = jiffies; 8029 vport->need_notify = 0; 8030 8031 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8032 if (vport->vport_id) { 8033 hclge_restore_mac_table_common(vport); 8034 hclge_restore_vport_vlan_table(vport); 8035 } else { 8036 hclge_restore_hw_table(hdev); 8037 } 8038 } 8039 8040 clear_bit(vport->vport_id, hdev->vport_config_block); 8041 8042 return 0; 8043 } 8044 8045 void hclge_vport_stop(struct hclge_vport *vport) 8046 { 8047 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8048 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8049 vport->need_notify = 0; 8050 } 8051 8052 static int hclge_client_start(struct hnae3_handle *handle) 8053 { 8054 struct hclge_vport *vport = hclge_get_vport(handle); 8055 8056 return hclge_vport_start(vport); 8057 } 8058 8059 static void hclge_client_stop(struct hnae3_handle *handle) 8060 { 8061 struct hclge_vport *vport = hclge_get_vport(handle); 8062 8063 hclge_vport_stop(vport); 8064 } 8065 8066 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8067 u16 cmdq_resp, u8 resp_code, 8068 enum hclge_mac_vlan_tbl_opcode op) 8069 { 8070 struct hclge_dev *hdev = vport->back; 8071 8072 if (cmdq_resp) { 8073 dev_err(&hdev->pdev->dev, 8074 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8075 cmdq_resp); 8076 return -EIO; 8077 } 8078 8079 if (op == HCLGE_MAC_VLAN_ADD) { 8080 if (!resp_code || resp_code == 1) 8081 return 0; 8082 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8083 resp_code == HCLGE_ADD_MC_OVERFLOW) 8084 return -ENOSPC; 8085 8086 dev_err(&hdev->pdev->dev, 8087 "add mac addr failed for undefined, code=%u.\n", 8088 resp_code); 8089 return -EIO; 8090 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8091 if (!resp_code) { 8092 return 0; 8093 } else if (resp_code == 1) { 8094 dev_dbg(&hdev->pdev->dev, 8095 "remove mac addr failed for miss.\n"); 8096 return -ENOENT; 8097 } 8098 8099 dev_err(&hdev->pdev->dev, 8100 "remove mac addr failed for undefined, code=%u.\n", 8101 resp_code); 8102 return -EIO; 8103 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8104 if (!resp_code) { 8105 return 0; 8106 } else if (resp_code == 1) { 8107 dev_dbg(&hdev->pdev->dev, 8108 "lookup mac addr failed for miss.\n"); 8109 return -ENOENT; 8110 } 8111 8112 dev_err(&hdev->pdev->dev, 8113 "lookup mac addr failed for undefined, code=%u.\n", 8114 resp_code); 8115 return -EIO; 8116 } 8117 8118 dev_err(&hdev->pdev->dev, 8119 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8120 8121 return -EINVAL; 8122 } 8123 8124 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8125 { 8126 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8127 8128 unsigned int word_num; 8129 unsigned int bit_num; 8130 8131 if (vfid > 255 || vfid < 0) 8132 return -EIO; 8133 8134 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8135 word_num = vfid / 32; 8136 bit_num = vfid % 32; 8137 if (clr) 8138 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8139 else 8140 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8141 } else { 8142 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8143 bit_num = vfid % 32; 8144 if (clr) 8145 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8146 else 8147 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8148 } 8149 8150 return 0; 8151 } 8152 8153 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8154 { 8155 #define HCLGE_DESC_NUMBER 3 8156 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8157 int i, j; 8158 8159 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8160 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8161 if (desc[i].data[j]) 8162 return false; 8163 8164 return true; 8165 } 8166 8167 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8168 const u8 *addr, bool is_mc) 8169 { 8170 const unsigned char *mac_addr = addr; 8171 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8172 (mac_addr[0]) | (mac_addr[1] << 8); 8173 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8174 8175 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8176 if (is_mc) { 8177 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8178 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8179 } 8180 8181 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8182 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8183 } 8184 8185 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8186 struct hclge_mac_vlan_tbl_entry_cmd *req) 8187 { 8188 struct hclge_dev *hdev = vport->back; 8189 struct hclge_desc desc; 8190 u8 resp_code; 8191 u16 retval; 8192 int ret; 8193 8194 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8195 8196 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8197 8198 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8199 if (ret) { 8200 dev_err(&hdev->pdev->dev, 8201 "del mac addr failed for cmd_send, ret =%d.\n", 8202 ret); 8203 return ret; 8204 } 8205 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8206 retval = le16_to_cpu(desc.retval); 8207 8208 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8209 HCLGE_MAC_VLAN_REMOVE); 8210 } 8211 8212 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8213 struct hclge_mac_vlan_tbl_entry_cmd *req, 8214 struct hclge_desc *desc, 8215 bool is_mc) 8216 { 8217 struct hclge_dev *hdev = vport->back; 8218 u8 resp_code; 8219 u16 retval; 8220 int ret; 8221 8222 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8223 if (is_mc) { 8224 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8225 memcpy(desc[0].data, 8226 req, 8227 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8228 hclge_cmd_setup_basic_desc(&desc[1], 8229 HCLGE_OPC_MAC_VLAN_ADD, 8230 true); 8231 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8232 hclge_cmd_setup_basic_desc(&desc[2], 8233 HCLGE_OPC_MAC_VLAN_ADD, 8234 true); 8235 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8236 } else { 8237 memcpy(desc[0].data, 8238 req, 8239 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8240 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8241 } 8242 if (ret) { 8243 dev_err(&hdev->pdev->dev, 8244 "lookup mac addr failed for cmd_send, ret =%d.\n", 8245 ret); 8246 return ret; 8247 } 8248 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8249 retval = le16_to_cpu(desc[0].retval); 8250 8251 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8252 HCLGE_MAC_VLAN_LKUP); 8253 } 8254 8255 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8256 struct hclge_mac_vlan_tbl_entry_cmd *req, 8257 struct hclge_desc *mc_desc) 8258 { 8259 struct hclge_dev *hdev = vport->back; 8260 int cfg_status; 8261 u8 resp_code; 8262 u16 retval; 8263 int ret; 8264 8265 if (!mc_desc) { 8266 struct hclge_desc desc; 8267 8268 hclge_cmd_setup_basic_desc(&desc, 8269 HCLGE_OPC_MAC_VLAN_ADD, 8270 false); 8271 memcpy(desc.data, req, 8272 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8273 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8274 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8275 retval = le16_to_cpu(desc.retval); 8276 8277 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8278 resp_code, 8279 HCLGE_MAC_VLAN_ADD); 8280 } else { 8281 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8282 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8283 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8284 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8285 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8286 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8287 memcpy(mc_desc[0].data, req, 8288 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8289 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8290 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8291 retval = le16_to_cpu(mc_desc[0].retval); 8292 8293 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8294 resp_code, 8295 HCLGE_MAC_VLAN_ADD); 8296 } 8297 8298 if (ret) { 8299 dev_err(&hdev->pdev->dev, 8300 "add mac addr failed for cmd_send, ret =%d.\n", 8301 ret); 8302 return ret; 8303 } 8304 8305 return cfg_status; 8306 } 8307 8308 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8309 u16 *allocated_size) 8310 { 8311 struct hclge_umv_spc_alc_cmd *req; 8312 struct hclge_desc desc; 8313 int ret; 8314 8315 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8316 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8317 8318 req->space_size = cpu_to_le32(space_size); 8319 8320 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8321 if (ret) { 8322 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8323 ret); 8324 return ret; 8325 } 8326 8327 *allocated_size = le32_to_cpu(desc.data[1]); 8328 8329 return 0; 8330 } 8331 8332 static int hclge_init_umv_space(struct hclge_dev *hdev) 8333 { 8334 u16 allocated_size = 0; 8335 int ret; 8336 8337 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8338 if (ret) 8339 return ret; 8340 8341 if (allocated_size < hdev->wanted_umv_size) 8342 dev_warn(&hdev->pdev->dev, 8343 "failed to alloc umv space, want %u, get %u\n", 8344 hdev->wanted_umv_size, allocated_size); 8345 8346 hdev->max_umv_size = allocated_size; 8347 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8348 hdev->share_umv_size = hdev->priv_umv_size + 8349 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8350 8351 if (hdev->ae_dev->dev_specs.mc_mac_size) 8352 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8353 8354 return 0; 8355 } 8356 8357 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8358 { 8359 struct hclge_vport *vport; 8360 int i; 8361 8362 for (i = 0; i < hdev->num_alloc_vport; i++) { 8363 vport = &hdev->vport[i]; 8364 vport->used_umv_num = 0; 8365 } 8366 8367 mutex_lock(&hdev->vport_lock); 8368 hdev->share_umv_size = hdev->priv_umv_size + 8369 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8370 mutex_unlock(&hdev->vport_lock); 8371 8372 hdev->used_mc_mac_num = 0; 8373 } 8374 8375 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8376 { 8377 struct hclge_dev *hdev = vport->back; 8378 bool is_full; 8379 8380 if (need_lock) 8381 mutex_lock(&hdev->vport_lock); 8382 8383 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8384 hdev->share_umv_size == 0); 8385 8386 if (need_lock) 8387 mutex_unlock(&hdev->vport_lock); 8388 8389 return is_full; 8390 } 8391 8392 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8393 { 8394 struct hclge_dev *hdev = vport->back; 8395 8396 if (is_free) { 8397 if (vport->used_umv_num > hdev->priv_umv_size) 8398 hdev->share_umv_size++; 8399 8400 if (vport->used_umv_num > 0) 8401 vport->used_umv_num--; 8402 } else { 8403 if (vport->used_umv_num >= hdev->priv_umv_size && 8404 hdev->share_umv_size > 0) 8405 hdev->share_umv_size--; 8406 vport->used_umv_num++; 8407 } 8408 } 8409 8410 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8411 const u8 *mac_addr) 8412 { 8413 struct hclge_mac_node *mac_node, *tmp; 8414 8415 list_for_each_entry_safe(mac_node, tmp, list, node) 8416 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8417 return mac_node; 8418 8419 return NULL; 8420 } 8421 8422 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8423 enum HCLGE_MAC_NODE_STATE state) 8424 { 8425 switch (state) { 8426 /* from set_rx_mode or tmp_add_list */ 8427 case HCLGE_MAC_TO_ADD: 8428 if (mac_node->state == HCLGE_MAC_TO_DEL) 8429 mac_node->state = HCLGE_MAC_ACTIVE; 8430 break; 8431 /* only from set_rx_mode */ 8432 case HCLGE_MAC_TO_DEL: 8433 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8434 list_del(&mac_node->node); 8435 kfree(mac_node); 8436 } else { 8437 mac_node->state = HCLGE_MAC_TO_DEL; 8438 } 8439 break; 8440 /* only from tmp_add_list, the mac_node->state won't be 8441 * ACTIVE. 8442 */ 8443 case HCLGE_MAC_ACTIVE: 8444 if (mac_node->state == HCLGE_MAC_TO_ADD) 8445 mac_node->state = HCLGE_MAC_ACTIVE; 8446 8447 break; 8448 } 8449 } 8450 8451 int hclge_update_mac_list(struct hclge_vport *vport, 8452 enum HCLGE_MAC_NODE_STATE state, 8453 enum HCLGE_MAC_ADDR_TYPE mac_type, 8454 const unsigned char *addr) 8455 { 8456 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8457 struct hclge_dev *hdev = vport->back; 8458 struct hclge_mac_node *mac_node; 8459 struct list_head *list; 8460 8461 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8462 &vport->uc_mac_list : &vport->mc_mac_list; 8463 8464 spin_lock_bh(&vport->mac_list_lock); 8465 8466 /* if the mac addr is already in the mac list, no need to add a new 8467 * one into it, just check the mac addr state, convert it to a new 8468 * state, or just remove it, or do nothing. 8469 */ 8470 mac_node = hclge_find_mac_node(list, addr); 8471 if (mac_node) { 8472 hclge_update_mac_node(mac_node, state); 8473 spin_unlock_bh(&vport->mac_list_lock); 8474 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8475 return 0; 8476 } 8477 8478 /* if this address is never added, unnecessary to delete */ 8479 if (state == HCLGE_MAC_TO_DEL) { 8480 spin_unlock_bh(&vport->mac_list_lock); 8481 hnae3_format_mac_addr(format_mac_addr, addr); 8482 dev_err(&hdev->pdev->dev, 8483 "failed to delete address %s from mac list\n", 8484 format_mac_addr); 8485 return -ENOENT; 8486 } 8487 8488 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8489 if (!mac_node) { 8490 spin_unlock_bh(&vport->mac_list_lock); 8491 return -ENOMEM; 8492 } 8493 8494 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8495 8496 mac_node->state = state; 8497 ether_addr_copy(mac_node->mac_addr, addr); 8498 list_add_tail(&mac_node->node, list); 8499 8500 spin_unlock_bh(&vport->mac_list_lock); 8501 8502 return 0; 8503 } 8504 8505 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8506 const unsigned char *addr) 8507 { 8508 struct hclge_vport *vport = hclge_get_vport(handle); 8509 8510 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8511 addr); 8512 } 8513 8514 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8515 const unsigned char *addr) 8516 { 8517 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8518 struct hclge_dev *hdev = vport->back; 8519 struct hclge_mac_vlan_tbl_entry_cmd req; 8520 struct hclge_desc desc; 8521 u16 egress_port = 0; 8522 int ret; 8523 8524 /* mac addr check */ 8525 if (is_zero_ether_addr(addr) || 8526 is_broadcast_ether_addr(addr) || 8527 is_multicast_ether_addr(addr)) { 8528 hnae3_format_mac_addr(format_mac_addr, addr); 8529 dev_err(&hdev->pdev->dev, 8530 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8531 format_mac_addr, is_zero_ether_addr(addr), 8532 is_broadcast_ether_addr(addr), 8533 is_multicast_ether_addr(addr)); 8534 return -EINVAL; 8535 } 8536 8537 memset(&req, 0, sizeof(req)); 8538 8539 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8540 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8541 8542 req.egress_port = cpu_to_le16(egress_port); 8543 8544 hclge_prepare_mac_addr(&req, addr, false); 8545 8546 /* Lookup the mac address in the mac_vlan table, and add 8547 * it if the entry is inexistent. Repeated unicast entry 8548 * is not allowed in the mac vlan table. 8549 */ 8550 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8551 if (ret == -ENOENT) { 8552 mutex_lock(&hdev->vport_lock); 8553 if (!hclge_is_umv_space_full(vport, false)) { 8554 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8555 if (!ret) 8556 hclge_update_umv_space(vport, false); 8557 mutex_unlock(&hdev->vport_lock); 8558 return ret; 8559 } 8560 mutex_unlock(&hdev->vport_lock); 8561 8562 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8563 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8564 hdev->priv_umv_size); 8565 8566 return -ENOSPC; 8567 } 8568 8569 /* check if we just hit the duplicate */ 8570 if (!ret) 8571 return -EEXIST; 8572 8573 return ret; 8574 } 8575 8576 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8577 const unsigned char *addr) 8578 { 8579 struct hclge_vport *vport = hclge_get_vport(handle); 8580 8581 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8582 addr); 8583 } 8584 8585 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8586 const unsigned char *addr) 8587 { 8588 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8589 struct hclge_dev *hdev = vport->back; 8590 struct hclge_mac_vlan_tbl_entry_cmd req; 8591 int ret; 8592 8593 /* mac addr check */ 8594 if (is_zero_ether_addr(addr) || 8595 is_broadcast_ether_addr(addr) || 8596 is_multicast_ether_addr(addr)) { 8597 hnae3_format_mac_addr(format_mac_addr, addr); 8598 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8599 format_mac_addr); 8600 return -EINVAL; 8601 } 8602 8603 memset(&req, 0, sizeof(req)); 8604 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8605 hclge_prepare_mac_addr(&req, addr, false); 8606 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8607 if (!ret || ret == -ENOENT) { 8608 mutex_lock(&hdev->vport_lock); 8609 hclge_update_umv_space(vport, true); 8610 mutex_unlock(&hdev->vport_lock); 8611 return 0; 8612 } 8613 8614 return ret; 8615 } 8616 8617 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8618 const unsigned char *addr) 8619 { 8620 struct hclge_vport *vport = hclge_get_vport(handle); 8621 8622 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8623 addr); 8624 } 8625 8626 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8627 const unsigned char *addr) 8628 { 8629 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8630 struct hclge_dev *hdev = vport->back; 8631 struct hclge_mac_vlan_tbl_entry_cmd req; 8632 struct hclge_desc desc[3]; 8633 bool is_new_addr = false; 8634 int status; 8635 8636 /* mac addr check */ 8637 if (!is_multicast_ether_addr(addr)) { 8638 hnae3_format_mac_addr(format_mac_addr, addr); 8639 dev_err(&hdev->pdev->dev, 8640 "Add mc mac err! invalid mac:%s.\n", 8641 format_mac_addr); 8642 return -EINVAL; 8643 } 8644 memset(&req, 0, sizeof(req)); 8645 hclge_prepare_mac_addr(&req, addr, true); 8646 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8647 if (status) { 8648 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8649 hdev->used_mc_mac_num >= 8650 hdev->ae_dev->dev_specs.mc_mac_size) 8651 goto err_no_space; 8652 8653 is_new_addr = true; 8654 8655 /* This mac addr do not exist, add new entry for it */ 8656 memset(desc[0].data, 0, sizeof(desc[0].data)); 8657 memset(desc[1].data, 0, sizeof(desc[0].data)); 8658 memset(desc[2].data, 0, sizeof(desc[0].data)); 8659 } 8660 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8661 if (status) 8662 return status; 8663 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8664 if (status == -ENOSPC) 8665 goto err_no_space; 8666 else if (!status && is_new_addr) 8667 hdev->used_mc_mac_num++; 8668 8669 return status; 8670 8671 err_no_space: 8672 /* if already overflow, not to print each time */ 8673 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8674 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8675 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8676 } 8677 8678 return -ENOSPC; 8679 } 8680 8681 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8682 const unsigned char *addr) 8683 { 8684 struct hclge_vport *vport = hclge_get_vport(handle); 8685 8686 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8687 addr); 8688 } 8689 8690 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8691 const unsigned char *addr) 8692 { 8693 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8694 struct hclge_dev *hdev = vport->back; 8695 struct hclge_mac_vlan_tbl_entry_cmd req; 8696 enum hclge_comm_cmd_status status; 8697 struct hclge_desc desc[3]; 8698 8699 /* mac addr check */ 8700 if (!is_multicast_ether_addr(addr)) { 8701 hnae3_format_mac_addr(format_mac_addr, addr); 8702 dev_dbg(&hdev->pdev->dev, 8703 "Remove mc mac err! invalid mac:%s.\n", 8704 format_mac_addr); 8705 return -EINVAL; 8706 } 8707 8708 memset(&req, 0, sizeof(req)); 8709 hclge_prepare_mac_addr(&req, addr, true); 8710 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8711 if (!status) { 8712 /* This mac addr exist, remove this handle's VFID for it */ 8713 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8714 if (status) 8715 return status; 8716 8717 if (hclge_is_all_function_id_zero(desc)) { 8718 /* All the vfid is zero, so need to delete this entry */ 8719 status = hclge_remove_mac_vlan_tbl(vport, &req); 8720 if (!status) 8721 hdev->used_mc_mac_num--; 8722 } else { 8723 /* Not all the vfid is zero, update the vfid */ 8724 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8725 } 8726 } else if (status == -ENOENT) { 8727 status = 0; 8728 } 8729 8730 return status; 8731 } 8732 8733 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8734 struct list_head *list, 8735 enum HCLGE_MAC_ADDR_TYPE mac_type) 8736 { 8737 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8738 struct hclge_mac_node *mac_node, *tmp; 8739 int ret; 8740 8741 if (mac_type == HCLGE_MAC_ADDR_UC) 8742 sync = hclge_add_uc_addr_common; 8743 else 8744 sync = hclge_add_mc_addr_common; 8745 8746 list_for_each_entry_safe(mac_node, tmp, list, node) { 8747 ret = sync(vport, mac_node->mac_addr); 8748 if (!ret) { 8749 mac_node->state = HCLGE_MAC_ACTIVE; 8750 } else { 8751 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8752 &vport->state); 8753 8754 /* If one unicast mac address is existing in hardware, 8755 * we need to try whether other unicast mac addresses 8756 * are new addresses that can be added. 8757 * Multicast mac address can be reusable, even though 8758 * there is no space to add new multicast mac address, 8759 * we should check whether other mac addresses are 8760 * existing in hardware for reuse. 8761 */ 8762 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8763 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8764 break; 8765 } 8766 } 8767 } 8768 8769 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8770 struct list_head *list, 8771 enum HCLGE_MAC_ADDR_TYPE mac_type) 8772 { 8773 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8774 struct hclge_mac_node *mac_node, *tmp; 8775 int ret; 8776 8777 if (mac_type == HCLGE_MAC_ADDR_UC) 8778 unsync = hclge_rm_uc_addr_common; 8779 else 8780 unsync = hclge_rm_mc_addr_common; 8781 8782 list_for_each_entry_safe(mac_node, tmp, list, node) { 8783 ret = unsync(vport, mac_node->mac_addr); 8784 if (!ret || ret == -ENOENT) { 8785 list_del(&mac_node->node); 8786 kfree(mac_node); 8787 } else { 8788 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8789 &vport->state); 8790 break; 8791 } 8792 } 8793 } 8794 8795 static bool hclge_sync_from_add_list(struct list_head *add_list, 8796 struct list_head *mac_list) 8797 { 8798 struct hclge_mac_node *mac_node, *tmp, *new_node; 8799 bool all_added = true; 8800 8801 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8802 if (mac_node->state == HCLGE_MAC_TO_ADD) 8803 all_added = false; 8804 8805 /* if the mac address from tmp_add_list is not in the 8806 * uc/mc_mac_list, it means have received a TO_DEL request 8807 * during the time window of adding the mac address into mac 8808 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8809 * then it will be removed at next time. else it must be TO_ADD, 8810 * this address hasn't been added into mac table, 8811 * so just remove the mac node. 8812 */ 8813 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8814 if (new_node) { 8815 hclge_update_mac_node(new_node, mac_node->state); 8816 list_del(&mac_node->node); 8817 kfree(mac_node); 8818 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8819 mac_node->state = HCLGE_MAC_TO_DEL; 8820 list_move_tail(&mac_node->node, mac_list); 8821 } else { 8822 list_del(&mac_node->node); 8823 kfree(mac_node); 8824 } 8825 } 8826 8827 return all_added; 8828 } 8829 8830 static void hclge_sync_from_del_list(struct list_head *del_list, 8831 struct list_head *mac_list) 8832 { 8833 struct hclge_mac_node *mac_node, *tmp, *new_node; 8834 8835 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8836 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8837 if (new_node) { 8838 /* If the mac addr exists in the mac list, it means 8839 * received a new TO_ADD request during the time window 8840 * of configuring the mac address. For the mac node 8841 * state is TO_ADD, and the address is already in the 8842 * in the hardware(due to delete fail), so we just need 8843 * to change the mac node state to ACTIVE. 8844 */ 8845 new_node->state = HCLGE_MAC_ACTIVE; 8846 list_del(&mac_node->node); 8847 kfree(mac_node); 8848 } else { 8849 list_move_tail(&mac_node->node, mac_list); 8850 } 8851 } 8852 } 8853 8854 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8855 enum HCLGE_MAC_ADDR_TYPE mac_type, 8856 bool is_all_added) 8857 { 8858 if (mac_type == HCLGE_MAC_ADDR_UC) { 8859 if (is_all_added) 8860 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8861 else if (hclge_is_umv_space_full(vport, true)) 8862 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8863 } else { 8864 if (is_all_added) 8865 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8866 else 8867 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8868 } 8869 } 8870 8871 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8872 enum HCLGE_MAC_ADDR_TYPE mac_type) 8873 { 8874 struct hclge_mac_node *mac_node, *tmp, *new_node; 8875 struct list_head tmp_add_list, tmp_del_list; 8876 struct list_head *list; 8877 bool all_added; 8878 8879 INIT_LIST_HEAD(&tmp_add_list); 8880 INIT_LIST_HEAD(&tmp_del_list); 8881 8882 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8883 * we can add/delete these mac addr outside the spin lock 8884 */ 8885 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8886 &vport->uc_mac_list : &vport->mc_mac_list; 8887 8888 spin_lock_bh(&vport->mac_list_lock); 8889 8890 list_for_each_entry_safe(mac_node, tmp, list, node) { 8891 switch (mac_node->state) { 8892 case HCLGE_MAC_TO_DEL: 8893 list_move_tail(&mac_node->node, &tmp_del_list); 8894 break; 8895 case HCLGE_MAC_TO_ADD: 8896 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8897 if (!new_node) 8898 goto stop_traverse; 8899 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8900 new_node->state = mac_node->state; 8901 list_add_tail(&new_node->node, &tmp_add_list); 8902 break; 8903 default: 8904 break; 8905 } 8906 } 8907 8908 stop_traverse: 8909 spin_unlock_bh(&vport->mac_list_lock); 8910 8911 /* delete first, in order to get max mac table space for adding */ 8912 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8913 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8914 8915 /* if some mac addresses were added/deleted fail, move back to the 8916 * mac_list, and retry at next time. 8917 */ 8918 spin_lock_bh(&vport->mac_list_lock); 8919 8920 hclge_sync_from_del_list(&tmp_del_list, list); 8921 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8922 8923 spin_unlock_bh(&vport->mac_list_lock); 8924 8925 hclge_update_overflow_flags(vport, mac_type, all_added); 8926 } 8927 8928 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8929 { 8930 struct hclge_dev *hdev = vport->back; 8931 8932 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8933 return false; 8934 8935 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8936 return true; 8937 8938 return false; 8939 } 8940 8941 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8942 { 8943 int i; 8944 8945 for (i = 0; i < hdev->num_alloc_vport; i++) { 8946 struct hclge_vport *vport = &hdev->vport[i]; 8947 8948 if (!hclge_need_sync_mac_table(vport)) 8949 continue; 8950 8951 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 8952 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 8953 } 8954 } 8955 8956 static void hclge_build_del_list(struct list_head *list, 8957 bool is_del_list, 8958 struct list_head *tmp_del_list) 8959 { 8960 struct hclge_mac_node *mac_cfg, *tmp; 8961 8962 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 8963 switch (mac_cfg->state) { 8964 case HCLGE_MAC_TO_DEL: 8965 case HCLGE_MAC_ACTIVE: 8966 list_move_tail(&mac_cfg->node, tmp_del_list); 8967 break; 8968 case HCLGE_MAC_TO_ADD: 8969 if (is_del_list) { 8970 list_del(&mac_cfg->node); 8971 kfree(mac_cfg); 8972 } 8973 break; 8974 } 8975 } 8976 } 8977 8978 static void hclge_unsync_del_list(struct hclge_vport *vport, 8979 int (*unsync)(struct hclge_vport *vport, 8980 const unsigned char *addr), 8981 bool is_del_list, 8982 struct list_head *tmp_del_list) 8983 { 8984 struct hclge_mac_node *mac_cfg, *tmp; 8985 int ret; 8986 8987 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 8988 ret = unsync(vport, mac_cfg->mac_addr); 8989 if (!ret || ret == -ENOENT) { 8990 /* clear all mac addr from hardware, but remain these 8991 * mac addr in the mac list, and restore them after 8992 * vf reset finished. 8993 */ 8994 if (!is_del_list && 8995 mac_cfg->state == HCLGE_MAC_ACTIVE) { 8996 mac_cfg->state = HCLGE_MAC_TO_ADD; 8997 } else { 8998 list_del(&mac_cfg->node); 8999 kfree(mac_cfg); 9000 } 9001 } else if (is_del_list) { 9002 mac_cfg->state = HCLGE_MAC_TO_DEL; 9003 } 9004 } 9005 } 9006 9007 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9008 enum HCLGE_MAC_ADDR_TYPE mac_type) 9009 { 9010 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9011 struct hclge_dev *hdev = vport->back; 9012 struct list_head tmp_del_list, *list; 9013 9014 if (mac_type == HCLGE_MAC_ADDR_UC) { 9015 list = &vport->uc_mac_list; 9016 unsync = hclge_rm_uc_addr_common; 9017 } else { 9018 list = &vport->mc_mac_list; 9019 unsync = hclge_rm_mc_addr_common; 9020 } 9021 9022 INIT_LIST_HEAD(&tmp_del_list); 9023 9024 if (!is_del_list) 9025 set_bit(vport->vport_id, hdev->vport_config_block); 9026 9027 spin_lock_bh(&vport->mac_list_lock); 9028 9029 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9030 9031 spin_unlock_bh(&vport->mac_list_lock); 9032 9033 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9034 9035 spin_lock_bh(&vport->mac_list_lock); 9036 9037 hclge_sync_from_del_list(&tmp_del_list, list); 9038 9039 spin_unlock_bh(&vport->mac_list_lock); 9040 } 9041 9042 /* remove all mac address when uninitailize */ 9043 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9044 enum HCLGE_MAC_ADDR_TYPE mac_type) 9045 { 9046 struct hclge_mac_node *mac_node, *tmp; 9047 struct hclge_dev *hdev = vport->back; 9048 struct list_head tmp_del_list, *list; 9049 9050 INIT_LIST_HEAD(&tmp_del_list); 9051 9052 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9053 &vport->uc_mac_list : &vport->mc_mac_list; 9054 9055 spin_lock_bh(&vport->mac_list_lock); 9056 9057 list_for_each_entry_safe(mac_node, tmp, list, node) { 9058 switch (mac_node->state) { 9059 case HCLGE_MAC_TO_DEL: 9060 case HCLGE_MAC_ACTIVE: 9061 list_move_tail(&mac_node->node, &tmp_del_list); 9062 break; 9063 case HCLGE_MAC_TO_ADD: 9064 list_del(&mac_node->node); 9065 kfree(mac_node); 9066 break; 9067 } 9068 } 9069 9070 spin_unlock_bh(&vport->mac_list_lock); 9071 9072 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9073 9074 if (!list_empty(&tmp_del_list)) 9075 dev_warn(&hdev->pdev->dev, 9076 "uninit %s mac list for vport %u not completely.\n", 9077 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9078 vport->vport_id); 9079 9080 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9081 list_del(&mac_node->node); 9082 kfree(mac_node); 9083 } 9084 } 9085 9086 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9087 { 9088 struct hclge_vport *vport; 9089 int i; 9090 9091 for (i = 0; i < hdev->num_alloc_vport; i++) { 9092 vport = &hdev->vport[i]; 9093 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9094 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9095 } 9096 } 9097 9098 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9099 u16 cmdq_resp, u8 resp_code) 9100 { 9101 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9102 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9103 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9104 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9105 9106 int return_status; 9107 9108 if (cmdq_resp) { 9109 dev_err(&hdev->pdev->dev, 9110 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9111 cmdq_resp); 9112 return -EIO; 9113 } 9114 9115 switch (resp_code) { 9116 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9117 case HCLGE_ETHERTYPE_ALREADY_ADD: 9118 return_status = 0; 9119 break; 9120 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9121 dev_err(&hdev->pdev->dev, 9122 "add mac ethertype failed for manager table overflow.\n"); 9123 return_status = -EIO; 9124 break; 9125 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9126 dev_err(&hdev->pdev->dev, 9127 "add mac ethertype failed for key conflict.\n"); 9128 return_status = -EIO; 9129 break; 9130 default: 9131 dev_err(&hdev->pdev->dev, 9132 "add mac ethertype failed for undefined, code=%u.\n", 9133 resp_code); 9134 return_status = -EIO; 9135 } 9136 9137 return return_status; 9138 } 9139 9140 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9141 u8 *mac_addr) 9142 { 9143 struct hclge_vport *vport = hclge_get_vport(handle); 9144 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9145 struct hclge_dev *hdev = vport->back; 9146 9147 vport = hclge_get_vf_vport(hdev, vf); 9148 if (!vport) 9149 return -EINVAL; 9150 9151 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9152 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9153 dev_info(&hdev->pdev->dev, 9154 "Specified MAC(=%s) is same as before, no change committed!\n", 9155 format_mac_addr); 9156 return 0; 9157 } 9158 9159 ether_addr_copy(vport->vf_info.mac, mac_addr); 9160 9161 /* there is a timewindow for PF to know VF unalive, it may 9162 * cause send mailbox fail, but it doesn't matter, VF will 9163 * query it when reinit. 9164 */ 9165 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9166 dev_info(&hdev->pdev->dev, 9167 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9168 vf, format_mac_addr); 9169 (void)hclge_inform_reset_assert_to_vf(vport); 9170 return 0; 9171 } 9172 9173 dev_info(&hdev->pdev->dev, 9174 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9175 vf, format_mac_addr); 9176 return 0; 9177 } 9178 9179 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9180 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9181 { 9182 struct hclge_desc desc; 9183 u8 resp_code; 9184 u16 retval; 9185 int ret; 9186 9187 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9188 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9189 9190 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9191 if (ret) { 9192 dev_err(&hdev->pdev->dev, 9193 "add mac ethertype failed for cmd_send, ret =%d.\n", 9194 ret); 9195 return ret; 9196 } 9197 9198 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9199 retval = le16_to_cpu(desc.retval); 9200 9201 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9202 } 9203 9204 static int init_mgr_tbl(struct hclge_dev *hdev) 9205 { 9206 int ret; 9207 int i; 9208 9209 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9210 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9211 if (ret) { 9212 dev_err(&hdev->pdev->dev, 9213 "add mac ethertype failed, ret =%d.\n", 9214 ret); 9215 return ret; 9216 } 9217 } 9218 9219 return 0; 9220 } 9221 9222 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9223 { 9224 struct hclge_vport *vport = hclge_get_vport(handle); 9225 struct hclge_dev *hdev = vport->back; 9226 9227 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9228 } 9229 9230 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9231 const u8 *old_addr, const u8 *new_addr) 9232 { 9233 struct list_head *list = &vport->uc_mac_list; 9234 struct hclge_mac_node *old_node, *new_node; 9235 9236 new_node = hclge_find_mac_node(list, new_addr); 9237 if (!new_node) { 9238 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9239 if (!new_node) 9240 return -ENOMEM; 9241 9242 new_node->state = HCLGE_MAC_TO_ADD; 9243 ether_addr_copy(new_node->mac_addr, new_addr); 9244 list_add(&new_node->node, list); 9245 } else { 9246 if (new_node->state == HCLGE_MAC_TO_DEL) 9247 new_node->state = HCLGE_MAC_ACTIVE; 9248 9249 /* make sure the new addr is in the list head, avoid dev 9250 * addr may be not re-added into mac table for the umv space 9251 * limitation after global/imp reset which will clear mac 9252 * table by hardware. 9253 */ 9254 list_move(&new_node->node, list); 9255 } 9256 9257 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9258 old_node = hclge_find_mac_node(list, old_addr); 9259 if (old_node) { 9260 if (old_node->state == HCLGE_MAC_TO_ADD) { 9261 list_del(&old_node->node); 9262 kfree(old_node); 9263 } else { 9264 old_node->state = HCLGE_MAC_TO_DEL; 9265 } 9266 } 9267 } 9268 9269 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9270 9271 return 0; 9272 } 9273 9274 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9275 bool is_first) 9276 { 9277 const unsigned char *new_addr = (const unsigned char *)p; 9278 struct hclge_vport *vport = hclge_get_vport(handle); 9279 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9280 struct hclge_dev *hdev = vport->back; 9281 unsigned char *old_addr = NULL; 9282 int ret; 9283 9284 /* mac addr check */ 9285 if (is_zero_ether_addr(new_addr) || 9286 is_broadcast_ether_addr(new_addr) || 9287 is_multicast_ether_addr(new_addr)) { 9288 hnae3_format_mac_addr(format_mac_addr, new_addr); 9289 dev_err(&hdev->pdev->dev, 9290 "change uc mac err! invalid mac: %s.\n", 9291 format_mac_addr); 9292 return -EINVAL; 9293 } 9294 9295 ret = hclge_pause_addr_cfg(hdev, new_addr); 9296 if (ret) { 9297 dev_err(&hdev->pdev->dev, 9298 "failed to configure mac pause address, ret = %d\n", 9299 ret); 9300 return ret; 9301 } 9302 9303 if (!is_first) 9304 old_addr = hdev->hw.mac.mac_addr; 9305 9306 spin_lock_bh(&vport->mac_list_lock); 9307 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9308 if (ret) { 9309 hnae3_format_mac_addr(format_mac_addr, new_addr); 9310 dev_err(&hdev->pdev->dev, 9311 "failed to change the mac addr:%s, ret = %d\n", 9312 format_mac_addr, ret); 9313 spin_unlock_bh(&vport->mac_list_lock); 9314 9315 if (!is_first) 9316 hclge_pause_addr_cfg(hdev, old_addr); 9317 9318 return ret; 9319 } 9320 /* we must update dev addr with spin lock protect, preventing dev addr 9321 * being removed by set_rx_mode path. 9322 */ 9323 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9324 spin_unlock_bh(&vport->mac_list_lock); 9325 9326 hclge_task_schedule(hdev, 0); 9327 9328 return 0; 9329 } 9330 9331 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9332 { 9333 struct mii_ioctl_data *data = if_mii(ifr); 9334 9335 if (!hnae3_dev_phy_imp_supported(hdev)) 9336 return -EOPNOTSUPP; 9337 9338 switch (cmd) { 9339 case SIOCGMIIPHY: 9340 data->phy_id = hdev->hw.mac.phy_addr; 9341 /* this command reads phy id and register at the same time */ 9342 fallthrough; 9343 case SIOCGMIIREG: 9344 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9345 return 0; 9346 9347 case SIOCSMIIREG: 9348 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9349 default: 9350 return -EOPNOTSUPP; 9351 } 9352 } 9353 9354 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9355 int cmd) 9356 { 9357 struct hclge_vport *vport = hclge_get_vport(handle); 9358 struct hclge_dev *hdev = vport->back; 9359 9360 switch (cmd) { 9361 case SIOCGHWTSTAMP: 9362 return hclge_ptp_get_cfg(hdev, ifr); 9363 case SIOCSHWTSTAMP: 9364 return hclge_ptp_set_cfg(hdev, ifr); 9365 default: 9366 if (!hdev->hw.mac.phydev) 9367 return hclge_mii_ioctl(hdev, ifr, cmd); 9368 } 9369 9370 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9371 } 9372 9373 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9374 bool bypass_en) 9375 { 9376 struct hclge_port_vlan_filter_bypass_cmd *req; 9377 struct hclge_desc desc; 9378 int ret; 9379 9380 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9381 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9382 req->vf_id = vf_id; 9383 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9384 bypass_en ? 1 : 0); 9385 9386 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9387 if (ret) 9388 dev_err(&hdev->pdev->dev, 9389 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9390 vf_id, ret); 9391 9392 return ret; 9393 } 9394 9395 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9396 u8 fe_type, bool filter_en, u8 vf_id) 9397 { 9398 struct hclge_vlan_filter_ctrl_cmd *req; 9399 struct hclge_desc desc; 9400 int ret; 9401 9402 /* read current vlan filter parameter */ 9403 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9404 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9405 req->vlan_type = vlan_type; 9406 req->vf_id = vf_id; 9407 9408 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9409 if (ret) { 9410 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9411 vf_id, ret); 9412 return ret; 9413 } 9414 9415 /* modify and write new config parameter */ 9416 hclge_comm_cmd_reuse_desc(&desc, false); 9417 req->vlan_fe = filter_en ? 9418 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9419 9420 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9421 if (ret) 9422 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9423 vf_id, ret); 9424 9425 return ret; 9426 } 9427 9428 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9429 { 9430 struct hclge_dev *hdev = vport->back; 9431 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9432 int ret; 9433 9434 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9435 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9436 HCLGE_FILTER_FE_EGRESS_V1_B, 9437 enable, vport->vport_id); 9438 9439 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9440 HCLGE_FILTER_FE_EGRESS, enable, 9441 vport->vport_id); 9442 if (ret) 9443 return ret; 9444 9445 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9446 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9447 !enable); 9448 } else if (!vport->vport_id) { 9449 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9450 enable = false; 9451 9452 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9453 HCLGE_FILTER_FE_INGRESS, 9454 enable, 0); 9455 } 9456 9457 return ret; 9458 } 9459 9460 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9461 { 9462 struct hnae3_handle *handle = &vport->nic; 9463 struct hclge_vport_vlan_cfg *vlan, *tmp; 9464 struct hclge_dev *hdev = vport->back; 9465 9466 if (vport->vport_id) { 9467 if (vport->port_base_vlan_cfg.state != 9468 HNAE3_PORT_BASE_VLAN_DISABLE) 9469 return true; 9470 9471 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9472 return false; 9473 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9474 return false; 9475 } 9476 9477 if (!vport->req_vlan_fltr_en) 9478 return false; 9479 9480 /* compatible with former device, always enable vlan filter */ 9481 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9482 return true; 9483 9484 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9485 if (vlan->vlan_id != 0) 9486 return true; 9487 9488 return false; 9489 } 9490 9491 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9492 { 9493 struct hclge_dev *hdev = vport->back; 9494 bool need_en; 9495 int ret; 9496 9497 mutex_lock(&hdev->vport_lock); 9498 9499 vport->req_vlan_fltr_en = request_en; 9500 9501 need_en = hclge_need_enable_vport_vlan_filter(vport); 9502 if (need_en == vport->cur_vlan_fltr_en) { 9503 mutex_unlock(&hdev->vport_lock); 9504 return 0; 9505 } 9506 9507 ret = hclge_set_vport_vlan_filter(vport, need_en); 9508 if (ret) { 9509 mutex_unlock(&hdev->vport_lock); 9510 return ret; 9511 } 9512 9513 vport->cur_vlan_fltr_en = need_en; 9514 9515 mutex_unlock(&hdev->vport_lock); 9516 9517 return 0; 9518 } 9519 9520 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9521 { 9522 struct hclge_vport *vport = hclge_get_vport(handle); 9523 9524 return hclge_enable_vport_vlan_filter(vport, enable); 9525 } 9526 9527 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9528 bool is_kill, u16 vlan, 9529 struct hclge_desc *desc) 9530 { 9531 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9532 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9533 u8 vf_byte_val; 9534 u8 vf_byte_off; 9535 int ret; 9536 9537 hclge_cmd_setup_basic_desc(&desc[0], 9538 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9539 hclge_cmd_setup_basic_desc(&desc[1], 9540 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9541 9542 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9543 9544 vf_byte_off = vfid / 8; 9545 vf_byte_val = 1 << (vfid % 8); 9546 9547 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9548 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9549 9550 req0->vlan_id = cpu_to_le16(vlan); 9551 req0->vlan_cfg = is_kill; 9552 9553 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9554 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9555 else 9556 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9557 9558 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9559 if (ret) { 9560 dev_err(&hdev->pdev->dev, 9561 "Send vf vlan command fail, ret =%d.\n", 9562 ret); 9563 return ret; 9564 } 9565 9566 return 0; 9567 } 9568 9569 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9570 bool is_kill, struct hclge_desc *desc) 9571 { 9572 struct hclge_vlan_filter_vf_cfg_cmd *req; 9573 9574 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9575 9576 if (!is_kill) { 9577 #define HCLGE_VF_VLAN_NO_ENTRY 2 9578 if (!req->resp_code || req->resp_code == 1) 9579 return 0; 9580 9581 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9582 set_bit(vfid, hdev->vf_vlan_full); 9583 dev_warn(&hdev->pdev->dev, 9584 "vf vlan table is full, vf vlan filter is disabled\n"); 9585 return 0; 9586 } 9587 9588 dev_err(&hdev->pdev->dev, 9589 "Add vf vlan filter fail, ret =%u.\n", 9590 req->resp_code); 9591 } else { 9592 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9593 if (!req->resp_code) 9594 return 0; 9595 9596 /* vf vlan filter is disabled when vf vlan table is full, 9597 * then new vlan id will not be added into vf vlan table. 9598 * Just return 0 without warning, avoid massive verbose 9599 * print logs when unload. 9600 */ 9601 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9602 return 0; 9603 9604 dev_err(&hdev->pdev->dev, 9605 "Kill vf vlan filter fail, ret =%u.\n", 9606 req->resp_code); 9607 } 9608 9609 return -EIO; 9610 } 9611 9612 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9613 bool is_kill, u16 vlan) 9614 { 9615 struct hclge_vport *vport = &hdev->vport[vfid]; 9616 struct hclge_desc desc[2]; 9617 int ret; 9618 9619 /* if vf vlan table is full, firmware will close vf vlan filter, it 9620 * is unable and unnecessary to add new vlan id to vf vlan filter. 9621 * If spoof check is enable, and vf vlan is full, it shouldn't add 9622 * new vlan, because tx packets with these vlan id will be dropped. 9623 */ 9624 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9625 if (vport->vf_info.spoofchk && vlan) { 9626 dev_err(&hdev->pdev->dev, 9627 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9628 return -EPERM; 9629 } 9630 return 0; 9631 } 9632 9633 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9634 if (ret) 9635 return ret; 9636 9637 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9638 } 9639 9640 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9641 u16 vlan_id, bool is_kill) 9642 { 9643 struct hclge_vlan_filter_pf_cfg_cmd *req; 9644 struct hclge_desc desc; 9645 u8 vlan_offset_byte_val; 9646 u8 vlan_offset_byte; 9647 u8 vlan_offset_160; 9648 int ret; 9649 9650 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9651 9652 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9653 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9654 HCLGE_VLAN_BYTE_SIZE; 9655 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9656 9657 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9658 req->vlan_offset = vlan_offset_160; 9659 req->vlan_cfg = is_kill; 9660 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9661 9662 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9663 if (ret) 9664 dev_err(&hdev->pdev->dev, 9665 "port vlan command, send fail, ret =%d.\n", ret); 9666 return ret; 9667 } 9668 9669 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9670 u16 vlan_id, bool is_kill) 9671 { 9672 /* vlan 0 may be added twice when 8021q module is enabled */ 9673 if (!is_kill && !vlan_id && 9674 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9675 return false; 9676 9677 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9678 dev_warn(&hdev->pdev->dev, 9679 "Add port vlan failed, vport %u is already in vlan %u\n", 9680 vport_id, vlan_id); 9681 return false; 9682 } 9683 9684 if (is_kill && 9685 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9686 dev_warn(&hdev->pdev->dev, 9687 "Delete port vlan failed, vport %u is not in vlan %u\n", 9688 vport_id, vlan_id); 9689 return false; 9690 } 9691 9692 return true; 9693 } 9694 9695 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9696 u16 vport_id, u16 vlan_id, 9697 bool is_kill) 9698 { 9699 u16 vport_idx, vport_num = 0; 9700 int ret; 9701 9702 if (is_kill && !vlan_id) 9703 return 0; 9704 9705 if (vlan_id >= VLAN_N_VID) 9706 return -EINVAL; 9707 9708 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9709 if (ret) { 9710 dev_err(&hdev->pdev->dev, 9711 "Set %u vport vlan filter config fail, ret =%d.\n", 9712 vport_id, ret); 9713 return ret; 9714 } 9715 9716 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9717 return 0; 9718 9719 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9720 vport_num++; 9721 9722 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9723 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9724 is_kill); 9725 9726 return ret; 9727 } 9728 9729 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9730 { 9731 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9732 struct hclge_vport_vtag_tx_cfg_cmd *req; 9733 struct hclge_dev *hdev = vport->back; 9734 struct hclge_desc desc; 9735 u16 bmap_index; 9736 int status; 9737 9738 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9739 9740 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9741 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9742 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9743 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9744 vcfg->accept_tag1 ? 1 : 0); 9745 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9746 vcfg->accept_untag1 ? 1 : 0); 9747 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9748 vcfg->accept_tag2 ? 1 : 0); 9749 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9750 vcfg->accept_untag2 ? 1 : 0); 9751 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9752 vcfg->insert_tag1_en ? 1 : 0); 9753 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9754 vcfg->insert_tag2_en ? 1 : 0); 9755 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9756 vcfg->tag_shift_mode_en ? 1 : 0); 9757 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9758 9759 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9760 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9761 HCLGE_VF_NUM_PER_BYTE; 9762 req->vf_bitmap[bmap_index] = 9763 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9764 9765 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9766 if (status) 9767 dev_err(&hdev->pdev->dev, 9768 "Send port txvlan cfg command fail, ret =%d\n", 9769 status); 9770 9771 return status; 9772 } 9773 9774 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9775 { 9776 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9777 struct hclge_vport_vtag_rx_cfg_cmd *req; 9778 struct hclge_dev *hdev = vport->back; 9779 struct hclge_desc desc; 9780 u16 bmap_index; 9781 int status; 9782 9783 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9784 9785 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9786 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9787 vcfg->strip_tag1_en ? 1 : 0); 9788 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9789 vcfg->strip_tag2_en ? 1 : 0); 9790 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9791 vcfg->vlan1_vlan_prionly ? 1 : 0); 9792 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9793 vcfg->vlan2_vlan_prionly ? 1 : 0); 9794 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9795 vcfg->strip_tag1_discard_en ? 1 : 0); 9796 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9797 vcfg->strip_tag2_discard_en ? 1 : 0); 9798 9799 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9800 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9801 HCLGE_VF_NUM_PER_BYTE; 9802 req->vf_bitmap[bmap_index] = 9803 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9804 9805 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9806 if (status) 9807 dev_err(&hdev->pdev->dev, 9808 "Send port rxvlan cfg command fail, ret =%d\n", 9809 status); 9810 9811 return status; 9812 } 9813 9814 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9815 u16 port_base_vlan_state, 9816 u16 vlan_tag, u8 qos) 9817 { 9818 int ret; 9819 9820 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9821 vport->txvlan_cfg.accept_tag1 = true; 9822 vport->txvlan_cfg.insert_tag1_en = false; 9823 vport->txvlan_cfg.default_tag1 = 0; 9824 } else { 9825 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9826 9827 vport->txvlan_cfg.accept_tag1 = 9828 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9829 vport->txvlan_cfg.insert_tag1_en = true; 9830 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9831 vlan_tag; 9832 } 9833 9834 vport->txvlan_cfg.accept_untag1 = true; 9835 9836 /* accept_tag2 and accept_untag2 are not supported on 9837 * pdev revision(0x20), new revision support them, 9838 * this two fields can not be configured by user. 9839 */ 9840 vport->txvlan_cfg.accept_tag2 = true; 9841 vport->txvlan_cfg.accept_untag2 = true; 9842 vport->txvlan_cfg.insert_tag2_en = false; 9843 vport->txvlan_cfg.default_tag2 = 0; 9844 vport->txvlan_cfg.tag_shift_mode_en = true; 9845 9846 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9847 vport->rxvlan_cfg.strip_tag1_en = false; 9848 vport->rxvlan_cfg.strip_tag2_en = 9849 vport->rxvlan_cfg.rx_vlan_offload_en; 9850 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9851 } else { 9852 vport->rxvlan_cfg.strip_tag1_en = 9853 vport->rxvlan_cfg.rx_vlan_offload_en; 9854 vport->rxvlan_cfg.strip_tag2_en = true; 9855 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9856 } 9857 9858 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9859 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9860 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9861 9862 ret = hclge_set_vlan_tx_offload_cfg(vport); 9863 if (ret) 9864 return ret; 9865 9866 return hclge_set_vlan_rx_offload_cfg(vport); 9867 } 9868 9869 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9870 { 9871 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9872 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9873 struct hclge_desc desc; 9874 int status; 9875 9876 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9877 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9878 rx_req->ot_fst_vlan_type = 9879 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9880 rx_req->ot_sec_vlan_type = 9881 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9882 rx_req->in_fst_vlan_type = 9883 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9884 rx_req->in_sec_vlan_type = 9885 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9886 9887 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9888 if (status) { 9889 dev_err(&hdev->pdev->dev, 9890 "Send rxvlan protocol type command fail, ret =%d\n", 9891 status); 9892 return status; 9893 } 9894 9895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9896 9897 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9898 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9899 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9900 9901 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9902 if (status) 9903 dev_err(&hdev->pdev->dev, 9904 "Send txvlan protocol type command fail, ret =%d\n", 9905 status); 9906 9907 return status; 9908 } 9909 9910 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9911 { 9912 struct hclge_vport *vport; 9913 bool enable = true; 9914 int ret; 9915 int i; 9916 9917 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9918 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9919 HCLGE_FILTER_FE_EGRESS_V1_B, 9920 true, 0); 9921 9922 /* for revision 0x21, vf vlan filter is per function */ 9923 for (i = 0; i < hdev->num_alloc_vport; i++) { 9924 vport = &hdev->vport[i]; 9925 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9926 HCLGE_FILTER_FE_EGRESS, true, 9927 vport->vport_id); 9928 if (ret) 9929 return ret; 9930 vport->cur_vlan_fltr_en = true; 9931 } 9932 9933 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 9934 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 9935 enable = false; 9936 9937 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9938 HCLGE_FILTER_FE_INGRESS, enable, 0); 9939 } 9940 9941 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9942 { 9943 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9944 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9945 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9946 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9947 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 9948 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 9949 9950 return hclge_set_vlan_protocol_type(hdev); 9951 } 9952 9953 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 9954 { 9955 struct hclge_port_base_vlan_config *cfg; 9956 struct hclge_vport *vport; 9957 int ret; 9958 int i; 9959 9960 for (i = 0; i < hdev->num_alloc_vport; i++) { 9961 vport = &hdev->vport[i]; 9962 cfg = &vport->port_base_vlan_cfg; 9963 9964 ret = hclge_vlan_offload_cfg(vport, cfg->state, 9965 cfg->vlan_info.vlan_tag, 9966 cfg->vlan_info.qos); 9967 if (ret) 9968 return ret; 9969 } 9970 return 0; 9971 } 9972 9973 static int hclge_init_vlan_config(struct hclge_dev *hdev) 9974 { 9975 struct hnae3_handle *handle = &hdev->vport[0].nic; 9976 int ret; 9977 9978 ret = hclge_init_vlan_filter(hdev); 9979 if (ret) 9980 return ret; 9981 9982 ret = hclge_init_vlan_type(hdev); 9983 if (ret) 9984 return ret; 9985 9986 ret = hclge_init_vport_vlan_offload(hdev); 9987 if (ret) 9988 return ret; 9989 9990 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 9991 } 9992 9993 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 9994 bool writen_to_tbl) 9995 { 9996 struct hclge_vport_vlan_cfg *vlan, *tmp; 9997 struct hclge_dev *hdev = vport->back; 9998 9999 mutex_lock(&hdev->vport_lock); 10000 10001 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10002 if (vlan->vlan_id == vlan_id) { 10003 mutex_unlock(&hdev->vport_lock); 10004 return; 10005 } 10006 } 10007 10008 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10009 if (!vlan) { 10010 mutex_unlock(&hdev->vport_lock); 10011 return; 10012 } 10013 10014 vlan->hd_tbl_status = writen_to_tbl; 10015 vlan->vlan_id = vlan_id; 10016 10017 list_add_tail(&vlan->node, &vport->vlan_list); 10018 mutex_unlock(&hdev->vport_lock); 10019 } 10020 10021 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10022 { 10023 struct hclge_vport_vlan_cfg *vlan, *tmp; 10024 struct hclge_dev *hdev = vport->back; 10025 int ret; 10026 10027 mutex_lock(&hdev->vport_lock); 10028 10029 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10030 if (!vlan->hd_tbl_status) { 10031 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10032 vport->vport_id, 10033 vlan->vlan_id, false); 10034 if (ret) { 10035 dev_err(&hdev->pdev->dev, 10036 "restore vport vlan list failed, ret=%d\n", 10037 ret); 10038 10039 mutex_unlock(&hdev->vport_lock); 10040 return ret; 10041 } 10042 } 10043 vlan->hd_tbl_status = true; 10044 } 10045 10046 mutex_unlock(&hdev->vport_lock); 10047 10048 return 0; 10049 } 10050 10051 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10052 bool is_write_tbl) 10053 { 10054 struct hclge_vport_vlan_cfg *vlan, *tmp; 10055 struct hclge_dev *hdev = vport->back; 10056 10057 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10058 if (vlan->vlan_id == vlan_id) { 10059 if (is_write_tbl && vlan->hd_tbl_status) 10060 hclge_set_vlan_filter_hw(hdev, 10061 htons(ETH_P_8021Q), 10062 vport->vport_id, 10063 vlan_id, 10064 true); 10065 10066 list_del(&vlan->node); 10067 kfree(vlan); 10068 break; 10069 } 10070 } 10071 } 10072 10073 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10074 { 10075 struct hclge_vport_vlan_cfg *vlan, *tmp; 10076 struct hclge_dev *hdev = vport->back; 10077 10078 mutex_lock(&hdev->vport_lock); 10079 10080 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10081 if (vlan->hd_tbl_status) 10082 hclge_set_vlan_filter_hw(hdev, 10083 htons(ETH_P_8021Q), 10084 vport->vport_id, 10085 vlan->vlan_id, 10086 true); 10087 10088 vlan->hd_tbl_status = false; 10089 if (is_del_list) { 10090 list_del(&vlan->node); 10091 kfree(vlan); 10092 } 10093 } 10094 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10095 mutex_unlock(&hdev->vport_lock); 10096 } 10097 10098 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10099 { 10100 struct hclge_vport_vlan_cfg *vlan, *tmp; 10101 struct hclge_vport *vport; 10102 int i; 10103 10104 mutex_lock(&hdev->vport_lock); 10105 10106 for (i = 0; i < hdev->num_alloc_vport; i++) { 10107 vport = &hdev->vport[i]; 10108 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10109 list_del(&vlan->node); 10110 kfree(vlan); 10111 } 10112 } 10113 10114 mutex_unlock(&hdev->vport_lock); 10115 } 10116 10117 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10118 { 10119 struct hclge_vlan_info *vlan_info; 10120 struct hclge_vport *vport; 10121 u16 vlan_proto; 10122 u16 vlan_id; 10123 u16 state; 10124 int vf_id; 10125 int ret; 10126 10127 /* PF should restore all vfs port base vlan */ 10128 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10129 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10130 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10131 &vport->port_base_vlan_cfg.vlan_info : 10132 &vport->port_base_vlan_cfg.old_vlan_info; 10133 10134 vlan_id = vlan_info->vlan_tag; 10135 vlan_proto = vlan_info->vlan_proto; 10136 state = vport->port_base_vlan_cfg.state; 10137 10138 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10139 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10140 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10141 vport->vport_id, 10142 vlan_id, false); 10143 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10144 } 10145 } 10146 } 10147 10148 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10149 { 10150 struct hclge_vport_vlan_cfg *vlan, *tmp; 10151 struct hclge_dev *hdev = vport->back; 10152 int ret; 10153 10154 mutex_lock(&hdev->vport_lock); 10155 10156 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10157 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10158 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10159 vport->vport_id, 10160 vlan->vlan_id, false); 10161 if (ret) 10162 break; 10163 vlan->hd_tbl_status = true; 10164 } 10165 } 10166 10167 mutex_unlock(&hdev->vport_lock); 10168 } 10169 10170 /* For global reset and imp reset, hardware will clear the mac table, 10171 * so we change the mac address state from ACTIVE to TO_ADD, then they 10172 * can be restored in the service task after reset complete. Furtherly, 10173 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10174 * be restored after reset, so just remove these mac nodes from mac_list. 10175 */ 10176 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10177 { 10178 struct hclge_mac_node *mac_node, *tmp; 10179 10180 list_for_each_entry_safe(mac_node, tmp, list, node) { 10181 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10182 mac_node->state = HCLGE_MAC_TO_ADD; 10183 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10184 list_del(&mac_node->node); 10185 kfree(mac_node); 10186 } 10187 } 10188 } 10189 10190 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10191 { 10192 spin_lock_bh(&vport->mac_list_lock); 10193 10194 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10195 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10196 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10197 10198 spin_unlock_bh(&vport->mac_list_lock); 10199 } 10200 10201 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10202 { 10203 struct hclge_vport *vport = &hdev->vport[0]; 10204 struct hnae3_handle *handle = &vport->nic; 10205 10206 hclge_restore_mac_table_common(vport); 10207 hclge_restore_vport_port_base_vlan_config(hdev); 10208 hclge_restore_vport_vlan_table(vport); 10209 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10210 hclge_restore_fd_entries(handle); 10211 } 10212 10213 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10214 { 10215 struct hclge_vport *vport = hclge_get_vport(handle); 10216 10217 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10218 vport->rxvlan_cfg.strip_tag1_en = false; 10219 vport->rxvlan_cfg.strip_tag2_en = enable; 10220 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10221 } else { 10222 vport->rxvlan_cfg.strip_tag1_en = enable; 10223 vport->rxvlan_cfg.strip_tag2_en = true; 10224 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10225 } 10226 10227 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10228 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10229 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10230 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10231 10232 return hclge_set_vlan_rx_offload_cfg(vport); 10233 } 10234 10235 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10236 { 10237 struct hclge_dev *hdev = vport->back; 10238 10239 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10240 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10241 } 10242 10243 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10244 u16 port_base_vlan_state, 10245 struct hclge_vlan_info *new_info, 10246 struct hclge_vlan_info *old_info) 10247 { 10248 struct hclge_dev *hdev = vport->back; 10249 int ret; 10250 10251 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10252 hclge_rm_vport_all_vlan_table(vport, false); 10253 /* force clear VLAN 0 */ 10254 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10255 if (ret) 10256 return ret; 10257 return hclge_set_vlan_filter_hw(hdev, 10258 htons(new_info->vlan_proto), 10259 vport->vport_id, 10260 new_info->vlan_tag, 10261 false); 10262 } 10263 10264 vport->port_base_vlan_cfg.tbl_sta = false; 10265 10266 /* force add VLAN 0 */ 10267 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10268 if (ret) 10269 return ret; 10270 10271 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10272 vport->vport_id, old_info->vlan_tag, 10273 true); 10274 if (ret) 10275 return ret; 10276 10277 return hclge_add_vport_all_vlan_table(vport); 10278 } 10279 10280 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10281 const struct hclge_vlan_info *old_cfg) 10282 { 10283 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10284 return true; 10285 10286 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10287 return true; 10288 10289 return false; 10290 } 10291 10292 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10293 struct hclge_vlan_info *new_info, 10294 struct hclge_vlan_info *old_info) 10295 { 10296 struct hclge_dev *hdev = vport->back; 10297 int ret; 10298 10299 /* add new VLAN tag */ 10300 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10301 vport->vport_id, new_info->vlan_tag, 10302 false); 10303 if (ret) 10304 return ret; 10305 10306 vport->port_base_vlan_cfg.tbl_sta = false; 10307 /* remove old VLAN tag */ 10308 if (old_info->vlan_tag == 0) 10309 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10310 true, 0); 10311 else 10312 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10313 vport->vport_id, 10314 old_info->vlan_tag, true); 10315 if (ret) 10316 dev_err(&hdev->pdev->dev, 10317 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10318 vport->vport_id, old_info->vlan_tag, ret); 10319 10320 return ret; 10321 } 10322 10323 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10324 struct hclge_vlan_info *vlan_info) 10325 { 10326 struct hnae3_handle *nic = &vport->nic; 10327 struct hclge_vlan_info *old_vlan_info; 10328 int ret; 10329 10330 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10331 10332 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10333 vlan_info->qos); 10334 if (ret) 10335 return ret; 10336 10337 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10338 goto out; 10339 10340 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10341 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10342 old_vlan_info); 10343 else 10344 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10345 old_vlan_info); 10346 if (ret) 10347 return ret; 10348 10349 out: 10350 vport->port_base_vlan_cfg.state = state; 10351 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10352 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10353 else 10354 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10355 10356 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10357 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10358 vport->port_base_vlan_cfg.tbl_sta = true; 10359 hclge_set_vport_vlan_fltr_change(vport); 10360 10361 return 0; 10362 } 10363 10364 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10365 enum hnae3_port_base_vlan_state state, 10366 u16 vlan, u8 qos) 10367 { 10368 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10369 if (!vlan && !qos) 10370 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10371 10372 return HNAE3_PORT_BASE_VLAN_ENABLE; 10373 } 10374 10375 if (!vlan && !qos) 10376 return HNAE3_PORT_BASE_VLAN_DISABLE; 10377 10378 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10379 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10380 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10381 10382 return HNAE3_PORT_BASE_VLAN_MODIFY; 10383 } 10384 10385 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10386 u16 vlan, u8 qos, __be16 proto) 10387 { 10388 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10389 struct hclge_vport *vport = hclge_get_vport(handle); 10390 struct hclge_dev *hdev = vport->back; 10391 struct hclge_vlan_info vlan_info; 10392 u16 state; 10393 int ret; 10394 10395 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10396 return -EOPNOTSUPP; 10397 10398 vport = hclge_get_vf_vport(hdev, vfid); 10399 if (!vport) 10400 return -EINVAL; 10401 10402 /* qos is a 3 bits value, so can not be bigger than 7 */ 10403 if (vlan > VLAN_N_VID - 1 || qos > 7) 10404 return -EINVAL; 10405 if (proto != htons(ETH_P_8021Q)) 10406 return -EPROTONOSUPPORT; 10407 10408 state = hclge_get_port_base_vlan_state(vport, 10409 vport->port_base_vlan_cfg.state, 10410 vlan, qos); 10411 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10412 return 0; 10413 10414 vlan_info.vlan_tag = vlan; 10415 vlan_info.qos = qos; 10416 vlan_info.vlan_proto = ntohs(proto); 10417 10418 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10419 if (ret) { 10420 dev_err(&hdev->pdev->dev, 10421 "failed to update port base vlan for vf %d, ret = %d\n", 10422 vfid, ret); 10423 return ret; 10424 } 10425 10426 /* there is a timewindow for PF to know VF unalive, it may 10427 * cause send mailbox fail, but it doesn't matter, VF will 10428 * query it when reinit. 10429 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10430 * VLAN state. 10431 */ 10432 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10433 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10434 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10435 vport->vport_id, 10436 state, 10437 &vlan_info); 10438 else 10439 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10440 &vport->need_notify); 10441 } 10442 return 0; 10443 } 10444 10445 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10446 { 10447 struct hclge_vlan_info *vlan_info; 10448 struct hclge_vport *vport; 10449 int ret; 10450 int vf; 10451 10452 /* clear port base vlan for all vf */ 10453 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10454 vport = &hdev->vport[vf]; 10455 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10456 10457 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10458 vport->vport_id, 10459 vlan_info->vlan_tag, true); 10460 if (ret) 10461 dev_err(&hdev->pdev->dev, 10462 "failed to clear vf vlan for vf%d, ret = %d\n", 10463 vf - HCLGE_VF_VPORT_START_NUM, ret); 10464 } 10465 } 10466 10467 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10468 u16 vlan_id, bool is_kill) 10469 { 10470 struct hclge_vport *vport = hclge_get_vport(handle); 10471 struct hclge_dev *hdev = vport->back; 10472 bool writen_to_tbl = false; 10473 int ret = 0; 10474 10475 /* When device is resetting or reset failed, firmware is unable to 10476 * handle mailbox. Just record the vlan id, and remove it after 10477 * reset finished. 10478 */ 10479 mutex_lock(&hdev->vport_lock); 10480 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10481 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10482 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10483 mutex_unlock(&hdev->vport_lock); 10484 return -EBUSY; 10485 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 10486 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10487 } 10488 mutex_unlock(&hdev->vport_lock); 10489 10490 /* when port base vlan enabled, we use port base vlan as the vlan 10491 * filter entry. In this case, we don't update vlan filter table 10492 * when user add new vlan or remove exist vlan, just update the vport 10493 * vlan list. The vlan id in vlan list will be writen in vlan filter 10494 * table until port base vlan disabled 10495 */ 10496 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10497 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10498 vlan_id, is_kill); 10499 writen_to_tbl = true; 10500 } 10501 10502 if (!ret) { 10503 if (!is_kill) { 10504 hclge_add_vport_vlan_table(vport, vlan_id, 10505 writen_to_tbl); 10506 } else if (is_kill && vlan_id != 0) { 10507 mutex_lock(&hdev->vport_lock); 10508 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10509 mutex_unlock(&hdev->vport_lock); 10510 } 10511 } else if (is_kill) { 10512 /* when remove hw vlan filter failed, record the vlan id, 10513 * and try to remove it from hw later, to be consistence 10514 * with stack 10515 */ 10516 mutex_lock(&hdev->vport_lock); 10517 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10518 mutex_unlock(&hdev->vport_lock); 10519 } 10520 10521 hclge_set_vport_vlan_fltr_change(vport); 10522 10523 return ret; 10524 } 10525 10526 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10527 { 10528 struct hclge_vport *vport; 10529 int ret; 10530 u16 i; 10531 10532 for (i = 0; i < hdev->num_alloc_vport; i++) { 10533 vport = &hdev->vport[i]; 10534 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10535 &vport->state)) 10536 continue; 10537 10538 ret = hclge_enable_vport_vlan_filter(vport, 10539 vport->req_vlan_fltr_en); 10540 if (ret) { 10541 dev_err(&hdev->pdev->dev, 10542 "failed to sync vlan filter state for vport%u, ret = %d\n", 10543 vport->vport_id, ret); 10544 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10545 &vport->state); 10546 return; 10547 } 10548 } 10549 } 10550 10551 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10552 { 10553 #define HCLGE_MAX_SYNC_COUNT 60 10554 10555 int i, ret, sync_cnt = 0; 10556 u16 vlan_id; 10557 10558 mutex_lock(&hdev->vport_lock); 10559 /* start from vport 1 for PF is always alive */ 10560 for (i = 0; i < hdev->num_alloc_vport; i++) { 10561 struct hclge_vport *vport = &hdev->vport[i]; 10562 10563 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10564 VLAN_N_VID); 10565 while (vlan_id != VLAN_N_VID) { 10566 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10567 vport->vport_id, vlan_id, 10568 true); 10569 if (ret && ret != -EINVAL) { 10570 mutex_unlock(&hdev->vport_lock); 10571 return; 10572 } 10573 10574 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10575 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10576 hclge_set_vport_vlan_fltr_change(vport); 10577 10578 sync_cnt++; 10579 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 10580 mutex_unlock(&hdev->vport_lock); 10581 return; 10582 } 10583 10584 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10585 VLAN_N_VID); 10586 } 10587 } 10588 mutex_unlock(&hdev->vport_lock); 10589 10590 hclge_sync_vlan_fltr_state(hdev); 10591 } 10592 10593 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10594 { 10595 struct hclge_config_max_frm_size_cmd *req; 10596 struct hclge_desc desc; 10597 10598 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10599 10600 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10601 req->max_frm_size = cpu_to_le16(new_mps); 10602 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10603 10604 return hclge_cmd_send(&hdev->hw, &desc, 1); 10605 } 10606 10607 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10608 { 10609 struct hclge_vport *vport = hclge_get_vport(handle); 10610 10611 return hclge_set_vport_mtu(vport, new_mtu); 10612 } 10613 10614 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10615 { 10616 struct hclge_dev *hdev = vport->back; 10617 int i, max_frm_size, ret; 10618 10619 /* HW supprt 2 layer vlan */ 10620 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10621 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10622 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10623 return -EINVAL; 10624 10625 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10626 mutex_lock(&hdev->vport_lock); 10627 /* VF's mps must fit within hdev->mps */ 10628 if (vport->vport_id && max_frm_size > hdev->mps) { 10629 mutex_unlock(&hdev->vport_lock); 10630 return -EINVAL; 10631 } else if (vport->vport_id) { 10632 vport->mps = max_frm_size; 10633 mutex_unlock(&hdev->vport_lock); 10634 return 0; 10635 } 10636 10637 /* PF's mps must be greater then VF's mps */ 10638 for (i = 1; i < hdev->num_alloc_vport; i++) 10639 if (max_frm_size < hdev->vport[i].mps) { 10640 dev_err(&hdev->pdev->dev, 10641 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10642 i, hdev->vport[i].mps); 10643 mutex_unlock(&hdev->vport_lock); 10644 return -EINVAL; 10645 } 10646 10647 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10648 10649 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10650 if (ret) { 10651 dev_err(&hdev->pdev->dev, 10652 "Change mtu fail, ret =%d\n", ret); 10653 goto out; 10654 } 10655 10656 hdev->mps = max_frm_size; 10657 vport->mps = max_frm_size; 10658 10659 ret = hclge_buffer_alloc(hdev); 10660 if (ret) 10661 dev_err(&hdev->pdev->dev, 10662 "Allocate buffer fail, ret =%d\n", ret); 10663 10664 out: 10665 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10666 mutex_unlock(&hdev->vport_lock); 10667 return ret; 10668 } 10669 10670 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10671 bool enable) 10672 { 10673 struct hclge_reset_tqp_queue_cmd *req; 10674 struct hclge_desc desc; 10675 int ret; 10676 10677 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10678 10679 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10680 req->tqp_id = cpu_to_le16(queue_id); 10681 if (enable) 10682 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10683 10684 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10685 if (ret) { 10686 dev_err(&hdev->pdev->dev, 10687 "Send tqp reset cmd error, status =%d\n", ret); 10688 return ret; 10689 } 10690 10691 return 0; 10692 } 10693 10694 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10695 u8 *reset_status) 10696 { 10697 struct hclge_reset_tqp_queue_cmd *req; 10698 struct hclge_desc desc; 10699 int ret; 10700 10701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10702 10703 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10704 req->tqp_id = cpu_to_le16(queue_id); 10705 10706 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10707 if (ret) { 10708 dev_err(&hdev->pdev->dev, 10709 "Get reset status error, status =%d\n", ret); 10710 return ret; 10711 } 10712 10713 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10714 10715 return 0; 10716 } 10717 10718 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10719 { 10720 struct hclge_comm_tqp *tqp; 10721 struct hnae3_queue *queue; 10722 10723 queue = handle->kinfo.tqp[queue_id]; 10724 tqp = container_of(queue, struct hclge_comm_tqp, q); 10725 10726 return tqp->index; 10727 } 10728 10729 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10730 { 10731 struct hclge_vport *vport = hclge_get_vport(handle); 10732 struct hclge_dev *hdev = vport->back; 10733 u16 reset_try_times = 0; 10734 u8 reset_status; 10735 u16 queue_gid; 10736 int ret; 10737 u16 i; 10738 10739 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10740 queue_gid = hclge_covert_handle_qid_global(handle, i); 10741 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10742 if (ret) { 10743 dev_err(&hdev->pdev->dev, 10744 "failed to send reset tqp cmd, ret = %d\n", 10745 ret); 10746 return ret; 10747 } 10748 10749 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10750 ret = hclge_get_reset_status(hdev, queue_gid, 10751 &reset_status); 10752 if (ret) 10753 return ret; 10754 10755 if (reset_status) 10756 break; 10757 10758 /* Wait for tqp hw reset */ 10759 usleep_range(1000, 1200); 10760 } 10761 10762 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10763 dev_err(&hdev->pdev->dev, 10764 "wait for tqp hw reset timeout\n"); 10765 return -ETIME; 10766 } 10767 10768 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10769 if (ret) { 10770 dev_err(&hdev->pdev->dev, 10771 "failed to deassert soft reset, ret = %d\n", 10772 ret); 10773 return ret; 10774 } 10775 reset_try_times = 0; 10776 } 10777 return 0; 10778 } 10779 10780 static int hclge_reset_rcb(struct hnae3_handle *handle) 10781 { 10782 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10783 #define HCLGE_RESET_RCB_SUCCESS 1U 10784 10785 struct hclge_vport *vport = hclge_get_vport(handle); 10786 struct hclge_dev *hdev = vport->back; 10787 struct hclge_reset_cmd *req; 10788 struct hclge_desc desc; 10789 u8 return_status; 10790 u16 queue_gid; 10791 int ret; 10792 10793 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10794 10795 req = (struct hclge_reset_cmd *)desc.data; 10796 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10797 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10798 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10799 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10800 10801 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10802 if (ret) { 10803 dev_err(&hdev->pdev->dev, 10804 "failed to send rcb reset cmd, ret = %d\n", ret); 10805 return ret; 10806 } 10807 10808 return_status = req->fun_reset_rcb_return_status; 10809 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10810 return 0; 10811 10812 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10813 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10814 return_status); 10815 return -EIO; 10816 } 10817 10818 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10819 * again to reset all tqps 10820 */ 10821 return hclge_reset_tqp_cmd(handle); 10822 } 10823 10824 int hclge_reset_tqp(struct hnae3_handle *handle) 10825 { 10826 struct hclge_vport *vport = hclge_get_vport(handle); 10827 struct hclge_dev *hdev = vport->back; 10828 int ret; 10829 10830 /* only need to disable PF's tqp */ 10831 if (!vport->vport_id) { 10832 ret = hclge_tqp_enable(handle, false); 10833 if (ret) { 10834 dev_err(&hdev->pdev->dev, 10835 "failed to disable tqp, ret = %d\n", ret); 10836 return ret; 10837 } 10838 } 10839 10840 return hclge_reset_rcb(handle); 10841 } 10842 10843 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10844 { 10845 struct hclge_vport *vport = hclge_get_vport(handle); 10846 struct hclge_dev *hdev = vport->back; 10847 10848 return hdev->fw_version; 10849 } 10850 10851 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10852 { 10853 struct phy_device *phydev = hdev->hw.mac.phydev; 10854 10855 if (!phydev) 10856 return; 10857 10858 phy_set_asym_pause(phydev, rx_en, tx_en); 10859 } 10860 10861 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10862 { 10863 int ret; 10864 10865 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10866 return 0; 10867 10868 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10869 if (ret) 10870 dev_err(&hdev->pdev->dev, 10871 "configure pauseparam error, ret = %d.\n", ret); 10872 10873 return ret; 10874 } 10875 10876 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10877 { 10878 struct phy_device *phydev = hdev->hw.mac.phydev; 10879 u16 remote_advertising = 0; 10880 u16 local_advertising; 10881 u32 rx_pause, tx_pause; 10882 u8 flowctl; 10883 10884 if (!phydev->link) 10885 return 0; 10886 10887 if (!phydev->autoneg) 10888 return hclge_mac_pause_setup_hw(hdev); 10889 10890 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10891 10892 if (phydev->pause) 10893 remote_advertising = LPA_PAUSE_CAP; 10894 10895 if (phydev->asym_pause) 10896 remote_advertising |= LPA_PAUSE_ASYM; 10897 10898 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10899 remote_advertising); 10900 tx_pause = flowctl & FLOW_CTRL_TX; 10901 rx_pause = flowctl & FLOW_CTRL_RX; 10902 10903 if (phydev->duplex == HCLGE_MAC_HALF) { 10904 tx_pause = 0; 10905 rx_pause = 0; 10906 } 10907 10908 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10909 } 10910 10911 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10912 u32 *rx_en, u32 *tx_en) 10913 { 10914 struct hclge_vport *vport = hclge_get_vport(handle); 10915 struct hclge_dev *hdev = vport->back; 10916 u8 media_type = hdev->hw.mac.media_type; 10917 10918 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10919 hclge_get_autoneg(handle) : 0; 10920 10921 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10922 *rx_en = 0; 10923 *tx_en = 0; 10924 return; 10925 } 10926 10927 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10928 *rx_en = 1; 10929 *tx_en = 0; 10930 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10931 *tx_en = 1; 10932 *rx_en = 0; 10933 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10934 *rx_en = 1; 10935 *tx_en = 1; 10936 } else { 10937 *rx_en = 0; 10938 *tx_en = 0; 10939 } 10940 } 10941 10942 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10943 u32 rx_en, u32 tx_en) 10944 { 10945 if (rx_en && tx_en) 10946 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10947 else if (rx_en && !tx_en) 10948 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10949 else if (!rx_en && tx_en) 10950 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10951 else 10952 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10953 10954 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10955 } 10956 10957 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10958 u32 rx_en, u32 tx_en) 10959 { 10960 struct hclge_vport *vport = hclge_get_vport(handle); 10961 struct hclge_dev *hdev = vport->back; 10962 struct phy_device *phydev = hdev->hw.mac.phydev; 10963 u32 fc_autoneg; 10964 10965 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 10966 fc_autoneg = hclge_get_autoneg(handle); 10967 if (auto_neg != fc_autoneg) { 10968 dev_info(&hdev->pdev->dev, 10969 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 10970 return -EOPNOTSUPP; 10971 } 10972 } 10973 10974 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10975 dev_info(&hdev->pdev->dev, 10976 "Priority flow control enabled. Cannot set link flow control.\n"); 10977 return -EOPNOTSUPP; 10978 } 10979 10980 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 10981 10982 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 10983 10984 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 10985 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 10986 10987 if (phydev) 10988 return phy_start_aneg(phydev); 10989 10990 return -EOPNOTSUPP; 10991 } 10992 10993 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 10994 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 10995 { 10996 struct hclge_vport *vport = hclge_get_vport(handle); 10997 struct hclge_dev *hdev = vport->back; 10998 10999 if (speed) 11000 *speed = hdev->hw.mac.speed; 11001 if (duplex) 11002 *duplex = hdev->hw.mac.duplex; 11003 if (auto_neg) 11004 *auto_neg = hdev->hw.mac.autoneg; 11005 if (lane_num) 11006 *lane_num = hdev->hw.mac.lane_num; 11007 } 11008 11009 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11010 u8 *module_type) 11011 { 11012 struct hclge_vport *vport = hclge_get_vport(handle); 11013 struct hclge_dev *hdev = vport->back; 11014 11015 /* When nic is down, the service task is not running, doesn't update 11016 * the port information per second. Query the port information before 11017 * return the media type, ensure getting the correct media information. 11018 */ 11019 hclge_update_port_info(hdev); 11020 11021 if (media_type) 11022 *media_type = hdev->hw.mac.media_type; 11023 11024 if (module_type) 11025 *module_type = hdev->hw.mac.module_type; 11026 } 11027 11028 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11029 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11030 { 11031 struct hclge_vport *vport = hclge_get_vport(handle); 11032 struct hclge_dev *hdev = vport->back; 11033 struct phy_device *phydev = hdev->hw.mac.phydev; 11034 int mdix_ctrl, mdix, is_resolved; 11035 unsigned int retval; 11036 11037 if (!phydev) { 11038 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11039 *tp_mdix = ETH_TP_MDI_INVALID; 11040 return; 11041 } 11042 11043 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11044 11045 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11046 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11047 HCLGE_PHY_MDIX_CTRL_S); 11048 11049 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11050 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11051 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11052 11053 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11054 11055 switch (mdix_ctrl) { 11056 case 0x0: 11057 *tp_mdix_ctrl = ETH_TP_MDI; 11058 break; 11059 case 0x1: 11060 *tp_mdix_ctrl = ETH_TP_MDI_X; 11061 break; 11062 case 0x3: 11063 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11064 break; 11065 default: 11066 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11067 break; 11068 } 11069 11070 if (!is_resolved) 11071 *tp_mdix = ETH_TP_MDI_INVALID; 11072 else if (mdix) 11073 *tp_mdix = ETH_TP_MDI_X; 11074 else 11075 *tp_mdix = ETH_TP_MDI; 11076 } 11077 11078 static void hclge_info_show(struct hclge_dev *hdev) 11079 { 11080 struct hnae3_handle *handle = &hdev->vport->nic; 11081 struct device *dev = &hdev->pdev->dev; 11082 11083 dev_info(dev, "PF info begin:\n"); 11084 11085 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11086 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11087 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11088 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11089 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11090 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11091 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11092 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11093 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11094 dev_info(dev, "This is %s PF\n", 11095 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11096 dev_info(dev, "DCB %s\n", 11097 handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable"); 11098 dev_info(dev, "MQPRIO %s\n", 11099 handle->kinfo.tc_info.mqprio_active ? "enable" : "disable"); 11100 dev_info(dev, "Default tx spare buffer size: %u\n", 11101 hdev->tx_spare_buf_size); 11102 11103 dev_info(dev, "PF info end.\n"); 11104 } 11105 11106 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11107 struct hclge_vport *vport) 11108 { 11109 struct hnae3_client *client = vport->nic.client; 11110 struct hclge_dev *hdev = ae_dev->priv; 11111 int rst_cnt = hdev->rst_stats.reset_cnt; 11112 int ret; 11113 11114 ret = client->ops->init_instance(&vport->nic); 11115 if (ret) 11116 return ret; 11117 11118 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11119 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11120 rst_cnt != hdev->rst_stats.reset_cnt) { 11121 ret = -EBUSY; 11122 goto init_nic_err; 11123 } 11124 11125 /* Enable nic hw error interrupts */ 11126 ret = hclge_config_nic_hw_error(hdev, true); 11127 if (ret) { 11128 dev_err(&ae_dev->pdev->dev, 11129 "fail(%d) to enable hw error interrupts\n", ret); 11130 goto init_nic_err; 11131 } 11132 11133 hnae3_set_client_init_flag(client, ae_dev, 1); 11134 11135 if (netif_msg_drv(&hdev->vport->nic)) 11136 hclge_info_show(hdev); 11137 11138 return ret; 11139 11140 init_nic_err: 11141 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11142 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11143 msleep(HCLGE_WAIT_RESET_DONE); 11144 11145 client->ops->uninit_instance(&vport->nic, 0); 11146 11147 return ret; 11148 } 11149 11150 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11151 struct hclge_vport *vport) 11152 { 11153 struct hclge_dev *hdev = ae_dev->priv; 11154 struct hnae3_client *client; 11155 int rst_cnt; 11156 int ret; 11157 11158 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11159 !hdev->nic_client) 11160 return 0; 11161 11162 client = hdev->roce_client; 11163 ret = hclge_init_roce_base_info(vport); 11164 if (ret) 11165 return ret; 11166 11167 rst_cnt = hdev->rst_stats.reset_cnt; 11168 ret = client->ops->init_instance(&vport->roce); 11169 if (ret) 11170 return ret; 11171 11172 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11173 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11174 rst_cnt != hdev->rst_stats.reset_cnt) { 11175 ret = -EBUSY; 11176 goto init_roce_err; 11177 } 11178 11179 /* Enable roce ras interrupts */ 11180 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11181 if (ret) { 11182 dev_err(&ae_dev->pdev->dev, 11183 "fail(%d) to enable roce ras interrupts\n", ret); 11184 goto init_roce_err; 11185 } 11186 11187 hnae3_set_client_init_flag(client, ae_dev, 1); 11188 11189 return 0; 11190 11191 init_roce_err: 11192 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11193 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11194 msleep(HCLGE_WAIT_RESET_DONE); 11195 11196 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11197 11198 return ret; 11199 } 11200 11201 static int hclge_init_client_instance(struct hnae3_client *client, 11202 struct hnae3_ae_dev *ae_dev) 11203 { 11204 struct hclge_dev *hdev = ae_dev->priv; 11205 struct hclge_vport *vport = &hdev->vport[0]; 11206 int ret; 11207 11208 switch (client->type) { 11209 case HNAE3_CLIENT_KNIC: 11210 hdev->nic_client = client; 11211 vport->nic.client = client; 11212 ret = hclge_init_nic_client_instance(ae_dev, vport); 11213 if (ret) 11214 goto clear_nic; 11215 11216 ret = hclge_init_roce_client_instance(ae_dev, vport); 11217 if (ret) 11218 goto clear_roce; 11219 11220 break; 11221 case HNAE3_CLIENT_ROCE: 11222 if (hnae3_dev_roce_supported(hdev)) { 11223 hdev->roce_client = client; 11224 vport->roce.client = client; 11225 } 11226 11227 ret = hclge_init_roce_client_instance(ae_dev, vport); 11228 if (ret) 11229 goto clear_roce; 11230 11231 break; 11232 default: 11233 return -EINVAL; 11234 } 11235 11236 return 0; 11237 11238 clear_nic: 11239 hdev->nic_client = NULL; 11240 vport->nic.client = NULL; 11241 return ret; 11242 clear_roce: 11243 hdev->roce_client = NULL; 11244 vport->roce.client = NULL; 11245 return ret; 11246 } 11247 11248 static void hclge_uninit_client_instance(struct hnae3_client *client, 11249 struct hnae3_ae_dev *ae_dev) 11250 { 11251 struct hclge_dev *hdev = ae_dev->priv; 11252 struct hclge_vport *vport = &hdev->vport[0]; 11253 11254 if (hdev->roce_client) { 11255 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11256 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11257 msleep(HCLGE_WAIT_RESET_DONE); 11258 11259 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11260 hdev->roce_client = NULL; 11261 vport->roce.client = NULL; 11262 } 11263 if (client->type == HNAE3_CLIENT_ROCE) 11264 return; 11265 if (hdev->nic_client && client->ops->uninit_instance) { 11266 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11267 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11268 msleep(HCLGE_WAIT_RESET_DONE); 11269 11270 client->ops->uninit_instance(&vport->nic, 0); 11271 hdev->nic_client = NULL; 11272 vport->nic.client = NULL; 11273 } 11274 } 11275 11276 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11277 { 11278 struct pci_dev *pdev = hdev->pdev; 11279 struct hclge_hw *hw = &hdev->hw; 11280 11281 /* for device does not have device memory, return directly */ 11282 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11283 return 0; 11284 11285 hw->hw.mem_base = 11286 devm_ioremap_wc(&pdev->dev, 11287 pci_resource_start(pdev, HCLGE_MEM_BAR), 11288 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11289 if (!hw->hw.mem_base) { 11290 dev_err(&pdev->dev, "failed to map device memory\n"); 11291 return -EFAULT; 11292 } 11293 11294 return 0; 11295 } 11296 11297 static int hclge_pci_init(struct hclge_dev *hdev) 11298 { 11299 struct pci_dev *pdev = hdev->pdev; 11300 struct hclge_hw *hw; 11301 int ret; 11302 11303 ret = pci_enable_device(pdev); 11304 if (ret) { 11305 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11306 return ret; 11307 } 11308 11309 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11310 if (ret) { 11311 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11312 if (ret) { 11313 dev_err(&pdev->dev, 11314 "can't set consistent PCI DMA"); 11315 goto err_disable_device; 11316 } 11317 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11318 } 11319 11320 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11321 if (ret) { 11322 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11323 goto err_disable_device; 11324 } 11325 11326 pci_set_master(pdev); 11327 hw = &hdev->hw; 11328 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11329 if (!hw->hw.io_base) { 11330 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11331 ret = -ENOMEM; 11332 goto err_release_regions; 11333 } 11334 11335 ret = hclge_dev_mem_map(hdev); 11336 if (ret) 11337 goto err_unmap_io_base; 11338 11339 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11340 11341 return 0; 11342 11343 err_unmap_io_base: 11344 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11345 err_release_regions: 11346 pci_release_regions(pdev); 11347 err_disable_device: 11348 pci_disable_device(pdev); 11349 11350 return ret; 11351 } 11352 11353 static void hclge_pci_uninit(struct hclge_dev *hdev) 11354 { 11355 struct pci_dev *pdev = hdev->pdev; 11356 11357 if (hdev->hw.hw.mem_base) 11358 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11359 11360 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11361 pci_free_irq_vectors(pdev); 11362 pci_release_mem_regions(pdev); 11363 pci_disable_device(pdev); 11364 } 11365 11366 static void hclge_state_init(struct hclge_dev *hdev) 11367 { 11368 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11369 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11370 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11371 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11372 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11373 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11374 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11375 } 11376 11377 static void hclge_state_uninit(struct hclge_dev *hdev) 11378 { 11379 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11380 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11381 11382 if (hdev->reset_timer.function) 11383 del_timer_sync(&hdev->reset_timer); 11384 if (hdev->service_task.work.func) 11385 cancel_delayed_work_sync(&hdev->service_task); 11386 } 11387 11388 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11389 enum hnae3_reset_type rst_type) 11390 { 11391 #define HCLGE_RESET_RETRY_WAIT_MS 500 11392 #define HCLGE_RESET_RETRY_CNT 5 11393 11394 struct hclge_dev *hdev = ae_dev->priv; 11395 int retry_cnt = 0; 11396 int ret; 11397 11398 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11399 down(&hdev->reset_sem); 11400 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11401 hdev->reset_type = rst_type; 11402 ret = hclge_reset_prepare(hdev); 11403 if (!ret && !hdev->reset_pending) 11404 break; 11405 11406 dev_err(&hdev->pdev->dev, 11407 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11408 ret, hdev->reset_pending, retry_cnt); 11409 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11410 up(&hdev->reset_sem); 11411 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11412 } 11413 11414 /* disable misc vector before reset done */ 11415 hclge_enable_vector(&hdev->misc_vector, false); 11416 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11417 11418 if (hdev->reset_type == HNAE3_FLR_RESET) 11419 hdev->rst_stats.flr_rst_cnt++; 11420 } 11421 11422 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11423 { 11424 struct hclge_dev *hdev = ae_dev->priv; 11425 int ret; 11426 11427 hclge_enable_vector(&hdev->misc_vector, true); 11428 11429 ret = hclge_reset_rebuild(hdev); 11430 if (ret) 11431 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11432 11433 hdev->reset_type = HNAE3_NONE_RESET; 11434 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11435 up(&hdev->reset_sem); 11436 } 11437 11438 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11439 { 11440 u16 i; 11441 11442 for (i = 0; i < hdev->num_alloc_vport; i++) { 11443 struct hclge_vport *vport = &hdev->vport[i]; 11444 int ret; 11445 11446 /* Send cmd to clear vport's FUNC_RST_ING */ 11447 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11448 if (ret) 11449 dev_warn(&hdev->pdev->dev, 11450 "clear vport(%u) rst failed %d!\n", 11451 vport->vport_id, ret); 11452 } 11453 } 11454 11455 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11456 { 11457 struct hclge_desc desc; 11458 int ret; 11459 11460 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11461 11462 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11463 /* This new command is only supported by new firmware, it will 11464 * fail with older firmware. Error value -EOPNOSUPP can only be 11465 * returned by older firmware running this command, to keep code 11466 * backward compatible we will override this value and return 11467 * success. 11468 */ 11469 if (ret && ret != -EOPNOTSUPP) { 11470 dev_err(&hdev->pdev->dev, 11471 "failed to clear hw resource, ret = %d\n", ret); 11472 return ret; 11473 } 11474 return 0; 11475 } 11476 11477 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11478 { 11479 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11480 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11481 } 11482 11483 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11484 { 11485 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11486 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11487 } 11488 11489 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11490 { 11491 struct hclge_vport *vport = hclge_get_vport(handle); 11492 11493 return &vport->back->hw.mac.wol; 11494 } 11495 11496 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11497 u32 *wol_supported) 11498 { 11499 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11500 struct hclge_desc desc; 11501 int ret; 11502 11503 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11504 true); 11505 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11506 11507 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11508 if (ret) { 11509 dev_err(&hdev->pdev->dev, 11510 "failed to query wol supported, ret = %d\n", ret); 11511 return ret; 11512 } 11513 11514 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11515 11516 return 0; 11517 } 11518 11519 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11520 struct hclge_wol_info *wol_info) 11521 { 11522 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11523 struct hclge_desc desc; 11524 int ret; 11525 11526 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11527 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11528 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11529 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11530 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11531 11532 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11533 if (ret) 11534 dev_err(&hdev->pdev->dev, 11535 "failed to set wol config, ret = %d\n", ret); 11536 11537 return ret; 11538 } 11539 11540 static int hclge_update_wol(struct hclge_dev *hdev) 11541 { 11542 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11543 11544 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11545 return 0; 11546 11547 return hclge_set_wol_cfg(hdev, wol_info); 11548 } 11549 11550 static int hclge_init_wol(struct hclge_dev *hdev) 11551 { 11552 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11553 int ret; 11554 11555 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11556 return 0; 11557 11558 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11559 ret = hclge_get_wol_supported_mode(hdev, 11560 &wol_info->wol_support_mode); 11561 if (ret) { 11562 wol_info->wol_support_mode = 0; 11563 return ret; 11564 } 11565 11566 return hclge_update_wol(hdev); 11567 } 11568 11569 static void hclge_get_wol(struct hnae3_handle *handle, 11570 struct ethtool_wolinfo *wol) 11571 { 11572 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11573 11574 wol->supported = wol_info->wol_support_mode; 11575 wol->wolopts = wol_info->wol_current_mode; 11576 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11577 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11578 } 11579 11580 static int hclge_set_wol(struct hnae3_handle *handle, 11581 struct ethtool_wolinfo *wol) 11582 { 11583 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11584 struct hclge_vport *vport = hclge_get_vport(handle); 11585 u32 wol_mode; 11586 int ret; 11587 11588 wol_mode = wol->wolopts; 11589 if (wol_mode & ~wol_info->wol_support_mode) 11590 return -EINVAL; 11591 11592 wol_info->wol_current_mode = wol_mode; 11593 if (wol_mode & WAKE_MAGICSECURE) { 11594 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11595 wol_info->wol_sopass_size = SOPASS_MAX; 11596 } else { 11597 wol_info->wol_sopass_size = 0; 11598 } 11599 11600 ret = hclge_set_wol_cfg(vport->back, wol_info); 11601 if (ret) 11602 wol_info->wol_current_mode = 0; 11603 11604 return ret; 11605 } 11606 11607 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11608 { 11609 struct pci_dev *pdev = ae_dev->pdev; 11610 struct hclge_dev *hdev; 11611 int ret; 11612 11613 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11614 if (!hdev) 11615 return -ENOMEM; 11616 11617 hdev->pdev = pdev; 11618 hdev->ae_dev = ae_dev; 11619 hdev->reset_type = HNAE3_NONE_RESET; 11620 hdev->reset_level = HNAE3_FUNC_RESET; 11621 ae_dev->priv = hdev; 11622 11623 /* HW supprt 2 layer vlan */ 11624 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11625 11626 mutex_init(&hdev->vport_lock); 11627 spin_lock_init(&hdev->fd_rule_lock); 11628 sema_init(&hdev->reset_sem, 1); 11629 11630 ret = hclge_pci_init(hdev); 11631 if (ret) 11632 goto out; 11633 11634 /* Firmware command queue initialize */ 11635 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11636 if (ret) 11637 goto err_pci_uninit; 11638 11639 /* Firmware command initialize */ 11640 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11641 true, hdev->reset_pending); 11642 if (ret) 11643 goto err_cmd_uninit; 11644 11645 ret = hclge_clear_hw_resource(hdev); 11646 if (ret) 11647 goto err_cmd_uninit; 11648 11649 ret = hclge_get_cap(hdev); 11650 if (ret) 11651 goto err_cmd_uninit; 11652 11653 ret = hclge_query_dev_specs(hdev); 11654 if (ret) { 11655 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11656 ret); 11657 goto err_cmd_uninit; 11658 } 11659 11660 ret = hclge_configure(hdev); 11661 if (ret) { 11662 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11663 goto err_cmd_uninit; 11664 } 11665 11666 ret = hclge_init_msi(hdev); 11667 if (ret) { 11668 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11669 goto err_cmd_uninit; 11670 } 11671 11672 ret = hclge_misc_irq_init(hdev); 11673 if (ret) 11674 goto err_msi_uninit; 11675 11676 ret = hclge_alloc_tqps(hdev); 11677 if (ret) { 11678 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11679 goto err_msi_irq_uninit; 11680 } 11681 11682 ret = hclge_alloc_vport(hdev); 11683 if (ret) 11684 goto err_msi_irq_uninit; 11685 11686 ret = hclge_map_tqp(hdev); 11687 if (ret) 11688 goto err_msi_irq_uninit; 11689 11690 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11691 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 11692 if (hnae3_dev_phy_imp_supported(hdev)) 11693 ret = hclge_update_tp_port_info(hdev); 11694 else 11695 ret = hclge_mac_mdio_config(hdev); 11696 11697 if (ret) 11698 goto err_msi_irq_uninit; 11699 } 11700 11701 ret = hclge_init_umv_space(hdev); 11702 if (ret) 11703 goto err_mdiobus_unreg; 11704 11705 ret = hclge_mac_init(hdev); 11706 if (ret) { 11707 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11708 goto err_mdiobus_unreg; 11709 } 11710 11711 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11712 if (ret) { 11713 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11714 goto err_mdiobus_unreg; 11715 } 11716 11717 ret = hclge_config_gro(hdev); 11718 if (ret) 11719 goto err_mdiobus_unreg; 11720 11721 ret = hclge_init_vlan_config(hdev); 11722 if (ret) { 11723 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11724 goto err_mdiobus_unreg; 11725 } 11726 11727 ret = hclge_tm_schd_init(hdev); 11728 if (ret) { 11729 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11730 goto err_mdiobus_unreg; 11731 } 11732 11733 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11734 &hdev->rss_cfg); 11735 if (ret) { 11736 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11737 goto err_mdiobus_unreg; 11738 } 11739 11740 ret = hclge_rss_init_hw(hdev); 11741 if (ret) { 11742 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11743 goto err_mdiobus_unreg; 11744 } 11745 11746 ret = init_mgr_tbl(hdev); 11747 if (ret) { 11748 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11749 goto err_mdiobus_unreg; 11750 } 11751 11752 ret = hclge_init_fd_config(hdev); 11753 if (ret) { 11754 dev_err(&pdev->dev, 11755 "fd table init fail, ret=%d\n", ret); 11756 goto err_mdiobus_unreg; 11757 } 11758 11759 ret = hclge_ptp_init(hdev); 11760 if (ret) 11761 goto err_mdiobus_unreg; 11762 11763 ret = hclge_update_port_info(hdev); 11764 if (ret) 11765 goto err_ptp_uninit; 11766 11767 INIT_KFIFO(hdev->mac_tnl_log); 11768 11769 hclge_dcb_ops_set(hdev); 11770 11771 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11772 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11773 11774 hclge_clear_all_event_cause(hdev); 11775 hclge_clear_resetting_state(hdev); 11776 11777 /* Log and clear the hw errors those already occurred */ 11778 if (hnae3_dev_ras_imp_supported(hdev)) 11779 hclge_handle_occurred_error(hdev); 11780 else 11781 hclge_handle_all_hns_hw_errors(ae_dev); 11782 11783 /* request delayed reset for the error recovery because an immediate 11784 * global reset on a PF affecting pending initialization of other PFs 11785 */ 11786 if (ae_dev->hw_err_reset_req) { 11787 enum hnae3_reset_type reset_level; 11788 11789 reset_level = hclge_get_reset_level(ae_dev, 11790 &ae_dev->hw_err_reset_req); 11791 hclge_set_def_reset_request(ae_dev, reset_level); 11792 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11793 } 11794 11795 hclge_init_rxd_adv_layout(hdev); 11796 11797 /* Enable MISC vector(vector0) */ 11798 hclge_enable_vector(&hdev->misc_vector, true); 11799 11800 ret = hclge_init_wol(hdev); 11801 if (ret) 11802 dev_warn(&pdev->dev, 11803 "failed to wake on lan init, ret = %d\n", ret); 11804 11805 ret = hclge_devlink_init(hdev); 11806 if (ret) 11807 goto err_ptp_uninit; 11808 11809 hclge_state_init(hdev); 11810 hdev->last_reset_time = jiffies; 11811 11812 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11813 HCLGE_DRIVER_NAME); 11814 11815 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11816 return 0; 11817 11818 err_ptp_uninit: 11819 hclge_ptp_uninit(hdev); 11820 err_mdiobus_unreg: 11821 if (hdev->hw.mac.phydev) 11822 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11823 err_msi_irq_uninit: 11824 hclge_misc_irq_uninit(hdev); 11825 err_msi_uninit: 11826 pci_free_irq_vectors(pdev); 11827 err_cmd_uninit: 11828 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11829 err_pci_uninit: 11830 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11831 pci_release_regions(pdev); 11832 pci_disable_device(pdev); 11833 out: 11834 mutex_destroy(&hdev->vport_lock); 11835 return ret; 11836 } 11837 11838 static void hclge_stats_clear(struct hclge_dev *hdev) 11839 { 11840 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11841 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11842 } 11843 11844 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11845 { 11846 return hclge_config_switch_param(hdev, vf, enable, 11847 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11848 } 11849 11850 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11851 { 11852 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11853 HCLGE_FILTER_FE_NIC_INGRESS_B, 11854 enable, vf); 11855 } 11856 11857 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11858 { 11859 int ret; 11860 11861 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11862 if (ret) { 11863 dev_err(&hdev->pdev->dev, 11864 "Set vf %d mac spoof check %s failed, ret=%d\n", 11865 vf, enable ? "on" : "off", ret); 11866 return ret; 11867 } 11868 11869 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11870 if (ret) 11871 dev_err(&hdev->pdev->dev, 11872 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11873 vf, enable ? "on" : "off", ret); 11874 11875 return ret; 11876 } 11877 11878 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11879 bool enable) 11880 { 11881 struct hclge_vport *vport = hclge_get_vport(handle); 11882 struct hclge_dev *hdev = vport->back; 11883 u32 new_spoofchk = enable ? 1 : 0; 11884 int ret; 11885 11886 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11887 return -EOPNOTSUPP; 11888 11889 vport = hclge_get_vf_vport(hdev, vf); 11890 if (!vport) 11891 return -EINVAL; 11892 11893 if (vport->vf_info.spoofchk == new_spoofchk) 11894 return 0; 11895 11896 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11897 dev_warn(&hdev->pdev->dev, 11898 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11899 vf); 11900 else if (enable && hclge_is_umv_space_full(vport, true)) 11901 dev_warn(&hdev->pdev->dev, 11902 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11903 vf); 11904 11905 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11906 if (ret) 11907 return ret; 11908 11909 vport->vf_info.spoofchk = new_spoofchk; 11910 return 0; 11911 } 11912 11913 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11914 { 11915 struct hclge_vport *vport = hdev->vport; 11916 int ret; 11917 int i; 11918 11919 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11920 return 0; 11921 11922 /* resume the vf spoof check state after reset */ 11923 for (i = 0; i < hdev->num_alloc_vport; i++) { 11924 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11925 vport->vf_info.spoofchk); 11926 if (ret) 11927 return ret; 11928 11929 vport++; 11930 } 11931 11932 return 0; 11933 } 11934 11935 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11936 { 11937 struct hclge_vport *vport = hclge_get_vport(handle); 11938 struct hclge_dev *hdev = vport->back; 11939 u32 new_trusted = enable ? 1 : 0; 11940 11941 vport = hclge_get_vf_vport(hdev, vf); 11942 if (!vport) 11943 return -EINVAL; 11944 11945 if (vport->vf_info.trusted == new_trusted) 11946 return 0; 11947 11948 vport->vf_info.trusted = new_trusted; 11949 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11950 hclge_task_schedule(hdev, 0); 11951 11952 return 0; 11953 } 11954 11955 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11956 { 11957 int ret; 11958 int vf; 11959 11960 /* reset vf rate to default value */ 11961 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11962 struct hclge_vport *vport = &hdev->vport[vf]; 11963 11964 vport->vf_info.max_tx_rate = 0; 11965 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11966 if (ret) 11967 dev_err(&hdev->pdev->dev, 11968 "vf%d failed to reset to default, ret=%d\n", 11969 vf - HCLGE_VF_VPORT_START_NUM, ret); 11970 } 11971 } 11972 11973 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 11974 int min_tx_rate, int max_tx_rate) 11975 { 11976 if (min_tx_rate != 0 || 11977 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 11978 dev_err(&hdev->pdev->dev, 11979 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 11980 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 11981 return -EINVAL; 11982 } 11983 11984 return 0; 11985 } 11986 11987 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 11988 int min_tx_rate, int max_tx_rate, bool force) 11989 { 11990 struct hclge_vport *vport = hclge_get_vport(handle); 11991 struct hclge_dev *hdev = vport->back; 11992 int ret; 11993 11994 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 11995 if (ret) 11996 return ret; 11997 11998 vport = hclge_get_vf_vport(hdev, vf); 11999 if (!vport) 12000 return -EINVAL; 12001 12002 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 12003 return 0; 12004 12005 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 12006 if (ret) 12007 return ret; 12008 12009 vport->vf_info.max_tx_rate = max_tx_rate; 12010 12011 return 0; 12012 } 12013 12014 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 12015 { 12016 struct hnae3_handle *handle = &hdev->vport->nic; 12017 struct hclge_vport *vport; 12018 int ret; 12019 int vf; 12020 12021 /* resume the vf max_tx_rate after reset */ 12022 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12023 vport = hclge_get_vf_vport(hdev, vf); 12024 if (!vport) 12025 return -EINVAL; 12026 12027 /* zero means max rate, after reset, firmware already set it to 12028 * max rate, so just continue. 12029 */ 12030 if (!vport->vf_info.max_tx_rate) 12031 continue; 12032 12033 ret = hclge_set_vf_rate(handle, vf, 0, 12034 vport->vf_info.max_tx_rate, true); 12035 if (ret) { 12036 dev_err(&hdev->pdev->dev, 12037 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12038 vf, vport->vf_info.max_tx_rate, ret); 12039 return ret; 12040 } 12041 } 12042 12043 return 0; 12044 } 12045 12046 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12047 { 12048 struct hclge_vport *vport = hdev->vport; 12049 int i; 12050 12051 for (i = 0; i < hdev->num_alloc_vport; i++) { 12052 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12053 vport++; 12054 } 12055 } 12056 12057 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12058 { 12059 struct hclge_dev *hdev = ae_dev->priv; 12060 struct pci_dev *pdev = ae_dev->pdev; 12061 int ret; 12062 12063 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12064 12065 hclge_stats_clear(hdev); 12066 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12067 * so here should not clean table in memory. 12068 */ 12069 if (hdev->reset_type == HNAE3_IMP_RESET || 12070 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12071 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12072 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12073 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12074 hclge_reset_umv_space(hdev); 12075 } 12076 12077 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12078 true, hdev->reset_pending); 12079 if (ret) { 12080 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12081 return ret; 12082 } 12083 12084 ret = hclge_map_tqp(hdev); 12085 if (ret) { 12086 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12087 return ret; 12088 } 12089 12090 ret = hclge_mac_init(hdev); 12091 if (ret) { 12092 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12093 return ret; 12094 } 12095 12096 ret = hclge_tp_port_init(hdev); 12097 if (ret) { 12098 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12099 ret); 12100 return ret; 12101 } 12102 12103 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12104 if (ret) { 12105 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12106 return ret; 12107 } 12108 12109 ret = hclge_config_gro(hdev); 12110 if (ret) 12111 return ret; 12112 12113 ret = hclge_init_vlan_config(hdev); 12114 if (ret) { 12115 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12116 return ret; 12117 } 12118 12119 hclge_reset_tc_config(hdev); 12120 12121 ret = hclge_tm_init_hw(hdev, true); 12122 if (ret) { 12123 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12124 return ret; 12125 } 12126 12127 ret = hclge_rss_init_hw(hdev); 12128 if (ret) { 12129 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12130 return ret; 12131 } 12132 12133 ret = init_mgr_tbl(hdev); 12134 if (ret) { 12135 dev_err(&pdev->dev, 12136 "failed to reinit manager table, ret = %d\n", ret); 12137 return ret; 12138 } 12139 12140 ret = hclge_init_fd_config(hdev); 12141 if (ret) { 12142 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12143 return ret; 12144 } 12145 12146 ret = hclge_ptp_init(hdev); 12147 if (ret) 12148 return ret; 12149 12150 /* Log and clear the hw errors those already occurred */ 12151 if (hnae3_dev_ras_imp_supported(hdev)) 12152 hclge_handle_occurred_error(hdev); 12153 else 12154 hclge_handle_all_hns_hw_errors(ae_dev); 12155 12156 /* Re-enable the hw error interrupts because 12157 * the interrupts get disabled on global reset. 12158 */ 12159 ret = hclge_config_nic_hw_error(hdev, true); 12160 if (ret) { 12161 dev_err(&pdev->dev, 12162 "fail(%d) to re-enable NIC hw error interrupts\n", 12163 ret); 12164 return ret; 12165 } 12166 12167 if (hdev->roce_client) { 12168 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12169 if (ret) { 12170 dev_err(&pdev->dev, 12171 "fail(%d) to re-enable roce ras interrupts\n", 12172 ret); 12173 return ret; 12174 } 12175 } 12176 12177 hclge_reset_vport_state(hdev); 12178 ret = hclge_reset_vport_spoofchk(hdev); 12179 if (ret) 12180 return ret; 12181 12182 ret = hclge_resume_vf_rate(hdev); 12183 if (ret) 12184 return ret; 12185 12186 hclge_init_rxd_adv_layout(hdev); 12187 12188 ret = hclge_update_wol(hdev); 12189 if (ret) 12190 dev_warn(&pdev->dev, 12191 "failed to update wol config, ret = %d\n", ret); 12192 12193 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12194 HCLGE_DRIVER_NAME); 12195 12196 return 0; 12197 } 12198 12199 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12200 { 12201 struct hclge_dev *hdev = ae_dev->priv; 12202 struct hclge_mac *mac = &hdev->hw.mac; 12203 12204 hclge_reset_vf_rate(hdev); 12205 hclge_clear_vf_vlan(hdev); 12206 hclge_state_uninit(hdev); 12207 hclge_ptp_uninit(hdev); 12208 hclge_uninit_rxd_adv_layout(hdev); 12209 hclge_uninit_mac_table(hdev); 12210 hclge_del_all_fd_entries(hdev); 12211 12212 if (mac->phydev) 12213 mdiobus_unregister(mac->mdio_bus); 12214 12215 /* Disable MISC vector(vector0) */ 12216 hclge_enable_vector(&hdev->misc_vector, false); 12217 synchronize_irq(hdev->misc_vector.vector_irq); 12218 12219 /* Disable all hw interrupts */ 12220 hclge_config_mac_tnl_int(hdev, false); 12221 hclge_config_nic_hw_error(hdev, false); 12222 hclge_config_rocee_ras_interrupt(hdev, false); 12223 12224 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12225 hclge_misc_irq_uninit(hdev); 12226 hclge_devlink_uninit(hdev); 12227 hclge_pci_uninit(hdev); 12228 hclge_uninit_vport_vlan_table(hdev); 12229 mutex_destroy(&hdev->vport_lock); 12230 ae_dev->priv = NULL; 12231 } 12232 12233 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12234 { 12235 struct hclge_vport *vport = hclge_get_vport(handle); 12236 struct hclge_dev *hdev = vport->back; 12237 12238 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12239 } 12240 12241 static void hclge_get_channels(struct hnae3_handle *handle, 12242 struct ethtool_channels *ch) 12243 { 12244 ch->max_combined = hclge_get_max_channels(handle); 12245 ch->other_count = 1; 12246 ch->max_other = 1; 12247 ch->combined_count = handle->kinfo.rss_size; 12248 } 12249 12250 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12251 u16 *alloc_tqps, u16 *max_rss_size) 12252 { 12253 struct hclge_vport *vport = hclge_get_vport(handle); 12254 struct hclge_dev *hdev = vport->back; 12255 12256 *alloc_tqps = vport->alloc_tqps; 12257 *max_rss_size = hdev->pf_rss_size_max; 12258 } 12259 12260 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12261 { 12262 struct hclge_vport *vport = hclge_get_vport(handle); 12263 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12264 struct hclge_dev *hdev = vport->back; 12265 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12266 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12267 u16 roundup_size; 12268 unsigned int i; 12269 12270 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12271 roundup_size = ilog2(roundup_size); 12272 /* Set the RSS TC mode according to the new RSS size */ 12273 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12274 tc_valid[i] = 0; 12275 12276 if (!(hdev->hw_tc_map & BIT(i))) 12277 continue; 12278 12279 tc_valid[i] = 1; 12280 tc_size[i] = roundup_size; 12281 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12282 } 12283 12284 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12285 tc_size); 12286 } 12287 12288 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12289 bool rxfh_configured) 12290 { 12291 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12292 struct hclge_vport *vport = hclge_get_vport(handle); 12293 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12294 struct hclge_dev *hdev = vport->back; 12295 u16 cur_rss_size = kinfo->rss_size; 12296 u16 cur_tqps = kinfo->num_tqps; 12297 u32 *rss_indir; 12298 unsigned int i; 12299 int ret; 12300 12301 kinfo->req_rss_size = new_tqps_num; 12302 12303 ret = hclge_tm_vport_map_update(hdev); 12304 if (ret) { 12305 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12306 return ret; 12307 } 12308 12309 ret = hclge_set_rss_tc_mode_cfg(handle); 12310 if (ret) 12311 return ret; 12312 12313 /* RSS indirection table has been configured by user */ 12314 if (rxfh_configured) 12315 goto out; 12316 12317 /* Reinitializes the rss indirect table according to the new RSS size */ 12318 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12319 GFP_KERNEL); 12320 if (!rss_indir) 12321 return -ENOMEM; 12322 12323 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12324 rss_indir[i] = i % kinfo->rss_size; 12325 12326 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12327 if (ret) 12328 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12329 ret); 12330 12331 kfree(rss_indir); 12332 12333 out: 12334 if (!ret) 12335 dev_info(&hdev->pdev->dev, 12336 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12337 cur_rss_size, kinfo->rss_size, 12338 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12339 12340 return ret; 12341 } 12342 12343 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12344 { 12345 struct hclge_set_led_state_cmd *req; 12346 struct hclge_desc desc; 12347 int ret; 12348 12349 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12350 12351 req = (struct hclge_set_led_state_cmd *)desc.data; 12352 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12353 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12354 12355 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12356 if (ret) 12357 dev_err(&hdev->pdev->dev, 12358 "Send set led state cmd error, ret =%d\n", ret); 12359 12360 return ret; 12361 } 12362 12363 enum hclge_led_status { 12364 HCLGE_LED_OFF, 12365 HCLGE_LED_ON, 12366 HCLGE_LED_NO_CHANGE = 0xFF, 12367 }; 12368 12369 static int hclge_set_led_id(struct hnae3_handle *handle, 12370 enum ethtool_phys_id_state status) 12371 { 12372 struct hclge_vport *vport = hclge_get_vport(handle); 12373 struct hclge_dev *hdev = vport->back; 12374 12375 switch (status) { 12376 case ETHTOOL_ID_ACTIVE: 12377 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12378 case ETHTOOL_ID_INACTIVE: 12379 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12380 default: 12381 return -EINVAL; 12382 } 12383 } 12384 12385 static void hclge_get_link_mode(struct hnae3_handle *handle, 12386 unsigned long *supported, 12387 unsigned long *advertising) 12388 { 12389 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12390 struct hclge_vport *vport = hclge_get_vport(handle); 12391 struct hclge_dev *hdev = vport->back; 12392 unsigned int idx = 0; 12393 12394 for (; idx < size; idx++) { 12395 supported[idx] = hdev->hw.mac.supported[idx]; 12396 advertising[idx] = hdev->hw.mac.advertising[idx]; 12397 } 12398 } 12399 12400 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12401 { 12402 struct hclge_vport *vport = hclge_get_vport(handle); 12403 struct hclge_dev *hdev = vport->back; 12404 bool gro_en_old = hdev->gro_en; 12405 int ret; 12406 12407 hdev->gro_en = enable; 12408 ret = hclge_config_gro(hdev); 12409 if (ret) 12410 hdev->gro_en = gro_en_old; 12411 12412 return ret; 12413 } 12414 12415 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12416 { 12417 struct hnae3_handle *handle = &vport->nic; 12418 struct hclge_dev *hdev = vport->back; 12419 bool uc_en = false; 12420 bool mc_en = false; 12421 u8 tmp_flags; 12422 bool bc_en; 12423 int ret; 12424 12425 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12426 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12427 vport->last_promisc_flags = vport->overflow_promisc_flags; 12428 } 12429 12430 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12431 &vport->state)) 12432 return 0; 12433 12434 /* for PF */ 12435 if (!vport->vport_id) { 12436 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12437 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12438 tmp_flags & HNAE3_MPE); 12439 if (!ret) 12440 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12441 &vport->state); 12442 else 12443 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12444 &vport->state); 12445 return ret; 12446 } 12447 12448 /* for VF */ 12449 if (vport->vf_info.trusted) { 12450 uc_en = vport->vf_info.request_uc_en > 0 || 12451 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12452 mc_en = vport->vf_info.request_mc_en > 0 || 12453 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12454 } 12455 bc_en = vport->vf_info.request_bc_en > 0; 12456 12457 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12458 mc_en, bc_en); 12459 if (ret) { 12460 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12461 return ret; 12462 } 12463 hclge_set_vport_vlan_fltr_change(vport); 12464 12465 return 0; 12466 } 12467 12468 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12469 { 12470 struct hclge_vport *vport; 12471 int ret; 12472 u16 i; 12473 12474 for (i = 0; i < hdev->num_alloc_vport; i++) { 12475 vport = &hdev->vport[i]; 12476 12477 ret = hclge_sync_vport_promisc_mode(vport); 12478 if (ret) 12479 return; 12480 } 12481 } 12482 12483 static bool hclge_module_existed(struct hclge_dev *hdev) 12484 { 12485 struct hclge_desc desc; 12486 u32 existed; 12487 int ret; 12488 12489 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12490 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12491 if (ret) { 12492 dev_err(&hdev->pdev->dev, 12493 "failed to get SFP exist state, ret = %d\n", ret); 12494 return false; 12495 } 12496 12497 existed = le32_to_cpu(desc.data[0]); 12498 12499 return existed != 0; 12500 } 12501 12502 /* need 6 bds(total 140 bytes) in one reading 12503 * return the number of bytes actually read, 0 means read failed. 12504 */ 12505 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12506 u32 len, u8 *data) 12507 { 12508 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12509 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12510 u16 read_len; 12511 u16 copy_len; 12512 int ret; 12513 int i; 12514 12515 /* setup all 6 bds to read module eeprom info. */ 12516 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12517 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12518 true); 12519 12520 /* bd0~bd4 need next flag */ 12521 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12522 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12523 } 12524 12525 /* setup bd0, this bd contains offset and read length. */ 12526 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12527 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12528 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12529 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12530 12531 ret = hclge_cmd_send(&hdev->hw, desc, i); 12532 if (ret) { 12533 dev_err(&hdev->pdev->dev, 12534 "failed to get SFP eeprom info, ret = %d\n", ret); 12535 return 0; 12536 } 12537 12538 /* copy sfp info from bd0 to out buffer. */ 12539 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12540 memcpy(data, sfp_info_bd0->data, copy_len); 12541 read_len = copy_len; 12542 12543 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12544 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12545 if (read_len >= len) 12546 return read_len; 12547 12548 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12549 memcpy(data + read_len, desc[i].data, copy_len); 12550 read_len += copy_len; 12551 } 12552 12553 return read_len; 12554 } 12555 12556 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12557 u32 len, u8 *data) 12558 { 12559 struct hclge_vport *vport = hclge_get_vport(handle); 12560 struct hclge_dev *hdev = vport->back; 12561 u32 read_len = 0; 12562 u16 data_len; 12563 12564 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12565 return -EOPNOTSUPP; 12566 12567 if (!hclge_module_existed(hdev)) 12568 return -ENXIO; 12569 12570 while (read_len < len) { 12571 data_len = hclge_get_sfp_eeprom_info(hdev, 12572 offset + read_len, 12573 len - read_len, 12574 data + read_len); 12575 if (!data_len) 12576 return -EIO; 12577 12578 read_len += data_len; 12579 } 12580 12581 return 0; 12582 } 12583 12584 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12585 u32 *status_code) 12586 { 12587 struct hclge_vport *vport = hclge_get_vport(handle); 12588 struct hclge_dev *hdev = vport->back; 12589 struct hclge_desc desc; 12590 int ret; 12591 12592 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12593 return -EOPNOTSUPP; 12594 12595 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12596 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12597 if (ret) { 12598 dev_err(&hdev->pdev->dev, 12599 "failed to query link diagnosis info, ret = %d\n", ret); 12600 return ret; 12601 } 12602 12603 *status_code = le32_to_cpu(desc.data[0]); 12604 return 0; 12605 } 12606 12607 /* After disable sriov, VF still has some config and info need clean, 12608 * which configed by PF. 12609 */ 12610 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12611 { 12612 struct hclge_dev *hdev = vport->back; 12613 struct hclge_vlan_info vlan_info; 12614 int ret; 12615 12616 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12617 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12618 vport->need_notify = 0; 12619 vport->mps = 0; 12620 12621 /* after disable sriov, clean VF rate configured by PF */ 12622 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12623 if (ret) 12624 dev_err(&hdev->pdev->dev, 12625 "failed to clean vf%d rate config, ret = %d\n", 12626 vfid, ret); 12627 12628 vlan_info.vlan_tag = 0; 12629 vlan_info.qos = 0; 12630 vlan_info.vlan_proto = ETH_P_8021Q; 12631 ret = hclge_update_port_base_vlan_cfg(vport, 12632 HNAE3_PORT_BASE_VLAN_DISABLE, 12633 &vlan_info); 12634 if (ret) 12635 dev_err(&hdev->pdev->dev, 12636 "failed to clean vf%d port base vlan, ret = %d\n", 12637 vfid, ret); 12638 12639 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12640 if (ret) 12641 dev_err(&hdev->pdev->dev, 12642 "failed to clean vf%d spoof config, ret = %d\n", 12643 vfid, ret); 12644 12645 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12646 } 12647 12648 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12649 { 12650 struct hclge_dev *hdev = ae_dev->priv; 12651 struct hclge_vport *vport; 12652 int i; 12653 12654 for (i = 0; i < num_vfs; i++) { 12655 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12656 12657 hclge_clear_vport_vf_info(vport, i); 12658 } 12659 } 12660 12661 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12662 u8 *priority) 12663 { 12664 struct hclge_vport *vport = hclge_get_vport(h); 12665 12666 if (dscp >= HNAE3_MAX_DSCP) 12667 return -EINVAL; 12668 12669 if (tc_mode) 12670 *tc_mode = vport->nic.kinfo.tc_map_mode; 12671 if (priority) 12672 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12673 vport->nic.kinfo.dscp_prio[dscp]; 12674 12675 return 0; 12676 } 12677 12678 static const struct hnae3_ae_ops hclge_ops = { 12679 .init_ae_dev = hclge_init_ae_dev, 12680 .uninit_ae_dev = hclge_uninit_ae_dev, 12681 .reset_prepare = hclge_reset_prepare_general, 12682 .reset_done = hclge_reset_done, 12683 .init_client_instance = hclge_init_client_instance, 12684 .uninit_client_instance = hclge_uninit_client_instance, 12685 .map_ring_to_vector = hclge_map_ring_to_vector, 12686 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12687 .get_vector = hclge_get_vector, 12688 .put_vector = hclge_put_vector, 12689 .set_promisc_mode = hclge_set_promisc_mode, 12690 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12691 .set_loopback = hclge_set_loopback, 12692 .start = hclge_ae_start, 12693 .stop = hclge_ae_stop, 12694 .client_start = hclge_client_start, 12695 .client_stop = hclge_client_stop, 12696 .get_status = hclge_get_status, 12697 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12698 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12699 .get_media_type = hclge_get_media_type, 12700 .check_port_speed = hclge_check_port_speed, 12701 .get_fec_stats = hclge_get_fec_stats, 12702 .get_fec = hclge_get_fec, 12703 .set_fec = hclge_set_fec, 12704 .get_rss_key_size = hclge_comm_get_rss_key_size, 12705 .get_rss = hclge_get_rss, 12706 .set_rss = hclge_set_rss, 12707 .set_rss_tuple = hclge_set_rss_tuple, 12708 .get_rss_tuple = hclge_get_rss_tuple, 12709 .get_tc_size = hclge_get_tc_size, 12710 .get_mac_addr = hclge_get_mac_addr, 12711 .set_mac_addr = hclge_set_mac_addr, 12712 .do_ioctl = hclge_do_ioctl, 12713 .add_uc_addr = hclge_add_uc_addr, 12714 .rm_uc_addr = hclge_rm_uc_addr, 12715 .add_mc_addr = hclge_add_mc_addr, 12716 .rm_mc_addr = hclge_rm_mc_addr, 12717 .set_autoneg = hclge_set_autoneg, 12718 .get_autoneg = hclge_get_autoneg, 12719 .restart_autoneg = hclge_restart_autoneg, 12720 .halt_autoneg = hclge_halt_autoneg, 12721 .get_pauseparam = hclge_get_pauseparam, 12722 .set_pauseparam = hclge_set_pauseparam, 12723 .set_mtu = hclge_set_mtu, 12724 .reset_queue = hclge_reset_tqp, 12725 .get_stats = hclge_get_stats, 12726 .get_mac_stats = hclge_get_mac_stat, 12727 .update_stats = hclge_update_stats, 12728 .get_strings = hclge_get_strings, 12729 .get_sset_count = hclge_get_sset_count, 12730 .get_fw_version = hclge_get_fw_version, 12731 .get_mdix_mode = hclge_get_mdix_mode, 12732 .enable_vlan_filter = hclge_enable_vlan_filter, 12733 .set_vlan_filter = hclge_set_vlan_filter, 12734 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12735 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12736 .reset_event = hclge_reset_event, 12737 .get_reset_level = hclge_get_reset_level, 12738 .set_default_reset_request = hclge_set_def_reset_request, 12739 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12740 .set_channels = hclge_set_channels, 12741 .get_channels = hclge_get_channels, 12742 .get_regs_len = hclge_get_regs_len, 12743 .get_regs = hclge_get_regs, 12744 .set_led_id = hclge_set_led_id, 12745 .get_link_mode = hclge_get_link_mode, 12746 .add_fd_entry = hclge_add_fd_entry, 12747 .del_fd_entry = hclge_del_fd_entry, 12748 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12749 .get_fd_rule_info = hclge_get_fd_rule_info, 12750 .get_fd_all_rules = hclge_get_all_rules, 12751 .enable_fd = hclge_enable_fd, 12752 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12753 .dbg_read_cmd = hclge_dbg_read_cmd, 12754 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12755 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12756 .ae_dev_resetting = hclge_ae_dev_resetting, 12757 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12758 .set_gro_en = hclge_gro_en, 12759 .get_global_queue_id = hclge_covert_handle_qid_global, 12760 .set_timer_task = hclge_set_timer_task, 12761 .mac_connect_phy = hclge_mac_connect_phy, 12762 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12763 .get_vf_config = hclge_get_vf_config, 12764 .set_vf_link_state = hclge_set_vf_link_state, 12765 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12766 .set_vf_trust = hclge_set_vf_trust, 12767 .set_vf_rate = hclge_set_vf_rate, 12768 .set_vf_mac = hclge_set_vf_mac, 12769 .get_module_eeprom = hclge_get_module_eeprom, 12770 .get_cmdq_stat = hclge_get_cmdq_stat, 12771 .add_cls_flower = hclge_add_cls_flower, 12772 .del_cls_flower = hclge_del_cls_flower, 12773 .cls_flower_active = hclge_is_cls_flower_active, 12774 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12775 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12776 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12777 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12778 .get_ts_info = hclge_ptp_get_ts_info, 12779 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12780 .clean_vf_config = hclge_clean_vport_config, 12781 .get_dscp_prio = hclge_get_dscp_prio, 12782 .get_wol = hclge_get_wol, 12783 .set_wol = hclge_set_wol, 12784 }; 12785 12786 static struct hnae3_ae_algo ae_algo = { 12787 .ops = &hclge_ops, 12788 .pdev_id_table = ae_algo_pci_tbl, 12789 }; 12790 12791 static int __init hclge_init(void) 12792 { 12793 pr_info("%s is initializing\n", HCLGE_NAME); 12794 12795 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 12796 if (!hclge_wq) { 12797 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12798 return -ENOMEM; 12799 } 12800 12801 hnae3_register_ae_algo(&ae_algo); 12802 12803 return 0; 12804 } 12805 12806 static void __exit hclge_exit(void) 12807 { 12808 hnae3_unregister_ae_algo_prepare(&ae_algo); 12809 hnae3_unregister_ae_algo(&ae_algo); 12810 destroy_workqueue(hclge_wq); 12811 } 12812 module_init(hclge_init); 12813 module_exit(hclge_exit); 12814 12815 MODULE_LICENSE("GPL"); 12816 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12817 MODULE_DESCRIPTION("HCLGE Driver"); 12818 MODULE_VERSION(HCLGE_MOD_VERSION); 12819