1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/pci.h> 14 #include <linux/platform_device.h> 15 #include <linux/if_vlan.h> 16 #include <linux/crash_dump.h> 17 18 #include <net/rtnetlink.h> 19 20 #include "hclge_cmd.h" 21 #include "hclge_dcb.h" 22 #include "hclge_main.h" 23 #include "hclge_mbx.h" 24 #include "hclge_mdio.h" 25 #include "hclge_regs.h" 26 #include "hclge_tm.h" 27 #include "hclge_err.h" 28 #include "hnae3.h" 29 #include "hclge_devlink.h" 30 #include "hclge_comm_cmd.h" 31 32 #include "hclge_trace.h" 33 34 #define HCLGE_NAME "hclge" 35 36 #define HCLGE_BUF_SIZE_UNIT 256U 37 #define HCLGE_BUF_MUL_BY 2 38 #define HCLGE_BUF_DIV_BY 2 39 #define NEED_RESERVE_TC_NUM 2 40 #define BUF_MAX_PERCENT 100 41 #define BUF_RESERVE_PERCENT 90 42 43 #define HCLGE_RESET_MAX_FAIL_CNT 5 44 #define HCLGE_RESET_SYNC_TIME 100 45 #define HCLGE_PF_RESET_SYNC_TIME 20 46 #define HCLGE_PF_RESET_SYNC_CNT 1500 47 48 #define HCLGE_LINK_STATUS_MS 10 49 50 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 51 static int hclge_init_vlan_config(struct hclge_dev *hdev); 52 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 53 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 54 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 55 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 56 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 57 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 58 unsigned long *addr); 59 static int hclge_set_default_loopback(struct hclge_dev *hdev); 60 61 static void hclge_sync_mac_table(struct hclge_dev *hdev); 62 static void hclge_restore_hw_table(struct hclge_dev *hdev); 63 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 64 static void hclge_sync_fd_table(struct hclge_dev *hdev); 65 static void hclge_update_fec_stats(struct hclge_dev *hdev); 66 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 67 int wait_cnt); 68 static int hclge_update_port_info(struct hclge_dev *hdev); 69 70 static struct hnae3_ae_algo ae_algo; 71 72 static struct workqueue_struct *hclge_wq; 73 74 static const struct pci_device_id ae_algo_pci_tbl[] = { 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 79 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 83 /* required last entry */ 84 {0, } 85 }; 86 87 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 88 89 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 90 "External Loopback test", 91 "App Loopback test", 92 "Serdes serial Loopback test", 93 "Serdes parallel Loopback test", 94 "Phy Loopback test" 95 }; 96 97 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 98 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 100 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 101 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 102 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 104 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 105 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 106 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 108 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 109 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 110 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 112 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 114 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 116 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 118 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 120 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 122 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 124 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 126 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 128 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 130 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 132 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 134 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 136 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 138 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 140 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 141 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 142 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 143 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 144 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 146 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 148 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 150 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 152 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 154 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 156 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 158 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 160 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 162 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 164 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 166 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 168 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 170 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 172 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 174 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 176 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 178 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 180 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 182 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 184 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 186 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 188 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 190 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 192 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 194 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 196 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 198 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 200 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 202 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 204 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 206 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 208 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 210 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 212 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 214 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 216 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 218 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 220 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 222 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 224 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 226 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 228 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 230 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 232 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 234 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 236 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 238 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 240 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 242 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 244 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 246 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 248 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 250 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 252 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 254 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 256 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 258 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 260 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 262 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 264 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 266 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 268 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 270 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 272 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 274 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 275 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 276 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 278 279 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 281 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 283 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 285 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 287 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 289 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 291 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 293 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 295 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 297 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 299 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 301 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 303 }; 304 305 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 306 { 307 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 308 .ethter_type = cpu_to_le16(ETH_P_LLDP), 309 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 310 .i_port_bitmap = 0x1, 311 }, 312 }; 313 314 static const struct key_info meta_data_key_info[] = { 315 { PACKET_TYPE_ID, 6 }, 316 { IP_FRAGEMENT, 1 }, 317 { ROCE_TYPE, 1 }, 318 { NEXT_KEY, 5 }, 319 { VLAN_NUMBER, 2 }, 320 { SRC_VPORT, 12 }, 321 { DST_VPORT, 12 }, 322 { TUNNEL_PACKET, 1 }, 323 }; 324 325 static const struct key_info tuple_key_info[] = { 326 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 327 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 328 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 329 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 330 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 331 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 332 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 333 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 334 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 335 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 336 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 337 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 338 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 339 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 340 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 341 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 342 { INNER_DST_MAC, 48, KEY_OPT_MAC, 343 offsetof(struct hclge_fd_rule, tuples.dst_mac), 344 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 345 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 346 offsetof(struct hclge_fd_rule, tuples.src_mac), 347 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 348 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 349 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 350 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 351 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 352 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 353 offsetof(struct hclge_fd_rule, tuples.ether_proto), 354 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 355 { INNER_L2_RSV, 16, KEY_OPT_LE16, 356 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 357 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 358 { INNER_IP_TOS, 8, KEY_OPT_U8, 359 offsetof(struct hclge_fd_rule, tuples.ip_tos), 360 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 361 { INNER_IP_PROTO, 8, KEY_OPT_U8, 362 offsetof(struct hclge_fd_rule, tuples.ip_proto), 363 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 364 { INNER_SRC_IP, 32, KEY_OPT_IP, 365 offsetof(struct hclge_fd_rule, tuples.src_ip), 366 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 367 { INNER_DST_IP, 32, KEY_OPT_IP, 368 offsetof(struct hclge_fd_rule, tuples.dst_ip), 369 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 370 { INNER_L3_RSV, 16, KEY_OPT_LE16, 371 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 372 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 373 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 374 offsetof(struct hclge_fd_rule, tuples.src_port), 375 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 376 { INNER_DST_PORT, 16, KEY_OPT_LE16, 377 offsetof(struct hclge_fd_rule, tuples.dst_port), 378 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 379 { INNER_L4_RSV, 32, KEY_OPT_LE32, 380 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 381 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 382 }; 383 384 /** 385 * hclge_cmd_send - send command to command queue 386 * @hw: pointer to the hw struct 387 * @desc: prefilled descriptor for describing the command 388 * @num : the number of descriptors to be sent 389 * 390 * This is the main send command for command queue, it 391 * sends the queue, cleans the queue, etc 392 **/ 393 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 394 { 395 return hclge_comm_cmd_send(&hw->hw, desc, num); 396 } 397 398 static void hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 399 int num, bool is_special) 400 { 401 int i; 402 403 trace_hclge_pf_cmd_send(hw, desc, 0, num); 404 405 if (!is_special) { 406 for (i = 1; i < num; i++) 407 trace_hclge_pf_cmd_send(hw, &desc[i], i, num); 408 } else { 409 for (i = 1; i < num; i++) 410 trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i], 411 i, num); 412 } 413 } 414 415 static void hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, 416 int num, bool is_special) 417 { 418 int i; 419 420 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 421 return; 422 423 trace_hclge_pf_cmd_get(hw, desc, 0, num); 424 425 if (!is_special) { 426 for (i = 1; i < num; i++) 427 trace_hclge_pf_cmd_get(hw, &desc[i], i, num); 428 } else { 429 for (i = 1; i < num; i++) 430 trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i], 431 i, num); 432 } 433 } 434 435 static const struct hclge_comm_cmq_ops hclge_cmq_ops = { 436 .trace_cmd_send = hclge_trace_cmd_send, 437 .trace_cmd_get = hclge_trace_cmd_get, 438 }; 439 440 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 441 { 442 #define HCLGE_MAC_CMD_NUM 21 443 444 u64 *data = (u64 *)(&hdev->mac_stats); 445 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 446 __le64 *desc_data; 447 u32 data_size; 448 int ret; 449 u32 i; 450 451 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 452 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 453 if (ret) { 454 dev_err(&hdev->pdev->dev, 455 "Get MAC pkt stats fail, status = %d.\n", ret); 456 457 return ret; 458 } 459 460 /* The first desc has a 64-bit header, so data size need to minus 1 */ 461 data_size = sizeof(desc) / (sizeof(u64)) - 1; 462 463 desc_data = (__le64 *)(&desc[0].data[0]); 464 for (i = 0; i < data_size; i++) { 465 /* data memory is continuous becase only the first desc has a 466 * header in this command 467 */ 468 *data += le64_to_cpu(*desc_data); 469 data++; 470 desc_data++; 471 } 472 473 return 0; 474 } 475 476 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 477 { 478 #define HCLGE_REG_NUM_PER_DESC 4 479 480 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 481 u64 *data = (u64 *)(&hdev->mac_stats); 482 struct hclge_desc *desc; 483 __le64 *desc_data; 484 u32 data_size; 485 u32 desc_num; 486 int ret; 487 u32 i; 488 489 /* The first desc has a 64-bit header, so need to consider it */ 490 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 491 492 /* This may be called inside atomic sections, 493 * so GFP_ATOMIC is more suitable here 494 */ 495 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 496 if (!desc) 497 return -ENOMEM; 498 499 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 500 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 501 if (ret) { 502 kfree(desc); 503 return ret; 504 } 505 506 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 507 508 desc_data = (__le64 *)(&desc[0].data[0]); 509 for (i = 0; i < data_size; i++) { 510 /* data memory is continuous becase only the first desc has a 511 * header in this command 512 */ 513 *data += le64_to_cpu(*desc_data); 514 data++; 515 desc_data++; 516 } 517 518 kfree(desc); 519 520 return 0; 521 } 522 523 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 524 { 525 struct hclge_desc desc; 526 int ret; 527 528 /* Driver needs total register number of both valid registers and 529 * reserved registers, but the old firmware only returns number 530 * of valid registers in device V2. To be compatible with these 531 * devices, driver uses a fixed value. 532 */ 533 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 534 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 535 return 0; 536 } 537 538 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 539 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 540 if (ret) { 541 dev_err(&hdev->pdev->dev, 542 "failed to query mac statistic reg number, ret = %d\n", 543 ret); 544 return ret; 545 } 546 547 *reg_num = le32_to_cpu(desc.data[0]); 548 if (*reg_num == 0) { 549 dev_err(&hdev->pdev->dev, 550 "mac statistic reg number is invalid!\n"); 551 return -ENODATA; 552 } 553 554 return 0; 555 } 556 557 int hclge_mac_update_stats(struct hclge_dev *hdev) 558 { 559 /* The firmware supports the new statistics acquisition method */ 560 if (hdev->ae_dev->dev_specs.mac_stats_num) 561 return hclge_mac_update_stats_complete(hdev); 562 else 563 return hclge_mac_update_stats_defective(hdev); 564 } 565 566 static int hclge_comm_get_count(struct hclge_dev *hdev, 567 const struct hclge_comm_stats_str strs[], 568 u32 size) 569 { 570 int count = 0; 571 u32 i; 572 573 for (i = 0; i < size; i++) 574 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 575 count++; 576 577 return count; 578 } 579 580 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 581 const struct hclge_comm_stats_str strs[], 582 int size, u64 *data) 583 { 584 u64 *buf = data; 585 int i; 586 587 for (i = 0; i < size; i++) { 588 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 589 continue; 590 591 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 592 buf++; 593 } 594 595 return buf; 596 } 597 598 static void hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 599 const struct hclge_comm_stats_str strs[], 600 int size, u8 **data) 601 { 602 int i; 603 604 if (stringset != ETH_SS_STATS) 605 return; 606 607 for (i = 0; i < size; i++) { 608 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 609 continue; 610 611 ethtool_puts(data, strs[i].desc); 612 } 613 } 614 615 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 616 { 617 struct hnae3_handle *handle; 618 int status; 619 620 handle = &hdev->vport[0].nic; 621 if (handle->client) { 622 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 623 if (status) { 624 dev_err(&hdev->pdev->dev, 625 "Update TQPS stats fail, status = %d.\n", 626 status); 627 } 628 } 629 630 hclge_update_fec_stats(hdev); 631 632 status = hclge_mac_update_stats(hdev); 633 if (status) 634 dev_err(&hdev->pdev->dev, 635 "Update MAC stats fail, status = %d.\n", status); 636 } 637 638 static void hclge_update_stats(struct hnae3_handle *handle) 639 { 640 struct hclge_vport *vport = hclge_get_vport(handle); 641 struct hclge_dev *hdev = vport->back; 642 int status; 643 644 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 645 return; 646 647 status = hclge_mac_update_stats(hdev); 648 if (status) 649 dev_err(&hdev->pdev->dev, 650 "Update MAC stats fail, status = %d.\n", 651 status); 652 653 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 654 if (status) 655 dev_err(&hdev->pdev->dev, 656 "Update TQPS stats fail, status = %d.\n", 657 status); 658 659 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 660 } 661 662 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 663 { 664 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 665 HNAE3_SUPPORT_PHY_LOOPBACK | \ 666 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 667 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 668 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 669 670 struct hclge_vport *vport = hclge_get_vport(handle); 671 struct hclge_dev *hdev = vport->back; 672 int count = 0; 673 674 /* Loopback test support rules: 675 * mac: only GE mode support 676 * serdes: all mac mode will support include GE/XGE/LGE/CGE 677 * phy: only support when phy device exist on board 678 */ 679 if (stringset == ETH_SS_TEST) { 680 /* clear loopback bit flags at first */ 681 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 682 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 683 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 684 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 685 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 686 count += 1; 687 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 688 } 689 690 if (hdev->ae_dev->dev_specs.hilink_version != 691 HCLGE_HILINK_H60) { 692 count += 1; 693 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 694 } 695 696 count += 1; 697 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 698 count += 1; 699 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 700 701 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 702 hdev->hw.mac.phydev->drv->set_loopback) || 703 hnae3_dev_phy_imp_supported(hdev)) { 704 count += 1; 705 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 706 } 707 } else if (stringset == ETH_SS_STATS) { 708 count = hclge_comm_get_count(hdev, g_mac_stats_string, 709 ARRAY_SIZE(g_mac_stats_string)) + 710 hclge_comm_tqps_get_sset_count(handle); 711 } 712 713 return count; 714 } 715 716 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 717 u8 **data) 718 { 719 struct hclge_vport *vport = hclge_get_vport(handle); 720 struct hclge_dev *hdev = vport->back; 721 const char *str; 722 int size; 723 724 if (stringset == ETH_SS_STATS) { 725 size = ARRAY_SIZE(g_mac_stats_string); 726 hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 727 size, data); 728 hclge_comm_tqps_get_strings(handle, data); 729 } else if (stringset == ETH_SS_TEST) { 730 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 731 str = hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL]; 732 ethtool_puts(data, str); 733 } 734 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 735 str = hns3_nic_test_strs[HNAE3_LOOP_APP]; 736 ethtool_puts(data, str); 737 } 738 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 739 str = hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES]; 740 ethtool_puts(data, str); 741 } 742 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 743 str = hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES]; 744 ethtool_puts(data, str); 745 } 746 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 747 str = hns3_nic_test_strs[HNAE3_LOOP_PHY]; 748 ethtool_puts(data, str); 749 } 750 } 751 } 752 753 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 754 { 755 struct hclge_vport *vport = hclge_get_vport(handle); 756 struct hclge_dev *hdev = vport->back; 757 u64 *p; 758 759 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 760 ARRAY_SIZE(g_mac_stats_string), data); 761 p = hclge_comm_tqps_get_stats(handle, p); 762 } 763 764 static void hclge_get_mac_stat(struct hnae3_handle *handle, 765 struct hns3_mac_stats *mac_stats) 766 { 767 struct hclge_vport *vport = hclge_get_vport(handle); 768 struct hclge_dev *hdev = vport->back; 769 770 hclge_update_stats(handle); 771 772 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 773 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 774 } 775 776 static int hclge_parse_func_status(struct hclge_dev *hdev, 777 struct hclge_func_status_cmd *status) 778 { 779 #define HCLGE_MAC_ID_MASK 0xF 780 781 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 782 return -EINVAL; 783 784 /* Set the pf to main pf */ 785 if (status->pf_state & HCLGE_PF_STATE_MAIN) 786 hdev->flag |= HCLGE_FLAG_MAIN; 787 else 788 hdev->flag &= ~HCLGE_FLAG_MAIN; 789 790 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 791 return 0; 792 } 793 794 static int hclge_query_function_status(struct hclge_dev *hdev) 795 { 796 #define HCLGE_QUERY_MAX_CNT 5 797 798 struct hclge_func_status_cmd *req; 799 struct hclge_desc desc; 800 int timeout = 0; 801 int ret; 802 803 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 804 req = (struct hclge_func_status_cmd *)desc.data; 805 806 do { 807 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 808 if (ret) { 809 dev_err(&hdev->pdev->dev, 810 "query function status failed %d.\n", ret); 811 return ret; 812 } 813 814 /* Check pf reset is done */ 815 if (req->pf_state) 816 break; 817 usleep_range(1000, 2000); 818 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 819 820 return hclge_parse_func_status(hdev, req); 821 } 822 823 static int hclge_query_pf_resource(struct hclge_dev *hdev) 824 { 825 struct hclge_pf_res_cmd *req; 826 struct hclge_desc desc; 827 int ret; 828 829 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 830 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 831 if (ret) { 832 dev_err(&hdev->pdev->dev, 833 "query pf resource failed %d.\n", ret); 834 return ret; 835 } 836 837 req = (struct hclge_pf_res_cmd *)desc.data; 838 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 839 le16_to_cpu(req->ext_tqp_num); 840 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 841 842 if (req->tx_buf_size) 843 hdev->tx_buf_size = 844 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 845 else 846 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 847 848 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 849 850 if (req->dv_buf_size) 851 hdev->dv_buf_size = 852 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 853 else 854 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 855 856 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 857 858 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 859 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 860 dev_err(&hdev->pdev->dev, 861 "only %u msi resources available, not enough for pf(min:2).\n", 862 hdev->num_nic_msi); 863 return -EINVAL; 864 } 865 866 if (hnae3_dev_roce_supported(hdev)) { 867 hdev->num_roce_msi = 868 le16_to_cpu(req->pf_intr_vector_number_roce); 869 870 /* PF should have NIC vectors and Roce vectors, 871 * NIC vectors are queued before Roce vectors. 872 */ 873 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 874 } else { 875 hdev->num_msi = hdev->num_nic_msi; 876 } 877 878 return 0; 879 } 880 881 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 882 { 883 switch (speed_cmd) { 884 case HCLGE_FW_MAC_SPEED_10M: 885 *speed = HCLGE_MAC_SPEED_10M; 886 break; 887 case HCLGE_FW_MAC_SPEED_100M: 888 *speed = HCLGE_MAC_SPEED_100M; 889 break; 890 case HCLGE_FW_MAC_SPEED_1G: 891 *speed = HCLGE_MAC_SPEED_1G; 892 break; 893 case HCLGE_FW_MAC_SPEED_10G: 894 *speed = HCLGE_MAC_SPEED_10G; 895 break; 896 case HCLGE_FW_MAC_SPEED_25G: 897 *speed = HCLGE_MAC_SPEED_25G; 898 break; 899 case HCLGE_FW_MAC_SPEED_40G: 900 *speed = HCLGE_MAC_SPEED_40G; 901 break; 902 case HCLGE_FW_MAC_SPEED_50G: 903 *speed = HCLGE_MAC_SPEED_50G; 904 break; 905 case HCLGE_FW_MAC_SPEED_100G: 906 *speed = HCLGE_MAC_SPEED_100G; 907 break; 908 case HCLGE_FW_MAC_SPEED_200G: 909 *speed = HCLGE_MAC_SPEED_200G; 910 break; 911 default: 912 return -EINVAL; 913 } 914 915 return 0; 916 } 917 918 static const struct hclge_speed_bit_map speed_bit_map[] = { 919 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 920 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 921 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 922 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 923 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 924 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 925 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS}, 926 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS}, 927 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS}, 928 }; 929 930 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 931 { 932 u16 i; 933 934 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 935 if (speed == speed_bit_map[i].speed) { 936 *speed_bit = speed_bit_map[i].speed_bit; 937 return 0; 938 } 939 } 940 941 return -EINVAL; 942 } 943 944 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 945 { 946 struct hclge_vport *vport = hclge_get_vport(handle); 947 struct hclge_dev *hdev = vport->back; 948 u32 speed_ability = hdev->hw.mac.speed_ability; 949 u32 speed_bit = 0; 950 int ret; 951 952 ret = hclge_get_speed_bit(speed, &speed_bit); 953 if (ret) 954 return ret; 955 956 if (speed_bit & speed_ability) 957 return 0; 958 959 return -EINVAL; 960 } 961 962 static void hclge_update_fec_support(struct hclge_mac *mac) 963 { 964 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 965 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 966 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 967 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 968 969 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 970 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 971 mac->supported); 972 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 973 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 974 mac->supported); 975 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 976 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 977 mac->supported); 978 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 979 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 980 mac->supported); 981 } 982 983 static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = { 984 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT}, 985 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT}, 986 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT}, 987 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT}, 988 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT}, 989 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT}, 990 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT}, 991 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 992 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 993 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 994 }; 995 996 static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = { 997 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT}, 998 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT}, 999 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT}, 1000 {HCLGE_SUPPORT_100G_R4_BIT, 1001 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT}, 1002 {HCLGE_SUPPORT_100G_R2_BIT, 1003 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT}, 1004 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1005 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 1006 {HCLGE_SUPPORT_200G_R4_BIT, 1007 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 1008 }; 1009 1010 static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = { 1011 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT}, 1012 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT}, 1013 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT}, 1014 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT}, 1015 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT}, 1016 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT}, 1017 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT}, 1018 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1019 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 1020 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 1021 }; 1022 1023 static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = { 1024 {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, 1025 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, 1026 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT}, 1027 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT}, 1028 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT}, 1029 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT}, 1030 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT}, 1031 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT}, 1032 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1033 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 1034 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 1035 }; 1036 1037 static void hclge_convert_setting_sr(u16 speed_ability, 1038 unsigned long *link_mode) 1039 { 1040 int i; 1041 1042 for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) { 1043 if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit) 1044 linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode, 1045 link_mode); 1046 } 1047 } 1048 1049 static void hclge_convert_setting_lr(u16 speed_ability, 1050 unsigned long *link_mode) 1051 { 1052 int i; 1053 1054 for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) { 1055 if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit) 1056 linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode, 1057 link_mode); 1058 } 1059 } 1060 1061 static void hclge_convert_setting_cr(u16 speed_ability, 1062 unsigned long *link_mode) 1063 { 1064 int i; 1065 1066 for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) { 1067 if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit) 1068 linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode, 1069 link_mode); 1070 } 1071 } 1072 1073 static void hclge_convert_setting_kr(u16 speed_ability, 1074 unsigned long *link_mode) 1075 { 1076 int i; 1077 1078 for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) { 1079 if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit) 1080 linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode, 1081 link_mode); 1082 } 1083 } 1084 1085 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1086 { 1087 /* If firmware has reported fec_ability, don't need to convert by speed */ 1088 if (mac->fec_ability) 1089 goto out; 1090 1091 switch (mac->speed) { 1092 case HCLGE_MAC_SPEED_10G: 1093 case HCLGE_MAC_SPEED_40G: 1094 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1095 BIT(HNAE3_FEC_NONE); 1096 break; 1097 case HCLGE_MAC_SPEED_25G: 1098 case HCLGE_MAC_SPEED_50G: 1099 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1100 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1101 break; 1102 case HCLGE_MAC_SPEED_100G: 1103 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1104 BIT(HNAE3_FEC_NONE); 1105 break; 1106 case HCLGE_MAC_SPEED_200G: 1107 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1108 BIT(HNAE3_FEC_LLRS); 1109 break; 1110 default: 1111 mac->fec_ability = 0; 1112 break; 1113 } 1114 1115 out: 1116 hclge_update_fec_support(mac); 1117 } 1118 1119 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1120 u16 speed_ability) 1121 { 1122 struct hclge_mac *mac = &hdev->hw.mac; 1123 1124 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1125 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1126 mac->supported); 1127 1128 hclge_convert_setting_sr(speed_ability, mac->supported); 1129 hclge_convert_setting_lr(speed_ability, mac->supported); 1130 hclge_convert_setting_cr(speed_ability, mac->supported); 1131 if (hnae3_dev_fec_supported(hdev)) 1132 hclge_convert_setting_fec(mac); 1133 1134 if (hnae3_dev_pause_supported(hdev)) 1135 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1136 1137 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1138 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1139 } 1140 1141 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1142 u16 speed_ability) 1143 { 1144 struct hclge_mac *mac = &hdev->hw.mac; 1145 1146 hclge_convert_setting_kr(speed_ability, mac->supported); 1147 if (hnae3_dev_fec_supported(hdev)) 1148 hclge_convert_setting_fec(mac); 1149 1150 if (hnae3_dev_pause_supported(hdev)) 1151 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1152 1153 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1154 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1155 } 1156 1157 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1158 u16 speed_ability) 1159 { 1160 unsigned long *supported = hdev->hw.mac.supported; 1161 1162 /* default to support all speed for GE port */ 1163 if (!speed_ability) 1164 speed_ability = HCLGE_SUPPORT_GE; 1165 1166 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1167 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1168 supported); 1169 1170 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1171 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1172 supported); 1173 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1174 supported); 1175 } 1176 1177 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1178 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1179 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1180 } 1181 1182 if (hnae3_dev_pause_supported(hdev)) { 1183 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1184 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1185 } 1186 1187 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1188 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1189 } 1190 1191 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1192 { 1193 u8 media_type = hdev->hw.mac.media_type; 1194 1195 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1196 hclge_parse_fiber_link_mode(hdev, speed_ability); 1197 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1198 hclge_parse_copper_link_mode(hdev, speed_ability); 1199 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1200 hclge_parse_backplane_link_mode(hdev, speed_ability); 1201 } 1202 1203 static u32 hclge_get_max_speed(u16 speed_ability) 1204 { 1205 if (speed_ability & HCLGE_SUPPORT_200G_BITS) 1206 return HCLGE_MAC_SPEED_200G; 1207 1208 if (speed_ability & HCLGE_SUPPORT_100G_BITS) 1209 return HCLGE_MAC_SPEED_100G; 1210 1211 if (speed_ability & HCLGE_SUPPORT_50G_BITS) 1212 return HCLGE_MAC_SPEED_50G; 1213 1214 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1215 return HCLGE_MAC_SPEED_40G; 1216 1217 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1218 return HCLGE_MAC_SPEED_25G; 1219 1220 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1221 return HCLGE_MAC_SPEED_10G; 1222 1223 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1224 return HCLGE_MAC_SPEED_1G; 1225 1226 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1227 return HCLGE_MAC_SPEED_100M; 1228 1229 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1230 return HCLGE_MAC_SPEED_10M; 1231 1232 return HCLGE_MAC_SPEED_1G; 1233 } 1234 1235 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1236 { 1237 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1238 #define SPEED_ABILITY_EXT_SHIFT 8 1239 1240 struct hclge_cfg_param_cmd *req; 1241 u64 mac_addr_tmp_high; 1242 u16 speed_ability_ext; 1243 u64 mac_addr_tmp; 1244 unsigned int i; 1245 1246 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1247 1248 /* get the configuration */ 1249 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1250 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1251 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1252 HCLGE_CFG_TQP_DESC_N_M, 1253 HCLGE_CFG_TQP_DESC_N_S); 1254 1255 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1256 HCLGE_CFG_PHY_ADDR_M, 1257 HCLGE_CFG_PHY_ADDR_S); 1258 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1259 HCLGE_CFG_MEDIA_TP_M, 1260 HCLGE_CFG_MEDIA_TP_S); 1261 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1262 HCLGE_CFG_RX_BUF_LEN_M, 1263 HCLGE_CFG_RX_BUF_LEN_S); 1264 /* get mac_address */ 1265 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1266 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1267 HCLGE_CFG_MAC_ADDR_H_M, 1268 HCLGE_CFG_MAC_ADDR_H_S); 1269 1270 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1271 1272 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1273 HCLGE_CFG_DEFAULT_SPEED_M, 1274 HCLGE_CFG_DEFAULT_SPEED_S); 1275 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1276 HCLGE_CFG_RSS_SIZE_M, 1277 HCLGE_CFG_RSS_SIZE_S); 1278 1279 for (i = 0; i < ETH_ALEN; i++) 1280 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1281 1282 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1283 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1284 1285 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1286 HCLGE_CFG_SPEED_ABILITY_M, 1287 HCLGE_CFG_SPEED_ABILITY_S); 1288 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1289 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1290 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1291 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1292 1293 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1294 HCLGE_CFG_VLAN_FLTR_CAP_M, 1295 HCLGE_CFG_VLAN_FLTR_CAP_S); 1296 1297 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1298 HCLGE_CFG_UMV_TBL_SPACE_M, 1299 HCLGE_CFG_UMV_TBL_SPACE_S); 1300 1301 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1302 HCLGE_CFG_PF_RSS_SIZE_M, 1303 HCLGE_CFG_PF_RSS_SIZE_S); 1304 1305 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1306 * power of 2, instead of reading out directly. This would 1307 * be more flexible for future changes and expansions. 1308 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1309 * it does not make sense if PF's field is 0. In this case, PF and VF 1310 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1311 */ 1312 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1313 1U << cfg->pf_rss_size_max : 1314 cfg->vf_rss_size_max; 1315 1316 /* The unit of the tx spare buffer size queried from configuration 1317 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1318 * needed here. 1319 */ 1320 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1321 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1322 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1323 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1324 } 1325 1326 /* hclge_get_cfg: query the static parameter from flash 1327 * @hdev: pointer to struct hclge_dev 1328 * @hcfg: the config structure to be getted 1329 */ 1330 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1331 { 1332 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1333 struct hclge_cfg_param_cmd *req; 1334 unsigned int i; 1335 int ret; 1336 1337 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1338 u32 offset = 0; 1339 1340 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1341 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1342 true); 1343 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1344 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1345 /* Len should be united by 4 bytes when send to hardware */ 1346 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1347 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1348 req->offset = cpu_to_le32(offset); 1349 } 1350 1351 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1352 if (ret) { 1353 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1354 return ret; 1355 } 1356 1357 hclge_parse_cfg(hcfg, desc); 1358 1359 return 0; 1360 } 1361 1362 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1363 { 1364 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1365 1366 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1367 1368 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1369 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1370 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1371 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1372 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1373 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1374 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1375 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1376 ae_dev->dev_specs.tnl_num = 0; 1377 } 1378 1379 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1380 struct hclge_desc *desc) 1381 { 1382 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1383 struct hclge_dev_specs_0_cmd *req0; 1384 struct hclge_dev_specs_1_cmd *req1; 1385 1386 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1387 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1388 1389 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1390 ae_dev->dev_specs.rss_ind_tbl_size = 1391 le16_to_cpu(req0->rss_ind_tbl_size); 1392 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1393 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1394 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1395 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1396 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1397 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1398 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1399 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1400 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1401 ae_dev->dev_specs.hilink_version = req1->hilink_version; 1402 } 1403 1404 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1405 { 1406 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1407 1408 if (!dev_specs->max_non_tso_bd_num) 1409 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1410 if (!dev_specs->rss_ind_tbl_size) 1411 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1412 if (!dev_specs->rss_key_size) 1413 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1414 if (!dev_specs->max_tm_rate) 1415 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1416 if (!dev_specs->max_qset_num) 1417 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1418 if (!dev_specs->max_int_gl) 1419 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1420 if (!dev_specs->max_frm_size) 1421 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1422 if (!dev_specs->umv_size) 1423 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1424 } 1425 1426 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1427 { 1428 u32 reg_num = 0; 1429 int ret; 1430 1431 ret = hclge_mac_query_reg_num(hdev, ®_num); 1432 if (ret && ret != -EOPNOTSUPP) 1433 return ret; 1434 1435 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1436 return 0; 1437 } 1438 1439 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1440 { 1441 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1442 int ret; 1443 int i; 1444 1445 ret = hclge_query_mac_stats_num(hdev); 1446 if (ret) 1447 return ret; 1448 1449 /* set default specifications as devices lower than version V3 do not 1450 * support querying specifications from firmware. 1451 */ 1452 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1453 hclge_set_default_dev_specs(hdev); 1454 return 0; 1455 } 1456 1457 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1458 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1459 true); 1460 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1461 } 1462 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1463 1464 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1465 if (ret) 1466 return ret; 1467 1468 hclge_parse_dev_specs(hdev, desc); 1469 hclge_check_dev_specs(hdev); 1470 1471 return 0; 1472 } 1473 1474 static int hclge_get_cap(struct hclge_dev *hdev) 1475 { 1476 int ret; 1477 1478 ret = hclge_query_function_status(hdev); 1479 if (ret) { 1480 dev_err(&hdev->pdev->dev, 1481 "query function status error %d.\n", ret); 1482 return ret; 1483 } 1484 1485 /* get pf resource */ 1486 return hclge_query_pf_resource(hdev); 1487 } 1488 1489 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1490 { 1491 #define HCLGE_MIN_TX_DESC 64 1492 #define HCLGE_MIN_RX_DESC 64 1493 1494 if (!is_kdump_kernel()) 1495 return; 1496 1497 dev_info(&hdev->pdev->dev, 1498 "Running kdump kernel. Using minimal resources\n"); 1499 1500 /* minimal queue pairs equals to the number of vports */ 1501 hdev->num_tqps = hdev->num_req_vfs + 1; 1502 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1503 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1504 } 1505 1506 static void hclge_init_tc_config(struct hclge_dev *hdev) 1507 { 1508 unsigned int i; 1509 1510 if (hdev->tc_max > HNAE3_MAX_TC || 1511 hdev->tc_max < 1) { 1512 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1513 hdev->tc_max); 1514 hdev->tc_max = 1; 1515 } 1516 1517 /* Dev does not support DCB */ 1518 if (!hnae3_dev_dcb_supported(hdev)) { 1519 hdev->tc_max = 1; 1520 hdev->pfc_max = 0; 1521 } else { 1522 hdev->pfc_max = hdev->tc_max; 1523 } 1524 1525 hdev->tm_info.num_tc = 1; 1526 1527 /* Currently not support uncontiuous tc */ 1528 for (i = 0; i < hdev->tm_info.num_tc; i++) 1529 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1530 1531 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1532 } 1533 1534 static int hclge_configure(struct hclge_dev *hdev) 1535 { 1536 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1537 struct hclge_cfg cfg; 1538 int ret; 1539 1540 ret = hclge_get_cfg(hdev, &cfg); 1541 if (ret) 1542 return ret; 1543 1544 hdev->base_tqp_pid = 0; 1545 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1546 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1547 hdev->rx_buf_len = cfg.rx_buf_len; 1548 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1549 hdev->hw.mac.media_type = cfg.media_type; 1550 hdev->hw.mac.phy_addr = cfg.phy_addr; 1551 hdev->num_tx_desc = cfg.tqp_desc_num; 1552 hdev->num_rx_desc = cfg.tqp_desc_num; 1553 hdev->tm_info.num_pg = 1; 1554 hdev->tc_max = cfg.tc_num; 1555 hdev->tm_info.hw_pfc_map = 0; 1556 if (cfg.umv_space) 1557 hdev->wanted_umv_size = cfg.umv_space; 1558 else 1559 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1560 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1561 hdev->gro_en = true; 1562 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1563 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1564 1565 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1566 hdev->fd_en = true; 1567 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1568 } 1569 1570 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1571 if (ret) { 1572 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1573 cfg.default_speed, ret); 1574 return ret; 1575 } 1576 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1577 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1578 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1579 1580 hclge_parse_link_mode(hdev, cfg.speed_ability); 1581 1582 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1583 1584 hclge_init_tc_config(hdev); 1585 hclge_init_kdump_kernel_config(hdev); 1586 1587 return ret; 1588 } 1589 1590 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1591 u16 tso_mss_max) 1592 { 1593 struct hclge_cfg_tso_status_cmd *req; 1594 struct hclge_desc desc; 1595 1596 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1597 1598 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1599 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1600 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1601 1602 return hclge_cmd_send(&hdev->hw, &desc, 1); 1603 } 1604 1605 static int hclge_config_gro(struct hclge_dev *hdev) 1606 { 1607 struct hclge_cfg_gro_status_cmd *req; 1608 struct hclge_desc desc; 1609 int ret; 1610 1611 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1612 return 0; 1613 1614 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1615 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1616 1617 req->gro_en = hdev->gro_en ? 1 : 0; 1618 1619 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1620 if (ret) 1621 dev_err(&hdev->pdev->dev, 1622 "GRO hardware config cmd failed, ret = %d\n", ret); 1623 1624 return ret; 1625 } 1626 1627 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1628 { 1629 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1630 struct hclge_comm_tqp *tqp; 1631 int i; 1632 1633 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1634 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1635 if (!hdev->htqp) 1636 return -ENOMEM; 1637 1638 tqp = hdev->htqp; 1639 1640 for (i = 0; i < hdev->num_tqps; i++) { 1641 tqp->dev = &hdev->pdev->dev; 1642 tqp->index = i; 1643 1644 tqp->q.ae_algo = &ae_algo; 1645 tqp->q.buf_size = hdev->rx_buf_len; 1646 tqp->q.tx_desc_num = hdev->num_tx_desc; 1647 tqp->q.rx_desc_num = hdev->num_rx_desc; 1648 1649 /* need an extended offset to configure queues >= 1650 * HCLGE_TQP_MAX_SIZE_DEV_V2 1651 */ 1652 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1653 tqp->q.io_base = hdev->hw.hw.io_base + 1654 HCLGE_TQP_REG_OFFSET + 1655 i * HCLGE_TQP_REG_SIZE; 1656 else 1657 tqp->q.io_base = hdev->hw.hw.io_base + 1658 HCLGE_TQP_REG_OFFSET + 1659 HCLGE_TQP_EXT_REG_OFFSET + 1660 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1661 HCLGE_TQP_REG_SIZE; 1662 1663 /* when device supports tx push and has device memory, 1664 * the queue can execute push mode or doorbell mode on 1665 * device memory. 1666 */ 1667 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1668 tqp->q.mem_base = hdev->hw.hw.mem_base + 1669 HCLGE_TQP_MEM_OFFSET(hdev, i); 1670 1671 tqp++; 1672 } 1673 1674 return 0; 1675 } 1676 1677 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1678 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1679 { 1680 struct hclge_tqp_map_cmd *req; 1681 struct hclge_desc desc; 1682 int ret; 1683 1684 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1685 1686 req = (struct hclge_tqp_map_cmd *)desc.data; 1687 req->tqp_id = cpu_to_le16(tqp_pid); 1688 req->tqp_vf = func_id; 1689 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1690 if (!is_pf) 1691 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1692 req->tqp_vid = cpu_to_le16(tqp_vid); 1693 1694 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1695 if (ret) 1696 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1697 1698 return ret; 1699 } 1700 1701 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1702 { 1703 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1704 struct hclge_dev *hdev = vport->back; 1705 int i, alloced; 1706 1707 for (i = 0, alloced = 0; i < hdev->num_tqps && 1708 alloced < num_tqps; i++) { 1709 if (!hdev->htqp[i].alloced) { 1710 hdev->htqp[i].q.handle = &vport->nic; 1711 hdev->htqp[i].q.tqp_index = alloced; 1712 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1713 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1714 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1715 hdev->htqp[i].alloced = true; 1716 alloced++; 1717 } 1718 } 1719 vport->alloc_tqps = alloced; 1720 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1721 vport->alloc_tqps / hdev->tm_info.num_tc); 1722 1723 /* ensure one to one mapping between irq and queue at default */ 1724 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1725 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1726 1727 return 0; 1728 } 1729 1730 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1731 u16 num_tx_desc, u16 num_rx_desc) 1732 1733 { 1734 struct hnae3_handle *nic = &vport->nic; 1735 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1736 struct hclge_dev *hdev = vport->back; 1737 int ret; 1738 1739 kinfo->num_tx_desc = num_tx_desc; 1740 kinfo->num_rx_desc = num_rx_desc; 1741 1742 kinfo->rx_buf_len = hdev->rx_buf_len; 1743 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1744 1745 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1746 sizeof(struct hnae3_queue *), GFP_KERNEL); 1747 if (!kinfo->tqp) 1748 return -ENOMEM; 1749 1750 ret = hclge_assign_tqp(vport, num_tqps); 1751 if (ret) 1752 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1753 1754 return ret; 1755 } 1756 1757 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1758 struct hclge_vport *vport) 1759 { 1760 struct hnae3_handle *nic = &vport->nic; 1761 struct hnae3_knic_private_info *kinfo; 1762 u16 i; 1763 1764 kinfo = &nic->kinfo; 1765 for (i = 0; i < vport->alloc_tqps; i++) { 1766 struct hclge_comm_tqp *q = 1767 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1768 bool is_pf; 1769 int ret; 1770 1771 is_pf = !(vport->vport_id); 1772 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1773 i, is_pf); 1774 if (ret) 1775 return ret; 1776 } 1777 1778 return 0; 1779 } 1780 1781 static int hclge_map_tqp(struct hclge_dev *hdev) 1782 { 1783 struct hclge_vport *vport = hdev->vport; 1784 u16 i, num_vport; 1785 1786 num_vport = hdev->num_req_vfs + 1; 1787 for (i = 0; i < num_vport; i++) { 1788 int ret; 1789 1790 ret = hclge_map_tqp_to_vport(hdev, vport); 1791 if (ret) 1792 return ret; 1793 1794 vport++; 1795 } 1796 1797 return 0; 1798 } 1799 1800 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1801 { 1802 struct hnae3_handle *nic = &vport->nic; 1803 struct hclge_dev *hdev = vport->back; 1804 int ret; 1805 1806 nic->pdev = hdev->pdev; 1807 nic->ae_algo = &ae_algo; 1808 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1809 MAX_NUMNODES); 1810 nic->kinfo.io_base = hdev->hw.hw.io_base; 1811 1812 ret = hclge_knic_setup(vport, num_tqps, 1813 hdev->num_tx_desc, hdev->num_rx_desc); 1814 if (ret) 1815 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1816 1817 return ret; 1818 } 1819 1820 static int hclge_alloc_vport(struct hclge_dev *hdev) 1821 { 1822 struct pci_dev *pdev = hdev->pdev; 1823 struct hclge_vport *vport; 1824 u32 tqp_main_vport; 1825 u32 tqp_per_vport; 1826 int num_vport, i; 1827 int ret; 1828 1829 /* We need to alloc a vport for main NIC of PF */ 1830 num_vport = hdev->num_req_vfs + 1; 1831 1832 if (hdev->num_tqps < num_vport) { 1833 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1834 hdev->num_tqps, num_vport); 1835 return -EINVAL; 1836 } 1837 1838 /* Alloc the same number of TQPs for every vport */ 1839 tqp_per_vport = hdev->num_tqps / num_vport; 1840 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1841 1842 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1843 GFP_KERNEL); 1844 if (!vport) 1845 return -ENOMEM; 1846 1847 hdev->vport = vport; 1848 hdev->num_alloc_vport = num_vport; 1849 1850 if (IS_ENABLED(CONFIG_PCI_IOV)) 1851 hdev->num_alloc_vfs = hdev->num_req_vfs; 1852 1853 for (i = 0; i < num_vport; i++) { 1854 vport->back = hdev; 1855 vport->vport_id = i; 1856 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1857 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1858 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1859 vport->port_base_vlan_cfg.tbl_sta = true; 1860 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1861 vport->req_vlan_fltr_en = true; 1862 INIT_LIST_HEAD(&vport->vlan_list); 1863 INIT_LIST_HEAD(&vport->uc_mac_list); 1864 INIT_LIST_HEAD(&vport->mc_mac_list); 1865 spin_lock_init(&vport->mac_list_lock); 1866 1867 if (i == 0) 1868 ret = hclge_vport_setup(vport, tqp_main_vport); 1869 else 1870 ret = hclge_vport_setup(vport, tqp_per_vport); 1871 if (ret) { 1872 dev_err(&pdev->dev, 1873 "vport setup failed for vport %d, %d\n", 1874 i, ret); 1875 return ret; 1876 } 1877 1878 vport++; 1879 } 1880 1881 return 0; 1882 } 1883 1884 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1885 struct hclge_pkt_buf_alloc *buf_alloc) 1886 { 1887 /* TX buffer size is unit by 128 byte */ 1888 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1889 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1890 struct hclge_tx_buff_alloc_cmd *req; 1891 struct hclge_desc desc; 1892 int ret; 1893 u8 i; 1894 1895 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1896 1897 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1898 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1899 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1900 1901 req->tx_pkt_buff[i] = 1902 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1903 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1904 } 1905 1906 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1907 if (ret) 1908 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1909 ret); 1910 1911 return ret; 1912 } 1913 1914 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1915 struct hclge_pkt_buf_alloc *buf_alloc) 1916 { 1917 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1918 1919 if (ret) 1920 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1921 1922 return ret; 1923 } 1924 1925 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1926 { 1927 unsigned int i; 1928 u32 cnt = 0; 1929 1930 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1931 if (hdev->hw_tc_map & BIT(i)) 1932 cnt++; 1933 return cnt; 1934 } 1935 1936 /* Get the number of pfc enabled TCs, which have private buffer */ 1937 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1938 struct hclge_pkt_buf_alloc *buf_alloc) 1939 { 1940 struct hclge_priv_buf *priv; 1941 unsigned int i; 1942 int cnt = 0; 1943 1944 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1945 priv = &buf_alloc->priv_buf[i]; 1946 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1947 priv->enable) 1948 cnt++; 1949 } 1950 1951 return cnt; 1952 } 1953 1954 /* Get the number of pfc disabled TCs, which have private buffer */ 1955 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1956 struct hclge_pkt_buf_alloc *buf_alloc) 1957 { 1958 struct hclge_priv_buf *priv; 1959 unsigned int i; 1960 int cnt = 0; 1961 1962 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1963 priv = &buf_alloc->priv_buf[i]; 1964 if (hdev->hw_tc_map & BIT(i) && 1965 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1966 priv->enable) 1967 cnt++; 1968 } 1969 1970 return cnt; 1971 } 1972 1973 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1974 { 1975 struct hclge_priv_buf *priv; 1976 u32 rx_priv = 0; 1977 int i; 1978 1979 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1980 priv = &buf_alloc->priv_buf[i]; 1981 if (priv->enable) 1982 rx_priv += priv->buf_size; 1983 } 1984 return rx_priv; 1985 } 1986 1987 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1988 { 1989 u32 i, total_tx_size = 0; 1990 1991 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1992 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1993 1994 return total_tx_size; 1995 } 1996 1997 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1998 struct hclge_pkt_buf_alloc *buf_alloc, 1999 u32 rx_all) 2000 { 2001 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2002 u32 tc_num = hclge_get_tc_num(hdev); 2003 u32 shared_buf, aligned_mps; 2004 u32 rx_priv; 2005 int i; 2006 2007 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2008 2009 if (hnae3_dev_dcb_supported(hdev)) 2010 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2011 hdev->dv_buf_size; 2012 else 2013 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2014 + hdev->dv_buf_size; 2015 2016 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2017 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2018 HCLGE_BUF_SIZE_UNIT); 2019 2020 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2021 if (rx_all < rx_priv + shared_std) 2022 return false; 2023 2024 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2025 buf_alloc->s_buf.buf_size = shared_buf; 2026 if (hnae3_dev_dcb_supported(hdev)) { 2027 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2028 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2029 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2030 HCLGE_BUF_SIZE_UNIT); 2031 } else { 2032 buf_alloc->s_buf.self.high = aligned_mps + 2033 HCLGE_NON_DCB_ADDITIONAL_BUF; 2034 buf_alloc->s_buf.self.low = aligned_mps; 2035 } 2036 2037 if (hnae3_dev_dcb_supported(hdev)) { 2038 hi_thrd = shared_buf - hdev->dv_buf_size; 2039 2040 if (tc_num <= NEED_RESERVE_TC_NUM) 2041 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2042 / BUF_MAX_PERCENT; 2043 2044 if (tc_num) 2045 hi_thrd = hi_thrd / tc_num; 2046 2047 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2048 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2049 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2050 } else { 2051 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2052 lo_thrd = aligned_mps; 2053 } 2054 2055 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2056 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2057 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2058 } 2059 2060 return true; 2061 } 2062 2063 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2064 struct hclge_pkt_buf_alloc *buf_alloc) 2065 { 2066 u32 i, total_size; 2067 2068 total_size = hdev->pkt_buf_size; 2069 2070 /* alloc tx buffer for all enabled tc */ 2071 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2072 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2073 2074 if (hdev->hw_tc_map & BIT(i)) { 2075 if (total_size < hdev->tx_buf_size) 2076 return -ENOMEM; 2077 2078 priv->tx_buf_size = hdev->tx_buf_size; 2079 } else { 2080 priv->tx_buf_size = 0; 2081 } 2082 2083 total_size -= priv->tx_buf_size; 2084 } 2085 2086 return 0; 2087 } 2088 2089 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2090 struct hclge_pkt_buf_alloc *buf_alloc) 2091 { 2092 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2093 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2094 unsigned int i; 2095 2096 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2097 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2098 2099 priv->enable = 0; 2100 priv->wl.low = 0; 2101 priv->wl.high = 0; 2102 priv->buf_size = 0; 2103 2104 if (!(hdev->hw_tc_map & BIT(i))) 2105 continue; 2106 2107 priv->enable = 1; 2108 2109 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2110 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2111 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2112 HCLGE_BUF_SIZE_UNIT); 2113 } else { 2114 priv->wl.low = 0; 2115 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2116 aligned_mps; 2117 } 2118 2119 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2120 } 2121 2122 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2123 } 2124 2125 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2126 struct hclge_pkt_buf_alloc *buf_alloc) 2127 { 2128 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2129 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2130 int i; 2131 2132 /* let the last to be cleared first */ 2133 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2134 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2135 unsigned int mask = BIT((unsigned int)i); 2136 2137 if (hdev->hw_tc_map & mask && 2138 !(hdev->tm_info.hw_pfc_map & mask)) { 2139 /* Clear the no pfc TC private buffer */ 2140 priv->wl.low = 0; 2141 priv->wl.high = 0; 2142 priv->buf_size = 0; 2143 priv->enable = 0; 2144 no_pfc_priv_num--; 2145 } 2146 2147 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2148 no_pfc_priv_num == 0) 2149 break; 2150 } 2151 2152 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2153 } 2154 2155 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2156 struct hclge_pkt_buf_alloc *buf_alloc) 2157 { 2158 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2159 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2160 int i; 2161 2162 /* let the last to be cleared first */ 2163 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2164 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2165 unsigned int mask = BIT((unsigned int)i); 2166 2167 if (hdev->hw_tc_map & mask && 2168 hdev->tm_info.hw_pfc_map & mask) { 2169 /* Reduce the number of pfc TC with private buffer */ 2170 priv->wl.low = 0; 2171 priv->enable = 0; 2172 priv->wl.high = 0; 2173 priv->buf_size = 0; 2174 pfc_priv_num--; 2175 } 2176 2177 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2178 pfc_priv_num == 0) 2179 break; 2180 } 2181 2182 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2183 } 2184 2185 static bool hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2186 struct hclge_pkt_buf_alloc *buf_alloc) 2187 { 2188 #define COMPENSATE_BUFFER 0x3C00 2189 #define COMPENSATE_HALF_MPS_NUM 5 2190 #define PRIV_WL_GAP 0x1800 2191 2192 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2193 u32 tc_num = hclge_get_tc_num(hdev); 2194 u32 half_mps = hdev->mps >> 1; 2195 u32 min_rx_priv; 2196 unsigned int i; 2197 2198 if (tc_num) 2199 rx_priv = rx_priv / tc_num; 2200 2201 if (tc_num <= NEED_RESERVE_TC_NUM) 2202 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2203 2204 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2205 COMPENSATE_HALF_MPS_NUM * half_mps; 2206 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2207 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2208 if (rx_priv < min_rx_priv) 2209 return false; 2210 2211 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2212 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2213 2214 priv->enable = 0; 2215 priv->wl.low = 0; 2216 priv->wl.high = 0; 2217 priv->buf_size = 0; 2218 2219 if (!(hdev->hw_tc_map & BIT(i))) 2220 continue; 2221 2222 priv->enable = 1; 2223 priv->buf_size = rx_priv; 2224 priv->wl.high = rx_priv - hdev->dv_buf_size; 2225 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2226 } 2227 2228 buf_alloc->s_buf.buf_size = 0; 2229 2230 return true; 2231 } 2232 2233 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2234 * @hdev: pointer to struct hclge_dev 2235 * @buf_alloc: pointer to buffer calculation data 2236 * @return: 0: calculate successful, negative: fail 2237 */ 2238 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2239 struct hclge_pkt_buf_alloc *buf_alloc) 2240 { 2241 /* When DCB is not supported, rx private buffer is not allocated. */ 2242 if (!hnae3_dev_dcb_supported(hdev)) { 2243 u32 rx_all = hdev->pkt_buf_size; 2244 2245 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2246 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2247 return -ENOMEM; 2248 2249 return 0; 2250 } 2251 2252 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2253 return 0; 2254 2255 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2256 return 0; 2257 2258 /* try to decrease the buffer size */ 2259 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2260 return 0; 2261 2262 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2263 return 0; 2264 2265 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2266 return 0; 2267 2268 return -ENOMEM; 2269 } 2270 2271 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2272 struct hclge_pkt_buf_alloc *buf_alloc) 2273 { 2274 struct hclge_rx_priv_buff_cmd *req; 2275 struct hclge_desc desc; 2276 int ret; 2277 int i; 2278 2279 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2280 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2281 2282 /* Alloc private buffer TCs */ 2283 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2284 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2285 2286 req->buf_num[i] = 2287 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2288 req->buf_num[i] |= 2289 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2290 } 2291 2292 req->shared_buf = 2293 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2294 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2295 2296 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2297 if (ret) 2298 dev_err(&hdev->pdev->dev, 2299 "rx private buffer alloc cmd failed %d\n", ret); 2300 2301 return ret; 2302 } 2303 2304 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2305 struct hclge_pkt_buf_alloc *buf_alloc) 2306 { 2307 struct hclge_rx_priv_wl_buf *req; 2308 struct hclge_priv_buf *priv; 2309 struct hclge_desc desc[2]; 2310 int i, j; 2311 int ret; 2312 2313 for (i = 0; i < 2; i++) { 2314 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2315 false); 2316 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2317 2318 /* The first descriptor set the NEXT bit to 1 */ 2319 if (i == 0) 2320 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2321 else 2322 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2323 2324 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2325 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2326 2327 priv = &buf_alloc->priv_buf[idx]; 2328 req->tc_wl[j].high = 2329 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2330 req->tc_wl[j].high |= 2331 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2332 req->tc_wl[j].low = 2333 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2334 req->tc_wl[j].low |= 2335 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2336 } 2337 } 2338 2339 /* Send 2 descriptor at one time */ 2340 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2341 if (ret) 2342 dev_err(&hdev->pdev->dev, 2343 "rx private waterline config cmd failed %d\n", 2344 ret); 2345 return ret; 2346 } 2347 2348 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2349 struct hclge_pkt_buf_alloc *buf_alloc) 2350 { 2351 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2352 struct hclge_rx_com_thrd *req; 2353 struct hclge_desc desc[2]; 2354 struct hclge_tc_thrd *tc; 2355 int i, j; 2356 int ret; 2357 2358 for (i = 0; i < 2; i++) { 2359 hclge_cmd_setup_basic_desc(&desc[i], 2360 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2361 req = (struct hclge_rx_com_thrd *)desc[i].data; 2362 2363 /* The first descriptor set the NEXT bit to 1 */ 2364 if (i == 0) 2365 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2366 else 2367 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2368 2369 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2370 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2371 2372 req->com_thrd[j].high = 2373 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2374 req->com_thrd[j].high |= 2375 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2376 req->com_thrd[j].low = 2377 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2378 req->com_thrd[j].low |= 2379 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2380 } 2381 } 2382 2383 /* Send 2 descriptors at one time */ 2384 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2385 if (ret) 2386 dev_err(&hdev->pdev->dev, 2387 "common threshold config cmd failed %d\n", ret); 2388 return ret; 2389 } 2390 2391 static int hclge_common_wl_config(struct hclge_dev *hdev, 2392 struct hclge_pkt_buf_alloc *buf_alloc) 2393 { 2394 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2395 struct hclge_rx_com_wl *req; 2396 struct hclge_desc desc; 2397 int ret; 2398 2399 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2400 2401 req = (struct hclge_rx_com_wl *)desc.data; 2402 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2403 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2404 2405 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2406 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2407 2408 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2409 if (ret) 2410 dev_err(&hdev->pdev->dev, 2411 "common waterline config cmd failed %d\n", ret); 2412 2413 return ret; 2414 } 2415 2416 int hclge_buffer_alloc(struct hclge_dev *hdev) 2417 { 2418 struct hclge_pkt_buf_alloc *pkt_buf; 2419 int ret; 2420 2421 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2422 if (!pkt_buf) 2423 return -ENOMEM; 2424 2425 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2426 if (ret) { 2427 dev_err(&hdev->pdev->dev, 2428 "could not calc tx buffer size for all TCs %d\n", ret); 2429 goto out; 2430 } 2431 2432 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2433 if (ret) { 2434 dev_err(&hdev->pdev->dev, 2435 "could not alloc tx buffers %d\n", ret); 2436 goto out; 2437 } 2438 2439 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2440 if (ret) { 2441 dev_err(&hdev->pdev->dev, 2442 "could not calc rx priv buffer size for all TCs %d\n", 2443 ret); 2444 goto out; 2445 } 2446 2447 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2448 if (ret) { 2449 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2450 ret); 2451 goto out; 2452 } 2453 2454 if (hnae3_dev_dcb_supported(hdev)) { 2455 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2456 if (ret) { 2457 dev_err(&hdev->pdev->dev, 2458 "could not configure rx private waterline %d\n", 2459 ret); 2460 goto out; 2461 } 2462 2463 ret = hclge_common_thrd_config(hdev, pkt_buf); 2464 if (ret) { 2465 dev_err(&hdev->pdev->dev, 2466 "could not configure common threshold %d\n", 2467 ret); 2468 goto out; 2469 } 2470 } 2471 2472 ret = hclge_common_wl_config(hdev, pkt_buf); 2473 if (ret) 2474 dev_err(&hdev->pdev->dev, 2475 "could not configure common waterline %d\n", ret); 2476 2477 out: 2478 kfree(pkt_buf); 2479 return ret; 2480 } 2481 2482 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2483 { 2484 struct hnae3_handle *roce = &vport->roce; 2485 struct hnae3_handle *nic = &vport->nic; 2486 struct hclge_dev *hdev = vport->back; 2487 2488 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2489 2490 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2491 return -EINVAL; 2492 2493 roce->rinfo.base_vector = hdev->num_nic_msi; 2494 2495 roce->rinfo.netdev = nic->kinfo.netdev; 2496 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2497 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2498 2499 roce->pdev = nic->pdev; 2500 roce->ae_algo = nic->ae_algo; 2501 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2502 MAX_NUMNODES); 2503 2504 return 0; 2505 } 2506 2507 static int hclge_init_msi(struct hclge_dev *hdev) 2508 { 2509 struct pci_dev *pdev = hdev->pdev; 2510 int vectors; 2511 int i; 2512 2513 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2514 hdev->num_msi, 2515 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2516 if (vectors < 0) { 2517 dev_err(&pdev->dev, 2518 "failed(%d) to allocate MSI/MSI-X vectors\n", 2519 vectors); 2520 return vectors; 2521 } 2522 if (vectors < hdev->num_msi) 2523 dev_warn(&hdev->pdev->dev, 2524 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2525 hdev->num_msi, vectors); 2526 2527 hdev->num_msi = vectors; 2528 hdev->num_msi_left = vectors; 2529 2530 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2531 sizeof(u16), GFP_KERNEL); 2532 if (!hdev->vector_status) { 2533 pci_free_irq_vectors(pdev); 2534 return -ENOMEM; 2535 } 2536 2537 for (i = 0; i < hdev->num_msi; i++) 2538 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2539 2540 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2541 sizeof(int), GFP_KERNEL); 2542 if (!hdev->vector_irq) { 2543 pci_free_irq_vectors(pdev); 2544 return -ENOMEM; 2545 } 2546 2547 return 0; 2548 } 2549 2550 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2551 { 2552 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2553 duplex = HCLGE_MAC_FULL; 2554 2555 return duplex; 2556 } 2557 2558 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2559 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2560 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2561 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2562 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2563 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2564 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2565 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2566 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2567 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2568 }; 2569 2570 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2571 { 2572 u16 i; 2573 2574 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2575 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2576 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2577 return 0; 2578 } 2579 } 2580 2581 return -EINVAL; 2582 } 2583 2584 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2585 u8 duplex, u8 lane_num) 2586 { 2587 struct hclge_config_mac_speed_dup_cmd *req; 2588 struct hclge_desc desc; 2589 u32 speed_fw; 2590 int ret; 2591 2592 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2593 2594 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2595 2596 if (duplex) 2597 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2598 2599 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2600 if (ret) { 2601 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2602 return ret; 2603 } 2604 2605 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2606 speed_fw); 2607 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2608 1); 2609 req->lane_num = lane_num; 2610 2611 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2612 if (ret) { 2613 dev_err(&hdev->pdev->dev, 2614 "mac speed/duplex config cmd failed %d.\n", ret); 2615 return ret; 2616 } 2617 2618 return 0; 2619 } 2620 2621 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2622 { 2623 struct hclge_mac *mac = &hdev->hw.mac; 2624 int ret; 2625 2626 duplex = hclge_check_speed_dup(duplex, speed); 2627 if (!mac->support_autoneg && mac->speed == (u32)speed && 2628 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2629 return 0; 2630 2631 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2632 if (ret) 2633 return ret; 2634 2635 hdev->hw.mac.speed = speed; 2636 hdev->hw.mac.duplex = duplex; 2637 if (!lane_num) 2638 hdev->hw.mac.lane_num = lane_num; 2639 2640 return 0; 2641 } 2642 2643 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2644 u8 duplex, u8 lane_num) 2645 { 2646 struct hclge_vport *vport = hclge_get_vport(handle); 2647 struct hclge_dev *hdev = vport->back; 2648 int ret; 2649 2650 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2651 2652 if (ret) 2653 return ret; 2654 2655 hdev->hw.mac.req_speed = (u32)speed; 2656 hdev->hw.mac.req_duplex = duplex; 2657 2658 return 0; 2659 } 2660 2661 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2662 { 2663 struct hclge_config_auto_neg_cmd *req; 2664 struct hclge_desc desc; 2665 u32 flag = 0; 2666 int ret; 2667 2668 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2669 2670 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2671 if (enable) 2672 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2673 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2674 2675 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2676 if (ret) 2677 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2678 ret); 2679 2680 return ret; 2681 } 2682 2683 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2684 { 2685 struct hclge_vport *vport = hclge_get_vport(handle); 2686 struct hclge_dev *hdev = vport->back; 2687 2688 if (!hdev->hw.mac.support_autoneg) { 2689 if (enable) { 2690 dev_err(&hdev->pdev->dev, 2691 "autoneg is not supported by current port\n"); 2692 return -EOPNOTSUPP; 2693 } else { 2694 return 0; 2695 } 2696 } 2697 2698 return hclge_set_autoneg_en(hdev, enable); 2699 } 2700 2701 static int hclge_get_autoneg(struct hnae3_handle *handle) 2702 { 2703 struct hclge_vport *vport = hclge_get_vport(handle); 2704 struct hclge_dev *hdev = vport->back; 2705 struct phy_device *phydev = hdev->hw.mac.phydev; 2706 2707 if (phydev) 2708 return phydev->autoneg; 2709 2710 return hdev->hw.mac.autoneg; 2711 } 2712 2713 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2714 { 2715 struct hclge_vport *vport = hclge_get_vport(handle); 2716 struct hclge_dev *hdev = vport->back; 2717 int ret; 2718 2719 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2720 2721 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2722 if (ret) 2723 return ret; 2724 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2725 } 2726 2727 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2728 { 2729 struct hclge_vport *vport = hclge_get_vport(handle); 2730 struct hclge_dev *hdev = vport->back; 2731 2732 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2733 return hclge_set_autoneg_en(hdev, !halt); 2734 2735 return 0; 2736 } 2737 2738 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2739 struct hclge_desc *desc, u32 desc_len) 2740 { 2741 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2742 u32 desc_index = 0; 2743 u32 data_index = 0; 2744 u32 i; 2745 2746 for (i = 0; i < lane_size; i++) { 2747 if (data_index >= HCLGE_DESC_DATA_LEN) { 2748 desc_index++; 2749 data_index = 0; 2750 } 2751 2752 if (desc_index >= desc_len) 2753 return; 2754 2755 hdev->fec_stats.per_lanes[i] += 2756 le32_to_cpu(desc[desc_index].data[data_index]); 2757 data_index++; 2758 } 2759 } 2760 2761 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2762 struct hclge_desc *desc, u32 desc_len) 2763 { 2764 struct hclge_query_fec_stats_cmd *req; 2765 2766 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2767 2768 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2769 hdev->fec_stats.rs_corr_blocks += 2770 le32_to_cpu(req->rs_fec_corr_blocks); 2771 hdev->fec_stats.rs_uncorr_blocks += 2772 le32_to_cpu(req->rs_fec_uncorr_blocks); 2773 hdev->fec_stats.rs_error_blocks += 2774 le32_to_cpu(req->rs_fec_error_blocks); 2775 hdev->fec_stats.base_r_corr_blocks += 2776 le32_to_cpu(req->base_r_fec_corr_blocks); 2777 hdev->fec_stats.base_r_uncorr_blocks += 2778 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2779 2780 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2781 } 2782 2783 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2784 { 2785 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2786 int ret; 2787 u32 i; 2788 2789 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2790 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2791 true); 2792 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2793 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2794 } 2795 2796 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2797 if (ret) 2798 return ret; 2799 2800 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2801 2802 return 0; 2803 } 2804 2805 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2806 { 2807 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2808 int ret; 2809 2810 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2811 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2812 return; 2813 2814 ret = hclge_update_fec_stats_hw(hdev); 2815 if (ret) 2816 dev_err(&hdev->pdev->dev, 2817 "failed to update fec stats, ret = %d\n", ret); 2818 2819 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2820 } 2821 2822 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2823 struct ethtool_fec_stats *fec_stats) 2824 { 2825 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2826 fec_stats->uncorrectable_blocks.total = 2827 hdev->fec_stats.rs_uncorr_blocks; 2828 } 2829 2830 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2831 struct ethtool_fec_stats *fec_stats) 2832 { 2833 u32 i; 2834 2835 if (hdev->fec_stats.base_r_lane_num == 0 || 2836 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2837 dev_err(&hdev->pdev->dev, 2838 "fec stats lane number(%llu) is invalid\n", 2839 hdev->fec_stats.base_r_lane_num); 2840 return; 2841 } 2842 2843 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2844 fec_stats->corrected_blocks.lanes[i] = 2845 hdev->fec_stats.base_r_corr_per_lanes[i]; 2846 fec_stats->uncorrectable_blocks.lanes[i] = 2847 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2848 } 2849 } 2850 2851 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2852 struct ethtool_fec_stats *fec_stats) 2853 { 2854 u32 fec_mode = hdev->hw.mac.fec_mode; 2855 2856 switch (fec_mode) { 2857 case BIT(HNAE3_FEC_RS): 2858 case BIT(HNAE3_FEC_LLRS): 2859 hclge_get_fec_stats_total(hdev, fec_stats); 2860 break; 2861 case BIT(HNAE3_FEC_BASER): 2862 hclge_get_fec_stats_lanes(hdev, fec_stats); 2863 break; 2864 default: 2865 dev_err(&hdev->pdev->dev, 2866 "fec stats is not supported by current fec mode(0x%x)\n", 2867 fec_mode); 2868 break; 2869 } 2870 } 2871 2872 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2873 struct ethtool_fec_stats *fec_stats) 2874 { 2875 struct hclge_vport *vport = hclge_get_vport(handle); 2876 struct hclge_dev *hdev = vport->back; 2877 u32 fec_mode = hdev->hw.mac.fec_mode; 2878 2879 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2880 fec_mode == BIT(HNAE3_FEC_AUTO) || 2881 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2882 return; 2883 2884 hclge_update_fec_stats(hdev); 2885 2886 hclge_comm_get_fec_stats(hdev, fec_stats); 2887 } 2888 2889 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2890 { 2891 struct hclge_config_fec_cmd *req; 2892 struct hclge_desc desc; 2893 int ret; 2894 2895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2896 2897 req = (struct hclge_config_fec_cmd *)desc.data; 2898 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2899 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2900 if (fec_mode & BIT(HNAE3_FEC_RS)) 2901 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2902 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2903 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2904 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2905 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2906 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2907 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2908 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2909 2910 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2911 if (ret) 2912 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2913 2914 return ret; 2915 } 2916 2917 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2918 { 2919 struct hclge_vport *vport = hclge_get_vport(handle); 2920 struct hclge_dev *hdev = vport->back; 2921 struct hclge_mac *mac = &hdev->hw.mac; 2922 int ret; 2923 2924 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2925 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2926 return -EINVAL; 2927 } 2928 2929 ret = hclge_set_fec_hw(hdev, fec_mode); 2930 if (ret) 2931 return ret; 2932 2933 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2934 return 0; 2935 } 2936 2937 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2938 u8 *fec_mode) 2939 { 2940 struct hclge_vport *vport = hclge_get_vport(handle); 2941 struct hclge_dev *hdev = vport->back; 2942 struct hclge_mac *mac = &hdev->hw.mac; 2943 2944 if (fec_ability) 2945 *fec_ability = mac->fec_ability; 2946 if (fec_mode) 2947 *fec_mode = mac->fec_mode; 2948 } 2949 2950 static int hclge_mac_init(struct hclge_dev *hdev) 2951 { 2952 struct hclge_mac *mac = &hdev->hw.mac; 2953 int ret; 2954 2955 hdev->support_sfp_query = true; 2956 2957 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2958 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2959 2960 if (hdev->hw.mac.support_autoneg) { 2961 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2962 if (ret) 2963 return ret; 2964 } 2965 2966 if (!hdev->hw.mac.autoneg) { 2967 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed, 2968 hdev->hw.mac.req_duplex, 2969 hdev->hw.mac.lane_num); 2970 if (ret) 2971 return ret; 2972 } 2973 2974 mac->link = 0; 2975 2976 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2977 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2978 if (ret) 2979 return ret; 2980 } 2981 2982 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2983 if (ret) { 2984 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2985 return ret; 2986 } 2987 2988 ret = hclge_set_default_loopback(hdev); 2989 if (ret) 2990 return ret; 2991 2992 ret = hclge_buffer_alloc(hdev); 2993 if (ret) 2994 dev_err(&hdev->pdev->dev, 2995 "allocate buffer fail, ret=%d\n", ret); 2996 2997 return ret; 2998 } 2999 3000 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 3001 { 3002 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3003 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 3004 hdev->last_mbx_scheduled = jiffies; 3005 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3006 } 3007 } 3008 3009 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 3010 { 3011 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3012 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 3013 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 3014 hdev->last_rst_scheduled = jiffies; 3015 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3016 } 3017 } 3018 3019 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 3020 { 3021 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3022 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 3023 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3024 } 3025 3026 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 3027 { 3028 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3029 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 3030 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 3031 } 3032 3033 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 3034 { 3035 struct hclge_link_status_cmd *req; 3036 struct hclge_desc desc; 3037 int ret; 3038 3039 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 3040 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3041 if (ret) { 3042 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 3043 ret); 3044 return ret; 3045 } 3046 3047 req = (struct hclge_link_status_cmd *)desc.data; 3048 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3049 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3050 3051 return 0; 3052 } 3053 3054 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3055 { 3056 struct phy_device *phydev = hdev->hw.mac.phydev; 3057 3058 *link_status = HCLGE_LINK_STATUS_DOWN; 3059 3060 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3061 return 0; 3062 3063 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3064 return 0; 3065 3066 return hclge_get_mac_link_status(hdev, link_status); 3067 } 3068 3069 static void hclge_push_link_status(struct hclge_dev *hdev) 3070 { 3071 struct hclge_vport *vport; 3072 int ret; 3073 u16 i; 3074 3075 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3076 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3077 3078 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3079 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3080 continue; 3081 3082 ret = hclge_push_vf_link_status(vport); 3083 if (ret) { 3084 dev_err(&hdev->pdev->dev, 3085 "failed to push link status to vf%u, ret = %d\n", 3086 i, ret); 3087 } 3088 } 3089 } 3090 3091 static void hclge_update_link_status(struct hclge_dev *hdev) 3092 { 3093 struct hnae3_handle *handle = &hdev->vport[0].nic; 3094 struct hnae3_client *client = hdev->nic_client; 3095 int state; 3096 int ret; 3097 3098 if (!client) 3099 return; 3100 3101 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3102 return; 3103 3104 ret = hclge_get_mac_phy_link(hdev, &state); 3105 if (ret) { 3106 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3107 return; 3108 } 3109 3110 if (state != hdev->hw.mac.link) { 3111 hdev->hw.mac.link = state; 3112 if (state == HCLGE_LINK_STATUS_UP) 3113 hclge_update_port_info(hdev); 3114 3115 client->ops->link_status_change(handle, state); 3116 hclge_config_mac_tnl_int(hdev, state); 3117 3118 if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) { 3119 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3120 struct hnae3_client *rclient = hdev->roce_client; 3121 3122 if (rclient && rclient->ops->link_status_change) 3123 rclient->ops->link_status_change(rhandle, 3124 state); 3125 } 3126 3127 hclge_push_link_status(hdev); 3128 } 3129 3130 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3131 } 3132 3133 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3134 { 3135 u32 speed_ability; 3136 3137 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3138 return; 3139 3140 switch (mac->module_type) { 3141 case HNAE3_MODULE_TYPE_FIBRE_LR: 3142 hclge_convert_setting_lr(speed_ability, mac->advertising); 3143 break; 3144 case HNAE3_MODULE_TYPE_FIBRE_SR: 3145 case HNAE3_MODULE_TYPE_AOC: 3146 hclge_convert_setting_sr(speed_ability, mac->advertising); 3147 break; 3148 case HNAE3_MODULE_TYPE_CR: 3149 hclge_convert_setting_cr(speed_ability, mac->advertising); 3150 break; 3151 case HNAE3_MODULE_TYPE_KR: 3152 hclge_convert_setting_kr(speed_ability, mac->advertising); 3153 break; 3154 default: 3155 break; 3156 } 3157 } 3158 3159 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3160 { 3161 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3162 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3163 mac->advertising); 3164 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3165 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3166 mac->advertising); 3167 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3168 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3169 mac->advertising); 3170 else 3171 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3172 mac->advertising); 3173 } 3174 3175 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3176 { 3177 struct hclge_mac *mac = &hdev->hw.mac; 3178 bool rx_en, tx_en; 3179 3180 switch (hdev->fc_mode_last_time) { 3181 case HCLGE_FC_RX_PAUSE: 3182 rx_en = true; 3183 tx_en = false; 3184 break; 3185 case HCLGE_FC_TX_PAUSE: 3186 rx_en = false; 3187 tx_en = true; 3188 break; 3189 case HCLGE_FC_FULL: 3190 rx_en = true; 3191 tx_en = true; 3192 break; 3193 default: 3194 rx_en = false; 3195 tx_en = false; 3196 break; 3197 } 3198 3199 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3200 } 3201 3202 static void hclge_update_advertising(struct hclge_dev *hdev) 3203 { 3204 struct hclge_mac *mac = &hdev->hw.mac; 3205 3206 linkmode_zero(mac->advertising); 3207 hclge_update_speed_advertising(mac); 3208 hclge_update_fec_advertising(mac); 3209 hclge_update_pause_advertising(hdev); 3210 } 3211 3212 static void hclge_update_port_capability(struct hclge_dev *hdev, 3213 struct hclge_mac *mac) 3214 { 3215 if (hnae3_dev_fec_supported(hdev)) 3216 hclge_convert_setting_fec(mac); 3217 3218 /* firmware can not identify back plane type, the media type 3219 * read from configuration can help deal it 3220 */ 3221 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3222 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3223 mac->module_type = HNAE3_MODULE_TYPE_KR; 3224 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3225 mac->module_type = HNAE3_MODULE_TYPE_TP; 3226 3227 if (mac->support_autoneg) { 3228 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3229 linkmode_copy(mac->advertising, mac->supported); 3230 } else { 3231 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3232 mac->supported); 3233 hclge_update_advertising(hdev); 3234 } 3235 } 3236 3237 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3238 { 3239 struct hclge_sfp_info_cmd *resp; 3240 struct hclge_desc desc; 3241 int ret; 3242 3243 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3244 resp = (struct hclge_sfp_info_cmd *)desc.data; 3245 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3246 if (ret == -EOPNOTSUPP) { 3247 dev_warn(&hdev->pdev->dev, 3248 "IMP do not support get SFP speed %d\n", ret); 3249 return ret; 3250 } else if (ret) { 3251 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3252 return ret; 3253 } 3254 3255 *speed = le32_to_cpu(resp->speed); 3256 3257 return 0; 3258 } 3259 3260 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3261 { 3262 struct hclge_sfp_info_cmd *resp; 3263 struct hclge_desc desc; 3264 int ret; 3265 3266 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3267 resp = (struct hclge_sfp_info_cmd *)desc.data; 3268 3269 resp->query_type = QUERY_ACTIVE_SPEED; 3270 3271 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3272 if (ret == -EOPNOTSUPP) { 3273 dev_warn(&hdev->pdev->dev, 3274 "IMP does not support get SFP info %d\n", ret); 3275 return ret; 3276 } else if (ret) { 3277 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3278 return ret; 3279 } 3280 3281 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3282 * set to mac->speed. 3283 */ 3284 if (!le32_to_cpu(resp->speed)) 3285 return 0; 3286 3287 mac->speed = le32_to_cpu(resp->speed); 3288 /* if resp->speed_ability is 0, it means it's an old version 3289 * firmware, do not update these params 3290 */ 3291 if (resp->speed_ability) { 3292 mac->module_type = le32_to_cpu(resp->module_type); 3293 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3294 mac->autoneg = resp->autoneg; 3295 mac->support_autoneg = resp->autoneg_ability; 3296 mac->speed_type = QUERY_ACTIVE_SPEED; 3297 mac->lane_num = resp->lane_num; 3298 if (!resp->active_fec) 3299 mac->fec_mode = 0; 3300 else 3301 mac->fec_mode = BIT(resp->active_fec); 3302 mac->fec_ability = resp->fec_ability; 3303 } else { 3304 mac->speed_type = QUERY_SFP_SPEED; 3305 } 3306 3307 return 0; 3308 } 3309 3310 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3311 struct ethtool_link_ksettings *cmd) 3312 { 3313 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3314 struct hclge_vport *vport = hclge_get_vport(handle); 3315 struct hclge_phy_link_ksetting_0_cmd *req0; 3316 struct hclge_phy_link_ksetting_1_cmd *req1; 3317 u32 supported, advertising, lp_advertising; 3318 struct hclge_dev *hdev = vport->back; 3319 int ret; 3320 3321 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3322 true); 3323 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3324 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3325 true); 3326 3327 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3328 if (ret) { 3329 dev_err(&hdev->pdev->dev, 3330 "failed to get phy link ksetting, ret = %d.\n", ret); 3331 return ret; 3332 } 3333 3334 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3335 cmd->base.autoneg = req0->autoneg; 3336 cmd->base.speed = le32_to_cpu(req0->speed); 3337 cmd->base.duplex = req0->duplex; 3338 cmd->base.port = req0->port; 3339 cmd->base.transceiver = req0->transceiver; 3340 cmd->base.phy_address = req0->phy_address; 3341 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3342 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3343 supported = le32_to_cpu(req0->supported); 3344 advertising = le32_to_cpu(req0->advertising); 3345 lp_advertising = le32_to_cpu(req0->lp_advertising); 3346 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3347 supported); 3348 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3349 advertising); 3350 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3351 lp_advertising); 3352 3353 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3354 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3355 cmd->base.master_slave_state = req1->master_slave_state; 3356 3357 return 0; 3358 } 3359 3360 static int 3361 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3362 const struct ethtool_link_ksettings *cmd) 3363 { 3364 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3365 struct hclge_vport *vport = hclge_get_vport(handle); 3366 struct hclge_phy_link_ksetting_0_cmd *req0; 3367 struct hclge_phy_link_ksetting_1_cmd *req1; 3368 struct hclge_dev *hdev = vport->back; 3369 u32 advertising; 3370 int ret; 3371 3372 if (cmd->base.autoneg == AUTONEG_DISABLE && 3373 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3374 (cmd->base.duplex != DUPLEX_HALF && 3375 cmd->base.duplex != DUPLEX_FULL))) 3376 return -EINVAL; 3377 3378 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3379 false); 3380 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3381 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3382 false); 3383 3384 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3385 req0->autoneg = cmd->base.autoneg; 3386 req0->speed = cpu_to_le32(cmd->base.speed); 3387 req0->duplex = cmd->base.duplex; 3388 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3389 cmd->link_modes.advertising); 3390 req0->advertising = cpu_to_le32(advertising); 3391 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3392 3393 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3394 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3395 3396 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3397 if (ret) { 3398 dev_err(&hdev->pdev->dev, 3399 "failed to set phy link ksettings, ret = %d.\n", ret); 3400 return ret; 3401 } 3402 3403 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3404 hdev->hw.mac.req_speed = cmd->base.speed; 3405 hdev->hw.mac.req_duplex = cmd->base.duplex; 3406 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3407 3408 return 0; 3409 } 3410 3411 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3412 { 3413 struct ethtool_link_ksettings cmd; 3414 int ret; 3415 3416 if (!hnae3_dev_phy_imp_supported(hdev)) 3417 return 0; 3418 3419 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3420 if (ret) 3421 return ret; 3422 3423 hdev->hw.mac.autoneg = cmd.base.autoneg; 3424 hdev->hw.mac.speed = cmd.base.speed; 3425 hdev->hw.mac.duplex = cmd.base.duplex; 3426 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3427 3428 return 0; 3429 } 3430 3431 static int hclge_tp_port_init(struct hclge_dev *hdev) 3432 { 3433 struct ethtool_link_ksettings cmd; 3434 3435 if (!hnae3_dev_phy_imp_supported(hdev)) 3436 return 0; 3437 3438 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3439 cmd.base.speed = hdev->hw.mac.req_speed; 3440 cmd.base.duplex = hdev->hw.mac.req_duplex; 3441 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3442 3443 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3444 } 3445 3446 static int hclge_update_port_info(struct hclge_dev *hdev) 3447 { 3448 struct hclge_mac *mac = &hdev->hw.mac; 3449 u32 speed; 3450 int ret; 3451 3452 /* get the port info from SFP cmd if not copper port */ 3453 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3454 return hclge_update_tp_port_info(hdev); 3455 3456 /* if IMP does not support get SFP/qSFP info, return directly */ 3457 if (!hdev->support_sfp_query) 3458 return 0; 3459 3460 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3461 speed = mac->speed; 3462 ret = hclge_get_sfp_info(hdev, mac); 3463 } else { 3464 speed = HCLGE_MAC_SPEED_UNKNOWN; 3465 ret = hclge_get_sfp_speed(hdev, &speed); 3466 } 3467 3468 if (ret == -EOPNOTSUPP) { 3469 hdev->support_sfp_query = false; 3470 return ret; 3471 } else if (ret) { 3472 return ret; 3473 } 3474 3475 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3476 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3477 hclge_update_port_capability(hdev, mac); 3478 if (mac->speed != speed) 3479 (void)hclge_tm_port_shaper_cfg(hdev); 3480 return 0; 3481 } 3482 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3483 HCLGE_MAC_FULL, mac->lane_num); 3484 } else { 3485 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3486 return 0; /* do nothing if no SFP */ 3487 3488 /* must config full duplex for SFP */ 3489 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3490 } 3491 } 3492 3493 static int hclge_get_status(struct hnae3_handle *handle) 3494 { 3495 struct hclge_vport *vport = hclge_get_vport(handle); 3496 struct hclge_dev *hdev = vport->back; 3497 3498 hclge_update_link_status(hdev); 3499 3500 return hdev->hw.mac.link; 3501 } 3502 3503 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3504 { 3505 if (!pci_num_vf(hdev->pdev)) { 3506 dev_err(&hdev->pdev->dev, 3507 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3508 return NULL; 3509 } 3510 3511 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3512 dev_err(&hdev->pdev->dev, 3513 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3514 vf, pci_num_vf(hdev->pdev)); 3515 return NULL; 3516 } 3517 3518 /* VF start from 1 in vport */ 3519 vf += HCLGE_VF_VPORT_START_NUM; 3520 return &hdev->vport[vf]; 3521 } 3522 3523 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3524 struct ifla_vf_info *ivf) 3525 { 3526 struct hclge_vport *vport = hclge_get_vport(handle); 3527 struct hclge_dev *hdev = vport->back; 3528 3529 vport = hclge_get_vf_vport(hdev, vf); 3530 if (!vport) 3531 return -EINVAL; 3532 3533 ivf->vf = vf; 3534 ivf->linkstate = vport->vf_info.link_state; 3535 ivf->spoofchk = vport->vf_info.spoofchk; 3536 ivf->trusted = vport->vf_info.trusted; 3537 ivf->min_tx_rate = 0; 3538 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3539 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3540 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3541 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3542 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3543 3544 return 0; 3545 } 3546 3547 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3548 int link_state) 3549 { 3550 struct hclge_vport *vport = hclge_get_vport(handle); 3551 struct hclge_dev *hdev = vport->back; 3552 int link_state_old; 3553 int ret; 3554 3555 vport = hclge_get_vf_vport(hdev, vf); 3556 if (!vport) 3557 return -EINVAL; 3558 3559 link_state_old = vport->vf_info.link_state; 3560 vport->vf_info.link_state = link_state; 3561 3562 /* return success directly if the VF is unalive, VF will 3563 * query link state itself when it starts work. 3564 */ 3565 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3566 return 0; 3567 3568 ret = hclge_push_vf_link_status(vport); 3569 if (ret) { 3570 vport->vf_info.link_state = link_state_old; 3571 dev_err(&hdev->pdev->dev, 3572 "failed to push vf%d link status, ret = %d\n", vf, ret); 3573 } 3574 3575 return ret; 3576 } 3577 3578 static void hclge_set_reset_pending(struct hclge_dev *hdev, 3579 enum hnae3_reset_type reset_type) 3580 { 3581 /* When an incorrect reset type is executed, the get_reset_level 3582 * function generates the HNAE3_NONE_RESET flag. As a result, this 3583 * type do not need to pending. 3584 */ 3585 if (reset_type != HNAE3_NONE_RESET) 3586 set_bit(reset_type, &hdev->reset_pending); 3587 } 3588 3589 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3590 { 3591 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3592 3593 /* fetch the events from their corresponding regs */ 3594 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3595 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3596 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3597 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3598 3599 /* Assumption: If by any chance reset and mailbox events are reported 3600 * together then we will only process reset event in this go and will 3601 * defer the processing of the mailbox events. Since, we would have not 3602 * cleared RX CMDQ event this time we would receive again another 3603 * interrupt from H/W just for the mailbox. 3604 * 3605 * check for vector0 reset event sources 3606 */ 3607 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3608 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3609 hclge_set_reset_pending(hdev, HNAE3_IMP_RESET); 3610 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3611 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3612 hdev->rst_stats.imp_rst_cnt++; 3613 return HCLGE_VECTOR0_EVENT_RST; 3614 } 3615 3616 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3617 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3618 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3619 hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET); 3620 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3621 hdev->rst_stats.global_rst_cnt++; 3622 return HCLGE_VECTOR0_EVENT_RST; 3623 } 3624 3625 /* check for vector0 msix event and hardware error event source */ 3626 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3627 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3628 return HCLGE_VECTOR0_EVENT_ERR; 3629 3630 /* check for vector0 ptp event source */ 3631 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3632 *clearval = msix_src_reg; 3633 return HCLGE_VECTOR0_EVENT_PTP; 3634 } 3635 3636 /* check for vector0 mailbox(=CMDQ RX) event source */ 3637 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3638 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3639 *clearval = cmdq_src_reg; 3640 return HCLGE_VECTOR0_EVENT_MBX; 3641 } 3642 3643 /* print other vector0 event source */ 3644 dev_info(&hdev->pdev->dev, 3645 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3646 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3647 3648 return HCLGE_VECTOR0_EVENT_OTHER; 3649 } 3650 3651 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3652 u32 regclr) 3653 { 3654 #define HCLGE_IMP_RESET_DELAY 5 3655 3656 switch (event_type) { 3657 case HCLGE_VECTOR0_EVENT_PTP: 3658 case HCLGE_VECTOR0_EVENT_RST: 3659 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3660 mdelay(HCLGE_IMP_RESET_DELAY); 3661 3662 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3663 break; 3664 case HCLGE_VECTOR0_EVENT_MBX: 3665 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3666 break; 3667 default: 3668 break; 3669 } 3670 } 3671 3672 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3673 { 3674 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3675 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3676 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3677 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3678 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3679 } 3680 3681 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3682 { 3683 writel(enable ? 1 : 0, vector->addr); 3684 } 3685 3686 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3687 { 3688 struct hclge_dev *hdev = data; 3689 unsigned long flags; 3690 u32 clearval = 0; 3691 u32 event_cause; 3692 3693 hclge_enable_vector(&hdev->misc_vector, false); 3694 event_cause = hclge_check_event_cause(hdev, &clearval); 3695 3696 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3697 switch (event_cause) { 3698 case HCLGE_VECTOR0_EVENT_ERR: 3699 hclge_errhand_task_schedule(hdev); 3700 break; 3701 case HCLGE_VECTOR0_EVENT_RST: 3702 hclge_reset_task_schedule(hdev); 3703 break; 3704 case HCLGE_VECTOR0_EVENT_PTP: 3705 spin_lock_irqsave(&hdev->ptp->lock, flags); 3706 hclge_ptp_clean_tx_hwts(hdev); 3707 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3708 break; 3709 case HCLGE_VECTOR0_EVENT_MBX: 3710 /* If we are here then, 3711 * 1. Either we are not handling any mbx task and we are not 3712 * scheduled as well 3713 * OR 3714 * 2. We could be handling a mbx task but nothing more is 3715 * scheduled. 3716 * In both cases, we should schedule mbx task as there are more 3717 * mbx messages reported by this interrupt. 3718 */ 3719 hclge_mbx_task_schedule(hdev); 3720 break; 3721 default: 3722 dev_warn(&hdev->pdev->dev, 3723 "received unknown or unhandled event of vector0\n"); 3724 break; 3725 } 3726 3727 hclge_clear_event_cause(hdev, event_cause, clearval); 3728 3729 /* Enable interrupt if it is not caused by reset event or error event */ 3730 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3731 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3732 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3733 hclge_enable_vector(&hdev->misc_vector, true); 3734 3735 return IRQ_HANDLED; 3736 } 3737 3738 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3739 { 3740 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3741 dev_warn(&hdev->pdev->dev, 3742 "vector(vector_id %d) has been freed.\n", vector_id); 3743 return; 3744 } 3745 3746 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3747 hdev->num_msi_left += 1; 3748 hdev->num_msi_used -= 1; 3749 } 3750 3751 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3752 { 3753 struct hclge_misc_vector *vector = &hdev->misc_vector; 3754 3755 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3756 3757 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3758 hdev->vector_status[0] = 0; 3759 3760 hdev->num_msi_left -= 1; 3761 hdev->num_msi_used += 1; 3762 } 3763 3764 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3765 { 3766 int ret; 3767 3768 hclge_get_misc_vector(hdev); 3769 3770 /* this would be explicitly freed in the end */ 3771 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3772 HCLGE_NAME, pci_name(hdev->pdev)); 3773 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3774 IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev); 3775 if (ret) { 3776 hclge_free_vector(hdev, 0); 3777 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3778 hdev->misc_vector.vector_irq); 3779 } 3780 3781 return ret; 3782 } 3783 3784 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3785 { 3786 free_irq(hdev->misc_vector.vector_irq, hdev); 3787 hclge_free_vector(hdev, 0); 3788 } 3789 3790 int hclge_notify_client(struct hclge_dev *hdev, 3791 enum hnae3_reset_notify_type type) 3792 { 3793 struct hnae3_handle *handle = &hdev->vport[0].nic; 3794 struct hnae3_client *client = hdev->nic_client; 3795 int ret; 3796 3797 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3798 return 0; 3799 3800 if (!client->ops->reset_notify) 3801 return -EOPNOTSUPP; 3802 3803 ret = client->ops->reset_notify(handle, type); 3804 if (ret) 3805 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3806 type, ret); 3807 3808 return ret; 3809 } 3810 3811 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3812 enum hnae3_reset_notify_type type) 3813 { 3814 struct hnae3_handle *handle = &hdev->vport[0].roce; 3815 struct hnae3_client *client = hdev->roce_client; 3816 int ret; 3817 3818 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3819 return 0; 3820 3821 if (!client->ops->reset_notify) 3822 return -EOPNOTSUPP; 3823 3824 ret = client->ops->reset_notify(handle, type); 3825 if (ret) 3826 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3827 type, ret); 3828 3829 return ret; 3830 } 3831 3832 static int hclge_reset_wait(struct hclge_dev *hdev) 3833 { 3834 #define HCLGE_RESET_WATI_MS 100 3835 #define HCLGE_RESET_WAIT_CNT 350 3836 3837 u32 val, reg, reg_bit; 3838 u32 cnt = 0; 3839 3840 switch (hdev->reset_type) { 3841 case HNAE3_IMP_RESET: 3842 reg = HCLGE_GLOBAL_RESET_REG; 3843 reg_bit = HCLGE_IMP_RESET_BIT; 3844 break; 3845 case HNAE3_GLOBAL_RESET: 3846 reg = HCLGE_GLOBAL_RESET_REG; 3847 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3848 break; 3849 case HNAE3_FUNC_RESET: 3850 reg = HCLGE_FUN_RST_ING; 3851 reg_bit = HCLGE_FUN_RST_ING_B; 3852 break; 3853 default: 3854 dev_err(&hdev->pdev->dev, 3855 "Wait for unsupported reset type: %d\n", 3856 hdev->reset_type); 3857 return -EINVAL; 3858 } 3859 3860 val = hclge_read_dev(&hdev->hw, reg); 3861 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3862 msleep(HCLGE_RESET_WATI_MS); 3863 val = hclge_read_dev(&hdev->hw, reg); 3864 cnt++; 3865 } 3866 3867 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3868 dev_warn(&hdev->pdev->dev, 3869 "Wait for reset timeout: %d\n", hdev->reset_type); 3870 return -EBUSY; 3871 } 3872 3873 return 0; 3874 } 3875 3876 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3877 { 3878 struct hclge_vf_rst_cmd *req; 3879 struct hclge_desc desc; 3880 3881 req = (struct hclge_vf_rst_cmd *)desc.data; 3882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3883 req->dest_vfid = func_id; 3884 3885 if (reset) 3886 req->vf_rst = 0x1; 3887 3888 return hclge_cmd_send(&hdev->hw, &desc, 1); 3889 } 3890 3891 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3892 { 3893 int i; 3894 3895 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3896 struct hclge_vport *vport = &hdev->vport[i]; 3897 int ret; 3898 3899 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3900 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3901 if (ret) { 3902 dev_err(&hdev->pdev->dev, 3903 "set vf(%u) rst failed %d!\n", 3904 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3905 ret); 3906 return ret; 3907 } 3908 3909 if (!reset || 3910 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3911 continue; 3912 3913 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3914 hdev->reset_type == HNAE3_FUNC_RESET) { 3915 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3916 &vport->need_notify); 3917 continue; 3918 } 3919 3920 /* Inform VF to process the reset. 3921 * hclge_inform_reset_assert_to_vf may fail if VF 3922 * driver is not loaded. 3923 */ 3924 ret = hclge_inform_reset_assert_to_vf(vport); 3925 if (ret) 3926 dev_warn(&hdev->pdev->dev, 3927 "inform reset to vf(%u) failed %d!\n", 3928 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3929 ret); 3930 } 3931 3932 return 0; 3933 } 3934 3935 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3936 { 3937 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3938 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3939 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3940 return; 3941 3942 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3943 HCLGE_MBX_SCHED_TIMEOUT)) 3944 dev_warn(&hdev->pdev->dev, 3945 "mbx service task is scheduled after %ums on cpu%u!\n", 3946 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3947 smp_processor_id()); 3948 3949 hclge_mbx_handler(hdev); 3950 3951 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3952 } 3953 3954 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3955 { 3956 struct hclge_pf_rst_sync_cmd *req; 3957 struct hclge_desc desc; 3958 int cnt = 0; 3959 int ret; 3960 3961 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3962 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3963 3964 do { 3965 /* vf need to down netdev by mbx during PF or FLR reset */ 3966 hclge_mailbox_service_task(hdev); 3967 3968 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3969 /* for compatible with old firmware, wait 3970 * 100 ms for VF to stop IO 3971 */ 3972 if (ret == -EOPNOTSUPP) { 3973 msleep(HCLGE_RESET_SYNC_TIME); 3974 return; 3975 } else if (ret) { 3976 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3977 ret); 3978 return; 3979 } else if (req->all_vf_ready) { 3980 return; 3981 } 3982 msleep(HCLGE_PF_RESET_SYNC_TIME); 3983 hclge_comm_cmd_reuse_desc(&desc, true); 3984 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3985 3986 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3987 } 3988 3989 void hclge_report_hw_error(struct hclge_dev *hdev, 3990 enum hnae3_hw_error_type type) 3991 { 3992 struct hnae3_client *client = hdev->nic_client; 3993 3994 if (!client || !client->ops->process_hw_error || 3995 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3996 return; 3997 3998 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3999 } 4000 4001 static void hclge_handle_imp_error(struct hclge_dev *hdev) 4002 { 4003 u32 reg_val; 4004 4005 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4006 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 4007 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 4008 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 4009 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4010 } 4011 4012 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 4013 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 4014 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4015 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4016 } 4017 } 4018 4019 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4020 { 4021 struct hclge_desc desc; 4022 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4023 int ret; 4024 4025 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4026 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4027 req->fun_reset_vfid = func_id; 4028 4029 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4030 if (ret) 4031 dev_err(&hdev->pdev->dev, 4032 "send function reset cmd fail, status =%d\n", ret); 4033 4034 return ret; 4035 } 4036 4037 static void hclge_do_reset(struct hclge_dev *hdev) 4038 { 4039 struct hnae3_handle *handle = &hdev->vport[0].nic; 4040 struct pci_dev *pdev = hdev->pdev; 4041 u32 val; 4042 4043 if (hclge_get_hw_reset_stat(handle)) { 4044 dev_info(&pdev->dev, "hardware reset not finish\n"); 4045 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4046 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4047 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4048 return; 4049 } 4050 4051 switch (hdev->reset_type) { 4052 case HNAE3_IMP_RESET: 4053 dev_info(&pdev->dev, "IMP reset requested\n"); 4054 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4055 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4056 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4057 break; 4058 case HNAE3_GLOBAL_RESET: 4059 dev_info(&pdev->dev, "global reset requested\n"); 4060 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4061 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4062 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4063 break; 4064 case HNAE3_FUNC_RESET: 4065 dev_info(&pdev->dev, "PF reset requested\n"); 4066 /* schedule again to check later */ 4067 hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET); 4068 hclge_reset_task_schedule(hdev); 4069 break; 4070 default: 4071 dev_warn(&pdev->dev, 4072 "unsupported reset type: %d\n", hdev->reset_type); 4073 break; 4074 } 4075 } 4076 4077 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4078 unsigned long *addr) 4079 { 4080 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4081 struct hclge_dev *hdev = ae_dev->priv; 4082 4083 /* return the highest priority reset level amongst all */ 4084 if (test_bit(HNAE3_IMP_RESET, addr)) { 4085 rst_level = HNAE3_IMP_RESET; 4086 clear_bit(HNAE3_IMP_RESET, addr); 4087 clear_bit(HNAE3_GLOBAL_RESET, addr); 4088 clear_bit(HNAE3_FUNC_RESET, addr); 4089 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4090 rst_level = HNAE3_GLOBAL_RESET; 4091 clear_bit(HNAE3_GLOBAL_RESET, addr); 4092 clear_bit(HNAE3_FUNC_RESET, addr); 4093 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4094 rst_level = HNAE3_FUNC_RESET; 4095 clear_bit(HNAE3_FUNC_RESET, addr); 4096 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4097 rst_level = HNAE3_FLR_RESET; 4098 clear_bit(HNAE3_FLR_RESET, addr); 4099 } 4100 4101 clear_bit(HNAE3_NONE_RESET, addr); 4102 4103 if (hdev->reset_type != HNAE3_NONE_RESET && 4104 rst_level < hdev->reset_type) 4105 return HNAE3_NONE_RESET; 4106 4107 return rst_level; 4108 } 4109 4110 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4111 { 4112 u32 clearval = 0; 4113 4114 switch (hdev->reset_type) { 4115 case HNAE3_IMP_RESET: 4116 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4117 break; 4118 case HNAE3_GLOBAL_RESET: 4119 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4120 break; 4121 default: 4122 break; 4123 } 4124 4125 if (!clearval) 4126 return; 4127 4128 /* For revision 0x20, the reset interrupt source 4129 * can only be cleared after hardware reset done 4130 */ 4131 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4132 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4133 clearval); 4134 4135 hclge_enable_vector(&hdev->misc_vector, true); 4136 } 4137 4138 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4139 { 4140 u32 reg_val; 4141 4142 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4143 if (enable) 4144 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4145 else 4146 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4147 4148 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4149 } 4150 4151 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4152 { 4153 int ret; 4154 4155 ret = hclge_set_all_vf_rst(hdev, true); 4156 if (ret) 4157 return ret; 4158 4159 hclge_func_reset_sync_vf(hdev); 4160 4161 return 0; 4162 } 4163 4164 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4165 { 4166 u32 reg_val; 4167 int ret = 0; 4168 4169 switch (hdev->reset_type) { 4170 case HNAE3_FUNC_RESET: 4171 ret = hclge_func_reset_notify_vf(hdev); 4172 if (ret) 4173 return ret; 4174 4175 ret = hclge_func_reset_cmd(hdev, 0); 4176 if (ret) { 4177 dev_err(&hdev->pdev->dev, 4178 "asserting function reset fail %d!\n", ret); 4179 return ret; 4180 } 4181 4182 /* After performaning pf reset, it is not necessary to do the 4183 * mailbox handling or send any command to firmware, because 4184 * any mailbox handling or command to firmware is only valid 4185 * after hclge_comm_cmd_init is called. 4186 */ 4187 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4188 hdev->rst_stats.pf_rst_cnt++; 4189 break; 4190 case HNAE3_FLR_RESET: 4191 ret = hclge_func_reset_notify_vf(hdev); 4192 if (ret) 4193 return ret; 4194 break; 4195 case HNAE3_IMP_RESET: 4196 hclge_handle_imp_error(hdev); 4197 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4198 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4199 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4200 break; 4201 default: 4202 break; 4203 } 4204 4205 /* inform hardware that preparatory work is done */ 4206 msleep(HCLGE_RESET_SYNC_TIME); 4207 hclge_reset_handshake(hdev, true); 4208 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4209 4210 return ret; 4211 } 4212 4213 static void hclge_show_rst_info(struct hclge_dev *hdev) 4214 { 4215 char *buf; 4216 4217 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4218 if (!buf) 4219 return; 4220 4221 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4222 4223 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4224 4225 kfree(buf); 4226 } 4227 4228 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4229 { 4230 #define MAX_RESET_FAIL_CNT 5 4231 4232 if (hdev->reset_pending) { 4233 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4234 hdev->reset_pending); 4235 return true; 4236 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4237 HCLGE_RESET_INT_M) { 4238 dev_info(&hdev->pdev->dev, 4239 "reset failed because new reset interrupt\n"); 4240 hclge_clear_reset_cause(hdev); 4241 return false; 4242 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4243 hdev->rst_stats.reset_fail_cnt++; 4244 hclge_set_reset_pending(hdev, hdev->reset_type); 4245 dev_info(&hdev->pdev->dev, 4246 "re-schedule reset task(%u)\n", 4247 hdev->rst_stats.reset_fail_cnt); 4248 return true; 4249 } 4250 4251 hclge_clear_reset_cause(hdev); 4252 4253 /* recover the handshake status when reset fail */ 4254 hclge_reset_handshake(hdev, true); 4255 4256 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4257 4258 hclge_show_rst_info(hdev); 4259 4260 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4261 4262 return false; 4263 } 4264 4265 static void hclge_update_reset_level(struct hclge_dev *hdev) 4266 { 4267 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4268 enum hnae3_reset_type reset_level; 4269 4270 /* reset request will not be set during reset, so clear 4271 * pending reset request to avoid unnecessary reset 4272 * caused by the same reason. 4273 */ 4274 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4275 4276 /* if default_reset_request has a higher level reset request, 4277 * it should be handled as soon as possible. since some errors 4278 * need this kind of reset to fix. 4279 */ 4280 reset_level = hclge_get_reset_level(ae_dev, 4281 &hdev->default_reset_request); 4282 if (reset_level != HNAE3_NONE_RESET) 4283 set_bit(reset_level, &hdev->reset_request); 4284 } 4285 4286 static int hclge_set_rst_done(struct hclge_dev *hdev) 4287 { 4288 struct hclge_pf_rst_done_cmd *req; 4289 struct hclge_desc desc; 4290 int ret; 4291 4292 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4293 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4294 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4295 4296 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4297 /* To be compatible with the old firmware, which does not support 4298 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4299 * return success 4300 */ 4301 if (ret == -EOPNOTSUPP) { 4302 dev_warn(&hdev->pdev->dev, 4303 "current firmware does not support command(0x%x)!\n", 4304 HCLGE_OPC_PF_RST_DONE); 4305 return 0; 4306 } else if (ret) { 4307 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4308 ret); 4309 } 4310 4311 return ret; 4312 } 4313 4314 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4315 { 4316 int ret = 0; 4317 4318 switch (hdev->reset_type) { 4319 case HNAE3_FUNC_RESET: 4320 case HNAE3_FLR_RESET: 4321 ret = hclge_set_all_vf_rst(hdev, false); 4322 break; 4323 case HNAE3_GLOBAL_RESET: 4324 case HNAE3_IMP_RESET: 4325 ret = hclge_set_rst_done(hdev); 4326 break; 4327 default: 4328 break; 4329 } 4330 4331 /* clear up the handshake status after re-initialize done */ 4332 hclge_reset_handshake(hdev, false); 4333 4334 return ret; 4335 } 4336 4337 static int hclge_reset_stack(struct hclge_dev *hdev) 4338 { 4339 int ret; 4340 4341 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4342 if (ret) 4343 return ret; 4344 4345 ret = hclge_reset_ae_dev(hdev->ae_dev); 4346 if (ret) 4347 return ret; 4348 4349 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4350 } 4351 4352 static int hclge_reset_prepare(struct hclge_dev *hdev) 4353 { 4354 int ret; 4355 4356 hdev->rst_stats.reset_cnt++; 4357 /* perform reset of the stack & ae device for a client */ 4358 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4359 if (ret) 4360 return ret; 4361 4362 rtnl_lock(); 4363 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4364 rtnl_unlock(); 4365 if (ret) 4366 return ret; 4367 4368 return hclge_reset_prepare_wait(hdev); 4369 } 4370 4371 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4372 { 4373 int ret; 4374 4375 hdev->rst_stats.hw_reset_done_cnt++; 4376 4377 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4378 if (ret) 4379 return ret; 4380 4381 rtnl_lock(); 4382 ret = hclge_reset_stack(hdev); 4383 rtnl_unlock(); 4384 if (ret) 4385 return ret; 4386 4387 hclge_clear_reset_cause(hdev); 4388 4389 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4390 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4391 * times 4392 */ 4393 if (ret && 4394 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4395 return ret; 4396 4397 ret = hclge_reset_prepare_up(hdev); 4398 if (ret) 4399 return ret; 4400 4401 rtnl_lock(); 4402 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4403 rtnl_unlock(); 4404 if (ret) 4405 return ret; 4406 4407 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4408 if (ret) 4409 return ret; 4410 4411 hdev->last_reset_time = jiffies; 4412 hdev->rst_stats.reset_fail_cnt = 0; 4413 hdev->rst_stats.reset_done_cnt++; 4414 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4415 4416 hclge_update_reset_level(hdev); 4417 4418 return 0; 4419 } 4420 4421 static void hclge_reset(struct hclge_dev *hdev) 4422 { 4423 if (hclge_reset_prepare(hdev)) 4424 goto err_reset; 4425 4426 if (hclge_reset_wait(hdev)) 4427 goto err_reset; 4428 4429 if (hclge_reset_rebuild(hdev)) 4430 goto err_reset; 4431 4432 return; 4433 4434 err_reset: 4435 if (hclge_reset_err_handle(hdev)) 4436 hclge_reset_task_schedule(hdev); 4437 } 4438 4439 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4440 { 4441 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4442 struct hclge_dev *hdev = ae_dev->priv; 4443 4444 /* We might end up getting called broadly because of 2 below cases: 4445 * 1. Recoverable error was conveyed through APEI and only way to bring 4446 * normalcy is to reset. 4447 * 2. A new reset request from the stack due to timeout 4448 * 4449 * check if this is a new reset request and we are not here just because 4450 * last reset attempt did not succeed and watchdog hit us again. We will 4451 * know this if last reset request did not occur very recently (watchdog 4452 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4453 * In case of new request we reset the "reset level" to PF reset. 4454 * And if it is a repeat reset request of the most recent one then we 4455 * want to make sure we throttle the reset request. Therefore, we will 4456 * not allow it again before 3*HZ times. 4457 */ 4458 4459 if (time_before(jiffies, (hdev->last_reset_time + 4460 HCLGE_RESET_INTERVAL))) { 4461 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4462 return; 4463 } 4464 4465 if (hdev->default_reset_request) { 4466 hdev->reset_level = 4467 hclge_get_reset_level(ae_dev, 4468 &hdev->default_reset_request); 4469 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4470 hdev->reset_level = HNAE3_FUNC_RESET; 4471 } 4472 4473 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4474 hdev->reset_level); 4475 4476 /* request reset & schedule reset task */ 4477 set_bit(hdev->reset_level, &hdev->reset_request); 4478 hclge_reset_task_schedule(hdev); 4479 4480 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4481 hdev->reset_level++; 4482 } 4483 4484 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4485 enum hnae3_reset_type rst_type) 4486 { 4487 #define HCLGE_SUPPORT_RESET_TYPE \ 4488 (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \ 4489 BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET)) 4490 4491 struct hclge_dev *hdev = ae_dev->priv; 4492 4493 if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) { 4494 /* To prevent reset triggered by hclge_reset_event */ 4495 set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); 4496 dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n", 4497 rst_type); 4498 return; 4499 } 4500 4501 set_bit(rst_type, &hdev->default_reset_request); 4502 } 4503 4504 static void hclge_reset_timer(struct timer_list *t) 4505 { 4506 struct hclge_dev *hdev = timer_container_of(hdev, t, reset_timer); 4507 4508 /* if default_reset_request has no value, it means that this reset 4509 * request has already be handled, so just return here 4510 */ 4511 if (!hdev->default_reset_request) 4512 return; 4513 4514 dev_info(&hdev->pdev->dev, 4515 "triggering reset in reset timer\n"); 4516 hclge_reset_event(hdev->pdev, NULL); 4517 } 4518 4519 static void hclge_reset_subtask(struct hclge_dev *hdev) 4520 { 4521 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4522 4523 /* check if there is any ongoing reset in the hardware. This status can 4524 * be checked from reset_pending. If there is then, we need to wait for 4525 * hardware to complete reset. 4526 * a. If we are able to figure out in reasonable time that hardware 4527 * has fully resetted then, we can proceed with driver, client 4528 * reset. 4529 * b. else, we can come back later to check this status so re-sched 4530 * now. 4531 */ 4532 hdev->last_reset_time = jiffies; 4533 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4534 if (hdev->reset_type != HNAE3_NONE_RESET) 4535 hclge_reset(hdev); 4536 4537 /* check if we got any *new* reset requests to be honored */ 4538 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4539 if (hdev->reset_type != HNAE3_NONE_RESET) 4540 hclge_do_reset(hdev); 4541 4542 hdev->reset_type = HNAE3_NONE_RESET; 4543 } 4544 4545 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4546 { 4547 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4548 enum hnae3_reset_type reset_type; 4549 4550 if (ae_dev->hw_err_reset_req) { 4551 reset_type = hclge_get_reset_level(ae_dev, 4552 &ae_dev->hw_err_reset_req); 4553 hclge_set_def_reset_request(ae_dev, reset_type); 4554 } 4555 4556 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4557 ae_dev->ops->reset_event(hdev->pdev, NULL); 4558 4559 /* enable interrupt after error handling complete */ 4560 hclge_enable_vector(&hdev->misc_vector, true); 4561 } 4562 4563 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4564 { 4565 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4566 4567 ae_dev->hw_err_reset_req = 0; 4568 4569 if (hclge_find_error_source(hdev)) { 4570 hclge_handle_error_info_log(ae_dev); 4571 hclge_handle_mac_tnl(hdev); 4572 hclge_handle_vf_queue_err_ras(hdev); 4573 } 4574 4575 hclge_handle_err_reset_request(hdev); 4576 } 4577 4578 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4579 { 4580 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4581 struct device *dev = &hdev->pdev->dev; 4582 u32 msix_sts_reg; 4583 4584 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4585 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4586 if (hclge_handle_hw_msix_error 4587 (hdev, &hdev->default_reset_request)) 4588 dev_info(dev, "received msix interrupt 0x%x\n", 4589 msix_sts_reg); 4590 } 4591 4592 hclge_handle_hw_ras_error(ae_dev); 4593 4594 hclge_handle_err_reset_request(hdev); 4595 } 4596 4597 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4598 { 4599 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4600 return; 4601 4602 if (hnae3_dev_ras_imp_supported(hdev)) 4603 hclge_handle_err_recovery(hdev); 4604 else 4605 hclge_misc_err_recovery(hdev); 4606 } 4607 4608 static void hclge_reset_service_task(struct hclge_dev *hdev) 4609 { 4610 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4611 return; 4612 4613 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4614 HCLGE_RESET_SCHED_TIMEOUT)) 4615 dev_warn(&hdev->pdev->dev, 4616 "reset service task is scheduled after %ums on cpu%u!\n", 4617 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4618 smp_processor_id()); 4619 4620 down(&hdev->reset_sem); 4621 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4622 4623 hclge_reset_subtask(hdev); 4624 4625 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4626 up(&hdev->reset_sem); 4627 } 4628 4629 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4630 { 4631 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4632 4633 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4634 int i; 4635 4636 /* start from vport 1 for PF is always alive */ 4637 for (i = 1; i < hdev->num_alloc_vport; i++) { 4638 struct hclge_vport *vport = &hdev->vport[i]; 4639 4640 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4641 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4642 continue; 4643 if (time_after(jiffies, vport->last_active_jiffies + 4644 alive_time)) { 4645 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4646 dev_warn(&hdev->pdev->dev, 4647 "VF %u heartbeat timeout\n", 4648 i - HCLGE_VF_VPORT_START_NUM); 4649 } 4650 } 4651 } 4652 4653 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4654 { 4655 unsigned long delta = round_jiffies_relative(HZ); 4656 4657 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4658 return; 4659 4660 /* Always handle the link updating to make sure link state is 4661 * updated when it is triggered by mbx. 4662 */ 4663 hclge_update_link_status(hdev); 4664 hclge_sync_mac_table(hdev); 4665 hclge_sync_promisc_mode(hdev); 4666 hclge_sync_fd_table(hdev); 4667 4668 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4669 delta = jiffies - hdev->last_serv_processed; 4670 4671 if (delta < round_jiffies_relative(HZ)) { 4672 delta = round_jiffies_relative(HZ) - delta; 4673 goto out; 4674 } 4675 } 4676 4677 hdev->serv_processed_cnt++; 4678 hclge_update_vport_alive(hdev); 4679 4680 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4681 hdev->last_serv_processed = jiffies; 4682 goto out; 4683 } 4684 4685 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4686 hclge_update_stats_for_all(hdev); 4687 4688 hclge_update_port_info(hdev); 4689 hclge_sync_vlan_filter(hdev); 4690 4691 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4692 hclge_rfs_filter_expire(hdev); 4693 4694 hdev->last_serv_processed = jiffies; 4695 4696 out: 4697 hclge_task_schedule(hdev, delta); 4698 } 4699 4700 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4701 { 4702 unsigned long flags; 4703 4704 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4705 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4706 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4707 return; 4708 4709 /* to prevent concurrence with the irq handler */ 4710 spin_lock_irqsave(&hdev->ptp->lock, flags); 4711 4712 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4713 * handler may handle it just before spin_lock_irqsave(). 4714 */ 4715 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4716 hclge_ptp_clean_tx_hwts(hdev); 4717 4718 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4719 } 4720 4721 static void hclge_service_task(struct work_struct *work) 4722 { 4723 struct hclge_dev *hdev = 4724 container_of(work, struct hclge_dev, service_task.work); 4725 4726 hclge_errhand_service_task(hdev); 4727 hclge_reset_service_task(hdev); 4728 hclge_ptp_service_task(hdev); 4729 hclge_mailbox_service_task(hdev); 4730 hclge_periodic_service_task(hdev); 4731 4732 /* Handle error recovery, reset and mbx again in case periodical task 4733 * delays the handling by calling hclge_task_schedule() in 4734 * hclge_periodic_service_task(). 4735 */ 4736 hclge_errhand_service_task(hdev); 4737 hclge_reset_service_task(hdev); 4738 hclge_mailbox_service_task(hdev); 4739 } 4740 4741 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4742 { 4743 /* VF handle has no client */ 4744 if (!handle->client) 4745 return container_of(handle, struct hclge_vport, nic); 4746 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4747 return container_of(handle, struct hclge_vport, roce); 4748 else 4749 return container_of(handle, struct hclge_vport, nic); 4750 } 4751 4752 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4753 struct hnae3_vector_info *vector_info) 4754 { 4755 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4756 4757 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4758 4759 /* need an extend offset to config vector >= 64 */ 4760 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4761 vector_info->io_addr = hdev->hw.hw.io_base + 4762 HCLGE_VECTOR_REG_BASE + 4763 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4764 else 4765 vector_info->io_addr = hdev->hw.hw.io_base + 4766 HCLGE_VECTOR_EXT_REG_BASE + 4767 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4768 HCLGE_VECTOR_REG_OFFSET_H + 4769 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4770 HCLGE_VECTOR_REG_OFFSET; 4771 4772 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4773 hdev->vector_irq[idx] = vector_info->vector; 4774 } 4775 4776 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4777 struct hnae3_vector_info *vector_info) 4778 { 4779 struct hclge_vport *vport = hclge_get_vport(handle); 4780 struct hnae3_vector_info *vector = vector_info; 4781 struct hclge_dev *hdev = vport->back; 4782 int alloc = 0; 4783 u16 i = 0; 4784 u16 j; 4785 4786 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4787 vector_num = min(hdev->num_msi_left, vector_num); 4788 4789 for (j = 0; j < vector_num; j++) { 4790 while (++i < hdev->num_nic_msi) { 4791 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4792 hclge_get_vector_info(hdev, i, vector); 4793 vector++; 4794 alloc++; 4795 4796 break; 4797 } 4798 } 4799 } 4800 hdev->num_msi_left -= alloc; 4801 hdev->num_msi_used += alloc; 4802 4803 return alloc; 4804 } 4805 4806 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4807 { 4808 int i; 4809 4810 for (i = 0; i < hdev->num_msi; i++) 4811 if (vector == hdev->vector_irq[i]) 4812 return i; 4813 4814 return -EINVAL; 4815 } 4816 4817 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4818 { 4819 struct hclge_vport *vport = hclge_get_vport(handle); 4820 struct hclge_dev *hdev = vport->back; 4821 int vector_id; 4822 4823 vector_id = hclge_get_vector_index(hdev, vector); 4824 if (vector_id < 0) { 4825 dev_err(&hdev->pdev->dev, 4826 "Get vector index fail. vector = %d\n", vector); 4827 return vector_id; 4828 } 4829 4830 hclge_free_vector(hdev, vector_id); 4831 4832 return 0; 4833 } 4834 4835 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4836 u8 *key, u8 *hfunc) 4837 { 4838 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4839 struct hclge_vport *vport = hclge_get_vport(handle); 4840 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4841 4842 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4843 4844 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4845 ae_dev->dev_specs.rss_ind_tbl_size); 4846 4847 return 0; 4848 } 4849 4850 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4851 const u8 *key, const u8 hfunc) 4852 { 4853 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4854 struct hclge_vport *vport = hclge_get_vport(handle); 4855 struct hclge_dev *hdev = vport->back; 4856 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4857 int ret, i; 4858 4859 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4860 if (ret) { 4861 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4862 return ret; 4863 } 4864 4865 /* Update the shadow RSS table with user specified qids */ 4866 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4867 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4868 4869 /* Update the hardware */ 4870 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4871 rss_cfg->rss_indirection_tbl); 4872 } 4873 4874 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4875 const struct ethtool_rxfh_fields *nfc) 4876 { 4877 struct hclge_vport *vport = hclge_get_vport(handle); 4878 struct hclge_dev *hdev = vport->back; 4879 int ret; 4880 4881 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4882 &hdev->rss_cfg, nfc); 4883 if (ret) { 4884 dev_err(&hdev->pdev->dev, 4885 "failed to set rss tuple, ret = %d.\n", ret); 4886 return ret; 4887 } 4888 4889 return 0; 4890 } 4891 4892 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4893 struct ethtool_rxfh_fields *nfc) 4894 { 4895 struct hclge_vport *vport = hclge_get_vport(handle); 4896 u8 tuple_sets; 4897 int ret; 4898 4899 nfc->data = 0; 4900 4901 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4902 &tuple_sets); 4903 if (ret || !tuple_sets) 4904 return ret; 4905 4906 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4907 4908 return 0; 4909 } 4910 4911 static int hclge_get_tc_size(struct hnae3_handle *handle) 4912 { 4913 struct hclge_vport *vport = hclge_get_vport(handle); 4914 struct hclge_dev *hdev = vport->back; 4915 4916 return hdev->pf_rss_size_max; 4917 } 4918 4919 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4920 { 4921 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4922 struct hclge_vport *vport = hdev->vport; 4923 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4924 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4925 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4926 struct hnae3_tc_info *tc_info; 4927 u16 roundup_size; 4928 u16 rss_size; 4929 int i; 4930 4931 tc_info = &vport->nic.kinfo.tc_info; 4932 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4933 rss_size = tc_info->tqp_count[i]; 4934 tc_valid[i] = 0; 4935 4936 if (!(hdev->hw_tc_map & BIT(i))) 4937 continue; 4938 4939 /* tc_size set to hardware is the log2 of roundup power of two 4940 * of rss_size, the acutal queue size is limited by indirection 4941 * table. 4942 */ 4943 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4944 rss_size == 0) { 4945 dev_err(&hdev->pdev->dev, 4946 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4947 rss_size); 4948 return -EINVAL; 4949 } 4950 4951 roundup_size = roundup_pow_of_two(rss_size); 4952 roundup_size = ilog2(roundup_size); 4953 4954 tc_valid[i] = 1; 4955 tc_size[i] = roundup_size; 4956 tc_offset[i] = tc_info->tqp_offset[i]; 4957 } 4958 4959 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4960 tc_size); 4961 } 4962 4963 int hclge_rss_init_hw(struct hclge_dev *hdev) 4964 { 4965 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4966 u8 *key = hdev->rss_cfg.rss_hash_key; 4967 u8 hfunc = hdev->rss_cfg.rss_algo; 4968 int ret; 4969 4970 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4971 rss_indir); 4972 if (ret) 4973 return ret; 4974 4975 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4976 if (ret) 4977 return ret; 4978 4979 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4980 if (ret) 4981 return ret; 4982 4983 return hclge_init_rss_tc_mode(hdev); 4984 } 4985 4986 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4987 int vector_id, bool en, 4988 struct hnae3_ring_chain_node *ring_chain) 4989 { 4990 struct hclge_dev *hdev = vport->back; 4991 struct hnae3_ring_chain_node *node; 4992 struct hclge_desc desc; 4993 struct hclge_ctrl_vector_chain_cmd *req = 4994 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4995 enum hclge_comm_cmd_status status; 4996 enum hclge_opcode_type op; 4997 u16 tqp_type_and_id; 4998 int i; 4999 5000 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 5001 hclge_cmd_setup_basic_desc(&desc, op, false); 5002 req->int_vector_id_l = hnae3_get_field(vector_id, 5003 HCLGE_VECTOR_ID_L_M, 5004 HCLGE_VECTOR_ID_L_S); 5005 req->int_vector_id_h = hnae3_get_field(vector_id, 5006 HCLGE_VECTOR_ID_H_M, 5007 HCLGE_VECTOR_ID_H_S); 5008 5009 i = 0; 5010 for (node = ring_chain; node; node = node->next) { 5011 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 5012 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 5013 HCLGE_INT_TYPE_S, 5014 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 5015 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 5016 HCLGE_TQP_ID_S, node->tqp_index); 5017 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 5018 HCLGE_INT_GL_IDX_S, 5019 hnae3_get_field(node->int_gl_idx, 5020 HNAE3_RING_GL_IDX_M, 5021 HNAE3_RING_GL_IDX_S)); 5022 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 5023 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 5024 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 5025 req->vfid = vport->vport_id; 5026 5027 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5028 if (status) { 5029 dev_err(&hdev->pdev->dev, 5030 "Map TQP fail, status is %d.\n", 5031 status); 5032 return -EIO; 5033 } 5034 i = 0; 5035 5036 hclge_cmd_setup_basic_desc(&desc, 5037 op, 5038 false); 5039 req->int_vector_id_l = 5040 hnae3_get_field(vector_id, 5041 HCLGE_VECTOR_ID_L_M, 5042 HCLGE_VECTOR_ID_L_S); 5043 req->int_vector_id_h = 5044 hnae3_get_field(vector_id, 5045 HCLGE_VECTOR_ID_H_M, 5046 HCLGE_VECTOR_ID_H_S); 5047 } 5048 } 5049 5050 if (i > 0) { 5051 req->int_cause_num = i; 5052 req->vfid = vport->vport_id; 5053 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5054 if (status) { 5055 dev_err(&hdev->pdev->dev, 5056 "Map TQP fail, status is %d.\n", status); 5057 return -EIO; 5058 } 5059 } 5060 5061 return 0; 5062 } 5063 5064 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5065 struct hnae3_ring_chain_node *ring_chain) 5066 { 5067 struct hclge_vport *vport = hclge_get_vport(handle); 5068 struct hclge_dev *hdev = vport->back; 5069 int vector_id; 5070 5071 vector_id = hclge_get_vector_index(hdev, vector); 5072 if (vector_id < 0) { 5073 dev_err(&hdev->pdev->dev, 5074 "failed to get vector index. vector=%d\n", vector); 5075 return vector_id; 5076 } 5077 5078 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5079 } 5080 5081 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5082 struct hnae3_ring_chain_node *ring_chain) 5083 { 5084 struct hclge_vport *vport = hclge_get_vport(handle); 5085 struct hclge_dev *hdev = vport->back; 5086 int vector_id, ret; 5087 5088 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5089 return 0; 5090 5091 vector_id = hclge_get_vector_index(hdev, vector); 5092 if (vector_id < 0) { 5093 dev_err(&handle->pdev->dev, 5094 "Get vector index fail. ret =%d\n", vector_id); 5095 return vector_id; 5096 } 5097 5098 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5099 if (ret) 5100 dev_err(&handle->pdev->dev, 5101 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5102 vector_id, ret); 5103 5104 return ret; 5105 } 5106 5107 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5108 bool en_uc, bool en_mc, bool en_bc) 5109 { 5110 struct hclge_vport *vport = &hdev->vport[vf_id]; 5111 struct hnae3_handle *handle = &vport->nic; 5112 struct hclge_promisc_cfg_cmd *req; 5113 struct hclge_desc desc; 5114 bool uc_tx_en = en_uc; 5115 u8 promisc_cfg = 0; 5116 int ret; 5117 5118 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5119 5120 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5121 req->vf_id = vf_id; 5122 5123 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5124 uc_tx_en = false; 5125 5126 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5127 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5128 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5129 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5130 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5131 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5132 req->extend_promisc = promisc_cfg; 5133 5134 /* to be compatible with DEVICE_VERSION_V1/2 */ 5135 promisc_cfg = 0; 5136 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5137 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5138 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5139 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5140 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5141 req->promisc = promisc_cfg; 5142 5143 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5144 if (ret) 5145 dev_err(&hdev->pdev->dev, 5146 "failed to set vport %u promisc mode, ret = %d.\n", 5147 vf_id, ret); 5148 5149 return ret; 5150 } 5151 5152 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5153 bool en_mc_pmc, bool en_bc_pmc) 5154 { 5155 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5156 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5157 } 5158 5159 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5160 bool en_mc_pmc) 5161 { 5162 struct hclge_vport *vport = hclge_get_vport(handle); 5163 struct hclge_dev *hdev = vport->back; 5164 bool en_bc_pmc = true; 5165 5166 /* For device whose version below V2, if broadcast promisc enabled, 5167 * vlan filter is always bypassed. So broadcast promisc should be 5168 * disabled until user enable promisc mode 5169 */ 5170 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5171 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5172 5173 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5174 en_bc_pmc); 5175 } 5176 5177 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5178 { 5179 struct hclge_vport *vport = hclge_get_vport(handle); 5180 5181 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5182 } 5183 5184 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5185 { 5186 if (hlist_empty(&hdev->fd_rule_list)) 5187 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5188 } 5189 5190 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5191 { 5192 if (!test_bit(location, hdev->fd_bmap)) { 5193 set_bit(location, hdev->fd_bmap); 5194 hdev->hclge_fd_rule_num++; 5195 } 5196 } 5197 5198 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5199 { 5200 if (test_bit(location, hdev->fd_bmap)) { 5201 clear_bit(location, hdev->fd_bmap); 5202 hdev->hclge_fd_rule_num--; 5203 } 5204 } 5205 5206 static void hclge_fd_free_node(struct hclge_dev *hdev, 5207 struct hclge_fd_rule *rule) 5208 { 5209 hlist_del(&rule->rule_node); 5210 kfree(rule); 5211 hclge_sync_fd_state(hdev); 5212 } 5213 5214 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5215 struct hclge_fd_rule *old_rule, 5216 struct hclge_fd_rule *new_rule, 5217 enum HCLGE_FD_NODE_STATE state) 5218 { 5219 switch (state) { 5220 case HCLGE_FD_TO_ADD: 5221 case HCLGE_FD_ACTIVE: 5222 /* 1) if the new state is TO_ADD, just replace the old rule 5223 * with the same location, no matter its state, because the 5224 * new rule will be configured to the hardware. 5225 * 2) if the new state is ACTIVE, it means the new rule 5226 * has been configured to the hardware, so just replace 5227 * the old rule node with the same location. 5228 * 3) for it doesn't add a new node to the list, so it's 5229 * unnecessary to update the rule number and fd_bmap. 5230 */ 5231 new_rule->rule_node.next = old_rule->rule_node.next; 5232 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5233 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5234 kfree(new_rule); 5235 break; 5236 case HCLGE_FD_DELETED: 5237 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5238 hclge_fd_free_node(hdev, old_rule); 5239 break; 5240 case HCLGE_FD_TO_DEL: 5241 /* if new request is TO_DEL, and old rule is existent 5242 * 1) the state of old rule is TO_DEL, we need do nothing, 5243 * because we delete rule by location, other rule content 5244 * is unncessary. 5245 * 2) the state of old rule is ACTIVE, we need to change its 5246 * state to TO_DEL, so the rule will be deleted when periodic 5247 * task being scheduled. 5248 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5249 * been added to hardware, so we just delete the rule node from 5250 * fd_rule_list directly. 5251 */ 5252 if (old_rule->state == HCLGE_FD_TO_ADD) { 5253 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5254 hclge_fd_free_node(hdev, old_rule); 5255 return; 5256 } 5257 old_rule->state = HCLGE_FD_TO_DEL; 5258 break; 5259 } 5260 } 5261 5262 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5263 u16 location, 5264 struct hclge_fd_rule **parent) 5265 { 5266 struct hclge_fd_rule *rule; 5267 struct hlist_node *node; 5268 5269 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5270 if (rule->location == location) 5271 return rule; 5272 else if (rule->location > location) 5273 return NULL; 5274 /* record the parent node, use to keep the nodes in fd_rule_list 5275 * in ascend order. 5276 */ 5277 *parent = rule; 5278 } 5279 5280 return NULL; 5281 } 5282 5283 /* insert fd rule node in ascend order according to rule->location */ 5284 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5285 struct hclge_fd_rule *rule, 5286 struct hclge_fd_rule *parent) 5287 { 5288 INIT_HLIST_NODE(&rule->rule_node); 5289 5290 if (parent) 5291 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5292 else 5293 hlist_add_head(&rule->rule_node, hlist); 5294 } 5295 5296 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5297 struct hclge_fd_user_def_cfg *cfg) 5298 { 5299 struct hclge_fd_user_def_cfg_cmd *req; 5300 struct hclge_desc desc; 5301 u16 data = 0; 5302 int ret; 5303 5304 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5305 5306 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5307 5308 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5309 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5310 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5311 req->ol2_cfg = cpu_to_le16(data); 5312 5313 data = 0; 5314 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5315 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5316 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5317 req->ol3_cfg = cpu_to_le16(data); 5318 5319 data = 0; 5320 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5321 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5322 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5323 req->ol4_cfg = cpu_to_le16(data); 5324 5325 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5326 if (ret) 5327 dev_err(&hdev->pdev->dev, 5328 "failed to set fd user def data, ret= %d\n", ret); 5329 return ret; 5330 } 5331 5332 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5333 { 5334 int ret; 5335 5336 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5337 return; 5338 5339 if (!locked) 5340 spin_lock_bh(&hdev->fd_rule_lock); 5341 5342 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5343 if (ret) 5344 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5345 5346 if (!locked) 5347 spin_unlock_bh(&hdev->fd_rule_lock); 5348 } 5349 5350 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5351 struct hclge_fd_rule *rule) 5352 { 5353 struct hlist_head *hlist = &hdev->fd_rule_list; 5354 struct hclge_fd_rule *fd_rule, *parent = NULL; 5355 struct hclge_fd_user_def_info *info, *old_info; 5356 struct hclge_fd_user_def_cfg *cfg; 5357 5358 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5359 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5360 return 0; 5361 5362 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5363 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5364 info = &rule->ep.user_def; 5365 5366 if (!cfg->ref_cnt || cfg->offset == info->offset) 5367 return 0; 5368 5369 if (cfg->ref_cnt > 1) 5370 goto error; 5371 5372 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5373 if (fd_rule) { 5374 old_info = &fd_rule->ep.user_def; 5375 if (info->layer == old_info->layer) 5376 return 0; 5377 } 5378 5379 error: 5380 dev_err(&hdev->pdev->dev, 5381 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5382 info->layer + 1); 5383 return -ENOSPC; 5384 } 5385 5386 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5387 struct hclge_fd_rule *rule) 5388 { 5389 struct hclge_fd_user_def_cfg *cfg; 5390 5391 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5392 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5393 return; 5394 5395 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5396 if (!cfg->ref_cnt) { 5397 cfg->offset = rule->ep.user_def.offset; 5398 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5399 } 5400 cfg->ref_cnt++; 5401 } 5402 5403 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5404 struct hclge_fd_rule *rule) 5405 { 5406 struct hclge_fd_user_def_cfg *cfg; 5407 5408 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5409 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5410 return; 5411 5412 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5413 if (!cfg->ref_cnt) 5414 return; 5415 5416 cfg->ref_cnt--; 5417 if (!cfg->ref_cnt) { 5418 cfg->offset = 0; 5419 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5420 } 5421 } 5422 5423 static void hclge_update_fd_list(struct hclge_dev *hdev, 5424 enum HCLGE_FD_NODE_STATE state, u16 location, 5425 struct hclge_fd_rule *new_rule) 5426 { 5427 struct hlist_head *hlist = &hdev->fd_rule_list; 5428 struct hclge_fd_rule *fd_rule, *parent = NULL; 5429 5430 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5431 if (fd_rule) { 5432 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5433 if (state == HCLGE_FD_ACTIVE) 5434 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5435 hclge_sync_fd_user_def_cfg(hdev, true); 5436 5437 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5438 return; 5439 } 5440 5441 /* it's unlikely to fail here, because we have checked the rule 5442 * exist before. 5443 */ 5444 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5445 dev_warn(&hdev->pdev->dev, 5446 "failed to delete fd rule %u, it's inexistent\n", 5447 location); 5448 return; 5449 } 5450 5451 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5452 hclge_sync_fd_user_def_cfg(hdev, true); 5453 5454 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5455 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5456 5457 if (state == HCLGE_FD_TO_ADD) { 5458 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5459 hclge_task_schedule(hdev, 0); 5460 } 5461 } 5462 5463 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5464 { 5465 struct hclge_get_fd_mode_cmd *req; 5466 struct hclge_desc desc; 5467 int ret; 5468 5469 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5470 5471 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5472 5473 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5474 if (ret) { 5475 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5476 return ret; 5477 } 5478 5479 *fd_mode = req->mode; 5480 5481 return ret; 5482 } 5483 5484 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5485 u32 *stage1_entry_num, 5486 u32 *stage2_entry_num, 5487 u16 *stage1_counter_num, 5488 u16 *stage2_counter_num) 5489 { 5490 struct hclge_get_fd_allocation_cmd *req; 5491 struct hclge_desc desc; 5492 int ret; 5493 5494 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5495 5496 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5497 5498 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5499 if (ret) { 5500 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5501 ret); 5502 return ret; 5503 } 5504 5505 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5506 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5507 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5508 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5509 5510 return ret; 5511 } 5512 5513 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5514 enum HCLGE_FD_STAGE stage_num) 5515 { 5516 struct hclge_set_fd_key_config_cmd *req; 5517 struct hclge_fd_key_cfg *stage; 5518 struct hclge_desc desc; 5519 int ret; 5520 5521 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5522 5523 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5524 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5525 req->stage = stage_num; 5526 req->key_select = stage->key_sel; 5527 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5528 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5529 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5530 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5531 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5532 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5533 5534 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5535 if (ret) 5536 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5537 5538 return ret; 5539 } 5540 5541 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5542 { 5543 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5544 5545 spin_lock_bh(&hdev->fd_rule_lock); 5546 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5547 spin_unlock_bh(&hdev->fd_rule_lock); 5548 5549 hclge_fd_set_user_def_cmd(hdev, cfg); 5550 } 5551 5552 static int hclge_init_fd_config(struct hclge_dev *hdev) 5553 { 5554 #define LOW_2_WORDS 0x03 5555 struct hclge_fd_key_cfg *key_cfg; 5556 int ret; 5557 5558 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5559 return 0; 5560 5561 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5562 if (ret) 5563 return ret; 5564 5565 switch (hdev->fd_cfg.fd_mode) { 5566 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5567 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5568 break; 5569 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5570 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5571 break; 5572 default: 5573 dev_err(&hdev->pdev->dev, 5574 "Unsupported flow director mode %u\n", 5575 hdev->fd_cfg.fd_mode); 5576 return -EOPNOTSUPP; 5577 } 5578 5579 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5580 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5581 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5582 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5583 key_cfg->outer_sipv6_word_en = 0; 5584 key_cfg->outer_dipv6_word_en = 0; 5585 5586 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5587 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5588 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5589 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5590 5591 /* If use max 400bit key, we can support tuples for ether type */ 5592 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5593 key_cfg->tuple_active |= 5594 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5595 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5596 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5597 } 5598 5599 /* roce_type is used to filter roce frames 5600 * dst_vport is used to specify the rule 5601 */ 5602 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5603 5604 ret = hclge_get_fd_allocation(hdev, 5605 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5606 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5607 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5608 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5609 if (ret) 5610 return ret; 5611 5612 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5613 } 5614 5615 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5616 int loc, u8 *key, bool is_add) 5617 { 5618 struct hclge_fd_tcam_config_1_cmd *req1; 5619 struct hclge_fd_tcam_config_2_cmd *req2; 5620 struct hclge_fd_tcam_config_3_cmd *req3; 5621 struct hclge_desc desc[3]; 5622 int ret; 5623 5624 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5625 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5626 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5627 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5628 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5629 5630 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5631 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5632 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5633 5634 req1->stage = stage; 5635 req1->xy_sel = sel_x ? 1 : 0; 5636 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5637 req1->index = cpu_to_le32(loc); 5638 req1->entry_vld = sel_x ? is_add : 0; 5639 5640 if (key) { 5641 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5642 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5643 sizeof(req2->tcam_data)); 5644 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5645 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5646 } 5647 5648 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5649 if (ret) 5650 dev_err(&hdev->pdev->dev, 5651 "config tcam key fail, ret=%d\n", 5652 ret); 5653 5654 return ret; 5655 } 5656 5657 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5658 struct hclge_fd_ad_data *action) 5659 { 5660 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5661 struct hclge_fd_ad_config_cmd *req; 5662 struct hclge_desc desc; 5663 u64 ad_data = 0; 5664 int ret; 5665 5666 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5667 5668 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5669 req->index = cpu_to_le32(loc); 5670 req->stage = stage; 5671 5672 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5673 action->write_rule_id_to_bd); 5674 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5675 action->rule_id); 5676 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5677 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5678 action->override_tc); 5679 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5680 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5681 } 5682 ad_data <<= 32; 5683 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5684 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5685 action->forward_to_direct_queue); 5686 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5687 action->queue_id); 5688 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5689 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5690 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5691 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5692 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5693 action->counter_id); 5694 5695 req->ad_data = cpu_to_le64(ad_data); 5696 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5697 if (ret) 5698 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5699 5700 return ret; 5701 } 5702 5703 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5704 struct hclge_fd_rule *rule) 5705 { 5706 int offset, moffset, ip_offset; 5707 enum HCLGE_FD_KEY_OPT key_opt; 5708 u16 tmp_x_s, tmp_y_s; 5709 u32 tmp_x_l, tmp_y_l; 5710 u8 *p = (u8 *)rule; 5711 int i; 5712 5713 if (rule->unused_tuple & BIT(tuple_bit)) 5714 return true; 5715 5716 key_opt = tuple_key_info[tuple_bit].key_opt; 5717 offset = tuple_key_info[tuple_bit].offset; 5718 moffset = tuple_key_info[tuple_bit].moffset; 5719 5720 switch (key_opt) { 5721 case KEY_OPT_U8: 5722 calc_x(*key_x, p[offset], p[moffset]); 5723 calc_y(*key_y, p[offset], p[moffset]); 5724 5725 return true; 5726 case KEY_OPT_LE16: 5727 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5728 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5729 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5730 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5731 5732 return true; 5733 case KEY_OPT_LE32: 5734 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5735 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5736 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5737 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5738 5739 return true; 5740 case KEY_OPT_MAC: 5741 for (i = 0; i < ETH_ALEN; i++) { 5742 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5743 p[moffset + i]); 5744 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5745 p[moffset + i]); 5746 } 5747 5748 return true; 5749 case KEY_OPT_IP: 5750 ip_offset = IPV4_INDEX * sizeof(u32); 5751 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5752 *(u32 *)(&p[moffset + ip_offset])); 5753 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5754 *(u32 *)(&p[moffset + ip_offset])); 5755 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5756 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5757 5758 return true; 5759 default: 5760 return false; 5761 } 5762 } 5763 5764 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5765 u8 vf_id, u8 network_port_id) 5766 { 5767 u32 port_number = 0; 5768 5769 if (port_type == HOST_PORT) { 5770 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5771 pf_id); 5772 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5773 vf_id); 5774 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5775 } else { 5776 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5777 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5778 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5779 } 5780 5781 return port_number; 5782 } 5783 5784 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5785 __le32 *key_x, __le32 *key_y, 5786 struct hclge_fd_rule *rule) 5787 { 5788 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5789 u8 cur_pos = 0, tuple_size, shift_bits; 5790 unsigned int i; 5791 5792 for (i = 0; i < MAX_META_DATA; i++) { 5793 tuple_size = meta_data_key_info[i].key_length; 5794 tuple_bit = key_cfg->meta_data_active & BIT(i); 5795 5796 switch (tuple_bit) { 5797 case BIT(ROCE_TYPE): 5798 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5799 cur_pos += tuple_size; 5800 break; 5801 case BIT(DST_VPORT): 5802 port_number = hclge_get_port_number(HOST_PORT, 0, 5803 rule->vf_id, 0); 5804 hnae3_set_field(meta_data, 5805 GENMASK(cur_pos + tuple_size, cur_pos), 5806 cur_pos, port_number); 5807 cur_pos += tuple_size; 5808 break; 5809 default: 5810 break; 5811 } 5812 } 5813 5814 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5815 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5816 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5817 5818 *key_x = cpu_to_le32(tmp_x << shift_bits); 5819 *key_y = cpu_to_le32(tmp_y << shift_bits); 5820 } 5821 5822 /* A complete key is combined with meta data key and tuple key. 5823 * Meta data key is stored at the MSB region, and tuple key is stored at 5824 * the LSB region, unused bits will be filled 0. 5825 */ 5826 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5827 struct hclge_fd_rule *rule) 5828 { 5829 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5830 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5831 u8 *cur_key_x, *cur_key_y; 5832 u8 meta_data_region; 5833 u8 tuple_size; 5834 int ret; 5835 u32 i; 5836 5837 memset(key_x, 0, sizeof(key_x)); 5838 memset(key_y, 0, sizeof(key_y)); 5839 cur_key_x = key_x; 5840 cur_key_y = key_y; 5841 5842 for (i = 0; i < MAX_TUPLE; i++) { 5843 bool tuple_valid; 5844 5845 tuple_size = tuple_key_info[i].key_length / 8; 5846 if (!(key_cfg->tuple_active & BIT(i))) 5847 continue; 5848 5849 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5850 cur_key_y, rule); 5851 if (tuple_valid) { 5852 cur_key_x += tuple_size; 5853 cur_key_y += tuple_size; 5854 } 5855 } 5856 5857 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5858 MAX_META_DATA_LENGTH / 8; 5859 5860 hclge_fd_convert_meta_data(key_cfg, 5861 (__le32 *)(key_x + meta_data_region), 5862 (__le32 *)(key_y + meta_data_region), 5863 rule); 5864 5865 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5866 true); 5867 if (ret) { 5868 dev_err(&hdev->pdev->dev, 5869 "fd key_y config fail, loc=%u, ret=%d\n", 5870 rule->queue_id, ret); 5871 return ret; 5872 } 5873 5874 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5875 true); 5876 if (ret) 5877 dev_err(&hdev->pdev->dev, 5878 "fd key_x config fail, loc=%u, ret=%d\n", 5879 rule->queue_id, ret); 5880 return ret; 5881 } 5882 5883 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5884 struct hclge_fd_rule *rule) 5885 { 5886 struct hclge_vport *vport = hdev->vport; 5887 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5888 struct hclge_fd_ad_data ad_data; 5889 5890 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5891 ad_data.ad_id = rule->location; 5892 5893 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5894 ad_data.drop_packet = true; 5895 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5896 ad_data.override_tc = true; 5897 ad_data.queue_id = 5898 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5899 ad_data.tc_size = 5900 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5901 } else { 5902 ad_data.forward_to_direct_queue = true; 5903 ad_data.queue_id = rule->queue_id; 5904 } 5905 5906 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5907 ad_data.use_counter = true; 5908 ad_data.counter_id = rule->vf_id % 5909 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5910 } else { 5911 ad_data.use_counter = false; 5912 ad_data.counter_id = 0; 5913 } 5914 5915 ad_data.use_next_stage = false; 5916 ad_data.next_input_key = 0; 5917 5918 ad_data.write_rule_id_to_bd = true; 5919 ad_data.rule_id = rule->location; 5920 5921 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5922 } 5923 5924 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5925 u32 *unused_tuple) 5926 { 5927 if (!spec || !unused_tuple) 5928 return -EINVAL; 5929 5930 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5931 5932 if (!spec->ip4src) 5933 *unused_tuple |= BIT(INNER_SRC_IP); 5934 5935 if (!spec->ip4dst) 5936 *unused_tuple |= BIT(INNER_DST_IP); 5937 5938 if (!spec->psrc) 5939 *unused_tuple |= BIT(INNER_SRC_PORT); 5940 5941 if (!spec->pdst) 5942 *unused_tuple |= BIT(INNER_DST_PORT); 5943 5944 if (!spec->tos) 5945 *unused_tuple |= BIT(INNER_IP_TOS); 5946 5947 return 0; 5948 } 5949 5950 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5951 u32 *unused_tuple) 5952 { 5953 if (!spec || !unused_tuple) 5954 return -EINVAL; 5955 5956 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5957 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5958 5959 if (!spec->ip4src) 5960 *unused_tuple |= BIT(INNER_SRC_IP); 5961 5962 if (!spec->ip4dst) 5963 *unused_tuple |= BIT(INNER_DST_IP); 5964 5965 if (!spec->tos) 5966 *unused_tuple |= BIT(INNER_IP_TOS); 5967 5968 if (!spec->proto) 5969 *unused_tuple |= BIT(INNER_IP_PROTO); 5970 5971 if (spec->l4_4_bytes) 5972 return -EOPNOTSUPP; 5973 5974 if (spec->ip_ver != ETH_RX_NFC_IP4) 5975 return -EOPNOTSUPP; 5976 5977 return 0; 5978 } 5979 5980 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5981 u32 *unused_tuple) 5982 { 5983 if (!spec || !unused_tuple) 5984 return -EINVAL; 5985 5986 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5987 5988 /* check whether src/dst ip address used */ 5989 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5990 *unused_tuple |= BIT(INNER_SRC_IP); 5991 5992 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5993 *unused_tuple |= BIT(INNER_DST_IP); 5994 5995 if (!spec->psrc) 5996 *unused_tuple |= BIT(INNER_SRC_PORT); 5997 5998 if (!spec->pdst) 5999 *unused_tuple |= BIT(INNER_DST_PORT); 6000 6001 if (!spec->tclass) 6002 *unused_tuple |= BIT(INNER_IP_TOS); 6003 6004 return 0; 6005 } 6006 6007 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 6008 u32 *unused_tuple) 6009 { 6010 if (!spec || !unused_tuple) 6011 return -EINVAL; 6012 6013 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6014 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 6015 6016 /* check whether src/dst ip address used */ 6017 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 6018 *unused_tuple |= BIT(INNER_SRC_IP); 6019 6020 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 6021 *unused_tuple |= BIT(INNER_DST_IP); 6022 6023 if (!spec->l4_proto) 6024 *unused_tuple |= BIT(INNER_IP_PROTO); 6025 6026 if (!spec->tclass) 6027 *unused_tuple |= BIT(INNER_IP_TOS); 6028 6029 if (spec->l4_4_bytes) 6030 return -EOPNOTSUPP; 6031 6032 return 0; 6033 } 6034 6035 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 6036 { 6037 if (!spec || !unused_tuple) 6038 return -EINVAL; 6039 6040 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 6041 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 6042 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 6043 6044 if (is_zero_ether_addr(spec->h_source)) 6045 *unused_tuple |= BIT(INNER_SRC_MAC); 6046 6047 if (is_zero_ether_addr(spec->h_dest)) 6048 *unused_tuple |= BIT(INNER_DST_MAC); 6049 6050 if (!spec->h_proto) 6051 *unused_tuple |= BIT(INNER_ETH_TYPE); 6052 6053 return 0; 6054 } 6055 6056 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 6057 struct ethtool_rx_flow_spec *fs, 6058 u32 *unused_tuple) 6059 { 6060 if (fs->flow_type & FLOW_EXT) { 6061 if (fs->h_ext.vlan_etype) { 6062 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 6063 return -EOPNOTSUPP; 6064 } 6065 6066 if (!fs->h_ext.vlan_tci) 6067 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6068 6069 if (fs->m_ext.vlan_tci && 6070 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 6071 dev_err(&hdev->pdev->dev, 6072 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6073 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6074 return -EINVAL; 6075 } 6076 } else { 6077 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6078 } 6079 6080 if (fs->flow_type & FLOW_MAC_EXT) { 6081 if (hdev->fd_cfg.fd_mode != 6082 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6083 dev_err(&hdev->pdev->dev, 6084 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6085 return -EOPNOTSUPP; 6086 } 6087 6088 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6089 *unused_tuple |= BIT(INNER_DST_MAC); 6090 else 6091 *unused_tuple &= ~BIT(INNER_DST_MAC); 6092 } 6093 6094 return 0; 6095 } 6096 6097 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6098 struct hclge_fd_user_def_info *info) 6099 { 6100 switch (flow_type) { 6101 case ETHER_FLOW: 6102 info->layer = HCLGE_FD_USER_DEF_L2; 6103 *unused_tuple &= ~BIT(INNER_L2_RSV); 6104 break; 6105 case IP_USER_FLOW: 6106 case IPV6_USER_FLOW: 6107 info->layer = HCLGE_FD_USER_DEF_L3; 6108 *unused_tuple &= ~BIT(INNER_L3_RSV); 6109 break; 6110 case TCP_V4_FLOW: 6111 case UDP_V4_FLOW: 6112 case TCP_V6_FLOW: 6113 case UDP_V6_FLOW: 6114 info->layer = HCLGE_FD_USER_DEF_L4; 6115 *unused_tuple &= ~BIT(INNER_L4_RSV); 6116 break; 6117 default: 6118 return -EOPNOTSUPP; 6119 } 6120 6121 return 0; 6122 } 6123 6124 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6125 { 6126 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6127 } 6128 6129 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6130 struct ethtool_rx_flow_spec *fs, 6131 u32 *unused_tuple, 6132 struct hclge_fd_user_def_info *info) 6133 { 6134 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6135 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6136 u16 data, offset, data_mask, offset_mask; 6137 int ret; 6138 6139 info->layer = HCLGE_FD_USER_DEF_NONE; 6140 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6141 6142 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6143 return 0; 6144 6145 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6146 * for data, and bit32~47 is used for offset. 6147 */ 6148 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6149 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6150 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6151 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6152 6153 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6154 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6155 return -EOPNOTSUPP; 6156 } 6157 6158 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6159 dev_err(&hdev->pdev->dev, 6160 "user-def offset[%u] should be no more than %u\n", 6161 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6162 return -EINVAL; 6163 } 6164 6165 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6166 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6167 return -EINVAL; 6168 } 6169 6170 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6171 if (ret) { 6172 dev_err(&hdev->pdev->dev, 6173 "unsupported flow type for user-def bytes, ret = %d\n", 6174 ret); 6175 return ret; 6176 } 6177 6178 info->data = data; 6179 info->data_mask = data_mask; 6180 info->offset = offset; 6181 6182 return 0; 6183 } 6184 6185 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6186 struct ethtool_rx_flow_spec *fs, 6187 u32 *unused_tuple, 6188 struct hclge_fd_user_def_info *info) 6189 { 6190 u32 flow_type; 6191 int ret; 6192 6193 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6194 dev_err(&hdev->pdev->dev, 6195 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6196 fs->location, 6197 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6198 return -EINVAL; 6199 } 6200 6201 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6202 if (ret) 6203 return ret; 6204 6205 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6206 switch (flow_type) { 6207 case SCTP_V4_FLOW: 6208 case TCP_V4_FLOW: 6209 case UDP_V4_FLOW: 6210 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6211 unused_tuple); 6212 break; 6213 case IP_USER_FLOW: 6214 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6215 unused_tuple); 6216 break; 6217 case SCTP_V6_FLOW: 6218 case TCP_V6_FLOW: 6219 case UDP_V6_FLOW: 6220 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6221 unused_tuple); 6222 break; 6223 case IPV6_USER_FLOW: 6224 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6225 unused_tuple); 6226 break; 6227 case ETHER_FLOW: 6228 if (hdev->fd_cfg.fd_mode != 6229 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6230 dev_err(&hdev->pdev->dev, 6231 "ETHER_FLOW is not supported in current fd mode!\n"); 6232 return -EOPNOTSUPP; 6233 } 6234 6235 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6236 unused_tuple); 6237 break; 6238 default: 6239 dev_err(&hdev->pdev->dev, 6240 "unsupported protocol type, protocol type = %#x\n", 6241 flow_type); 6242 return -EOPNOTSUPP; 6243 } 6244 6245 if (ret) { 6246 dev_err(&hdev->pdev->dev, 6247 "failed to check flow union tuple, ret = %d\n", 6248 ret); 6249 return ret; 6250 } 6251 6252 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6253 } 6254 6255 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6256 struct hclge_fd_rule *rule, u8 ip_proto) 6257 { 6258 rule->tuples.src_ip[IPV4_INDEX] = 6259 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6260 rule->tuples_mask.src_ip[IPV4_INDEX] = 6261 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6262 6263 rule->tuples.dst_ip[IPV4_INDEX] = 6264 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6265 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6266 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6267 6268 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6269 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6270 6271 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6272 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6273 6274 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6275 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6276 6277 rule->tuples.ether_proto = ETH_P_IP; 6278 rule->tuples_mask.ether_proto = 0xFFFF; 6279 6280 rule->tuples.ip_proto = ip_proto; 6281 rule->tuples_mask.ip_proto = 0xFF; 6282 } 6283 6284 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6285 struct hclge_fd_rule *rule) 6286 { 6287 rule->tuples.src_ip[IPV4_INDEX] = 6288 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6289 rule->tuples_mask.src_ip[IPV4_INDEX] = 6290 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6291 6292 rule->tuples.dst_ip[IPV4_INDEX] = 6293 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6294 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6295 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6296 6297 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6298 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6299 6300 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6301 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6302 6303 rule->tuples.ether_proto = ETH_P_IP; 6304 rule->tuples_mask.ether_proto = 0xFFFF; 6305 } 6306 6307 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6308 struct hclge_fd_rule *rule, u8 ip_proto) 6309 { 6310 ipv6_addr_be32_to_cpu(rule->tuples.src_ip, 6311 fs->h_u.tcp_ip6_spec.ip6src); 6312 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, 6313 fs->m_u.tcp_ip6_spec.ip6src); 6314 6315 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, 6316 fs->h_u.tcp_ip6_spec.ip6dst); 6317 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, 6318 fs->m_u.tcp_ip6_spec.ip6dst); 6319 6320 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6321 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6322 6323 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6324 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6325 6326 rule->tuples.ether_proto = ETH_P_IPV6; 6327 rule->tuples_mask.ether_proto = 0xFFFF; 6328 6329 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6330 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6331 6332 rule->tuples.ip_proto = ip_proto; 6333 rule->tuples_mask.ip_proto = 0xFF; 6334 } 6335 6336 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6337 struct hclge_fd_rule *rule) 6338 { 6339 ipv6_addr_be32_to_cpu(rule->tuples.src_ip, 6340 fs->h_u.usr_ip6_spec.ip6src); 6341 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, 6342 fs->m_u.usr_ip6_spec.ip6src); 6343 6344 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, 6345 fs->h_u.usr_ip6_spec.ip6dst); 6346 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, 6347 fs->m_u.usr_ip6_spec.ip6dst); 6348 6349 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6350 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6351 6352 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6353 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6354 6355 rule->tuples.ether_proto = ETH_P_IPV6; 6356 rule->tuples_mask.ether_proto = 0xFFFF; 6357 } 6358 6359 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6360 struct hclge_fd_rule *rule) 6361 { 6362 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6363 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6364 6365 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6366 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6367 6368 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6369 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6370 } 6371 6372 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6373 struct hclge_fd_rule *rule) 6374 { 6375 switch (info->layer) { 6376 case HCLGE_FD_USER_DEF_L2: 6377 rule->tuples.l2_user_def = info->data; 6378 rule->tuples_mask.l2_user_def = info->data_mask; 6379 break; 6380 case HCLGE_FD_USER_DEF_L3: 6381 rule->tuples.l3_user_def = info->data; 6382 rule->tuples_mask.l3_user_def = info->data_mask; 6383 break; 6384 case HCLGE_FD_USER_DEF_L4: 6385 rule->tuples.l4_user_def = (u32)info->data << 16; 6386 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6387 break; 6388 default: 6389 break; 6390 } 6391 6392 rule->ep.user_def = *info; 6393 } 6394 6395 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6396 struct hclge_fd_rule *rule, 6397 struct hclge_fd_user_def_info *info) 6398 { 6399 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6400 6401 switch (flow_type) { 6402 case SCTP_V4_FLOW: 6403 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6404 break; 6405 case TCP_V4_FLOW: 6406 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6407 break; 6408 case UDP_V4_FLOW: 6409 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6410 break; 6411 case IP_USER_FLOW: 6412 hclge_fd_get_ip4_tuple(fs, rule); 6413 break; 6414 case SCTP_V6_FLOW: 6415 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6416 break; 6417 case TCP_V6_FLOW: 6418 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6419 break; 6420 case UDP_V6_FLOW: 6421 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6422 break; 6423 case IPV6_USER_FLOW: 6424 hclge_fd_get_ip6_tuple(fs, rule); 6425 break; 6426 case ETHER_FLOW: 6427 hclge_fd_get_ether_tuple(fs, rule); 6428 break; 6429 default: 6430 return -EOPNOTSUPP; 6431 } 6432 6433 if (fs->flow_type & FLOW_EXT) { 6434 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6435 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6436 hclge_fd_get_user_def_tuple(info, rule); 6437 } 6438 6439 if (fs->flow_type & FLOW_MAC_EXT) { 6440 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6441 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6442 } 6443 6444 return 0; 6445 } 6446 6447 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6448 struct hclge_fd_rule *rule) 6449 { 6450 int ret; 6451 6452 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6453 if (ret) 6454 return ret; 6455 6456 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6457 } 6458 6459 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6460 struct hclge_fd_rule *rule) 6461 { 6462 int ret; 6463 6464 spin_lock_bh(&hdev->fd_rule_lock); 6465 6466 if (hdev->fd_active_type != rule->rule_type && 6467 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6468 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6469 dev_err(&hdev->pdev->dev, 6470 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6471 rule->rule_type, hdev->fd_active_type); 6472 spin_unlock_bh(&hdev->fd_rule_lock); 6473 return -EINVAL; 6474 } 6475 6476 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6477 if (ret) 6478 goto out; 6479 6480 ret = hclge_clear_arfs_rules(hdev); 6481 if (ret) 6482 goto out; 6483 6484 ret = hclge_fd_config_rule(hdev, rule); 6485 if (ret) 6486 goto out; 6487 6488 rule->state = HCLGE_FD_ACTIVE; 6489 hdev->fd_active_type = rule->rule_type; 6490 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6491 6492 out: 6493 spin_unlock_bh(&hdev->fd_rule_lock); 6494 return ret; 6495 } 6496 6497 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6498 { 6499 struct hclge_vport *vport = hclge_get_vport(handle); 6500 struct hclge_dev *hdev = vport->back; 6501 6502 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6503 } 6504 6505 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6506 u16 *vport_id, u8 *action, u16 *queue_id) 6507 { 6508 struct hclge_vport *vport = hdev->vport; 6509 6510 if (ring_cookie == RX_CLS_FLOW_DISC) { 6511 *action = HCLGE_FD_ACTION_DROP_PACKET; 6512 } else { 6513 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6514 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6515 u16 tqps; 6516 6517 /* To keep consistent with user's configuration, minus 1 when 6518 * printing 'vf', because vf id from ethtool is added 1 for vf. 6519 */ 6520 if (vf > hdev->num_req_vfs) { 6521 dev_err(&hdev->pdev->dev, 6522 "Error: vf id (%u) should be less than %u\n", 6523 vf - 1U, hdev->num_req_vfs); 6524 return -EINVAL; 6525 } 6526 6527 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6528 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6529 6530 if (ring >= tqps) { 6531 dev_err(&hdev->pdev->dev, 6532 "Error: queue id (%u) > max tqp num (%u)\n", 6533 ring, tqps - 1U); 6534 return -EINVAL; 6535 } 6536 6537 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6538 *queue_id = ring; 6539 } 6540 6541 return 0; 6542 } 6543 6544 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6545 struct ethtool_rxnfc *cmd) 6546 { 6547 struct hclge_vport *vport = hclge_get_vport(handle); 6548 struct hclge_dev *hdev = vport->back; 6549 struct hclge_fd_user_def_info info; 6550 u16 dst_vport_id = 0, q_index = 0; 6551 struct ethtool_rx_flow_spec *fs; 6552 struct hclge_fd_rule *rule; 6553 u32 unused = 0; 6554 u8 action; 6555 int ret; 6556 6557 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6558 dev_err(&hdev->pdev->dev, 6559 "flow table director is not supported\n"); 6560 return -EOPNOTSUPP; 6561 } 6562 6563 if (!hdev->fd_en) { 6564 dev_err(&hdev->pdev->dev, 6565 "please enable flow director first\n"); 6566 return -EOPNOTSUPP; 6567 } 6568 6569 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6570 6571 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6572 if (ret) 6573 return ret; 6574 6575 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6576 &action, &q_index); 6577 if (ret) 6578 return ret; 6579 6580 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6581 if (!rule) 6582 return -ENOMEM; 6583 6584 ret = hclge_fd_get_tuple(fs, rule, &info); 6585 if (ret) { 6586 kfree(rule); 6587 return ret; 6588 } 6589 6590 rule->flow_type = fs->flow_type; 6591 rule->location = fs->location; 6592 rule->unused_tuple = unused; 6593 rule->vf_id = dst_vport_id; 6594 rule->queue_id = q_index; 6595 rule->action = action; 6596 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6597 6598 ret = hclge_add_fd_entry_common(hdev, rule); 6599 if (ret) 6600 kfree(rule); 6601 6602 return ret; 6603 } 6604 6605 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6606 struct ethtool_rxnfc *cmd) 6607 { 6608 struct hclge_vport *vport = hclge_get_vport(handle); 6609 struct hclge_dev *hdev = vport->back; 6610 struct ethtool_rx_flow_spec *fs; 6611 int ret; 6612 6613 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6614 return -EOPNOTSUPP; 6615 6616 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6617 6618 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6619 return -EINVAL; 6620 6621 spin_lock_bh(&hdev->fd_rule_lock); 6622 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6623 !test_bit(fs->location, hdev->fd_bmap)) { 6624 dev_err(&hdev->pdev->dev, 6625 "Delete fail, rule %u is inexistent\n", fs->location); 6626 spin_unlock_bh(&hdev->fd_rule_lock); 6627 return -ENOENT; 6628 } 6629 6630 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6631 NULL, false); 6632 if (ret) 6633 goto out; 6634 6635 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6636 6637 out: 6638 spin_unlock_bh(&hdev->fd_rule_lock); 6639 return ret; 6640 } 6641 6642 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6643 bool clear_list) 6644 { 6645 struct hclge_fd_rule *rule; 6646 struct hlist_node *node; 6647 u16 location; 6648 6649 spin_lock_bh(&hdev->fd_rule_lock); 6650 6651 for_each_set_bit(location, hdev->fd_bmap, 6652 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6653 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6654 NULL, false); 6655 6656 if (clear_list) { 6657 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6658 rule_node) { 6659 hlist_del(&rule->rule_node); 6660 kfree(rule); 6661 } 6662 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6663 hdev->hclge_fd_rule_num = 0; 6664 bitmap_zero(hdev->fd_bmap, 6665 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6666 } 6667 6668 spin_unlock_bh(&hdev->fd_rule_lock); 6669 } 6670 6671 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6672 { 6673 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6674 return; 6675 6676 hclge_clear_fd_rules_in_list(hdev, true); 6677 hclge_fd_disable_user_def(hdev); 6678 } 6679 6680 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6681 { 6682 struct hclge_vport *vport = hclge_get_vport(handle); 6683 struct hclge_dev *hdev = vport->back; 6684 struct hclge_fd_rule *rule; 6685 struct hlist_node *node; 6686 6687 /* Return ok here, because reset error handling will check this 6688 * return value. If error is returned here, the reset process will 6689 * fail. 6690 */ 6691 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6692 return 0; 6693 6694 /* if fd is disabled, should not restore it when reset */ 6695 if (!hdev->fd_en) 6696 return 0; 6697 6698 spin_lock_bh(&hdev->fd_rule_lock); 6699 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6700 if (rule->state == HCLGE_FD_ACTIVE) 6701 rule->state = HCLGE_FD_TO_ADD; 6702 } 6703 spin_unlock_bh(&hdev->fd_rule_lock); 6704 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6705 6706 return 0; 6707 } 6708 6709 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6710 struct ethtool_rxnfc *cmd) 6711 { 6712 struct hclge_vport *vport = hclge_get_vport(handle); 6713 struct hclge_dev *hdev = vport->back; 6714 6715 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6716 return -EOPNOTSUPP; 6717 6718 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6719 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6720 6721 return 0; 6722 } 6723 6724 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6725 struct ethtool_tcpip4_spec *spec, 6726 struct ethtool_tcpip4_spec *spec_mask) 6727 { 6728 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6729 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6730 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6731 6732 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6733 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6734 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6735 6736 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6737 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6738 0 : cpu_to_be16(rule->tuples_mask.src_port); 6739 6740 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6741 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6742 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6743 6744 spec->tos = rule->tuples.ip_tos; 6745 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6746 0 : rule->tuples_mask.ip_tos; 6747 } 6748 6749 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6750 struct ethtool_usrip4_spec *spec, 6751 struct ethtool_usrip4_spec *spec_mask) 6752 { 6753 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6754 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6755 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6756 6757 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6758 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6759 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6760 6761 spec->tos = rule->tuples.ip_tos; 6762 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6763 0 : rule->tuples_mask.ip_tos; 6764 6765 spec->proto = rule->tuples.ip_proto; 6766 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6767 0 : rule->tuples_mask.ip_proto; 6768 6769 spec->ip_ver = ETH_RX_NFC_IP4; 6770 } 6771 6772 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6773 struct ethtool_tcpip6_spec *spec, 6774 struct ethtool_tcpip6_spec *spec_mask) 6775 { 6776 ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip); 6777 ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip); 6778 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6779 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6780 else 6781 ipv6_addr_cpu_to_be32(spec_mask->ip6src, 6782 rule->tuples_mask.src_ip); 6783 6784 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6785 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6786 else 6787 ipv6_addr_cpu_to_be32(spec_mask->ip6dst, 6788 rule->tuples_mask.dst_ip); 6789 6790 spec->tclass = rule->tuples.ip_tos; 6791 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6792 0 : rule->tuples_mask.ip_tos; 6793 6794 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6795 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6796 0 : cpu_to_be16(rule->tuples_mask.src_port); 6797 6798 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6799 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6800 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6801 } 6802 6803 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6804 struct ethtool_usrip6_spec *spec, 6805 struct ethtool_usrip6_spec *spec_mask) 6806 { 6807 ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip); 6808 ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip); 6809 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6810 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6811 else 6812 ipv6_addr_cpu_to_be32(spec_mask->ip6src, 6813 rule->tuples_mask.src_ip); 6814 6815 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6816 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6817 else 6818 ipv6_addr_cpu_to_be32(spec_mask->ip6dst, 6819 rule->tuples_mask.dst_ip); 6820 6821 spec->tclass = rule->tuples.ip_tos; 6822 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6823 0 : rule->tuples_mask.ip_tos; 6824 6825 spec->l4_proto = rule->tuples.ip_proto; 6826 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6827 0 : rule->tuples_mask.ip_proto; 6828 } 6829 6830 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6831 struct ethhdr *spec, 6832 struct ethhdr *spec_mask) 6833 { 6834 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6835 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6836 6837 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6838 eth_zero_addr(spec_mask->h_source); 6839 else 6840 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6841 6842 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6843 eth_zero_addr(spec_mask->h_dest); 6844 else 6845 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6846 6847 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6848 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6849 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6850 } 6851 6852 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6853 struct hclge_fd_rule *rule) 6854 { 6855 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6856 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6857 fs->h_ext.data[0] = 0; 6858 fs->h_ext.data[1] = 0; 6859 fs->m_ext.data[0] = 0; 6860 fs->m_ext.data[1] = 0; 6861 } else { 6862 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6863 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6864 fs->m_ext.data[0] = 6865 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6866 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6867 } 6868 } 6869 6870 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6871 struct hclge_fd_rule *rule) 6872 { 6873 if (fs->flow_type & FLOW_EXT) { 6874 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6875 fs->m_ext.vlan_tci = 6876 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6877 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6878 6879 hclge_fd_get_user_def_info(fs, rule); 6880 } 6881 6882 if (fs->flow_type & FLOW_MAC_EXT) { 6883 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6884 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6885 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6886 else 6887 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6888 rule->tuples_mask.dst_mac); 6889 } 6890 } 6891 6892 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6893 u16 location) 6894 { 6895 struct hclge_fd_rule *rule = NULL; 6896 struct hlist_node *node2; 6897 6898 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6899 if (rule->location == location) 6900 return rule; 6901 else if (rule->location > location) 6902 return NULL; 6903 } 6904 6905 return NULL; 6906 } 6907 6908 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6909 struct hclge_fd_rule *rule) 6910 { 6911 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6912 fs->ring_cookie = RX_CLS_FLOW_DISC; 6913 } else { 6914 u64 vf_id; 6915 6916 fs->ring_cookie = rule->queue_id; 6917 vf_id = rule->vf_id; 6918 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6919 fs->ring_cookie |= vf_id; 6920 } 6921 } 6922 6923 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6924 struct ethtool_rxnfc *cmd) 6925 { 6926 struct hclge_vport *vport = hclge_get_vport(handle); 6927 struct hclge_fd_rule *rule = NULL; 6928 struct hclge_dev *hdev = vport->back; 6929 struct ethtool_rx_flow_spec *fs; 6930 6931 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6932 return -EOPNOTSUPP; 6933 6934 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6935 6936 spin_lock_bh(&hdev->fd_rule_lock); 6937 6938 rule = hclge_get_fd_rule(hdev, fs->location); 6939 if (!rule) { 6940 spin_unlock_bh(&hdev->fd_rule_lock); 6941 return -ENOENT; 6942 } 6943 6944 fs->flow_type = rule->flow_type; 6945 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6946 case SCTP_V4_FLOW: 6947 case TCP_V4_FLOW: 6948 case UDP_V4_FLOW: 6949 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6950 &fs->m_u.tcp_ip4_spec); 6951 break; 6952 case IP_USER_FLOW: 6953 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6954 &fs->m_u.usr_ip4_spec); 6955 break; 6956 case SCTP_V6_FLOW: 6957 case TCP_V6_FLOW: 6958 case UDP_V6_FLOW: 6959 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6960 &fs->m_u.tcp_ip6_spec); 6961 break; 6962 case IPV6_USER_FLOW: 6963 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6964 &fs->m_u.usr_ip6_spec); 6965 break; 6966 /* The flow type of fd rule has been checked before adding in to rule 6967 * list. As other flow types have been handled, it must be ETHER_FLOW 6968 * for the default case 6969 */ 6970 default: 6971 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6972 &fs->m_u.ether_spec); 6973 break; 6974 } 6975 6976 hclge_fd_get_ext_info(fs, rule); 6977 6978 hclge_fd_get_ring_cookie(fs, rule); 6979 6980 spin_unlock_bh(&hdev->fd_rule_lock); 6981 6982 return 0; 6983 } 6984 6985 static int hclge_get_all_rules(struct hnae3_handle *handle, 6986 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6987 { 6988 struct hclge_vport *vport = hclge_get_vport(handle); 6989 struct hclge_dev *hdev = vport->back; 6990 struct hclge_fd_rule *rule; 6991 struct hlist_node *node2; 6992 u32 cnt = 0; 6993 6994 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6995 return -EOPNOTSUPP; 6996 6997 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6998 6999 spin_lock_bh(&hdev->fd_rule_lock); 7000 hlist_for_each_entry_safe(rule, node2, 7001 &hdev->fd_rule_list, rule_node) { 7002 if (cnt == cmd->rule_cnt) { 7003 spin_unlock_bh(&hdev->fd_rule_lock); 7004 return -EMSGSIZE; 7005 } 7006 7007 if (rule->state == HCLGE_FD_TO_DEL) 7008 continue; 7009 7010 rule_locs[cnt] = rule->location; 7011 cnt++; 7012 } 7013 7014 spin_unlock_bh(&hdev->fd_rule_lock); 7015 7016 cmd->rule_cnt = cnt; 7017 7018 return 0; 7019 } 7020 7021 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 7022 struct hclge_fd_rule_tuples *tuples) 7023 { 7024 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 7025 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 7026 7027 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 7028 tuples->ip_proto = fkeys->basic.ip_proto; 7029 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 7030 7031 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 7032 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 7033 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 7034 } else { 7035 int i; 7036 7037 for (i = 0; i < IPV6_ADDR_WORDS; i++) { 7038 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 7039 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 7040 } 7041 } 7042 } 7043 7044 /* traverse all rules, check whether an existed rule has the same tuples */ 7045 static struct hclge_fd_rule * 7046 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 7047 const struct hclge_fd_rule_tuples *tuples) 7048 { 7049 struct hclge_fd_rule *rule = NULL; 7050 struct hlist_node *node; 7051 7052 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7053 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 7054 return rule; 7055 } 7056 7057 return NULL; 7058 } 7059 7060 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 7061 struct hclge_fd_rule *rule) 7062 { 7063 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 7064 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 7065 BIT(INNER_SRC_PORT); 7066 rule->action = 0; 7067 rule->vf_id = 0; 7068 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 7069 rule->state = HCLGE_FD_TO_ADD; 7070 if (tuples->ether_proto == ETH_P_IP) { 7071 if (tuples->ip_proto == IPPROTO_TCP) 7072 rule->flow_type = TCP_V4_FLOW; 7073 else 7074 rule->flow_type = UDP_V4_FLOW; 7075 } else { 7076 if (tuples->ip_proto == IPPROTO_TCP) 7077 rule->flow_type = TCP_V6_FLOW; 7078 else 7079 rule->flow_type = UDP_V6_FLOW; 7080 } 7081 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7082 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7083 } 7084 7085 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7086 u16 flow_id, struct flow_keys *fkeys) 7087 { 7088 struct hclge_vport *vport = hclge_get_vport(handle); 7089 struct hclge_fd_rule_tuples new_tuples = {}; 7090 struct hclge_dev *hdev = vport->back; 7091 struct hclge_fd_rule *rule; 7092 u16 bit_id; 7093 7094 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7095 return -EOPNOTSUPP; 7096 7097 /* when there is already fd rule existed add by user, 7098 * arfs should not work 7099 */ 7100 spin_lock_bh(&hdev->fd_rule_lock); 7101 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7102 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7103 spin_unlock_bh(&hdev->fd_rule_lock); 7104 return -EOPNOTSUPP; 7105 } 7106 7107 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7108 7109 /* check is there flow director filter existed for this flow, 7110 * if not, create a new filter for it; 7111 * if filter exist with different queue id, modify the filter; 7112 * if filter exist with same queue id, do nothing 7113 */ 7114 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7115 if (!rule) { 7116 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7117 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7118 spin_unlock_bh(&hdev->fd_rule_lock); 7119 return -ENOSPC; 7120 } 7121 7122 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7123 if (!rule) { 7124 spin_unlock_bh(&hdev->fd_rule_lock); 7125 return -ENOMEM; 7126 } 7127 7128 rule->location = bit_id; 7129 rule->arfs.flow_id = flow_id; 7130 rule->queue_id = queue_id; 7131 hclge_fd_build_arfs_rule(&new_tuples, rule); 7132 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7133 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7134 } else if (rule->queue_id != queue_id) { 7135 rule->queue_id = queue_id; 7136 rule->state = HCLGE_FD_TO_ADD; 7137 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7138 hclge_task_schedule(hdev, 0); 7139 } 7140 spin_unlock_bh(&hdev->fd_rule_lock); 7141 return rule->location; 7142 } 7143 7144 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7145 { 7146 #ifdef CONFIG_RFS_ACCEL 7147 struct hnae3_handle *handle = &hdev->vport[0].nic; 7148 struct hclge_fd_rule *rule; 7149 struct hlist_node *node; 7150 7151 spin_lock_bh(&hdev->fd_rule_lock); 7152 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7153 spin_unlock_bh(&hdev->fd_rule_lock); 7154 return; 7155 } 7156 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7157 if (rule->state != HCLGE_FD_ACTIVE) 7158 continue; 7159 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7160 rule->arfs.flow_id, rule->location)) { 7161 rule->state = HCLGE_FD_TO_DEL; 7162 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7163 } 7164 } 7165 spin_unlock_bh(&hdev->fd_rule_lock); 7166 #endif 7167 } 7168 7169 /* make sure being called after lock up with fd_rule_lock */ 7170 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7171 { 7172 #ifdef CONFIG_RFS_ACCEL 7173 struct hclge_fd_rule *rule; 7174 struct hlist_node *node; 7175 int ret; 7176 7177 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7178 return 0; 7179 7180 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7181 switch (rule->state) { 7182 case HCLGE_FD_TO_DEL: 7183 case HCLGE_FD_ACTIVE: 7184 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7185 rule->location, NULL, false); 7186 if (ret) 7187 return ret; 7188 fallthrough; 7189 case HCLGE_FD_TO_ADD: 7190 hclge_fd_dec_rule_cnt(hdev, rule->location); 7191 hlist_del(&rule->rule_node); 7192 kfree(rule); 7193 break; 7194 default: 7195 break; 7196 } 7197 } 7198 hclge_sync_fd_state(hdev); 7199 7200 #endif 7201 return 0; 7202 } 7203 7204 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7205 struct hclge_fd_rule *rule) 7206 { 7207 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7208 struct flow_match_basic match; 7209 u16 ethtype_key, ethtype_mask; 7210 7211 flow_rule_match_basic(flow, &match); 7212 ethtype_key = ntohs(match.key->n_proto); 7213 ethtype_mask = ntohs(match.mask->n_proto); 7214 7215 if (ethtype_key == ETH_P_ALL) { 7216 ethtype_key = 0; 7217 ethtype_mask = 0; 7218 } 7219 rule->tuples.ether_proto = ethtype_key; 7220 rule->tuples_mask.ether_proto = ethtype_mask; 7221 rule->tuples.ip_proto = match.key->ip_proto; 7222 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7223 } else { 7224 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7225 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7226 } 7227 } 7228 7229 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7230 struct hclge_fd_rule *rule) 7231 { 7232 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7233 struct flow_match_eth_addrs match; 7234 7235 flow_rule_match_eth_addrs(flow, &match); 7236 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7237 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7238 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7239 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7240 } else { 7241 rule->unused_tuple |= BIT(INNER_DST_MAC); 7242 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7243 } 7244 } 7245 7246 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7247 struct hclge_fd_rule *rule) 7248 { 7249 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7250 struct flow_match_vlan match; 7251 7252 flow_rule_match_vlan(flow, &match); 7253 rule->tuples.vlan_tag1 = match.key->vlan_id | 7254 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7255 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7256 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7257 } else { 7258 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7259 } 7260 } 7261 7262 static int hclge_get_cls_key_ip(const struct flow_rule *flow, 7263 struct hclge_fd_rule *rule, 7264 struct netlink_ext_ack *extack) 7265 { 7266 u16 addr_type = 0; 7267 7268 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7269 struct flow_match_control match; 7270 7271 flow_rule_match_control(flow, &match); 7272 addr_type = match.key->addr_type; 7273 7274 if (flow_rule_has_control_flags(match.mask->flags, extack)) 7275 return -EOPNOTSUPP; 7276 } 7277 7278 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7279 struct flow_match_ipv4_addrs match; 7280 7281 flow_rule_match_ipv4_addrs(flow, &match); 7282 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7283 rule->tuples_mask.src_ip[IPV4_INDEX] = 7284 be32_to_cpu(match.mask->src); 7285 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7286 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7287 be32_to_cpu(match.mask->dst); 7288 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7289 struct flow_match_ipv6_addrs match; 7290 7291 flow_rule_match_ipv6_addrs(flow, &match); 7292 ipv6_addr_be32_to_cpu(rule->tuples.src_ip, 7293 match.key->src.s6_addr32); 7294 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, 7295 match.mask->src.s6_addr32); 7296 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, 7297 match.key->dst.s6_addr32); 7298 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, 7299 match.mask->dst.s6_addr32); 7300 } else { 7301 rule->unused_tuple |= BIT(INNER_SRC_IP); 7302 rule->unused_tuple |= BIT(INNER_DST_IP); 7303 } 7304 7305 return 0; 7306 } 7307 7308 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7309 struct hclge_fd_rule *rule) 7310 { 7311 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7312 struct flow_match_ports match; 7313 7314 flow_rule_match_ports(flow, &match); 7315 7316 rule->tuples.src_port = be16_to_cpu(match.key->src); 7317 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7318 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7319 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7320 } else { 7321 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7322 rule->unused_tuple |= BIT(INNER_DST_PORT); 7323 } 7324 } 7325 7326 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7327 struct flow_cls_offload *cls_flower, 7328 struct hclge_fd_rule *rule) 7329 { 7330 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7331 struct netlink_ext_ack *extack = cls_flower->common.extack; 7332 struct flow_dissector *dissector = flow->match.dissector; 7333 int ret; 7334 7335 if (dissector->used_keys & 7336 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 7337 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 7338 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7339 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 7340 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7341 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7342 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) { 7343 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n", 7344 dissector->used_keys); 7345 return -EOPNOTSUPP; 7346 } 7347 7348 hclge_get_cls_key_basic(flow, rule); 7349 hclge_get_cls_key_mac(flow, rule); 7350 hclge_get_cls_key_vlan(flow, rule); 7351 7352 ret = hclge_get_cls_key_ip(flow, rule, extack); 7353 if (ret) 7354 return ret; 7355 7356 hclge_get_cls_key_port(flow, rule); 7357 7358 return 0; 7359 } 7360 7361 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7362 struct flow_cls_offload *cls_flower, int tc) 7363 { 7364 u32 prio = cls_flower->common.prio; 7365 7366 if (tc < 0 || tc > hdev->tc_max) { 7367 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7368 return -EINVAL; 7369 } 7370 7371 if (prio == 0 || 7372 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7373 dev_err(&hdev->pdev->dev, 7374 "prio %u should be in range[1, %u]\n", 7375 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7376 return -EINVAL; 7377 } 7378 7379 if (test_bit(prio - 1, hdev->fd_bmap)) { 7380 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7381 return -EINVAL; 7382 } 7383 return 0; 7384 } 7385 7386 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7387 struct flow_cls_offload *cls_flower, 7388 int tc) 7389 { 7390 struct hclge_vport *vport = hclge_get_vport(handle); 7391 struct hclge_dev *hdev = vport->back; 7392 struct hclge_fd_rule *rule; 7393 int ret; 7394 7395 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7396 dev_err(&hdev->pdev->dev, 7397 "cls flower is not supported\n"); 7398 return -EOPNOTSUPP; 7399 } 7400 7401 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7402 if (ret) { 7403 dev_err(&hdev->pdev->dev, 7404 "failed to check cls flower params, ret = %d\n", ret); 7405 return ret; 7406 } 7407 7408 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7409 if (!rule) 7410 return -ENOMEM; 7411 7412 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7413 if (ret) { 7414 kfree(rule); 7415 return ret; 7416 } 7417 7418 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7419 rule->cls_flower.tc = tc; 7420 rule->location = cls_flower->common.prio - 1; 7421 rule->vf_id = 0; 7422 rule->cls_flower.cookie = cls_flower->cookie; 7423 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7424 7425 ret = hclge_add_fd_entry_common(hdev, rule); 7426 if (ret) 7427 kfree(rule); 7428 7429 return ret; 7430 } 7431 7432 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7433 unsigned long cookie) 7434 { 7435 struct hclge_fd_rule *rule; 7436 struct hlist_node *node; 7437 7438 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7439 if (rule->cls_flower.cookie == cookie) 7440 return rule; 7441 } 7442 7443 return NULL; 7444 } 7445 7446 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7447 struct flow_cls_offload *cls_flower) 7448 { 7449 struct hclge_vport *vport = hclge_get_vport(handle); 7450 struct hclge_dev *hdev = vport->back; 7451 struct hclge_fd_rule *rule; 7452 int ret; 7453 7454 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7455 return -EOPNOTSUPP; 7456 7457 spin_lock_bh(&hdev->fd_rule_lock); 7458 7459 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7460 if (!rule) { 7461 spin_unlock_bh(&hdev->fd_rule_lock); 7462 return -EINVAL; 7463 } 7464 7465 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7466 NULL, false); 7467 if (ret) { 7468 /* if tcam config fail, set rule state to TO_DEL, 7469 * so the rule will be deleted when periodic 7470 * task being scheduled. 7471 */ 7472 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL); 7473 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7474 spin_unlock_bh(&hdev->fd_rule_lock); 7475 return ret; 7476 } 7477 7478 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7479 spin_unlock_bh(&hdev->fd_rule_lock); 7480 7481 return 0; 7482 } 7483 7484 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7485 { 7486 struct hclge_fd_rule *rule; 7487 struct hlist_node *node; 7488 int ret = 0; 7489 7490 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7491 return; 7492 7493 spin_lock_bh(&hdev->fd_rule_lock); 7494 7495 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7496 switch (rule->state) { 7497 case HCLGE_FD_TO_ADD: 7498 ret = hclge_fd_config_rule(hdev, rule); 7499 if (ret) 7500 goto out; 7501 rule->state = HCLGE_FD_ACTIVE; 7502 break; 7503 case HCLGE_FD_TO_DEL: 7504 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7505 rule->location, NULL, false); 7506 if (ret) 7507 goto out; 7508 hclge_fd_dec_rule_cnt(hdev, rule->location); 7509 hclge_fd_free_node(hdev, rule); 7510 break; 7511 default: 7512 break; 7513 } 7514 } 7515 7516 out: 7517 if (ret) 7518 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7519 7520 spin_unlock_bh(&hdev->fd_rule_lock); 7521 } 7522 7523 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7524 { 7525 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7526 return; 7527 7528 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7529 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7530 7531 hclge_clear_fd_rules_in_list(hdev, clear_list); 7532 } 7533 7534 hclge_sync_fd_user_def_cfg(hdev, false); 7535 7536 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7537 } 7538 7539 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7540 { 7541 struct hclge_vport *vport = hclge_get_vport(handle); 7542 struct hclge_dev *hdev = vport->back; 7543 7544 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7545 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7546 } 7547 7548 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7549 { 7550 struct hclge_vport *vport = hclge_get_vport(handle); 7551 struct hclge_dev *hdev = vport->back; 7552 7553 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7554 } 7555 7556 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7557 { 7558 struct hclge_vport *vport = hclge_get_vport(handle); 7559 struct hclge_dev *hdev = vport->back; 7560 7561 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7562 } 7563 7564 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7565 { 7566 struct hclge_vport *vport = hclge_get_vport(handle); 7567 struct hclge_dev *hdev = vport->back; 7568 7569 return hdev->rst_stats.hw_reset_done_cnt; 7570 } 7571 7572 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7573 { 7574 struct hclge_vport *vport = hclge_get_vport(handle); 7575 struct hclge_dev *hdev = vport->back; 7576 7577 hdev->fd_en = enable; 7578 7579 if (!enable) 7580 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7581 else 7582 hclge_restore_fd_entries(handle); 7583 7584 hclge_task_schedule(hdev, 0); 7585 } 7586 7587 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7588 { 7589 #define HCLGE_LINK_STATUS_WAIT_CNT 3 7590 7591 struct hclge_desc desc; 7592 struct hclge_config_mac_mode_cmd *req = 7593 (struct hclge_config_mac_mode_cmd *)desc.data; 7594 u32 loop_en = 0; 7595 int ret; 7596 7597 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7598 7599 if (enable) { 7600 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7601 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7602 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7603 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7604 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7605 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7606 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7607 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7608 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7609 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7610 } 7611 7612 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7613 7614 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7615 if (ret) { 7616 dev_err(&hdev->pdev->dev, 7617 "mac enable fail, ret =%d.\n", ret); 7618 return; 7619 } 7620 7621 if (!enable) 7622 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7623 HCLGE_LINK_STATUS_WAIT_CNT); 7624 } 7625 7626 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7627 u8 switch_param, u8 param_mask) 7628 { 7629 struct hclge_mac_vlan_switch_cmd *req; 7630 struct hclge_desc desc; 7631 u32 func_id; 7632 int ret; 7633 7634 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7635 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7636 7637 /* read current config parameter */ 7638 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7639 true); 7640 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7641 req->func_id = cpu_to_le32(func_id); 7642 7643 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7644 if (ret) { 7645 dev_err(&hdev->pdev->dev, 7646 "read mac vlan switch parameter fail, ret = %d\n", ret); 7647 return ret; 7648 } 7649 7650 /* modify and write new config parameter */ 7651 hclge_comm_cmd_reuse_desc(&desc, false); 7652 req->switch_param = (req->switch_param & param_mask) | switch_param; 7653 req->param_mask = param_mask; 7654 7655 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7656 if (ret) 7657 dev_err(&hdev->pdev->dev, 7658 "set mac vlan switch parameter fail, ret = %d\n", ret); 7659 return ret; 7660 } 7661 7662 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7663 int link_ret) 7664 { 7665 #define HCLGE_PHY_LINK_STATUS_NUM 200 7666 7667 struct phy_device *phydev = hdev->hw.mac.phydev; 7668 int i = 0; 7669 int ret; 7670 7671 do { 7672 ret = phy_read_status(phydev); 7673 if (ret) { 7674 dev_err(&hdev->pdev->dev, 7675 "phy update link status fail, ret = %d\n", ret); 7676 return; 7677 } 7678 7679 if (phydev->link == link_ret) 7680 break; 7681 7682 msleep(HCLGE_LINK_STATUS_MS); 7683 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7684 } 7685 7686 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7687 int wait_cnt) 7688 { 7689 int link_status; 7690 int i = 0; 7691 int ret; 7692 7693 do { 7694 ret = hclge_get_mac_link_status(hdev, &link_status); 7695 if (ret) 7696 return ret; 7697 if (link_status == link_ret) 7698 return 0; 7699 7700 msleep(HCLGE_LINK_STATUS_MS); 7701 } while (++i < wait_cnt); 7702 return -EBUSY; 7703 } 7704 7705 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7706 bool is_phy) 7707 { 7708 #define HCLGE_MAC_LINK_STATUS_NUM 100 7709 7710 int link_ret; 7711 7712 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7713 7714 if (is_phy) 7715 hclge_phy_link_status_wait(hdev, link_ret); 7716 7717 return hclge_mac_link_status_wait(hdev, link_ret, 7718 HCLGE_MAC_LINK_STATUS_NUM); 7719 } 7720 7721 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7722 { 7723 struct hclge_config_mac_mode_cmd *req; 7724 struct hclge_desc desc; 7725 u32 loop_en; 7726 int ret; 7727 7728 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7729 /* 1 Read out the MAC mode config at first */ 7730 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7731 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7732 if (ret) { 7733 dev_err(&hdev->pdev->dev, 7734 "mac loopback get fail, ret =%d.\n", ret); 7735 return ret; 7736 } 7737 7738 /* 2 Then setup the loopback flag */ 7739 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7740 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7741 7742 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7743 7744 /* 3 Config mac work mode with loopback flag 7745 * and its original configure parameters 7746 */ 7747 hclge_comm_cmd_reuse_desc(&desc, false); 7748 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7749 if (ret) 7750 dev_err(&hdev->pdev->dev, 7751 "mac loopback set fail, ret =%d.\n", ret); 7752 return ret; 7753 } 7754 7755 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7756 enum hnae3_loop loop_mode) 7757 { 7758 struct hclge_common_lb_cmd *req; 7759 struct hclge_desc desc; 7760 u8 loop_mode_b; 7761 int ret; 7762 7763 req = (struct hclge_common_lb_cmd *)desc.data; 7764 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7765 7766 switch (loop_mode) { 7767 case HNAE3_LOOP_SERIAL_SERDES: 7768 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7769 break; 7770 case HNAE3_LOOP_PARALLEL_SERDES: 7771 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7772 break; 7773 case HNAE3_LOOP_PHY: 7774 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7775 break; 7776 default: 7777 dev_err(&hdev->pdev->dev, 7778 "unsupported loopback mode %d\n", loop_mode); 7779 return -ENOTSUPP; 7780 } 7781 7782 req->mask = loop_mode_b; 7783 if (en) 7784 req->enable = loop_mode_b; 7785 7786 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7787 if (ret) 7788 dev_err(&hdev->pdev->dev, 7789 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7790 loop_mode, ret); 7791 7792 return ret; 7793 } 7794 7795 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7796 { 7797 #define HCLGE_COMMON_LB_RETRY_MS 10 7798 #define HCLGE_COMMON_LB_RETRY_NUM 100 7799 7800 struct hclge_common_lb_cmd *req; 7801 struct hclge_desc desc; 7802 u32 i = 0; 7803 int ret; 7804 7805 req = (struct hclge_common_lb_cmd *)desc.data; 7806 7807 do { 7808 msleep(HCLGE_COMMON_LB_RETRY_MS); 7809 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7810 true); 7811 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7812 if (ret) { 7813 dev_err(&hdev->pdev->dev, 7814 "failed to get loopback done status, ret = %d\n", 7815 ret); 7816 return ret; 7817 } 7818 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7819 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7820 7821 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7822 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7823 return -EBUSY; 7824 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7825 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7826 return -EIO; 7827 } 7828 7829 return 0; 7830 } 7831 7832 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7833 enum hnae3_loop loop_mode) 7834 { 7835 int ret; 7836 7837 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7838 if (ret) 7839 return ret; 7840 7841 return hclge_cfg_common_loopback_wait(hdev); 7842 } 7843 7844 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7845 enum hnae3_loop loop_mode) 7846 { 7847 int ret; 7848 7849 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7850 if (ret) 7851 return ret; 7852 7853 hclge_cfg_mac_mode(hdev, en); 7854 7855 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7856 if (ret) 7857 dev_err(&hdev->pdev->dev, 7858 "serdes loopback config mac mode timeout\n"); 7859 7860 return ret; 7861 } 7862 7863 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7864 struct phy_device *phydev) 7865 { 7866 int ret; 7867 7868 if (!phydev->suspended) { 7869 ret = phy_suspend(phydev); 7870 if (ret) 7871 return ret; 7872 } 7873 7874 ret = phy_resume(phydev); 7875 if (ret) 7876 return ret; 7877 7878 return phy_loopback(phydev, true, 0); 7879 } 7880 7881 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7882 struct phy_device *phydev) 7883 { 7884 int ret; 7885 7886 ret = phy_loopback(phydev, false, 0); 7887 if (ret) 7888 return ret; 7889 7890 return phy_suspend(phydev); 7891 } 7892 7893 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7894 { 7895 struct phy_device *phydev = hdev->hw.mac.phydev; 7896 int ret; 7897 7898 if (!phydev) { 7899 if (hnae3_dev_phy_imp_supported(hdev)) 7900 return hclge_set_common_loopback(hdev, en, 7901 HNAE3_LOOP_PHY); 7902 return -ENOTSUPP; 7903 } 7904 7905 if (en) 7906 ret = hclge_enable_phy_loopback(hdev, phydev); 7907 else 7908 ret = hclge_disable_phy_loopback(hdev, phydev); 7909 if (ret) { 7910 dev_err(&hdev->pdev->dev, 7911 "set phy loopback fail, ret = %d\n", ret); 7912 return ret; 7913 } 7914 7915 hclge_cfg_mac_mode(hdev, en); 7916 7917 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7918 if (ret) 7919 dev_err(&hdev->pdev->dev, 7920 "phy loopback config mac mode timeout\n"); 7921 7922 return ret; 7923 } 7924 7925 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7926 u16 stream_id, bool enable) 7927 { 7928 struct hclge_desc desc; 7929 struct hclge_cfg_com_tqp_queue_cmd *req = 7930 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7931 7932 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7933 req->tqp_id = cpu_to_le16(tqp_id); 7934 req->stream_id = cpu_to_le16(stream_id); 7935 if (enable) 7936 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7937 7938 return hclge_cmd_send(&hdev->hw, &desc, 1); 7939 } 7940 7941 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7942 { 7943 struct hclge_vport *vport = hclge_get_vport(handle); 7944 struct hclge_dev *hdev = vport->back; 7945 int ret; 7946 u16 i; 7947 7948 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7949 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7950 if (ret) 7951 return ret; 7952 } 7953 return 0; 7954 } 7955 7956 static int hclge_set_loopback(struct hnae3_handle *handle, 7957 enum hnae3_loop loop_mode, bool en) 7958 { 7959 struct hclge_vport *vport = hclge_get_vport(handle); 7960 struct hclge_dev *hdev = vport->back; 7961 int ret = 0; 7962 7963 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7964 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7965 * the same, the packets are looped back in the SSU. If SSU loopback 7966 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7967 */ 7968 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7969 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7970 7971 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7972 HCLGE_SWITCH_ALW_LPBK_MASK); 7973 if (ret) 7974 return ret; 7975 } 7976 7977 switch (loop_mode) { 7978 case HNAE3_LOOP_APP: 7979 ret = hclge_set_app_loopback(hdev, en); 7980 break; 7981 case HNAE3_LOOP_SERIAL_SERDES: 7982 case HNAE3_LOOP_PARALLEL_SERDES: 7983 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7984 break; 7985 case HNAE3_LOOP_PHY: 7986 ret = hclge_set_phy_loopback(hdev, en); 7987 break; 7988 case HNAE3_LOOP_EXTERNAL: 7989 break; 7990 default: 7991 ret = -ENOTSUPP; 7992 dev_err(&hdev->pdev->dev, 7993 "loop_mode %d is not supported\n", loop_mode); 7994 break; 7995 } 7996 7997 if (ret) 7998 return ret; 7999 8000 ret = hclge_tqp_enable(handle, en); 8001 if (ret) 8002 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 8003 str_enable_disable(en), ret); 8004 8005 return ret; 8006 } 8007 8008 static int hclge_set_default_loopback(struct hclge_dev *hdev) 8009 { 8010 int ret; 8011 8012 ret = hclge_set_app_loopback(hdev, false); 8013 if (ret) 8014 return ret; 8015 8016 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 8017 if (ret) 8018 return ret; 8019 8020 return hclge_cfg_common_loopback(hdev, false, 8021 HNAE3_LOOP_PARALLEL_SERDES); 8022 } 8023 8024 static void hclge_flush_link_update(struct hclge_dev *hdev) 8025 { 8026 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 8027 8028 unsigned long last = hdev->serv_processed_cnt; 8029 int i = 0; 8030 8031 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 8032 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 8033 last == hdev->serv_processed_cnt) 8034 usleep_range(1, 1); 8035 } 8036 8037 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 8038 { 8039 struct hclge_vport *vport = hclge_get_vport(handle); 8040 struct hclge_dev *hdev = vport->back; 8041 8042 if (enable) { 8043 hclge_task_schedule(hdev, 0); 8044 } else { 8045 /* Set the DOWN flag here to disable link updating */ 8046 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8047 8048 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 8049 hclge_flush_link_update(hdev); 8050 } 8051 } 8052 8053 static int hclge_ae_start(struct hnae3_handle *handle) 8054 { 8055 struct hclge_vport *vport = hclge_get_vport(handle); 8056 struct hclge_dev *hdev = vport->back; 8057 8058 /* mac enable */ 8059 hclge_cfg_mac_mode(hdev, true); 8060 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 8061 hdev->hw.mac.link = 0; 8062 8063 /* reset tqp stats */ 8064 hclge_comm_reset_tqp_stats(handle); 8065 8066 hclge_mac_start_phy(hdev); 8067 8068 return 0; 8069 } 8070 8071 static void hclge_ae_stop(struct hnae3_handle *handle) 8072 { 8073 struct hclge_vport *vport = hclge_get_vport(handle); 8074 struct hclge_dev *hdev = vport->back; 8075 8076 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8077 spin_lock_bh(&hdev->fd_rule_lock); 8078 hclge_clear_arfs_rules(hdev); 8079 spin_unlock_bh(&hdev->fd_rule_lock); 8080 8081 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8082 * so it only need to stop phy here. 8083 */ 8084 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 8085 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 8086 HCLGE_PFC_DISABLE); 8087 if (hdev->reset_type != HNAE3_FUNC_RESET && 8088 hdev->reset_type != HNAE3_FLR_RESET) { 8089 hclge_mac_stop_phy(hdev); 8090 hclge_update_link_status(hdev); 8091 return; 8092 } 8093 } 8094 8095 hclge_reset_tqp(handle); 8096 8097 hclge_config_mac_tnl_int(hdev, false); 8098 8099 /* Mac disable */ 8100 hclge_cfg_mac_mode(hdev, false); 8101 8102 hclge_mac_stop_phy(hdev); 8103 8104 /* reset tqp stats */ 8105 hclge_comm_reset_tqp_stats(handle); 8106 hclge_update_link_status(hdev); 8107 } 8108 8109 int hclge_vport_start(struct hclge_vport *vport) 8110 { 8111 struct hclge_dev *hdev = vport->back; 8112 8113 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8114 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8115 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8116 vport->last_active_jiffies = jiffies; 8117 vport->need_notify = 0; 8118 8119 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8120 if (vport->vport_id) { 8121 hclge_restore_mac_table_common(vport); 8122 hclge_restore_vport_vlan_table(vport); 8123 } else { 8124 hclge_restore_hw_table(hdev); 8125 } 8126 } 8127 8128 clear_bit(vport->vport_id, hdev->vport_config_block); 8129 8130 return 0; 8131 } 8132 8133 void hclge_vport_stop(struct hclge_vport *vport) 8134 { 8135 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8136 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8137 vport->need_notify = 0; 8138 } 8139 8140 static int hclge_client_start(struct hnae3_handle *handle) 8141 { 8142 struct hclge_vport *vport = hclge_get_vport(handle); 8143 8144 return hclge_vport_start(vport); 8145 } 8146 8147 static void hclge_client_stop(struct hnae3_handle *handle) 8148 { 8149 struct hclge_vport *vport = hclge_get_vport(handle); 8150 8151 hclge_vport_stop(vport); 8152 } 8153 8154 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8155 u16 cmdq_resp, u8 resp_code, 8156 enum hclge_mac_vlan_tbl_opcode op) 8157 { 8158 struct hclge_dev *hdev = vport->back; 8159 8160 if (cmdq_resp) { 8161 dev_err(&hdev->pdev->dev, 8162 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8163 cmdq_resp); 8164 return -EIO; 8165 } 8166 8167 if (op == HCLGE_MAC_VLAN_ADD) { 8168 if (!resp_code || resp_code == 1) 8169 return 0; 8170 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8171 resp_code == HCLGE_ADD_MC_OVERFLOW) 8172 return -ENOSPC; 8173 8174 dev_err(&hdev->pdev->dev, 8175 "add mac addr failed for undefined, code=%u.\n", 8176 resp_code); 8177 return -EIO; 8178 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8179 if (!resp_code) { 8180 return 0; 8181 } else if (resp_code == 1) { 8182 dev_dbg(&hdev->pdev->dev, 8183 "remove mac addr failed for miss.\n"); 8184 return -ENOENT; 8185 } 8186 8187 dev_err(&hdev->pdev->dev, 8188 "remove mac addr failed for undefined, code=%u.\n", 8189 resp_code); 8190 return -EIO; 8191 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8192 if (!resp_code) { 8193 return 0; 8194 } else if (resp_code == 1) { 8195 dev_dbg(&hdev->pdev->dev, 8196 "lookup mac addr failed for miss.\n"); 8197 return -ENOENT; 8198 } 8199 8200 dev_err(&hdev->pdev->dev, 8201 "lookup mac addr failed for undefined, code=%u.\n", 8202 resp_code); 8203 return -EIO; 8204 } 8205 8206 dev_err(&hdev->pdev->dev, 8207 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8208 8209 return -EINVAL; 8210 } 8211 8212 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8213 { 8214 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8215 8216 unsigned int word_num; 8217 unsigned int bit_num; 8218 8219 if (vfid > 255 || vfid < 0) 8220 return -EIO; 8221 8222 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8223 word_num = vfid / 32; 8224 bit_num = vfid % 32; 8225 if (clr) 8226 desc[1].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 8227 else 8228 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8229 } else { 8230 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8231 bit_num = vfid % 32; 8232 if (clr) 8233 desc[2].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 8234 else 8235 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8236 } 8237 8238 return 0; 8239 } 8240 8241 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8242 { 8243 #define HCLGE_DESC_NUMBER 3 8244 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8245 int i, j; 8246 8247 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8248 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8249 if (desc[i].data[j]) 8250 return false; 8251 8252 return true; 8253 } 8254 8255 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8256 const u8 *addr, bool is_mc) 8257 { 8258 const unsigned char *mac_addr = addr; 8259 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8260 (mac_addr[0]) | (mac_addr[1] << 8); 8261 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8262 8263 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8264 if (is_mc) { 8265 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8266 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8267 } 8268 8269 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8270 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8271 } 8272 8273 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8274 struct hclge_mac_vlan_tbl_entry_cmd *req) 8275 { 8276 struct hclge_dev *hdev = vport->back; 8277 struct hclge_desc desc; 8278 u8 resp_code; 8279 u16 retval; 8280 int ret; 8281 8282 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8283 8284 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8285 8286 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8287 if (ret) { 8288 dev_err(&hdev->pdev->dev, 8289 "del mac addr failed for cmd_send, ret =%d.\n", 8290 ret); 8291 return ret; 8292 } 8293 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8294 retval = le16_to_cpu(desc.retval); 8295 8296 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8297 HCLGE_MAC_VLAN_REMOVE); 8298 } 8299 8300 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8301 struct hclge_mac_vlan_tbl_entry_cmd *req, 8302 struct hclge_desc *desc, 8303 bool is_mc) 8304 { 8305 struct hclge_dev *hdev = vport->back; 8306 u8 resp_code; 8307 u16 retval; 8308 int ret; 8309 8310 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8311 if (is_mc) { 8312 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8313 memcpy(desc[0].data, 8314 req, 8315 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8316 hclge_cmd_setup_basic_desc(&desc[1], 8317 HCLGE_OPC_MAC_VLAN_ADD, 8318 true); 8319 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8320 hclge_cmd_setup_basic_desc(&desc[2], 8321 HCLGE_OPC_MAC_VLAN_ADD, 8322 true); 8323 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8324 } else { 8325 memcpy(desc[0].data, 8326 req, 8327 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8328 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8329 } 8330 if (ret) { 8331 dev_err(&hdev->pdev->dev, 8332 "lookup mac addr failed for cmd_send, ret =%d.\n", 8333 ret); 8334 return ret; 8335 } 8336 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8337 retval = le16_to_cpu(desc[0].retval); 8338 8339 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8340 HCLGE_MAC_VLAN_LKUP); 8341 } 8342 8343 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8344 struct hclge_mac_vlan_tbl_entry_cmd *req, 8345 struct hclge_desc *mc_desc) 8346 { 8347 struct hclge_dev *hdev = vport->back; 8348 int cfg_status; 8349 u8 resp_code; 8350 u16 retval; 8351 int ret; 8352 8353 if (!mc_desc) { 8354 struct hclge_desc desc; 8355 8356 hclge_cmd_setup_basic_desc(&desc, 8357 HCLGE_OPC_MAC_VLAN_ADD, 8358 false); 8359 memcpy(desc.data, req, 8360 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8361 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8362 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8363 retval = le16_to_cpu(desc.retval); 8364 8365 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8366 resp_code, 8367 HCLGE_MAC_VLAN_ADD); 8368 } else { 8369 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8370 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8371 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8372 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8373 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8374 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8375 memcpy(mc_desc[0].data, req, 8376 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8377 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8378 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8379 retval = le16_to_cpu(mc_desc[0].retval); 8380 8381 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8382 resp_code, 8383 HCLGE_MAC_VLAN_ADD); 8384 } 8385 8386 if (ret) { 8387 dev_err(&hdev->pdev->dev, 8388 "add mac addr failed for cmd_send, ret =%d.\n", 8389 ret); 8390 return ret; 8391 } 8392 8393 return cfg_status; 8394 } 8395 8396 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8397 u16 *allocated_size) 8398 { 8399 struct hclge_umv_spc_alc_cmd *req; 8400 struct hclge_desc desc; 8401 int ret; 8402 8403 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8404 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8405 8406 req->space_size = cpu_to_le32(space_size); 8407 8408 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8409 if (ret) { 8410 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8411 ret); 8412 return ret; 8413 } 8414 8415 *allocated_size = le32_to_cpu(desc.data[1]); 8416 8417 return 0; 8418 } 8419 8420 static int hclge_init_umv_space(struct hclge_dev *hdev) 8421 { 8422 u16 allocated_size = 0; 8423 int ret; 8424 8425 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8426 if (ret) 8427 return ret; 8428 8429 if (allocated_size < hdev->wanted_umv_size) 8430 dev_warn(&hdev->pdev->dev, 8431 "failed to alloc umv space, want %u, get %u\n", 8432 hdev->wanted_umv_size, allocated_size); 8433 8434 hdev->max_umv_size = allocated_size; 8435 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8436 hdev->share_umv_size = hdev->priv_umv_size + 8437 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8438 8439 if (hdev->ae_dev->dev_specs.mc_mac_size) 8440 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8441 8442 return 0; 8443 } 8444 8445 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8446 { 8447 struct hclge_vport *vport; 8448 int i; 8449 8450 for (i = 0; i < hdev->num_alloc_vport; i++) { 8451 vport = &hdev->vport[i]; 8452 vport->used_umv_num = 0; 8453 } 8454 8455 mutex_lock(&hdev->vport_lock); 8456 hdev->share_umv_size = hdev->priv_umv_size + 8457 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8458 mutex_unlock(&hdev->vport_lock); 8459 8460 hdev->used_mc_mac_num = 0; 8461 } 8462 8463 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8464 { 8465 struct hclge_dev *hdev = vport->back; 8466 bool is_full; 8467 8468 if (need_lock) 8469 mutex_lock(&hdev->vport_lock); 8470 8471 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8472 hdev->share_umv_size == 0); 8473 8474 if (need_lock) 8475 mutex_unlock(&hdev->vport_lock); 8476 8477 return is_full; 8478 } 8479 8480 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8481 { 8482 struct hclge_dev *hdev = vport->back; 8483 8484 if (is_free) { 8485 if (vport->used_umv_num > hdev->priv_umv_size) 8486 hdev->share_umv_size++; 8487 8488 if (vport->used_umv_num > 0) 8489 vport->used_umv_num--; 8490 } else { 8491 if (vport->used_umv_num >= hdev->priv_umv_size && 8492 hdev->share_umv_size > 0) 8493 hdev->share_umv_size--; 8494 vport->used_umv_num++; 8495 } 8496 } 8497 8498 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8499 const u8 *mac_addr) 8500 { 8501 struct hclge_mac_node *mac_node, *tmp; 8502 8503 list_for_each_entry_safe(mac_node, tmp, list, node) 8504 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8505 return mac_node; 8506 8507 return NULL; 8508 } 8509 8510 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8511 enum HCLGE_MAC_NODE_STATE state) 8512 { 8513 switch (state) { 8514 /* from set_rx_mode or tmp_add_list */ 8515 case HCLGE_MAC_TO_ADD: 8516 if (mac_node->state == HCLGE_MAC_TO_DEL) 8517 mac_node->state = HCLGE_MAC_ACTIVE; 8518 break; 8519 /* only from set_rx_mode */ 8520 case HCLGE_MAC_TO_DEL: 8521 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8522 list_del(&mac_node->node); 8523 kfree(mac_node); 8524 } else { 8525 mac_node->state = HCLGE_MAC_TO_DEL; 8526 } 8527 break; 8528 /* only from tmp_add_list, the mac_node->state won't be 8529 * ACTIVE. 8530 */ 8531 case HCLGE_MAC_ACTIVE: 8532 if (mac_node->state == HCLGE_MAC_TO_ADD) 8533 mac_node->state = HCLGE_MAC_ACTIVE; 8534 8535 break; 8536 } 8537 } 8538 8539 int hclge_update_mac_list(struct hclge_vport *vport, 8540 enum HCLGE_MAC_NODE_STATE state, 8541 enum HCLGE_MAC_ADDR_TYPE mac_type, 8542 const unsigned char *addr) 8543 { 8544 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8545 struct hclge_dev *hdev = vport->back; 8546 struct hclge_mac_node *mac_node; 8547 struct list_head *list; 8548 8549 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8550 &vport->uc_mac_list : &vport->mc_mac_list; 8551 8552 spin_lock_bh(&vport->mac_list_lock); 8553 8554 /* if the mac addr is already in the mac list, no need to add a new 8555 * one into it, just check the mac addr state, convert it to a new 8556 * state, or just remove it, or do nothing. 8557 */ 8558 mac_node = hclge_find_mac_node(list, addr); 8559 if (mac_node) { 8560 hclge_update_mac_node(mac_node, state); 8561 spin_unlock_bh(&vport->mac_list_lock); 8562 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8563 return 0; 8564 } 8565 8566 /* if this address is never added, unnecessary to delete */ 8567 if (state == HCLGE_MAC_TO_DEL) { 8568 spin_unlock_bh(&vport->mac_list_lock); 8569 hnae3_format_mac_addr(format_mac_addr, addr); 8570 dev_err(&hdev->pdev->dev, 8571 "failed to delete address %s from mac list\n", 8572 format_mac_addr); 8573 return -ENOENT; 8574 } 8575 8576 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8577 if (!mac_node) { 8578 spin_unlock_bh(&vport->mac_list_lock); 8579 return -ENOMEM; 8580 } 8581 8582 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8583 8584 mac_node->state = state; 8585 ether_addr_copy(mac_node->mac_addr, addr); 8586 list_add_tail(&mac_node->node, list); 8587 8588 spin_unlock_bh(&vport->mac_list_lock); 8589 8590 return 0; 8591 } 8592 8593 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8594 const unsigned char *addr) 8595 { 8596 struct hclge_vport *vport = hclge_get_vport(handle); 8597 8598 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8599 addr); 8600 } 8601 8602 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8603 const unsigned char *addr) 8604 { 8605 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8606 struct hclge_dev *hdev = vport->back; 8607 struct hclge_mac_vlan_tbl_entry_cmd req; 8608 struct hclge_desc desc; 8609 u16 egress_port = 0; 8610 int ret; 8611 8612 /* mac addr check */ 8613 if (is_zero_ether_addr(addr) || 8614 is_broadcast_ether_addr(addr) || 8615 is_multicast_ether_addr(addr)) { 8616 hnae3_format_mac_addr(format_mac_addr, addr); 8617 dev_err(&hdev->pdev->dev, 8618 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8619 format_mac_addr, is_zero_ether_addr(addr), 8620 is_broadcast_ether_addr(addr), 8621 is_multicast_ether_addr(addr)); 8622 return -EINVAL; 8623 } 8624 8625 memset(&req, 0, sizeof(req)); 8626 8627 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8628 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8629 8630 req.egress_port = cpu_to_le16(egress_port); 8631 8632 hclge_prepare_mac_addr(&req, addr, false); 8633 8634 /* Lookup the mac address in the mac_vlan table, and add 8635 * it if the entry is inexistent. Repeated unicast entry 8636 * is not allowed in the mac vlan table. 8637 */ 8638 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8639 if (ret == -ENOENT) { 8640 mutex_lock(&hdev->vport_lock); 8641 if (!hclge_is_umv_space_full(vport, false)) { 8642 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8643 if (!ret) 8644 hclge_update_umv_space(vport, false); 8645 mutex_unlock(&hdev->vport_lock); 8646 return ret; 8647 } 8648 mutex_unlock(&hdev->vport_lock); 8649 8650 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8651 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8652 hdev->priv_umv_size); 8653 8654 return -ENOSPC; 8655 } 8656 8657 /* check if we just hit the duplicate */ 8658 if (!ret) 8659 return -EEXIST; 8660 8661 return ret; 8662 } 8663 8664 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8665 const unsigned char *addr) 8666 { 8667 struct hclge_vport *vport = hclge_get_vport(handle); 8668 8669 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8670 addr); 8671 } 8672 8673 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8674 const unsigned char *addr) 8675 { 8676 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8677 struct hclge_dev *hdev = vport->back; 8678 struct hclge_mac_vlan_tbl_entry_cmd req; 8679 int ret; 8680 8681 /* mac addr check */ 8682 if (is_zero_ether_addr(addr) || 8683 is_broadcast_ether_addr(addr) || 8684 is_multicast_ether_addr(addr)) { 8685 hnae3_format_mac_addr(format_mac_addr, addr); 8686 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8687 format_mac_addr); 8688 return -EINVAL; 8689 } 8690 8691 memset(&req, 0, sizeof(req)); 8692 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8693 hclge_prepare_mac_addr(&req, addr, false); 8694 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8695 if (!ret || ret == -ENOENT) { 8696 mutex_lock(&hdev->vport_lock); 8697 hclge_update_umv_space(vport, true); 8698 mutex_unlock(&hdev->vport_lock); 8699 return 0; 8700 } 8701 8702 return ret; 8703 } 8704 8705 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8706 const unsigned char *addr) 8707 { 8708 struct hclge_vport *vport = hclge_get_vport(handle); 8709 8710 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8711 addr); 8712 } 8713 8714 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8715 const unsigned char *addr) 8716 { 8717 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8718 struct hclge_dev *hdev = vport->back; 8719 struct hclge_mac_vlan_tbl_entry_cmd req; 8720 struct hclge_desc desc[3]; 8721 bool is_new_addr = false; 8722 int status; 8723 8724 /* mac addr check */ 8725 if (!is_multicast_ether_addr(addr)) { 8726 hnae3_format_mac_addr(format_mac_addr, addr); 8727 dev_err(&hdev->pdev->dev, 8728 "Add mc mac err! invalid mac:%s.\n", 8729 format_mac_addr); 8730 return -EINVAL; 8731 } 8732 memset(&req, 0, sizeof(req)); 8733 hclge_prepare_mac_addr(&req, addr, true); 8734 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8735 if (status) { 8736 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8737 hdev->used_mc_mac_num >= 8738 hdev->ae_dev->dev_specs.mc_mac_size) 8739 goto err_no_space; 8740 8741 is_new_addr = true; 8742 8743 /* This mac addr do not exist, add new entry for it */ 8744 memset(desc[0].data, 0, sizeof(desc[0].data)); 8745 memset(desc[1].data, 0, sizeof(desc[0].data)); 8746 memset(desc[2].data, 0, sizeof(desc[0].data)); 8747 } 8748 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8749 if (status) 8750 return status; 8751 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8752 if (status == -ENOSPC) 8753 goto err_no_space; 8754 else if (!status && is_new_addr) 8755 hdev->used_mc_mac_num++; 8756 8757 return status; 8758 8759 err_no_space: 8760 /* if already overflow, not to print each time */ 8761 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8762 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8763 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8764 } 8765 8766 return -ENOSPC; 8767 } 8768 8769 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8770 const unsigned char *addr) 8771 { 8772 struct hclge_vport *vport = hclge_get_vport(handle); 8773 8774 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8775 addr); 8776 } 8777 8778 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8779 const unsigned char *addr) 8780 { 8781 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8782 struct hclge_dev *hdev = vport->back; 8783 struct hclge_mac_vlan_tbl_entry_cmd req; 8784 enum hclge_comm_cmd_status status; 8785 struct hclge_desc desc[3]; 8786 8787 /* mac addr check */ 8788 if (!is_multicast_ether_addr(addr)) { 8789 hnae3_format_mac_addr(format_mac_addr, addr); 8790 dev_dbg(&hdev->pdev->dev, 8791 "Remove mc mac err! invalid mac:%s.\n", 8792 format_mac_addr); 8793 return -EINVAL; 8794 } 8795 8796 memset(&req, 0, sizeof(req)); 8797 hclge_prepare_mac_addr(&req, addr, true); 8798 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8799 if (!status) { 8800 /* This mac addr exist, remove this handle's VFID for it */ 8801 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8802 if (status) 8803 return status; 8804 8805 if (hclge_is_all_function_id_zero(desc)) { 8806 /* All the vfid is zero, so need to delete this entry */ 8807 status = hclge_remove_mac_vlan_tbl(vport, &req); 8808 if (!status) 8809 hdev->used_mc_mac_num--; 8810 } else { 8811 /* Not all the vfid is zero, update the vfid */ 8812 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8813 } 8814 } else if (status == -ENOENT) { 8815 status = 0; 8816 } 8817 8818 return status; 8819 } 8820 8821 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8822 struct list_head *list, 8823 enum HCLGE_MAC_ADDR_TYPE mac_type) 8824 { 8825 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8826 struct hclge_mac_node *mac_node, *tmp; 8827 int ret; 8828 8829 if (mac_type == HCLGE_MAC_ADDR_UC) 8830 sync = hclge_add_uc_addr_common; 8831 else 8832 sync = hclge_add_mc_addr_common; 8833 8834 list_for_each_entry_safe(mac_node, tmp, list, node) { 8835 ret = sync(vport, mac_node->mac_addr); 8836 if (!ret) { 8837 mac_node->state = HCLGE_MAC_ACTIVE; 8838 } else { 8839 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8840 &vport->state); 8841 8842 /* If one unicast mac address is existing in hardware, 8843 * we need to try whether other unicast mac addresses 8844 * are new addresses that can be added. 8845 * Multicast mac address can be reusable, even though 8846 * there is no space to add new multicast mac address, 8847 * we should check whether other mac addresses are 8848 * existing in hardware for reuse. 8849 */ 8850 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8851 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8852 break; 8853 } 8854 } 8855 } 8856 8857 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8858 struct list_head *list, 8859 enum HCLGE_MAC_ADDR_TYPE mac_type) 8860 { 8861 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8862 struct hclge_mac_node *mac_node, *tmp; 8863 int ret; 8864 8865 if (mac_type == HCLGE_MAC_ADDR_UC) 8866 unsync = hclge_rm_uc_addr_common; 8867 else 8868 unsync = hclge_rm_mc_addr_common; 8869 8870 list_for_each_entry_safe(mac_node, tmp, list, node) { 8871 ret = unsync(vport, mac_node->mac_addr); 8872 if (!ret || ret == -ENOENT) { 8873 list_del(&mac_node->node); 8874 kfree(mac_node); 8875 } else { 8876 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8877 &vport->state); 8878 break; 8879 } 8880 } 8881 } 8882 8883 static bool hclge_sync_from_add_list(struct list_head *add_list, 8884 struct list_head *mac_list) 8885 { 8886 struct hclge_mac_node *mac_node, *tmp, *new_node; 8887 bool all_added = true; 8888 8889 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8890 if (mac_node->state == HCLGE_MAC_TO_ADD) 8891 all_added = false; 8892 8893 /* if the mac address from tmp_add_list is not in the 8894 * uc/mc_mac_list, it means have received a TO_DEL request 8895 * during the time window of adding the mac address into mac 8896 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8897 * then it will be removed at next time. else it must be TO_ADD, 8898 * this address hasn't been added into mac table, 8899 * so just remove the mac node. 8900 */ 8901 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8902 if (new_node) { 8903 hclge_update_mac_node(new_node, mac_node->state); 8904 list_del(&mac_node->node); 8905 kfree(mac_node); 8906 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8907 mac_node->state = HCLGE_MAC_TO_DEL; 8908 list_move_tail(&mac_node->node, mac_list); 8909 } else { 8910 list_del(&mac_node->node); 8911 kfree(mac_node); 8912 } 8913 } 8914 8915 return all_added; 8916 } 8917 8918 static void hclge_sync_from_del_list(struct list_head *del_list, 8919 struct list_head *mac_list) 8920 { 8921 struct hclge_mac_node *mac_node, *tmp, *new_node; 8922 8923 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8924 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8925 if (new_node) { 8926 /* If the mac addr exists in the mac list, it means 8927 * received a new TO_ADD request during the time window 8928 * of configuring the mac address. For the mac node 8929 * state is TO_ADD, and the address is already in the 8930 * in the hardware(due to delete fail), so we just need 8931 * to change the mac node state to ACTIVE. 8932 */ 8933 new_node->state = HCLGE_MAC_ACTIVE; 8934 list_del(&mac_node->node); 8935 kfree(mac_node); 8936 } else { 8937 list_move_tail(&mac_node->node, mac_list); 8938 } 8939 } 8940 } 8941 8942 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8943 enum HCLGE_MAC_ADDR_TYPE mac_type, 8944 bool is_all_added) 8945 { 8946 if (mac_type == HCLGE_MAC_ADDR_UC) { 8947 if (is_all_added) 8948 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8949 else if (hclge_is_umv_space_full(vport, true)) 8950 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8951 } else { 8952 if (is_all_added) 8953 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8954 else 8955 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8956 } 8957 } 8958 8959 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8960 enum HCLGE_MAC_ADDR_TYPE mac_type) 8961 { 8962 struct hclge_mac_node *mac_node, *tmp, *new_node; 8963 struct list_head tmp_add_list, tmp_del_list; 8964 struct list_head *list; 8965 bool all_added; 8966 8967 INIT_LIST_HEAD(&tmp_add_list); 8968 INIT_LIST_HEAD(&tmp_del_list); 8969 8970 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8971 * we can add/delete these mac addr outside the spin lock 8972 */ 8973 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8974 &vport->uc_mac_list : &vport->mc_mac_list; 8975 8976 spin_lock_bh(&vport->mac_list_lock); 8977 8978 list_for_each_entry_safe(mac_node, tmp, list, node) { 8979 switch (mac_node->state) { 8980 case HCLGE_MAC_TO_DEL: 8981 list_move_tail(&mac_node->node, &tmp_del_list); 8982 break; 8983 case HCLGE_MAC_TO_ADD: 8984 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8985 if (!new_node) 8986 goto stop_traverse; 8987 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8988 new_node->state = mac_node->state; 8989 list_add_tail(&new_node->node, &tmp_add_list); 8990 break; 8991 default: 8992 break; 8993 } 8994 } 8995 8996 stop_traverse: 8997 spin_unlock_bh(&vport->mac_list_lock); 8998 8999 /* delete first, in order to get max mac table space for adding */ 9000 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9001 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 9002 9003 /* if some mac addresses were added/deleted fail, move back to the 9004 * mac_list, and retry at next time. 9005 */ 9006 spin_lock_bh(&vport->mac_list_lock); 9007 9008 hclge_sync_from_del_list(&tmp_del_list, list); 9009 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 9010 9011 spin_unlock_bh(&vport->mac_list_lock); 9012 9013 hclge_update_overflow_flags(vport, mac_type, all_added); 9014 } 9015 9016 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 9017 { 9018 struct hclge_dev *hdev = vport->back; 9019 9020 if (test_bit(vport->vport_id, hdev->vport_config_block)) 9021 return false; 9022 9023 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 9024 return true; 9025 9026 return false; 9027 } 9028 9029 static void hclge_sync_mac_table(struct hclge_dev *hdev) 9030 { 9031 int i; 9032 9033 for (i = 0; i < hdev->num_alloc_vport; i++) { 9034 struct hclge_vport *vport = &hdev->vport[i]; 9035 9036 if (!hclge_need_sync_mac_table(vport)) 9037 continue; 9038 9039 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 9040 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 9041 } 9042 } 9043 9044 static void hclge_build_del_list(struct list_head *list, 9045 bool is_del_list, 9046 struct list_head *tmp_del_list) 9047 { 9048 struct hclge_mac_node *mac_cfg, *tmp; 9049 9050 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 9051 switch (mac_cfg->state) { 9052 case HCLGE_MAC_TO_DEL: 9053 case HCLGE_MAC_ACTIVE: 9054 list_move_tail(&mac_cfg->node, tmp_del_list); 9055 break; 9056 case HCLGE_MAC_TO_ADD: 9057 if (is_del_list) { 9058 list_del(&mac_cfg->node); 9059 kfree(mac_cfg); 9060 } 9061 break; 9062 } 9063 } 9064 } 9065 9066 static void hclge_unsync_del_list(struct hclge_vport *vport, 9067 int (*unsync)(struct hclge_vport *vport, 9068 const unsigned char *addr), 9069 bool is_del_list, 9070 struct list_head *tmp_del_list) 9071 { 9072 struct hclge_mac_node *mac_cfg, *tmp; 9073 int ret; 9074 9075 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 9076 ret = unsync(vport, mac_cfg->mac_addr); 9077 if (!ret || ret == -ENOENT) { 9078 /* clear all mac addr from hardware, but remain these 9079 * mac addr in the mac list, and restore them after 9080 * vf reset finished. 9081 */ 9082 if (!is_del_list && 9083 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9084 mac_cfg->state = HCLGE_MAC_TO_ADD; 9085 } else { 9086 list_del(&mac_cfg->node); 9087 kfree(mac_cfg); 9088 } 9089 } else if (is_del_list) { 9090 mac_cfg->state = HCLGE_MAC_TO_DEL; 9091 } 9092 } 9093 } 9094 9095 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9096 enum HCLGE_MAC_ADDR_TYPE mac_type) 9097 { 9098 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9099 struct hclge_dev *hdev = vport->back; 9100 struct list_head tmp_del_list, *list; 9101 9102 if (mac_type == HCLGE_MAC_ADDR_UC) { 9103 list = &vport->uc_mac_list; 9104 unsync = hclge_rm_uc_addr_common; 9105 } else { 9106 list = &vport->mc_mac_list; 9107 unsync = hclge_rm_mc_addr_common; 9108 } 9109 9110 INIT_LIST_HEAD(&tmp_del_list); 9111 9112 if (!is_del_list) 9113 set_bit(vport->vport_id, hdev->vport_config_block); 9114 9115 spin_lock_bh(&vport->mac_list_lock); 9116 9117 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9118 9119 spin_unlock_bh(&vport->mac_list_lock); 9120 9121 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9122 9123 spin_lock_bh(&vport->mac_list_lock); 9124 9125 hclge_sync_from_del_list(&tmp_del_list, list); 9126 9127 spin_unlock_bh(&vport->mac_list_lock); 9128 } 9129 9130 /* remove all mac address when uninitailize */ 9131 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9132 enum HCLGE_MAC_ADDR_TYPE mac_type) 9133 { 9134 struct hclge_mac_node *mac_node, *tmp; 9135 struct hclge_dev *hdev = vport->back; 9136 struct list_head tmp_del_list, *list; 9137 9138 INIT_LIST_HEAD(&tmp_del_list); 9139 9140 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9141 &vport->uc_mac_list : &vport->mc_mac_list; 9142 9143 spin_lock_bh(&vport->mac_list_lock); 9144 9145 list_for_each_entry_safe(mac_node, tmp, list, node) { 9146 switch (mac_node->state) { 9147 case HCLGE_MAC_TO_DEL: 9148 case HCLGE_MAC_ACTIVE: 9149 list_move_tail(&mac_node->node, &tmp_del_list); 9150 break; 9151 case HCLGE_MAC_TO_ADD: 9152 list_del(&mac_node->node); 9153 kfree(mac_node); 9154 break; 9155 } 9156 } 9157 9158 spin_unlock_bh(&vport->mac_list_lock); 9159 9160 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9161 9162 if (!list_empty(&tmp_del_list)) 9163 dev_warn(&hdev->pdev->dev, 9164 "uninit %s mac list for vport %u not completely.\n", 9165 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9166 vport->vport_id); 9167 9168 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9169 list_del(&mac_node->node); 9170 kfree(mac_node); 9171 } 9172 } 9173 9174 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9175 { 9176 struct hclge_vport *vport; 9177 int i; 9178 9179 for (i = 0; i < hdev->num_alloc_vport; i++) { 9180 vport = &hdev->vport[i]; 9181 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9182 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9183 } 9184 } 9185 9186 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9187 u16 cmdq_resp, u8 resp_code) 9188 { 9189 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9190 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9191 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9192 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9193 9194 int return_status; 9195 9196 if (cmdq_resp) { 9197 dev_err(&hdev->pdev->dev, 9198 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9199 cmdq_resp); 9200 return -EIO; 9201 } 9202 9203 switch (resp_code) { 9204 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9205 case HCLGE_ETHERTYPE_ALREADY_ADD: 9206 return_status = 0; 9207 break; 9208 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9209 dev_err(&hdev->pdev->dev, 9210 "add mac ethertype failed for manager table overflow.\n"); 9211 return_status = -EIO; 9212 break; 9213 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9214 dev_err(&hdev->pdev->dev, 9215 "add mac ethertype failed for key conflict.\n"); 9216 return_status = -EIO; 9217 break; 9218 default: 9219 dev_err(&hdev->pdev->dev, 9220 "add mac ethertype failed for undefined, code=%u.\n", 9221 resp_code); 9222 return_status = -EIO; 9223 } 9224 9225 return return_status; 9226 } 9227 9228 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9229 u8 *mac_addr) 9230 { 9231 struct hclge_vport *vport = hclge_get_vport(handle); 9232 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9233 struct hclge_dev *hdev = vport->back; 9234 9235 vport = hclge_get_vf_vport(hdev, vf); 9236 if (!vport) 9237 return -EINVAL; 9238 9239 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9240 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9241 dev_info(&hdev->pdev->dev, 9242 "Specified MAC(=%s) is same as before, no change committed!\n", 9243 format_mac_addr); 9244 return 0; 9245 } 9246 9247 ether_addr_copy(vport->vf_info.mac, mac_addr); 9248 9249 /* there is a timewindow for PF to know VF unalive, it may 9250 * cause send mailbox fail, but it doesn't matter, VF will 9251 * query it when reinit. 9252 */ 9253 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9254 dev_info(&hdev->pdev->dev, 9255 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9256 vf, format_mac_addr); 9257 (void)hclge_inform_reset_assert_to_vf(vport); 9258 return 0; 9259 } 9260 9261 dev_info(&hdev->pdev->dev, 9262 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9263 vf, format_mac_addr); 9264 return 0; 9265 } 9266 9267 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9268 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9269 { 9270 struct hclge_desc desc; 9271 u8 resp_code; 9272 u16 retval; 9273 int ret; 9274 9275 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9276 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9277 9278 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9279 if (ret) { 9280 dev_err(&hdev->pdev->dev, 9281 "add mac ethertype failed for cmd_send, ret =%d.\n", 9282 ret); 9283 return ret; 9284 } 9285 9286 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9287 retval = le16_to_cpu(desc.retval); 9288 9289 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9290 } 9291 9292 static int init_mgr_tbl(struct hclge_dev *hdev) 9293 { 9294 int ret; 9295 u32 i; 9296 9297 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9298 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9299 if (ret) { 9300 dev_err(&hdev->pdev->dev, 9301 "add mac ethertype failed, ret =%d.\n", 9302 ret); 9303 return ret; 9304 } 9305 } 9306 9307 return 0; 9308 } 9309 9310 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9311 { 9312 struct hclge_vport *vport = hclge_get_vport(handle); 9313 struct hclge_dev *hdev = vport->back; 9314 9315 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9316 } 9317 9318 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9319 const u8 *old_addr, const u8 *new_addr) 9320 { 9321 struct list_head *list = &vport->uc_mac_list; 9322 struct hclge_mac_node *old_node, *new_node; 9323 9324 new_node = hclge_find_mac_node(list, new_addr); 9325 if (!new_node) { 9326 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9327 if (!new_node) 9328 return -ENOMEM; 9329 9330 new_node->state = HCLGE_MAC_TO_ADD; 9331 ether_addr_copy(new_node->mac_addr, new_addr); 9332 list_add(&new_node->node, list); 9333 } else { 9334 if (new_node->state == HCLGE_MAC_TO_DEL) 9335 new_node->state = HCLGE_MAC_ACTIVE; 9336 9337 /* make sure the new addr is in the list head, avoid dev 9338 * addr may be not re-added into mac table for the umv space 9339 * limitation after global/imp reset which will clear mac 9340 * table by hardware. 9341 */ 9342 list_move(&new_node->node, list); 9343 } 9344 9345 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9346 old_node = hclge_find_mac_node(list, old_addr); 9347 if (old_node) { 9348 if (old_node->state == HCLGE_MAC_TO_ADD) { 9349 list_del(&old_node->node); 9350 kfree(old_node); 9351 } else { 9352 old_node->state = HCLGE_MAC_TO_DEL; 9353 } 9354 } 9355 } 9356 9357 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9358 9359 return 0; 9360 } 9361 9362 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9363 bool is_first) 9364 { 9365 const unsigned char *new_addr = (const unsigned char *)p; 9366 struct hclge_vport *vport = hclge_get_vport(handle); 9367 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9368 struct hclge_dev *hdev = vport->back; 9369 unsigned char *old_addr = NULL; 9370 int ret; 9371 9372 /* mac addr check */ 9373 if (is_zero_ether_addr(new_addr) || 9374 is_broadcast_ether_addr(new_addr) || 9375 is_multicast_ether_addr(new_addr)) { 9376 hnae3_format_mac_addr(format_mac_addr, new_addr); 9377 dev_err(&hdev->pdev->dev, 9378 "change uc mac err! invalid mac: %s.\n", 9379 format_mac_addr); 9380 return -EINVAL; 9381 } 9382 9383 ret = hclge_pause_addr_cfg(hdev, new_addr); 9384 if (ret) { 9385 dev_err(&hdev->pdev->dev, 9386 "failed to configure mac pause address, ret = %d\n", 9387 ret); 9388 return ret; 9389 } 9390 9391 if (!is_first) 9392 old_addr = hdev->hw.mac.mac_addr; 9393 9394 spin_lock_bh(&vport->mac_list_lock); 9395 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9396 if (ret) { 9397 hnae3_format_mac_addr(format_mac_addr, new_addr); 9398 dev_err(&hdev->pdev->dev, 9399 "failed to change the mac addr:%s, ret = %d\n", 9400 format_mac_addr, ret); 9401 spin_unlock_bh(&vport->mac_list_lock); 9402 9403 if (!is_first) 9404 hclge_pause_addr_cfg(hdev, old_addr); 9405 9406 return ret; 9407 } 9408 /* we must update dev addr with spin lock protect, preventing dev addr 9409 * being removed by set_rx_mode path. 9410 */ 9411 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9412 spin_unlock_bh(&vport->mac_list_lock); 9413 9414 hclge_task_schedule(hdev, 0); 9415 9416 return 0; 9417 } 9418 9419 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9420 { 9421 struct mii_ioctl_data *data = if_mii(ifr); 9422 9423 if (!hnae3_dev_phy_imp_supported(hdev)) 9424 return -EOPNOTSUPP; 9425 9426 switch (cmd) { 9427 case SIOCGMIIPHY: 9428 data->phy_id = hdev->hw.mac.phy_addr; 9429 /* this command reads phy id and register at the same time */ 9430 fallthrough; 9431 case SIOCGMIIREG: 9432 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9433 return 0; 9434 9435 case SIOCSMIIREG: 9436 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9437 default: 9438 return -EOPNOTSUPP; 9439 } 9440 } 9441 9442 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9443 int cmd) 9444 { 9445 struct hclge_vport *vport = hclge_get_vport(handle); 9446 struct hclge_dev *hdev = vport->back; 9447 9448 switch (cmd) { 9449 case SIOCGHWTSTAMP: 9450 return hclge_ptp_get_cfg(hdev, ifr); 9451 case SIOCSHWTSTAMP: 9452 return hclge_ptp_set_cfg(hdev, ifr); 9453 default: 9454 if (!hdev->hw.mac.phydev) 9455 return hclge_mii_ioctl(hdev, ifr, cmd); 9456 } 9457 9458 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9459 } 9460 9461 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9462 bool bypass_en) 9463 { 9464 struct hclge_port_vlan_filter_bypass_cmd *req; 9465 struct hclge_desc desc; 9466 int ret; 9467 9468 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9469 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9470 req->vf_id = vf_id; 9471 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9472 bypass_en ? 1 : 0); 9473 9474 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9475 if (ret) 9476 dev_err(&hdev->pdev->dev, 9477 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9478 vf_id, ret); 9479 9480 return ret; 9481 } 9482 9483 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9484 u8 fe_type, bool filter_en, u8 vf_id) 9485 { 9486 struct hclge_vlan_filter_ctrl_cmd *req; 9487 struct hclge_desc desc; 9488 int ret; 9489 9490 /* read current vlan filter parameter */ 9491 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9492 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9493 req->vlan_type = vlan_type; 9494 req->vf_id = vf_id; 9495 9496 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9497 if (ret) { 9498 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9499 vf_id, ret); 9500 return ret; 9501 } 9502 9503 /* modify and write new config parameter */ 9504 hclge_comm_cmd_reuse_desc(&desc, false); 9505 req->vlan_fe = filter_en ? 9506 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9507 9508 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9509 if (ret) 9510 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9511 vf_id, ret); 9512 9513 return ret; 9514 } 9515 9516 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9517 { 9518 struct hclge_dev *hdev = vport->back; 9519 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9520 int ret; 9521 9522 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9523 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9524 HCLGE_FILTER_FE_EGRESS_V1_B, 9525 enable, vport->vport_id); 9526 9527 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9528 HCLGE_FILTER_FE_EGRESS, enable, 9529 vport->vport_id); 9530 if (ret) 9531 return ret; 9532 9533 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9534 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9535 !enable); 9536 } else if (!vport->vport_id) { 9537 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9538 enable = false; 9539 9540 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9541 HCLGE_FILTER_FE_INGRESS, 9542 enable, 0); 9543 } 9544 9545 return ret; 9546 } 9547 9548 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9549 { 9550 struct hnae3_handle *handle = &vport->nic; 9551 struct hclge_vport_vlan_cfg *vlan, *tmp; 9552 struct hclge_dev *hdev = vport->back; 9553 9554 if (vport->vport_id) { 9555 if (vport->port_base_vlan_cfg.state != 9556 HNAE3_PORT_BASE_VLAN_DISABLE) 9557 return true; 9558 9559 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9560 return false; 9561 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9562 return false; 9563 } 9564 9565 if (!vport->req_vlan_fltr_en) 9566 return false; 9567 9568 /* compatible with former device, always enable vlan filter */ 9569 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9570 return true; 9571 9572 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9573 if (vlan->vlan_id != 0) 9574 return true; 9575 9576 return false; 9577 } 9578 9579 static int __hclge_enable_vport_vlan_filter(struct hclge_vport *vport, 9580 bool request_en) 9581 { 9582 bool need_en; 9583 int ret; 9584 9585 need_en = hclge_need_enable_vport_vlan_filter(vport); 9586 if (need_en == vport->cur_vlan_fltr_en) 9587 return 0; 9588 9589 ret = hclge_set_vport_vlan_filter(vport, need_en); 9590 if (ret) 9591 return ret; 9592 9593 vport->cur_vlan_fltr_en = need_en; 9594 9595 return 0; 9596 } 9597 9598 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9599 { 9600 struct hclge_dev *hdev = vport->back; 9601 int ret; 9602 9603 mutex_lock(&hdev->vport_lock); 9604 vport->req_vlan_fltr_en = request_en; 9605 ret = __hclge_enable_vport_vlan_filter(vport, request_en); 9606 mutex_unlock(&hdev->vport_lock); 9607 9608 return ret; 9609 } 9610 9611 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9612 { 9613 struct hclge_vport *vport = hclge_get_vport(handle); 9614 9615 return hclge_enable_vport_vlan_filter(vport, enable); 9616 } 9617 9618 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9619 bool is_kill, u16 vlan, 9620 struct hclge_desc *desc) 9621 { 9622 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9623 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9624 u8 vf_byte_val; 9625 u8 vf_byte_off; 9626 int ret; 9627 9628 hclge_cmd_setup_basic_desc(&desc[0], 9629 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9630 hclge_cmd_setup_basic_desc(&desc[1], 9631 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9632 9633 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9634 9635 vf_byte_off = vfid / 8; 9636 vf_byte_val = 1 << (vfid % 8); 9637 9638 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9639 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9640 9641 req0->vlan_id = cpu_to_le16(vlan); 9642 req0->vlan_cfg = is_kill; 9643 9644 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9645 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9646 else 9647 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9648 9649 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9650 if (ret) { 9651 dev_err(&hdev->pdev->dev, 9652 "Send vf vlan command fail, ret =%d.\n", 9653 ret); 9654 return ret; 9655 } 9656 9657 return 0; 9658 } 9659 9660 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9661 bool is_kill, struct hclge_desc *desc) 9662 { 9663 struct hclge_vlan_filter_vf_cfg_cmd *req; 9664 9665 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9666 9667 if (!is_kill) { 9668 #define HCLGE_VF_VLAN_NO_ENTRY 2 9669 if (!req->resp_code || req->resp_code == 1) 9670 return 0; 9671 9672 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9673 set_bit(vfid, hdev->vf_vlan_full); 9674 dev_warn(&hdev->pdev->dev, 9675 "vf vlan table is full, vf vlan filter is disabled\n"); 9676 return 0; 9677 } 9678 9679 dev_err(&hdev->pdev->dev, 9680 "Add vf vlan filter fail, ret =%u.\n", 9681 req->resp_code); 9682 } else { 9683 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9684 if (!req->resp_code) 9685 return 0; 9686 9687 /* vf vlan filter is disabled when vf vlan table is full, 9688 * then new vlan id will not be added into vf vlan table. 9689 * Just return 0 without warning, avoid massive verbose 9690 * print logs when unload. 9691 */ 9692 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9693 return 0; 9694 9695 dev_err(&hdev->pdev->dev, 9696 "Kill vf vlan filter fail, ret =%u.\n", 9697 req->resp_code); 9698 } 9699 9700 return -EIO; 9701 } 9702 9703 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9704 bool is_kill, u16 vlan) 9705 { 9706 struct hclge_vport *vport = &hdev->vport[vfid]; 9707 struct hclge_desc desc[2]; 9708 int ret; 9709 9710 /* if vf vlan table is full, firmware will close vf vlan filter, it 9711 * is unable and unnecessary to add new vlan id to vf vlan filter. 9712 * If spoof check is enable, and vf vlan is full, it shouldn't add 9713 * new vlan, because tx packets with these vlan id will be dropped. 9714 */ 9715 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9716 if (vport->vf_info.spoofchk && vlan) { 9717 dev_err(&hdev->pdev->dev, 9718 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9719 return -EPERM; 9720 } 9721 return 0; 9722 } 9723 9724 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9725 if (ret) 9726 return ret; 9727 9728 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9729 } 9730 9731 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9732 u16 vlan_id, bool is_kill) 9733 { 9734 struct hclge_vlan_filter_pf_cfg_cmd *req; 9735 struct hclge_desc desc; 9736 u8 vlan_offset_byte_val; 9737 u8 vlan_offset_byte; 9738 u8 vlan_offset_160; 9739 int ret; 9740 9741 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9742 9743 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9744 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9745 HCLGE_VLAN_BYTE_SIZE; 9746 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9747 9748 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9749 req->vlan_offset = vlan_offset_160; 9750 req->vlan_cfg = is_kill; 9751 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9752 9753 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9754 if (ret) 9755 dev_err(&hdev->pdev->dev, 9756 "port vlan command, send fail, ret =%d.\n", ret); 9757 return ret; 9758 } 9759 9760 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9761 u16 vlan_id, bool is_kill) 9762 { 9763 /* vlan 0 may be added twice when 8021q module is enabled */ 9764 if (!is_kill && !vlan_id && 9765 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9766 return false; 9767 9768 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9769 dev_warn(&hdev->pdev->dev, 9770 "Add port vlan failed, vport %u is already in vlan %u\n", 9771 vport_id, vlan_id); 9772 return false; 9773 } 9774 9775 if (is_kill && 9776 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9777 dev_warn(&hdev->pdev->dev, 9778 "Delete port vlan failed, vport %u is not in vlan %u\n", 9779 vport_id, vlan_id); 9780 return false; 9781 } 9782 9783 return true; 9784 } 9785 9786 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9787 u16 vport_id, u16 vlan_id, 9788 bool is_kill) 9789 { 9790 u16 vport_idx, vport_num = 0; 9791 int ret; 9792 9793 if (is_kill && !vlan_id) 9794 return 0; 9795 9796 if (vlan_id >= VLAN_N_VID) 9797 return -EINVAL; 9798 9799 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9800 if (ret) { 9801 dev_err(&hdev->pdev->dev, 9802 "Set %u vport vlan filter config fail, ret =%d.\n", 9803 vport_id, ret); 9804 return ret; 9805 } 9806 9807 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9808 return 0; 9809 9810 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9811 vport_num++; 9812 9813 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9814 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9815 is_kill); 9816 9817 return ret; 9818 } 9819 9820 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9821 { 9822 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9823 struct hclge_vport_vtag_tx_cfg_cmd *req; 9824 struct hclge_dev *hdev = vport->back; 9825 struct hclge_desc desc; 9826 u16 bmap_index; 9827 int status; 9828 9829 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9830 9831 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9832 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9833 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9834 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9835 vcfg->accept_tag1 ? 1 : 0); 9836 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9837 vcfg->accept_untag1 ? 1 : 0); 9838 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9839 vcfg->accept_tag2 ? 1 : 0); 9840 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9841 vcfg->accept_untag2 ? 1 : 0); 9842 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9843 vcfg->insert_tag1_en ? 1 : 0); 9844 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9845 vcfg->insert_tag2_en ? 1 : 0); 9846 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9847 vcfg->tag_shift_mode_en ? 1 : 0); 9848 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9849 9850 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9851 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9852 HCLGE_VF_NUM_PER_BYTE; 9853 req->vf_bitmap[bmap_index] = 9854 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9855 9856 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9857 if (status) 9858 dev_err(&hdev->pdev->dev, 9859 "Send port txvlan cfg command fail, ret =%d\n", 9860 status); 9861 9862 return status; 9863 } 9864 9865 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9866 { 9867 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9868 struct hclge_vport_vtag_rx_cfg_cmd *req; 9869 struct hclge_dev *hdev = vport->back; 9870 struct hclge_desc desc; 9871 u16 bmap_index; 9872 int status; 9873 9874 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9875 9876 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9877 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9878 vcfg->strip_tag1_en ? 1 : 0); 9879 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9880 vcfg->strip_tag2_en ? 1 : 0); 9881 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9882 vcfg->vlan1_vlan_prionly ? 1 : 0); 9883 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9884 vcfg->vlan2_vlan_prionly ? 1 : 0); 9885 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9886 vcfg->strip_tag1_discard_en ? 1 : 0); 9887 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9888 vcfg->strip_tag2_discard_en ? 1 : 0); 9889 9890 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9891 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9892 HCLGE_VF_NUM_PER_BYTE; 9893 req->vf_bitmap[bmap_index] = 9894 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9895 9896 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9897 if (status) 9898 dev_err(&hdev->pdev->dev, 9899 "Send port rxvlan cfg command fail, ret =%d\n", 9900 status); 9901 9902 return status; 9903 } 9904 9905 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9906 u16 port_base_vlan_state, 9907 u16 vlan_tag, u8 qos) 9908 { 9909 int ret; 9910 9911 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9912 vport->txvlan_cfg.accept_tag1 = true; 9913 vport->txvlan_cfg.insert_tag1_en = false; 9914 vport->txvlan_cfg.default_tag1 = 0; 9915 } else { 9916 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9917 9918 vport->txvlan_cfg.accept_tag1 = 9919 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9920 vport->txvlan_cfg.insert_tag1_en = true; 9921 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9922 vlan_tag; 9923 } 9924 9925 vport->txvlan_cfg.accept_untag1 = true; 9926 9927 /* accept_tag2 and accept_untag2 are not supported on 9928 * pdev revision(0x20), new revision support them, 9929 * this two fields can not be configured by user. 9930 */ 9931 vport->txvlan_cfg.accept_tag2 = true; 9932 vport->txvlan_cfg.accept_untag2 = true; 9933 vport->txvlan_cfg.insert_tag2_en = false; 9934 vport->txvlan_cfg.default_tag2 = 0; 9935 vport->txvlan_cfg.tag_shift_mode_en = true; 9936 9937 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9938 vport->rxvlan_cfg.strip_tag1_en = false; 9939 vport->rxvlan_cfg.strip_tag2_en = 9940 vport->rxvlan_cfg.rx_vlan_offload_en; 9941 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9942 } else { 9943 vport->rxvlan_cfg.strip_tag1_en = 9944 vport->rxvlan_cfg.rx_vlan_offload_en; 9945 vport->rxvlan_cfg.strip_tag2_en = true; 9946 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9947 } 9948 9949 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9950 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9951 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9952 9953 ret = hclge_set_vlan_tx_offload_cfg(vport); 9954 if (ret) 9955 return ret; 9956 9957 return hclge_set_vlan_rx_offload_cfg(vport); 9958 } 9959 9960 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9961 { 9962 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9963 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9964 struct hclge_desc desc; 9965 int status; 9966 9967 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9968 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9969 rx_req->ot_fst_vlan_type = 9970 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9971 rx_req->ot_sec_vlan_type = 9972 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9973 rx_req->in_fst_vlan_type = 9974 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9975 rx_req->in_sec_vlan_type = 9976 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9977 9978 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9979 if (status) { 9980 dev_err(&hdev->pdev->dev, 9981 "Send rxvlan protocol type command fail, ret =%d\n", 9982 status); 9983 return status; 9984 } 9985 9986 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9987 9988 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9989 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9990 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9991 9992 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9993 if (status) 9994 dev_err(&hdev->pdev->dev, 9995 "Send txvlan protocol type command fail, ret =%d\n", 9996 status); 9997 9998 return status; 9999 } 10000 10001 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 10002 { 10003 struct hclge_vport *vport; 10004 bool enable = true; 10005 int ret; 10006 int i; 10007 10008 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10009 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 10010 HCLGE_FILTER_FE_EGRESS_V1_B, 10011 true, 0); 10012 10013 /* for revision 0x21, vf vlan filter is per function */ 10014 for (i = 0; i < hdev->num_alloc_vport; i++) { 10015 vport = &hdev->vport[i]; 10016 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 10017 HCLGE_FILTER_FE_EGRESS, true, 10018 vport->vport_id); 10019 if (ret) 10020 return ret; 10021 vport->cur_vlan_fltr_en = true; 10022 } 10023 10024 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 10025 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 10026 enable = false; 10027 10028 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 10029 HCLGE_FILTER_FE_INGRESS, enable, 0); 10030 } 10031 10032 static int hclge_init_vlan_type(struct hclge_dev *hdev) 10033 { 10034 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 10035 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 10036 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 10037 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 10038 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 10039 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 10040 10041 return hclge_set_vlan_protocol_type(hdev); 10042 } 10043 10044 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 10045 { 10046 struct hclge_port_base_vlan_config *cfg; 10047 struct hclge_vport *vport; 10048 int ret; 10049 int i; 10050 10051 for (i = 0; i < hdev->num_alloc_vport; i++) { 10052 vport = &hdev->vport[i]; 10053 cfg = &vport->port_base_vlan_cfg; 10054 10055 ret = hclge_vlan_offload_cfg(vport, cfg->state, 10056 cfg->vlan_info.vlan_tag, 10057 cfg->vlan_info.qos); 10058 if (ret) 10059 return ret; 10060 } 10061 return 0; 10062 } 10063 10064 static int hclge_init_vlan_config(struct hclge_dev *hdev) 10065 { 10066 struct hnae3_handle *handle = &hdev->vport[0].nic; 10067 int ret; 10068 10069 ret = hclge_init_vlan_filter(hdev); 10070 if (ret) 10071 return ret; 10072 10073 ret = hclge_init_vlan_type(hdev); 10074 if (ret) 10075 return ret; 10076 10077 ret = hclge_init_vport_vlan_offload(hdev); 10078 if (ret) 10079 return ret; 10080 10081 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 10082 } 10083 10084 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10085 bool writen_to_tbl) 10086 { 10087 struct hclge_vport_vlan_cfg *vlan, *tmp; 10088 struct hclge_dev *hdev = vport->back; 10089 10090 mutex_lock(&hdev->vport_lock); 10091 10092 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10093 if (vlan->vlan_id == vlan_id) { 10094 mutex_unlock(&hdev->vport_lock); 10095 return; 10096 } 10097 } 10098 10099 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10100 if (!vlan) { 10101 mutex_unlock(&hdev->vport_lock); 10102 return; 10103 } 10104 10105 vlan->hd_tbl_status = writen_to_tbl; 10106 vlan->vlan_id = vlan_id; 10107 10108 list_add_tail(&vlan->node, &vport->vlan_list); 10109 mutex_unlock(&hdev->vport_lock); 10110 } 10111 10112 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10113 { 10114 struct hclge_vport_vlan_cfg *vlan, *tmp; 10115 struct hclge_dev *hdev = vport->back; 10116 int ret; 10117 10118 mutex_lock(&hdev->vport_lock); 10119 10120 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10121 if (!vlan->hd_tbl_status) { 10122 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10123 vport->vport_id, 10124 vlan->vlan_id, false); 10125 if (ret) { 10126 dev_err(&hdev->pdev->dev, 10127 "restore vport vlan list failed, ret=%d\n", 10128 ret); 10129 10130 mutex_unlock(&hdev->vport_lock); 10131 return ret; 10132 } 10133 } 10134 vlan->hd_tbl_status = true; 10135 } 10136 10137 mutex_unlock(&hdev->vport_lock); 10138 10139 return 0; 10140 } 10141 10142 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10143 bool is_write_tbl) 10144 { 10145 struct hclge_vport_vlan_cfg *vlan, *tmp; 10146 struct hclge_dev *hdev = vport->back; 10147 10148 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10149 if (vlan->vlan_id == vlan_id) { 10150 if (is_write_tbl && vlan->hd_tbl_status) 10151 hclge_set_vlan_filter_hw(hdev, 10152 htons(ETH_P_8021Q), 10153 vport->vport_id, 10154 vlan_id, 10155 true); 10156 10157 list_del(&vlan->node); 10158 kfree(vlan); 10159 break; 10160 } 10161 } 10162 } 10163 10164 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10165 { 10166 struct hclge_vport_vlan_cfg *vlan, *tmp; 10167 struct hclge_dev *hdev = vport->back; 10168 10169 mutex_lock(&hdev->vport_lock); 10170 10171 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10172 if (vlan->hd_tbl_status) 10173 hclge_set_vlan_filter_hw(hdev, 10174 htons(ETH_P_8021Q), 10175 vport->vport_id, 10176 vlan->vlan_id, 10177 true); 10178 10179 vlan->hd_tbl_status = false; 10180 if (is_del_list) { 10181 list_del(&vlan->node); 10182 kfree(vlan); 10183 } 10184 } 10185 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10186 mutex_unlock(&hdev->vport_lock); 10187 } 10188 10189 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10190 { 10191 struct hclge_vport_vlan_cfg *vlan, *tmp; 10192 struct hclge_vport *vport; 10193 int i; 10194 10195 mutex_lock(&hdev->vport_lock); 10196 10197 for (i = 0; i < hdev->num_alloc_vport; i++) { 10198 vport = &hdev->vport[i]; 10199 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10200 list_del(&vlan->node); 10201 kfree(vlan); 10202 } 10203 } 10204 10205 mutex_unlock(&hdev->vport_lock); 10206 } 10207 10208 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10209 { 10210 struct hclge_vlan_info *vlan_info; 10211 struct hclge_vport *vport; 10212 u16 vlan_proto; 10213 u16 vlan_id; 10214 u16 state; 10215 int vf_id; 10216 int ret; 10217 10218 /* PF should restore all vfs port base vlan */ 10219 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10220 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10221 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10222 &vport->port_base_vlan_cfg.vlan_info : 10223 &vport->port_base_vlan_cfg.old_vlan_info; 10224 10225 vlan_id = vlan_info->vlan_tag; 10226 vlan_proto = vlan_info->vlan_proto; 10227 state = vport->port_base_vlan_cfg.state; 10228 10229 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10230 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10231 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10232 vport->vport_id, 10233 vlan_id, false); 10234 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10235 } 10236 } 10237 } 10238 10239 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10240 { 10241 struct hclge_vport_vlan_cfg *vlan, *tmp; 10242 struct hclge_dev *hdev = vport->back; 10243 int ret; 10244 10245 mutex_lock(&hdev->vport_lock); 10246 10247 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10248 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10249 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10250 vport->vport_id, 10251 vlan->vlan_id, false); 10252 if (ret) 10253 break; 10254 vlan->hd_tbl_status = true; 10255 } 10256 } 10257 10258 mutex_unlock(&hdev->vport_lock); 10259 } 10260 10261 /* For global reset and imp reset, hardware will clear the mac table, 10262 * so we change the mac address state from ACTIVE to TO_ADD, then they 10263 * can be restored in the service task after reset complete. Furtherly, 10264 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10265 * be restored after reset, so just remove these mac nodes from mac_list. 10266 */ 10267 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10268 { 10269 struct hclge_mac_node *mac_node, *tmp; 10270 10271 list_for_each_entry_safe(mac_node, tmp, list, node) { 10272 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10273 mac_node->state = HCLGE_MAC_TO_ADD; 10274 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10275 list_del(&mac_node->node); 10276 kfree(mac_node); 10277 } 10278 } 10279 } 10280 10281 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10282 { 10283 spin_lock_bh(&vport->mac_list_lock); 10284 10285 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10286 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10287 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10288 10289 spin_unlock_bh(&vport->mac_list_lock); 10290 } 10291 10292 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10293 { 10294 struct hclge_vport *vport = &hdev->vport[0]; 10295 struct hnae3_handle *handle = &vport->nic; 10296 10297 hclge_restore_mac_table_common(vport); 10298 hclge_restore_vport_port_base_vlan_config(hdev); 10299 hclge_restore_vport_vlan_table(vport); 10300 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10301 hclge_restore_fd_entries(handle); 10302 } 10303 10304 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10305 { 10306 struct hclge_vport *vport = hclge_get_vport(handle); 10307 10308 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10309 vport->rxvlan_cfg.strip_tag1_en = false; 10310 vport->rxvlan_cfg.strip_tag2_en = enable; 10311 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10312 } else { 10313 vport->rxvlan_cfg.strip_tag1_en = enable; 10314 vport->rxvlan_cfg.strip_tag2_en = true; 10315 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10316 } 10317 10318 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10319 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10320 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10321 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10322 10323 return hclge_set_vlan_rx_offload_cfg(vport); 10324 } 10325 10326 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10327 { 10328 struct hclge_dev *hdev = vport->back; 10329 10330 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10331 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10332 } 10333 10334 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10335 u16 port_base_vlan_state, 10336 struct hclge_vlan_info *new_info, 10337 struct hclge_vlan_info *old_info) 10338 { 10339 struct hclge_dev *hdev = vport->back; 10340 int ret; 10341 10342 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10343 hclge_rm_vport_all_vlan_table(vport, false); 10344 /* force clear VLAN 0 */ 10345 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10346 if (ret) 10347 return ret; 10348 return hclge_set_vlan_filter_hw(hdev, 10349 htons(new_info->vlan_proto), 10350 vport->vport_id, 10351 new_info->vlan_tag, 10352 false); 10353 } 10354 10355 vport->port_base_vlan_cfg.tbl_sta = false; 10356 10357 /* force add VLAN 0 */ 10358 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10359 if (ret) 10360 return ret; 10361 10362 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10363 vport->vport_id, old_info->vlan_tag, 10364 true); 10365 if (ret) 10366 return ret; 10367 10368 return hclge_add_vport_all_vlan_table(vport); 10369 } 10370 10371 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10372 const struct hclge_vlan_info *old_cfg) 10373 { 10374 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10375 return true; 10376 10377 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10378 return true; 10379 10380 return false; 10381 } 10382 10383 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10384 struct hclge_vlan_info *new_info, 10385 struct hclge_vlan_info *old_info) 10386 { 10387 struct hclge_dev *hdev = vport->back; 10388 int ret; 10389 10390 /* add new VLAN tag */ 10391 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10392 vport->vport_id, new_info->vlan_tag, 10393 false); 10394 if (ret) 10395 return ret; 10396 10397 vport->port_base_vlan_cfg.tbl_sta = false; 10398 /* remove old VLAN tag */ 10399 if (old_info->vlan_tag == 0) 10400 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10401 true, 0); 10402 else 10403 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10404 vport->vport_id, 10405 old_info->vlan_tag, true); 10406 if (ret) 10407 dev_err(&hdev->pdev->dev, 10408 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10409 vport->vport_id, old_info->vlan_tag, ret); 10410 10411 return ret; 10412 } 10413 10414 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10415 struct hclge_vlan_info *vlan_info) 10416 { 10417 struct hnae3_handle *nic = &vport->nic; 10418 struct hclge_vlan_info *old_vlan_info; 10419 int ret; 10420 10421 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10422 10423 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10424 vlan_info->qos); 10425 if (ret) 10426 return ret; 10427 10428 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10429 goto out; 10430 10431 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10432 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10433 old_vlan_info); 10434 else 10435 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10436 old_vlan_info); 10437 if (ret) 10438 return ret; 10439 10440 out: 10441 vport->port_base_vlan_cfg.state = state; 10442 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10443 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10444 else 10445 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10446 10447 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10448 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10449 vport->port_base_vlan_cfg.tbl_sta = true; 10450 hclge_set_vport_vlan_fltr_change(vport); 10451 10452 return 0; 10453 } 10454 10455 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10456 enum hnae3_port_base_vlan_state state, 10457 u16 vlan, u8 qos) 10458 { 10459 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10460 if (!vlan && !qos) 10461 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10462 10463 return HNAE3_PORT_BASE_VLAN_ENABLE; 10464 } 10465 10466 if (!vlan && !qos) 10467 return HNAE3_PORT_BASE_VLAN_DISABLE; 10468 10469 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10470 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10471 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10472 10473 return HNAE3_PORT_BASE_VLAN_MODIFY; 10474 } 10475 10476 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10477 u16 vlan, u8 qos, __be16 proto) 10478 { 10479 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10480 struct hclge_vport *vport = hclge_get_vport(handle); 10481 struct hclge_dev *hdev = vport->back; 10482 struct hclge_vlan_info vlan_info; 10483 u16 state; 10484 int ret; 10485 10486 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10487 return -EOPNOTSUPP; 10488 10489 vport = hclge_get_vf_vport(hdev, vfid); 10490 if (!vport) 10491 return -EINVAL; 10492 10493 /* qos is a 3 bits value, so can not be bigger than 7 */ 10494 if (vlan > VLAN_N_VID - 1 || qos > 7) 10495 return -EINVAL; 10496 if (proto != htons(ETH_P_8021Q)) 10497 return -EPROTONOSUPPORT; 10498 10499 state = hclge_get_port_base_vlan_state(vport, 10500 vport->port_base_vlan_cfg.state, 10501 vlan, qos); 10502 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10503 return 0; 10504 10505 vlan_info.vlan_tag = vlan; 10506 vlan_info.qos = qos; 10507 vlan_info.vlan_proto = ntohs(proto); 10508 10509 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10510 if (ret) { 10511 dev_err(&hdev->pdev->dev, 10512 "failed to update port base vlan for vf %d, ret = %d\n", 10513 vfid, ret); 10514 return ret; 10515 } 10516 10517 /* there is a timewindow for PF to know VF unalive, it may 10518 * cause send mailbox fail, but it doesn't matter, VF will 10519 * query it when reinit. 10520 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10521 * VLAN state. 10522 */ 10523 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10524 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10525 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10526 vport->vport_id, 10527 state, 10528 &vlan_info); 10529 else 10530 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10531 &vport->need_notify); 10532 } 10533 return 0; 10534 } 10535 10536 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10537 { 10538 struct hclge_vlan_info *vlan_info; 10539 struct hclge_vport *vport; 10540 int ret; 10541 int vf; 10542 10543 /* clear port base vlan for all vf */ 10544 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10545 vport = &hdev->vport[vf]; 10546 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10547 10548 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10549 vport->vport_id, 10550 vlan_info->vlan_tag, true); 10551 if (ret) 10552 dev_err(&hdev->pdev->dev, 10553 "failed to clear vf vlan for vf%d, ret = %d\n", 10554 vf - HCLGE_VF_VPORT_START_NUM, ret); 10555 } 10556 } 10557 10558 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10559 u16 vlan_id, bool is_kill) 10560 { 10561 struct hclge_vport *vport = hclge_get_vport(handle); 10562 struct hclge_dev *hdev = vport->back; 10563 bool writen_to_tbl = false; 10564 int ret = 0; 10565 10566 /* When device is resetting or reset failed, firmware is unable to 10567 * handle mailbox. Just record the vlan id, and remove it after 10568 * reset finished. 10569 */ 10570 mutex_lock(&hdev->vport_lock); 10571 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10572 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10573 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10574 mutex_unlock(&hdev->vport_lock); 10575 return -EBUSY; 10576 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 10577 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10578 } 10579 mutex_unlock(&hdev->vport_lock); 10580 10581 /* when port base vlan enabled, we use port base vlan as the vlan 10582 * filter entry. In this case, we don't update vlan filter table 10583 * when user add new vlan or remove exist vlan, just update the vport 10584 * vlan list. The vlan id in vlan list will be writen in vlan filter 10585 * table until port base vlan disabled 10586 */ 10587 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10588 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10589 vlan_id, is_kill); 10590 writen_to_tbl = true; 10591 } 10592 10593 if (!ret) { 10594 if (!is_kill) { 10595 hclge_add_vport_vlan_table(vport, vlan_id, 10596 writen_to_tbl); 10597 } else if (is_kill && vlan_id != 0) { 10598 mutex_lock(&hdev->vport_lock); 10599 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10600 mutex_unlock(&hdev->vport_lock); 10601 } 10602 } else if (is_kill) { 10603 /* when remove hw vlan filter failed, record the vlan id, 10604 * and try to remove it from hw later, to be consistence 10605 * with stack 10606 */ 10607 mutex_lock(&hdev->vport_lock); 10608 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10609 mutex_unlock(&hdev->vport_lock); 10610 } 10611 10612 hclge_set_vport_vlan_fltr_change(vport); 10613 10614 return ret; 10615 } 10616 10617 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10618 { 10619 struct hclge_vport *vport; 10620 int ret; 10621 u16 i; 10622 10623 for (i = 0; i < hdev->num_alloc_vport; i++) { 10624 vport = &hdev->vport[i]; 10625 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10626 &vport->state)) 10627 continue; 10628 10629 mutex_lock(&hdev->vport_lock); 10630 ret = __hclge_enable_vport_vlan_filter(vport, 10631 vport->req_vlan_fltr_en); 10632 if (ret) { 10633 dev_err(&hdev->pdev->dev, 10634 "failed to sync vlan filter state for vport%u, ret = %d\n", 10635 vport->vport_id, ret); 10636 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10637 &vport->state); 10638 mutex_unlock(&hdev->vport_lock); 10639 return; 10640 } 10641 mutex_unlock(&hdev->vport_lock); 10642 } 10643 } 10644 10645 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10646 { 10647 #define HCLGE_MAX_SYNC_COUNT 60 10648 10649 int i, ret, sync_cnt = 0; 10650 u16 vlan_id; 10651 10652 mutex_lock(&hdev->vport_lock); 10653 /* start from vport 1 for PF is always alive */ 10654 for (i = 0; i < hdev->num_alloc_vport; i++) { 10655 struct hclge_vport *vport = &hdev->vport[i]; 10656 10657 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10658 VLAN_N_VID); 10659 while (vlan_id != VLAN_N_VID) { 10660 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10661 vport->vport_id, vlan_id, 10662 true); 10663 if (ret && ret != -EINVAL) { 10664 mutex_unlock(&hdev->vport_lock); 10665 return; 10666 } 10667 10668 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10669 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10670 hclge_set_vport_vlan_fltr_change(vport); 10671 10672 sync_cnt++; 10673 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 10674 mutex_unlock(&hdev->vport_lock); 10675 return; 10676 } 10677 10678 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10679 VLAN_N_VID); 10680 } 10681 } 10682 mutex_unlock(&hdev->vport_lock); 10683 10684 hclge_sync_vlan_fltr_state(hdev); 10685 } 10686 10687 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10688 { 10689 struct hclge_config_max_frm_size_cmd *req; 10690 struct hclge_desc desc; 10691 10692 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10693 10694 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10695 req->max_frm_size = cpu_to_le16(new_mps); 10696 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10697 10698 return hclge_cmd_send(&hdev->hw, &desc, 1); 10699 } 10700 10701 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10702 { 10703 struct hclge_vport *vport = hclge_get_vport(handle); 10704 10705 return hclge_set_vport_mtu(vport, new_mtu); 10706 } 10707 10708 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10709 { 10710 struct hclge_dev *hdev = vport->back; 10711 int i, max_frm_size, ret; 10712 10713 /* HW supprt 2 layer vlan */ 10714 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10715 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10716 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10717 return -EINVAL; 10718 10719 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10720 mutex_lock(&hdev->vport_lock); 10721 /* VF's mps must fit within hdev->mps */ 10722 if (vport->vport_id && (u32)max_frm_size > hdev->mps) { 10723 mutex_unlock(&hdev->vport_lock); 10724 return -EINVAL; 10725 } else if (vport->vport_id) { 10726 vport->mps = max_frm_size; 10727 mutex_unlock(&hdev->vport_lock); 10728 return 0; 10729 } 10730 10731 /* PF's mps must be greater then VF's mps */ 10732 for (i = 1; i < hdev->num_alloc_vport; i++) 10733 if ((u32)max_frm_size < hdev->vport[i].mps) { 10734 dev_err(&hdev->pdev->dev, 10735 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10736 i, hdev->vport[i].mps); 10737 mutex_unlock(&hdev->vport_lock); 10738 return -EINVAL; 10739 } 10740 10741 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10742 10743 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10744 if (ret) { 10745 dev_err(&hdev->pdev->dev, 10746 "Change mtu fail, ret =%d\n", ret); 10747 goto out; 10748 } 10749 10750 hdev->mps = max_frm_size; 10751 vport->mps = max_frm_size; 10752 10753 ret = hclge_buffer_alloc(hdev); 10754 if (ret) 10755 dev_err(&hdev->pdev->dev, 10756 "Allocate buffer fail, ret =%d\n", ret); 10757 10758 out: 10759 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10760 mutex_unlock(&hdev->vport_lock); 10761 return ret; 10762 } 10763 10764 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10765 bool enable) 10766 { 10767 struct hclge_reset_tqp_queue_cmd *req; 10768 struct hclge_desc desc; 10769 int ret; 10770 10771 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10772 10773 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10774 req->tqp_id = cpu_to_le16(queue_id); 10775 if (enable) 10776 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10777 10778 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10779 if (ret) { 10780 dev_err(&hdev->pdev->dev, 10781 "Send tqp reset cmd error, status =%d\n", ret); 10782 return ret; 10783 } 10784 10785 return 0; 10786 } 10787 10788 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10789 u8 *reset_status) 10790 { 10791 struct hclge_reset_tqp_queue_cmd *req; 10792 struct hclge_desc desc; 10793 int ret; 10794 10795 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10796 10797 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10798 req->tqp_id = cpu_to_le16(queue_id); 10799 10800 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10801 if (ret) { 10802 dev_err(&hdev->pdev->dev, 10803 "Get reset status error, status =%d\n", ret); 10804 return ret; 10805 } 10806 10807 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10808 10809 return 0; 10810 } 10811 10812 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10813 { 10814 struct hclge_comm_tqp *tqp; 10815 struct hnae3_queue *queue; 10816 10817 queue = handle->kinfo.tqp[queue_id]; 10818 tqp = container_of(queue, struct hclge_comm_tqp, q); 10819 10820 return tqp->index; 10821 } 10822 10823 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10824 { 10825 struct hclge_vport *vport = hclge_get_vport(handle); 10826 struct hclge_dev *hdev = vport->back; 10827 u16 reset_try_times = 0; 10828 u8 reset_status; 10829 u16 queue_gid; 10830 int ret; 10831 u16 i; 10832 10833 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10834 queue_gid = hclge_covert_handle_qid_global(handle, i); 10835 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10836 if (ret) { 10837 dev_err(&hdev->pdev->dev, 10838 "failed to send reset tqp cmd, ret = %d\n", 10839 ret); 10840 return ret; 10841 } 10842 10843 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10844 ret = hclge_get_reset_status(hdev, queue_gid, 10845 &reset_status); 10846 if (ret) 10847 return ret; 10848 10849 if (reset_status) 10850 break; 10851 10852 /* Wait for tqp hw reset */ 10853 usleep_range(1000, 1200); 10854 } 10855 10856 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10857 dev_err(&hdev->pdev->dev, 10858 "wait for tqp hw reset timeout\n"); 10859 return -ETIME; 10860 } 10861 10862 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10863 if (ret) { 10864 dev_err(&hdev->pdev->dev, 10865 "failed to deassert soft reset, ret = %d\n", 10866 ret); 10867 return ret; 10868 } 10869 reset_try_times = 0; 10870 } 10871 return 0; 10872 } 10873 10874 static int hclge_reset_rcb(struct hnae3_handle *handle) 10875 { 10876 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10877 #define HCLGE_RESET_RCB_SUCCESS 1U 10878 10879 struct hclge_vport *vport = hclge_get_vport(handle); 10880 struct hclge_dev *hdev = vport->back; 10881 struct hclge_reset_cmd *req; 10882 struct hclge_desc desc; 10883 u8 return_status; 10884 u16 queue_gid; 10885 int ret; 10886 10887 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10888 10889 req = (struct hclge_reset_cmd *)desc.data; 10890 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10891 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10892 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10893 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10894 10895 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10896 if (ret) { 10897 dev_err(&hdev->pdev->dev, 10898 "failed to send rcb reset cmd, ret = %d\n", ret); 10899 return ret; 10900 } 10901 10902 return_status = req->fun_reset_rcb_return_status; 10903 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10904 return 0; 10905 10906 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10907 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10908 return_status); 10909 return -EIO; 10910 } 10911 10912 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10913 * again to reset all tqps 10914 */ 10915 return hclge_reset_tqp_cmd(handle); 10916 } 10917 10918 int hclge_reset_tqp(struct hnae3_handle *handle) 10919 { 10920 struct hclge_vport *vport = hclge_get_vport(handle); 10921 struct hclge_dev *hdev = vport->back; 10922 int ret; 10923 10924 /* only need to disable PF's tqp */ 10925 if (!vport->vport_id) { 10926 ret = hclge_tqp_enable(handle, false); 10927 if (ret) { 10928 dev_err(&hdev->pdev->dev, 10929 "failed to disable tqp, ret = %d\n", ret); 10930 return ret; 10931 } 10932 } 10933 10934 return hclge_reset_rcb(handle); 10935 } 10936 10937 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10938 { 10939 struct hclge_vport *vport = hclge_get_vport(handle); 10940 struct hclge_dev *hdev = vport->back; 10941 10942 return hdev->fw_version; 10943 } 10944 10945 int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version) 10946 { 10947 struct hclge_comm_query_scc_cmd *resp; 10948 struct hclge_desc desc; 10949 int ret; 10950 10951 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_SCC_VER, 1); 10952 resp = (struct hclge_comm_query_scc_cmd *)desc.data; 10953 10954 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10955 if (ret) 10956 return ret; 10957 10958 *scc_version = le32_to_cpu(resp->scc_version); 10959 10960 return 0; 10961 } 10962 10963 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10964 { 10965 struct phy_device *phydev = hdev->hw.mac.phydev; 10966 10967 if (!phydev) 10968 return; 10969 10970 phy_set_asym_pause(phydev, rx_en, tx_en); 10971 } 10972 10973 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10974 { 10975 int ret; 10976 10977 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10978 return 0; 10979 10980 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10981 if (ret) 10982 dev_err(&hdev->pdev->dev, 10983 "configure pauseparam error, ret = %d.\n", ret); 10984 10985 return ret; 10986 } 10987 10988 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10989 { 10990 struct phy_device *phydev = hdev->hw.mac.phydev; 10991 u16 remote_advertising = 0; 10992 u16 local_advertising; 10993 u32 rx_pause, tx_pause; 10994 u8 flowctl; 10995 10996 if (!phydev->link) 10997 return 0; 10998 10999 if (!phydev->autoneg) 11000 return hclge_mac_pause_setup_hw(hdev); 11001 11002 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 11003 11004 if (phydev->pause) 11005 remote_advertising = LPA_PAUSE_CAP; 11006 11007 if (phydev->asym_pause) 11008 remote_advertising |= LPA_PAUSE_ASYM; 11009 11010 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 11011 remote_advertising); 11012 tx_pause = flowctl & FLOW_CTRL_TX; 11013 rx_pause = flowctl & FLOW_CTRL_RX; 11014 11015 if (phydev->duplex == HCLGE_MAC_HALF) { 11016 tx_pause = 0; 11017 rx_pause = 0; 11018 } 11019 11020 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 11021 } 11022 11023 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 11024 u32 *rx_en, u32 *tx_en) 11025 { 11026 struct hclge_vport *vport = hclge_get_vport(handle); 11027 struct hclge_dev *hdev = vport->back; 11028 u8 media_type = hdev->hw.mac.media_type; 11029 11030 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 11031 hclge_get_autoneg(handle) : 0; 11032 11033 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11034 *rx_en = 0; 11035 *tx_en = 0; 11036 return; 11037 } 11038 11039 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 11040 *rx_en = 1; 11041 *tx_en = 0; 11042 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 11043 *tx_en = 1; 11044 *rx_en = 0; 11045 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 11046 *rx_en = 1; 11047 *tx_en = 1; 11048 } else { 11049 *rx_en = 0; 11050 *tx_en = 0; 11051 } 11052 } 11053 11054 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 11055 u32 rx_en, u32 tx_en) 11056 { 11057 if (rx_en && tx_en) 11058 hdev->fc_mode_last_time = HCLGE_FC_FULL; 11059 else if (rx_en && !tx_en) 11060 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 11061 else if (!rx_en && tx_en) 11062 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 11063 else 11064 hdev->fc_mode_last_time = HCLGE_FC_NONE; 11065 11066 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 11067 } 11068 11069 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 11070 u32 rx_en, u32 tx_en) 11071 { 11072 struct hclge_vport *vport = hclge_get_vport(handle); 11073 struct hclge_dev *hdev = vport->back; 11074 struct phy_device *phydev = hdev->hw.mac.phydev; 11075 u32 fc_autoneg; 11076 11077 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 11078 fc_autoneg = hclge_get_autoneg(handle); 11079 if (auto_neg != fc_autoneg) { 11080 dev_info(&hdev->pdev->dev, 11081 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 11082 return -EOPNOTSUPP; 11083 } 11084 } 11085 11086 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11087 dev_info(&hdev->pdev->dev, 11088 "Priority flow control enabled. Cannot set link flow control.\n"); 11089 return -EOPNOTSUPP; 11090 } 11091 11092 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 11093 11094 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 11095 11096 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 11097 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 11098 11099 if (phydev) 11100 return phy_start_aneg(phydev); 11101 11102 return -EOPNOTSUPP; 11103 } 11104 11105 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 11106 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 11107 { 11108 struct hclge_vport *vport = hclge_get_vport(handle); 11109 struct hclge_dev *hdev = vport->back; 11110 11111 if (speed) 11112 *speed = hdev->hw.mac.speed; 11113 if (duplex) 11114 *duplex = hdev->hw.mac.duplex; 11115 if (auto_neg) 11116 *auto_neg = hdev->hw.mac.autoneg; 11117 if (lane_num) 11118 *lane_num = hdev->hw.mac.lane_num; 11119 } 11120 11121 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11122 u8 *module_type) 11123 { 11124 struct hclge_vport *vport = hclge_get_vport(handle); 11125 struct hclge_dev *hdev = vport->back; 11126 11127 /* When nic is down, the service task is not running, doesn't update 11128 * the port information per second. Query the port information before 11129 * return the media type, ensure getting the correct media information. 11130 */ 11131 hclge_update_port_info(hdev); 11132 11133 if (media_type) 11134 *media_type = hdev->hw.mac.media_type; 11135 11136 if (module_type) 11137 *module_type = hdev->hw.mac.module_type; 11138 } 11139 11140 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11141 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11142 { 11143 struct hclge_vport *vport = hclge_get_vport(handle); 11144 struct hclge_dev *hdev = vport->back; 11145 struct phy_device *phydev = hdev->hw.mac.phydev; 11146 int mdix_ctrl, mdix, is_resolved; 11147 unsigned int retval; 11148 11149 if (!phydev) { 11150 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11151 *tp_mdix = ETH_TP_MDI_INVALID; 11152 return; 11153 } 11154 11155 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11156 11157 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11158 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11159 HCLGE_PHY_MDIX_CTRL_S); 11160 11161 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11162 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11163 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11164 11165 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11166 11167 switch (mdix_ctrl) { 11168 case 0x0: 11169 *tp_mdix_ctrl = ETH_TP_MDI; 11170 break; 11171 case 0x1: 11172 *tp_mdix_ctrl = ETH_TP_MDI_X; 11173 break; 11174 case 0x3: 11175 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11176 break; 11177 default: 11178 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11179 break; 11180 } 11181 11182 if (!is_resolved) 11183 *tp_mdix = ETH_TP_MDI_INVALID; 11184 else if (mdix) 11185 *tp_mdix = ETH_TP_MDI_X; 11186 else 11187 *tp_mdix = ETH_TP_MDI; 11188 } 11189 11190 static void hclge_info_show(struct hclge_dev *hdev) 11191 { 11192 struct hnae3_handle *handle = &hdev->vport->nic; 11193 struct device *dev = &hdev->pdev->dev; 11194 11195 dev_info(dev, "PF info begin:\n"); 11196 11197 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11198 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11199 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11200 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11201 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11202 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11203 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11204 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11205 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11206 dev_info(dev, "This is %s PF\n", 11207 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11208 dev_info(dev, "DCB %s\n", 11209 str_enable_disable(handle->kinfo.tc_info.dcb_ets_active)); 11210 dev_info(dev, "MQPRIO %s\n", 11211 str_enable_disable(handle->kinfo.tc_info.mqprio_active)); 11212 dev_info(dev, "Default tx spare buffer size: %u\n", 11213 hdev->tx_spare_buf_size); 11214 11215 dev_info(dev, "PF info end.\n"); 11216 } 11217 11218 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11219 struct hclge_vport *vport) 11220 { 11221 struct hnae3_client *client = vport->nic.client; 11222 struct hclge_dev *hdev = ae_dev->priv; 11223 u32 rst_cnt = hdev->rst_stats.reset_cnt; 11224 int ret; 11225 11226 ret = client->ops->init_instance(&vport->nic); 11227 if (ret) 11228 return ret; 11229 11230 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11231 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11232 rst_cnt != hdev->rst_stats.reset_cnt) { 11233 ret = -EBUSY; 11234 goto init_nic_err; 11235 } 11236 11237 /* Enable nic hw error interrupts */ 11238 ret = hclge_config_nic_hw_error(hdev, true); 11239 if (ret) { 11240 dev_err(&ae_dev->pdev->dev, 11241 "fail(%d) to enable hw error interrupts\n", ret); 11242 goto init_nic_err; 11243 } 11244 11245 hnae3_set_client_init_flag(client, ae_dev, 1); 11246 11247 if (netif_msg_drv(&hdev->vport->nic)) 11248 hclge_info_show(hdev); 11249 11250 return ret; 11251 11252 init_nic_err: 11253 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11254 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11255 msleep(HCLGE_WAIT_RESET_DONE); 11256 11257 client->ops->uninit_instance(&vport->nic, 0); 11258 11259 return ret; 11260 } 11261 11262 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11263 struct hclge_vport *vport) 11264 { 11265 struct hclge_dev *hdev = ae_dev->priv; 11266 struct hnae3_client *client; 11267 u32 rst_cnt; 11268 int ret; 11269 11270 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11271 !hdev->nic_client) 11272 return 0; 11273 11274 client = hdev->roce_client; 11275 ret = hclge_init_roce_base_info(vport); 11276 if (ret) 11277 return ret; 11278 11279 rst_cnt = hdev->rst_stats.reset_cnt; 11280 ret = client->ops->init_instance(&vport->roce); 11281 if (ret) 11282 return ret; 11283 11284 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11285 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11286 rst_cnt != hdev->rst_stats.reset_cnt) { 11287 ret = -EBUSY; 11288 goto init_roce_err; 11289 } 11290 11291 /* Enable roce ras interrupts */ 11292 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11293 if (ret) { 11294 dev_err(&ae_dev->pdev->dev, 11295 "fail(%d) to enable roce ras interrupts\n", ret); 11296 goto init_roce_err; 11297 } 11298 11299 hnae3_set_client_init_flag(client, ae_dev, 1); 11300 11301 return 0; 11302 11303 init_roce_err: 11304 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11305 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11306 msleep(HCLGE_WAIT_RESET_DONE); 11307 11308 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11309 11310 return ret; 11311 } 11312 11313 static int hclge_init_client_instance(struct hnae3_client *client, 11314 struct hnae3_ae_dev *ae_dev) 11315 { 11316 struct hclge_dev *hdev = ae_dev->priv; 11317 struct hclge_vport *vport = &hdev->vport[0]; 11318 int ret; 11319 11320 switch (client->type) { 11321 case HNAE3_CLIENT_KNIC: 11322 hdev->nic_client = client; 11323 vport->nic.client = client; 11324 ret = hclge_init_nic_client_instance(ae_dev, vport); 11325 if (ret) 11326 goto clear_nic; 11327 11328 ret = hclge_init_roce_client_instance(ae_dev, vport); 11329 if (ret) 11330 goto clear_roce; 11331 11332 break; 11333 case HNAE3_CLIENT_ROCE: 11334 if (hnae3_dev_roce_supported(hdev)) { 11335 hdev->roce_client = client; 11336 vport->roce.client = client; 11337 } 11338 11339 ret = hclge_init_roce_client_instance(ae_dev, vport); 11340 if (ret) 11341 goto clear_roce; 11342 11343 break; 11344 default: 11345 return -EINVAL; 11346 } 11347 11348 return 0; 11349 11350 clear_nic: 11351 hdev->nic_client = NULL; 11352 vport->nic.client = NULL; 11353 return ret; 11354 clear_roce: 11355 hdev->roce_client = NULL; 11356 vport->roce.client = NULL; 11357 return ret; 11358 } 11359 11360 static bool hclge_uninit_need_wait(struct hclge_dev *hdev) 11361 { 11362 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11363 test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 11364 } 11365 11366 static void hclge_uninit_client_instance(struct hnae3_client *client, 11367 struct hnae3_ae_dev *ae_dev) 11368 { 11369 struct hclge_dev *hdev = ae_dev->priv; 11370 struct hclge_vport *vport = &hdev->vport[0]; 11371 11372 if (hdev->roce_client) { 11373 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11374 while (hclge_uninit_need_wait(hdev)) 11375 msleep(HCLGE_WAIT_RESET_DONE); 11376 11377 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11378 hdev->roce_client = NULL; 11379 vport->roce.client = NULL; 11380 } 11381 if (client->type == HNAE3_CLIENT_ROCE) 11382 return; 11383 if (hdev->nic_client && client->ops->uninit_instance) { 11384 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11385 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11386 msleep(HCLGE_WAIT_RESET_DONE); 11387 11388 client->ops->uninit_instance(&vport->nic, 0); 11389 hdev->nic_client = NULL; 11390 vport->nic.client = NULL; 11391 } 11392 } 11393 11394 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11395 { 11396 struct pci_dev *pdev = hdev->pdev; 11397 struct hclge_hw *hw = &hdev->hw; 11398 11399 /* for device does not have device memory, return directly */ 11400 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11401 return 0; 11402 11403 hw->hw.mem_base = 11404 devm_ioremap_wc(&pdev->dev, 11405 pci_resource_start(pdev, HCLGE_MEM_BAR), 11406 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11407 if (!hw->hw.mem_base) { 11408 dev_err(&pdev->dev, "failed to map device memory\n"); 11409 return -EFAULT; 11410 } 11411 11412 return 0; 11413 } 11414 11415 static int hclge_pci_init(struct hclge_dev *hdev) 11416 { 11417 struct pci_dev *pdev = hdev->pdev; 11418 struct hclge_hw *hw; 11419 int ret; 11420 11421 ret = pci_enable_device(pdev); 11422 if (ret) { 11423 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11424 return ret; 11425 } 11426 11427 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11428 if (ret) { 11429 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11430 if (ret) { 11431 dev_err(&pdev->dev, 11432 "can't set consistent PCI DMA\n"); 11433 goto err_disable_device; 11434 } 11435 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11436 } 11437 11438 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11439 if (ret) { 11440 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11441 goto err_disable_device; 11442 } 11443 11444 pci_set_master(pdev); 11445 hw = &hdev->hw; 11446 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11447 if (!hw->hw.io_base) { 11448 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11449 ret = -ENOMEM; 11450 goto err_release_regions; 11451 } 11452 11453 ret = hclge_dev_mem_map(hdev); 11454 if (ret) 11455 goto err_unmap_io_base; 11456 11457 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11458 11459 return 0; 11460 11461 err_unmap_io_base: 11462 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11463 err_release_regions: 11464 pci_release_regions(pdev); 11465 err_disable_device: 11466 pci_disable_device(pdev); 11467 11468 return ret; 11469 } 11470 11471 static void hclge_pci_uninit(struct hclge_dev *hdev) 11472 { 11473 struct pci_dev *pdev = hdev->pdev; 11474 11475 if (hdev->hw.hw.mem_base) 11476 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11477 11478 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11479 pci_free_irq_vectors(pdev); 11480 pci_release_regions(pdev); 11481 pci_disable_device(pdev); 11482 } 11483 11484 static void hclge_state_init(struct hclge_dev *hdev) 11485 { 11486 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11487 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11488 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11489 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11490 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11491 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11492 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11493 } 11494 11495 static void hclge_state_uninit(struct hclge_dev *hdev) 11496 { 11497 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11498 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11499 11500 if (hdev->reset_timer.function) 11501 timer_delete_sync(&hdev->reset_timer); 11502 if (hdev->service_task.work.func) 11503 cancel_delayed_work_sync(&hdev->service_task); 11504 } 11505 11506 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11507 enum hnae3_reset_type rst_type) 11508 { 11509 #define HCLGE_RESET_RETRY_WAIT_MS 500 11510 #define HCLGE_RESET_RETRY_CNT 5 11511 11512 struct hclge_dev *hdev = ae_dev->priv; 11513 int retry_cnt = 0; 11514 int ret; 11515 11516 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11517 down(&hdev->reset_sem); 11518 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11519 hdev->reset_type = rst_type; 11520 ret = hclge_reset_prepare(hdev); 11521 if (!ret && !hdev->reset_pending) 11522 break; 11523 11524 dev_err(&hdev->pdev->dev, 11525 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11526 ret, hdev->reset_pending, retry_cnt); 11527 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11528 up(&hdev->reset_sem); 11529 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11530 } 11531 11532 /* disable misc vector before reset done */ 11533 hclge_enable_vector(&hdev->misc_vector, false); 11534 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11535 11536 if (hdev->reset_type == HNAE3_FLR_RESET) 11537 hdev->rst_stats.flr_rst_cnt++; 11538 } 11539 11540 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11541 { 11542 struct hclge_dev *hdev = ae_dev->priv; 11543 int ret; 11544 11545 hclge_enable_vector(&hdev->misc_vector, true); 11546 11547 ret = hclge_reset_rebuild(hdev); 11548 if (ret) 11549 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11550 11551 hdev->reset_type = HNAE3_NONE_RESET; 11552 if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11553 up(&hdev->reset_sem); 11554 } 11555 11556 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11557 { 11558 u16 i; 11559 11560 for (i = 0; i < hdev->num_alloc_vport; i++) { 11561 struct hclge_vport *vport = &hdev->vport[i]; 11562 int ret; 11563 11564 /* Send cmd to clear vport's FUNC_RST_ING */ 11565 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11566 if (ret) 11567 dev_warn(&hdev->pdev->dev, 11568 "clear vport(%u) rst failed %d!\n", 11569 vport->vport_id, ret); 11570 } 11571 } 11572 11573 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11574 { 11575 struct hclge_desc desc; 11576 int ret; 11577 11578 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11579 11580 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11581 /* This new command is only supported by new firmware, it will 11582 * fail with older firmware. Error value -EOPNOSUPP can only be 11583 * returned by older firmware running this command, to keep code 11584 * backward compatible we will override this value and return 11585 * success. 11586 */ 11587 if (ret && ret != -EOPNOTSUPP) { 11588 dev_err(&hdev->pdev->dev, 11589 "failed to clear hw resource, ret = %d\n", ret); 11590 return ret; 11591 } 11592 return 0; 11593 } 11594 11595 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11596 { 11597 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11598 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11599 } 11600 11601 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11602 { 11603 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11604 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11605 } 11606 11607 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11608 { 11609 struct hclge_vport *vport = hclge_get_vport(handle); 11610 11611 return &vport->back->hw.mac.wol; 11612 } 11613 11614 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11615 u32 *wol_supported) 11616 { 11617 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11618 struct hclge_desc desc; 11619 int ret; 11620 11621 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11622 true); 11623 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11624 11625 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11626 if (ret) { 11627 dev_err(&hdev->pdev->dev, 11628 "failed to query wol supported, ret = %d\n", ret); 11629 return ret; 11630 } 11631 11632 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11633 11634 return 0; 11635 } 11636 11637 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11638 struct hclge_wol_info *wol_info) 11639 { 11640 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11641 struct hclge_desc desc; 11642 int ret; 11643 11644 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11645 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11646 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11647 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11648 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11649 11650 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11651 if (ret) 11652 dev_err(&hdev->pdev->dev, 11653 "failed to set wol config, ret = %d\n", ret); 11654 11655 return ret; 11656 } 11657 11658 static int hclge_update_wol(struct hclge_dev *hdev) 11659 { 11660 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11661 11662 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11663 return 0; 11664 11665 return hclge_set_wol_cfg(hdev, wol_info); 11666 } 11667 11668 static int hclge_init_wol(struct hclge_dev *hdev) 11669 { 11670 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11671 int ret; 11672 11673 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11674 return 0; 11675 11676 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11677 ret = hclge_get_wol_supported_mode(hdev, 11678 &wol_info->wol_support_mode); 11679 if (ret) { 11680 wol_info->wol_support_mode = 0; 11681 return ret; 11682 } 11683 11684 return hclge_update_wol(hdev); 11685 } 11686 11687 static void hclge_get_wol(struct hnae3_handle *handle, 11688 struct ethtool_wolinfo *wol) 11689 { 11690 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11691 11692 wol->supported = wol_info->wol_support_mode; 11693 wol->wolopts = wol_info->wol_current_mode; 11694 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11695 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11696 } 11697 11698 static int hclge_set_wol(struct hnae3_handle *handle, 11699 struct ethtool_wolinfo *wol) 11700 { 11701 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11702 struct hclge_vport *vport = hclge_get_vport(handle); 11703 u32 wol_mode; 11704 int ret; 11705 11706 wol_mode = wol->wolopts; 11707 if (wol_mode & ~wol_info->wol_support_mode) 11708 return -EINVAL; 11709 11710 wol_info->wol_current_mode = wol_mode; 11711 if (wol_mode & WAKE_MAGICSECURE) { 11712 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11713 wol_info->wol_sopass_size = SOPASS_MAX; 11714 } else { 11715 wol_info->wol_sopass_size = 0; 11716 } 11717 11718 ret = hclge_set_wol_cfg(vport->back, wol_info); 11719 if (ret) 11720 wol_info->wol_current_mode = 0; 11721 11722 return ret; 11723 } 11724 11725 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11726 { 11727 struct pci_dev *pdev = ae_dev->pdev; 11728 struct hclge_dev *hdev; 11729 int ret; 11730 11731 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11732 if (!hdev) 11733 return -ENOMEM; 11734 11735 hdev->pdev = pdev; 11736 hdev->ae_dev = ae_dev; 11737 hdev->reset_type = HNAE3_NONE_RESET; 11738 hdev->reset_level = HNAE3_FUNC_RESET; 11739 ae_dev->priv = hdev; 11740 11741 /* HW supprt 2 layer vlan */ 11742 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11743 11744 mutex_init(&hdev->vport_lock); 11745 spin_lock_init(&hdev->fd_rule_lock); 11746 sema_init(&hdev->reset_sem, 1); 11747 11748 ret = hclge_pci_init(hdev); 11749 if (ret) 11750 goto out; 11751 11752 /* Firmware command queue initialize */ 11753 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11754 if (ret) 11755 goto err_pci_uninit; 11756 11757 /* Firmware command initialize */ 11758 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops); 11759 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11760 true, hdev->reset_pending); 11761 if (ret) 11762 goto err_cmd_uninit; 11763 11764 ret = hclge_clear_hw_resource(hdev); 11765 if (ret) 11766 goto err_cmd_uninit; 11767 11768 ret = hclge_get_cap(hdev); 11769 if (ret) 11770 goto err_cmd_uninit; 11771 11772 ret = hclge_query_dev_specs(hdev); 11773 if (ret) { 11774 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11775 ret); 11776 goto err_cmd_uninit; 11777 } 11778 11779 ret = hclge_configure(hdev); 11780 if (ret) { 11781 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11782 goto err_cmd_uninit; 11783 } 11784 11785 ret = hclge_init_msi(hdev); 11786 if (ret) { 11787 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11788 goto err_cmd_uninit; 11789 } 11790 11791 ret = hclge_misc_irq_init(hdev); 11792 if (ret) 11793 goto err_msi_uninit; 11794 11795 ret = hclge_alloc_tqps(hdev); 11796 if (ret) { 11797 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11798 goto err_msi_irq_uninit; 11799 } 11800 11801 ret = hclge_alloc_vport(hdev); 11802 if (ret) 11803 goto err_msi_irq_uninit; 11804 11805 ret = hclge_map_tqp(hdev); 11806 if (ret) 11807 goto err_msi_irq_uninit; 11808 11809 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11810 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 11811 if (hnae3_dev_phy_imp_supported(hdev)) 11812 ret = hclge_update_tp_port_info(hdev); 11813 else 11814 ret = hclge_mac_mdio_config(hdev); 11815 11816 if (ret) 11817 goto err_msi_irq_uninit; 11818 } 11819 11820 ret = hclge_init_umv_space(hdev); 11821 if (ret) 11822 goto err_mdiobus_unreg; 11823 11824 ret = hclge_mac_init(hdev); 11825 if (ret) { 11826 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11827 goto err_mdiobus_unreg; 11828 } 11829 11830 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11831 if (ret) { 11832 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11833 goto err_mdiobus_unreg; 11834 } 11835 11836 ret = hclge_config_gro(hdev); 11837 if (ret) 11838 goto err_mdiobus_unreg; 11839 11840 ret = hclge_init_vlan_config(hdev); 11841 if (ret) { 11842 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11843 goto err_mdiobus_unreg; 11844 } 11845 11846 ret = hclge_tm_schd_init(hdev); 11847 if (ret) { 11848 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11849 goto err_mdiobus_unreg; 11850 } 11851 11852 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11853 &hdev->rss_cfg); 11854 if (ret) { 11855 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11856 goto err_mdiobus_unreg; 11857 } 11858 11859 ret = hclge_rss_init_hw(hdev); 11860 if (ret) { 11861 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11862 goto err_mdiobus_unreg; 11863 } 11864 11865 ret = init_mgr_tbl(hdev); 11866 if (ret) { 11867 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11868 goto err_mdiobus_unreg; 11869 } 11870 11871 ret = hclge_init_fd_config(hdev); 11872 if (ret) { 11873 dev_err(&pdev->dev, 11874 "fd table init fail, ret=%d\n", ret); 11875 goto err_mdiobus_unreg; 11876 } 11877 11878 ret = hclge_ptp_init(hdev); 11879 if (ret) 11880 goto err_mdiobus_unreg; 11881 11882 ret = hclge_update_port_info(hdev); 11883 if (ret) 11884 goto err_ptp_uninit; 11885 11886 INIT_KFIFO(hdev->mac_tnl_log); 11887 11888 hclge_dcb_ops_set(hdev); 11889 11890 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11891 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11892 11893 hclge_clear_all_event_cause(hdev); 11894 hclge_clear_resetting_state(hdev); 11895 11896 /* Log and clear the hw errors those already occurred */ 11897 if (hnae3_dev_ras_imp_supported(hdev)) 11898 hclge_handle_occurred_error(hdev); 11899 else 11900 hclge_handle_all_hns_hw_errors(ae_dev); 11901 11902 /* request delayed reset for the error recovery because an immediate 11903 * global reset on a PF affecting pending initialization of other PFs 11904 */ 11905 if (ae_dev->hw_err_reset_req) { 11906 enum hnae3_reset_type reset_level; 11907 11908 reset_level = hclge_get_reset_level(ae_dev, 11909 &ae_dev->hw_err_reset_req); 11910 hclge_set_def_reset_request(ae_dev, reset_level); 11911 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11912 } 11913 11914 hclge_init_rxd_adv_layout(hdev); 11915 11916 ret = hclge_init_wol(hdev); 11917 if (ret) 11918 dev_warn(&pdev->dev, 11919 "failed to wake on lan init, ret = %d\n", ret); 11920 11921 ret = hclge_devlink_init(hdev); 11922 if (ret) 11923 goto err_ptp_uninit; 11924 11925 hclge_state_init(hdev); 11926 hdev->last_reset_time = jiffies; 11927 11928 /* Enable MISC vector(vector0) */ 11929 enable_irq(hdev->misc_vector.vector_irq); 11930 hclge_enable_vector(&hdev->misc_vector, true); 11931 11932 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11933 HCLGE_DRIVER_NAME); 11934 11935 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11936 return 0; 11937 11938 err_ptp_uninit: 11939 hclge_ptp_uninit(hdev); 11940 err_mdiobus_unreg: 11941 if (hdev->hw.mac.phydev) 11942 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11943 err_msi_irq_uninit: 11944 hclge_misc_irq_uninit(hdev); 11945 err_msi_uninit: 11946 pci_free_irq_vectors(pdev); 11947 err_cmd_uninit: 11948 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11949 err_pci_uninit: 11950 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11951 pci_release_regions(pdev); 11952 pci_disable_device(pdev); 11953 out: 11954 mutex_destroy(&hdev->vport_lock); 11955 return ret; 11956 } 11957 11958 static void hclge_stats_clear(struct hclge_dev *hdev) 11959 { 11960 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11961 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11962 } 11963 11964 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11965 { 11966 return hclge_config_switch_param(hdev, vf, enable, 11967 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11968 } 11969 11970 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11971 { 11972 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11973 HCLGE_FILTER_FE_NIC_INGRESS_B, 11974 enable, vf); 11975 } 11976 11977 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11978 { 11979 int ret; 11980 11981 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11982 if (ret) { 11983 dev_err(&hdev->pdev->dev, 11984 "Set vf %d mac spoof check %s failed, ret=%d\n", 11985 vf, str_on_off(enable), ret); 11986 return ret; 11987 } 11988 11989 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11990 if (ret) 11991 dev_err(&hdev->pdev->dev, 11992 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11993 vf, str_on_off(enable), ret); 11994 11995 return ret; 11996 } 11997 11998 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11999 bool enable) 12000 { 12001 struct hclge_vport *vport = hclge_get_vport(handle); 12002 struct hclge_dev *hdev = vport->back; 12003 u32 new_spoofchk = enable ? 1 : 0; 12004 int ret; 12005 12006 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 12007 return -EOPNOTSUPP; 12008 12009 vport = hclge_get_vf_vport(hdev, vf); 12010 if (!vport) 12011 return -EINVAL; 12012 12013 if (vport->vf_info.spoofchk == new_spoofchk) 12014 return 0; 12015 12016 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 12017 dev_warn(&hdev->pdev->dev, 12018 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 12019 vf); 12020 else if (enable && hclge_is_umv_space_full(vport, true)) 12021 dev_warn(&hdev->pdev->dev, 12022 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 12023 vf); 12024 12025 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 12026 if (ret) 12027 return ret; 12028 12029 vport->vf_info.spoofchk = new_spoofchk; 12030 return 0; 12031 } 12032 12033 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 12034 { 12035 struct hclge_vport *vport = hdev->vport; 12036 int ret; 12037 int i; 12038 12039 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 12040 return 0; 12041 12042 /* resume the vf spoof check state after reset */ 12043 for (i = 0; i < hdev->num_alloc_vport; i++) { 12044 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 12045 vport->vf_info.spoofchk); 12046 if (ret) 12047 return ret; 12048 12049 vport++; 12050 } 12051 12052 return 0; 12053 } 12054 12055 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 12056 { 12057 struct hclge_vport *vport = hclge_get_vport(handle); 12058 struct hclge_dev *hdev = vport->back; 12059 u32 new_trusted = enable ? 1 : 0; 12060 12061 vport = hclge_get_vf_vport(hdev, vf); 12062 if (!vport) 12063 return -EINVAL; 12064 12065 if (vport->vf_info.trusted == new_trusted) 12066 return 0; 12067 12068 vport->vf_info.trusted = new_trusted; 12069 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12070 hclge_task_schedule(hdev, 0); 12071 12072 return 0; 12073 } 12074 12075 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 12076 { 12077 int ret; 12078 int vf; 12079 12080 /* reset vf rate to default value */ 12081 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 12082 struct hclge_vport *vport = &hdev->vport[vf]; 12083 12084 vport->vf_info.max_tx_rate = 0; 12085 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 12086 if (ret) 12087 dev_err(&hdev->pdev->dev, 12088 "vf%d failed to reset to default, ret=%d\n", 12089 vf - HCLGE_VF_VPORT_START_NUM, ret); 12090 } 12091 } 12092 12093 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 12094 int min_tx_rate, int max_tx_rate) 12095 { 12096 if (min_tx_rate != 0 || 12097 max_tx_rate < 0 || (u32)max_tx_rate > hdev->hw.mac.max_speed) { 12098 dev_err(&hdev->pdev->dev, 12099 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 12100 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 12101 return -EINVAL; 12102 } 12103 12104 return 0; 12105 } 12106 12107 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 12108 int min_tx_rate, int max_tx_rate, bool force) 12109 { 12110 struct hclge_vport *vport = hclge_get_vport(handle); 12111 struct hclge_dev *hdev = vport->back; 12112 int ret; 12113 12114 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 12115 if (ret) 12116 return ret; 12117 12118 vport = hclge_get_vf_vport(hdev, vf); 12119 if (!vport) 12120 return -EINVAL; 12121 12122 if (!force && (u32)max_tx_rate == vport->vf_info.max_tx_rate) 12123 return 0; 12124 12125 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 12126 if (ret) 12127 return ret; 12128 12129 vport->vf_info.max_tx_rate = max_tx_rate; 12130 12131 return 0; 12132 } 12133 12134 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 12135 { 12136 struct hnae3_handle *handle = &hdev->vport->nic; 12137 struct hclge_vport *vport; 12138 int ret; 12139 int vf; 12140 12141 /* resume the vf max_tx_rate after reset */ 12142 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12143 vport = hclge_get_vf_vport(hdev, vf); 12144 if (!vport) 12145 return -EINVAL; 12146 12147 /* zero means max rate, after reset, firmware already set it to 12148 * max rate, so just continue. 12149 */ 12150 if (!vport->vf_info.max_tx_rate) 12151 continue; 12152 12153 ret = hclge_set_vf_rate(handle, vf, 0, 12154 vport->vf_info.max_tx_rate, true); 12155 if (ret) { 12156 dev_err(&hdev->pdev->dev, 12157 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12158 vf, vport->vf_info.max_tx_rate, ret); 12159 return ret; 12160 } 12161 } 12162 12163 return 0; 12164 } 12165 12166 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12167 { 12168 struct hclge_vport *vport = hdev->vport; 12169 int i; 12170 12171 for (i = 0; i < hdev->num_alloc_vport; i++) { 12172 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12173 vport++; 12174 } 12175 } 12176 12177 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12178 { 12179 struct hclge_dev *hdev = ae_dev->priv; 12180 struct pci_dev *pdev = ae_dev->pdev; 12181 int ret; 12182 12183 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12184 12185 hclge_stats_clear(hdev); 12186 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12187 * so here should not clean table in memory. 12188 */ 12189 if (hdev->reset_type == HNAE3_IMP_RESET || 12190 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12191 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12192 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12193 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12194 hclge_reset_umv_space(hdev); 12195 } 12196 12197 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12198 true, hdev->reset_pending); 12199 if (ret) { 12200 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12201 return ret; 12202 } 12203 12204 ret = hclge_map_tqp(hdev); 12205 if (ret) { 12206 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12207 return ret; 12208 } 12209 12210 ret = hclge_mac_init(hdev); 12211 if (ret) { 12212 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12213 return ret; 12214 } 12215 12216 ret = hclge_tp_port_init(hdev); 12217 if (ret) { 12218 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12219 ret); 12220 return ret; 12221 } 12222 12223 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12224 if (ret) { 12225 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12226 return ret; 12227 } 12228 12229 ret = hclge_config_gro(hdev); 12230 if (ret) 12231 return ret; 12232 12233 ret = hclge_init_vlan_config(hdev); 12234 if (ret) { 12235 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12236 return ret; 12237 } 12238 12239 hclge_reset_tc_config(hdev); 12240 12241 ret = hclge_tm_init_hw(hdev, true); 12242 if (ret) { 12243 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12244 return ret; 12245 } 12246 12247 ret = hclge_rss_init_hw(hdev); 12248 if (ret) { 12249 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12250 return ret; 12251 } 12252 12253 ret = init_mgr_tbl(hdev); 12254 if (ret) { 12255 dev_err(&pdev->dev, 12256 "failed to reinit manager table, ret = %d\n", ret); 12257 return ret; 12258 } 12259 12260 ret = hclge_init_fd_config(hdev); 12261 if (ret) { 12262 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12263 return ret; 12264 } 12265 12266 ret = hclge_ptp_init(hdev); 12267 if (ret) 12268 return ret; 12269 12270 /* Log and clear the hw errors those already occurred */ 12271 if (hnae3_dev_ras_imp_supported(hdev)) 12272 hclge_handle_occurred_error(hdev); 12273 else 12274 hclge_handle_all_hns_hw_errors(ae_dev); 12275 12276 /* Re-enable the hw error interrupts because 12277 * the interrupts get disabled on global reset. 12278 */ 12279 ret = hclge_config_nic_hw_error(hdev, true); 12280 if (ret) { 12281 dev_err(&pdev->dev, 12282 "fail(%d) to re-enable NIC hw error interrupts\n", 12283 ret); 12284 return ret; 12285 } 12286 12287 if (hdev->roce_client) { 12288 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12289 if (ret) { 12290 dev_err(&pdev->dev, 12291 "fail(%d) to re-enable roce ras interrupts\n", 12292 ret); 12293 return ret; 12294 } 12295 } 12296 12297 hclge_reset_vport_state(hdev); 12298 ret = hclge_reset_vport_spoofchk(hdev); 12299 if (ret) 12300 return ret; 12301 12302 ret = hclge_resume_vf_rate(hdev); 12303 if (ret) 12304 return ret; 12305 12306 hclge_init_rxd_adv_layout(hdev); 12307 12308 ret = hclge_update_wol(hdev); 12309 if (ret) 12310 dev_warn(&pdev->dev, 12311 "failed to update wol config, ret = %d\n", ret); 12312 12313 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12314 HCLGE_DRIVER_NAME); 12315 12316 return 0; 12317 } 12318 12319 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12320 { 12321 struct hclge_dev *hdev = ae_dev->priv; 12322 struct hclge_mac *mac = &hdev->hw.mac; 12323 12324 hclge_reset_vf_rate(hdev); 12325 hclge_clear_vf_vlan(hdev); 12326 hclge_state_uninit(hdev); 12327 hclge_ptp_uninit(hdev); 12328 hclge_uninit_rxd_adv_layout(hdev); 12329 hclge_uninit_mac_table(hdev); 12330 hclge_del_all_fd_entries(hdev); 12331 12332 if (mac->phydev) 12333 mdiobus_unregister(mac->mdio_bus); 12334 12335 /* Disable MISC vector(vector0) */ 12336 hclge_enable_vector(&hdev->misc_vector, false); 12337 disable_irq(hdev->misc_vector.vector_irq); 12338 12339 /* Disable all hw interrupts */ 12340 hclge_config_mac_tnl_int(hdev, false); 12341 hclge_config_nic_hw_error(hdev, false); 12342 hclge_config_rocee_ras_interrupt(hdev, false); 12343 12344 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12345 hclge_misc_irq_uninit(hdev); 12346 hclge_devlink_uninit(hdev); 12347 hclge_pci_uninit(hdev); 12348 hclge_uninit_vport_vlan_table(hdev); 12349 mutex_destroy(&hdev->vport_lock); 12350 ae_dev->priv = NULL; 12351 } 12352 12353 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12354 { 12355 struct hclge_vport *vport = hclge_get_vport(handle); 12356 struct hclge_dev *hdev = vport->back; 12357 12358 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12359 } 12360 12361 static void hclge_get_channels(struct hnae3_handle *handle, 12362 struct ethtool_channels *ch) 12363 { 12364 ch->max_combined = hclge_get_max_channels(handle); 12365 ch->other_count = 1; 12366 ch->max_other = 1; 12367 ch->combined_count = handle->kinfo.rss_size; 12368 } 12369 12370 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12371 u16 *alloc_tqps, u16 *max_rss_size) 12372 { 12373 struct hclge_vport *vport = hclge_get_vport(handle); 12374 struct hclge_dev *hdev = vport->back; 12375 12376 *alloc_tqps = vport->alloc_tqps; 12377 *max_rss_size = hdev->pf_rss_size_max; 12378 } 12379 12380 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12381 { 12382 struct hclge_vport *vport = hclge_get_vport(handle); 12383 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12384 struct hclge_dev *hdev = vport->back; 12385 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12386 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12387 u16 roundup_size; 12388 unsigned int i; 12389 12390 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12391 roundup_size = ilog2(roundup_size); 12392 /* Set the RSS TC mode according to the new RSS size */ 12393 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12394 tc_valid[i] = 0; 12395 12396 if (!(hdev->hw_tc_map & BIT(i))) 12397 continue; 12398 12399 tc_valid[i] = 1; 12400 tc_size[i] = roundup_size; 12401 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12402 } 12403 12404 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12405 tc_size); 12406 } 12407 12408 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12409 bool rxfh_configured) 12410 { 12411 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12412 struct hclge_vport *vport = hclge_get_vport(handle); 12413 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12414 struct hclge_dev *hdev = vport->back; 12415 u16 cur_rss_size = kinfo->rss_size; 12416 u16 cur_tqps = kinfo->num_tqps; 12417 u32 *rss_indir; 12418 unsigned int i; 12419 int ret; 12420 12421 kinfo->req_rss_size = new_tqps_num; 12422 12423 ret = hclge_tm_vport_map_update(hdev); 12424 if (ret) { 12425 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12426 return ret; 12427 } 12428 12429 ret = hclge_set_rss_tc_mode_cfg(handle); 12430 if (ret) 12431 return ret; 12432 12433 /* RSS indirection table has been configured by user */ 12434 if (rxfh_configured) 12435 goto out; 12436 12437 /* Reinitializes the rss indirect table according to the new RSS size */ 12438 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12439 GFP_KERNEL); 12440 if (!rss_indir) 12441 return -ENOMEM; 12442 12443 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12444 rss_indir[i] = i % kinfo->rss_size; 12445 12446 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12447 if (ret) 12448 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12449 ret); 12450 12451 kfree(rss_indir); 12452 12453 out: 12454 if (!ret) 12455 dev_info(&hdev->pdev->dev, 12456 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12457 cur_rss_size, kinfo->rss_size, 12458 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12459 12460 return ret; 12461 } 12462 12463 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12464 { 12465 struct hclge_set_led_state_cmd *req; 12466 struct hclge_desc desc; 12467 int ret; 12468 12469 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12470 12471 req = (struct hclge_set_led_state_cmd *)desc.data; 12472 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12473 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12474 12475 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12476 if (ret) 12477 dev_err(&hdev->pdev->dev, 12478 "Send set led state cmd error, ret =%d\n", ret); 12479 12480 return ret; 12481 } 12482 12483 enum hclge_led_status { 12484 HCLGE_LED_OFF, 12485 HCLGE_LED_ON, 12486 HCLGE_LED_NO_CHANGE = 0xFF, 12487 }; 12488 12489 static int hclge_set_led_id(struct hnae3_handle *handle, 12490 enum ethtool_phys_id_state status) 12491 { 12492 struct hclge_vport *vport = hclge_get_vport(handle); 12493 struct hclge_dev *hdev = vport->back; 12494 12495 switch (status) { 12496 case ETHTOOL_ID_ACTIVE: 12497 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12498 case ETHTOOL_ID_INACTIVE: 12499 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12500 default: 12501 return -EINVAL; 12502 } 12503 } 12504 12505 static void hclge_get_link_mode(struct hnae3_handle *handle, 12506 unsigned long *supported, 12507 unsigned long *advertising) 12508 { 12509 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12510 struct hclge_vport *vport = hclge_get_vport(handle); 12511 struct hclge_dev *hdev = vport->back; 12512 unsigned int idx = 0; 12513 12514 for (; idx < size; idx++) { 12515 supported[idx] = hdev->hw.mac.supported[idx]; 12516 advertising[idx] = hdev->hw.mac.advertising[idx]; 12517 } 12518 } 12519 12520 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12521 { 12522 struct hclge_vport *vport = hclge_get_vport(handle); 12523 struct hclge_dev *hdev = vport->back; 12524 bool gro_en_old = hdev->gro_en; 12525 int ret; 12526 12527 hdev->gro_en = enable; 12528 ret = hclge_config_gro(hdev); 12529 if (ret) 12530 hdev->gro_en = gro_en_old; 12531 12532 return ret; 12533 } 12534 12535 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12536 { 12537 struct hnae3_handle *handle = &vport->nic; 12538 struct hclge_dev *hdev = vport->back; 12539 bool uc_en = false; 12540 bool mc_en = false; 12541 u8 tmp_flags; 12542 bool bc_en; 12543 int ret; 12544 12545 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12546 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12547 vport->last_promisc_flags = vport->overflow_promisc_flags; 12548 } 12549 12550 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12551 &vport->state)) 12552 return 0; 12553 12554 /* for PF */ 12555 if (!vport->vport_id) { 12556 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12557 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12558 tmp_flags & HNAE3_MPE); 12559 if (!ret) 12560 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12561 &vport->state); 12562 else 12563 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12564 &vport->state); 12565 return ret; 12566 } 12567 12568 /* for VF */ 12569 if (vport->vf_info.trusted) { 12570 uc_en = vport->vf_info.request_uc_en > 0 || 12571 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12572 mc_en = vport->vf_info.request_mc_en > 0 || 12573 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12574 } 12575 bc_en = vport->vf_info.request_bc_en > 0; 12576 12577 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12578 mc_en, bc_en); 12579 if (ret) { 12580 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12581 return ret; 12582 } 12583 hclge_set_vport_vlan_fltr_change(vport); 12584 12585 return 0; 12586 } 12587 12588 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12589 { 12590 struct hclge_vport *vport; 12591 int ret; 12592 u16 i; 12593 12594 for (i = 0; i < hdev->num_alloc_vport; i++) { 12595 vport = &hdev->vport[i]; 12596 12597 ret = hclge_sync_vport_promisc_mode(vport); 12598 if (ret) 12599 return; 12600 } 12601 } 12602 12603 static bool hclge_module_existed(struct hclge_dev *hdev) 12604 { 12605 struct hclge_desc desc; 12606 u32 existed; 12607 int ret; 12608 12609 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12610 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12611 if (ret) { 12612 dev_err(&hdev->pdev->dev, 12613 "failed to get SFP exist state, ret = %d\n", ret); 12614 return false; 12615 } 12616 12617 existed = le32_to_cpu(desc.data[0]); 12618 12619 return existed != 0; 12620 } 12621 12622 /* need 6 bds(total 140 bytes) in one reading 12623 * return the number of bytes actually read, 0 means read failed. 12624 */ 12625 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12626 u32 len, u8 *data) 12627 { 12628 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12629 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12630 u16 read_len; 12631 u16 copy_len; 12632 int ret; 12633 int i; 12634 12635 /* setup all 6 bds to read module eeprom info. */ 12636 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12637 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12638 true); 12639 12640 /* bd0~bd4 need next flag */ 12641 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12642 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12643 } 12644 12645 /* setup bd0, this bd contains offset and read length. */ 12646 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12647 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12648 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12649 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12650 12651 ret = hclge_cmd_send(&hdev->hw, desc, i); 12652 if (ret) { 12653 dev_err(&hdev->pdev->dev, 12654 "failed to get SFP eeprom info, ret = %d\n", ret); 12655 return 0; 12656 } 12657 12658 /* copy sfp info from bd0 to out buffer. */ 12659 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12660 memcpy(data, sfp_info_bd0->data, copy_len); 12661 read_len = copy_len; 12662 12663 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12664 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12665 if (read_len >= len) 12666 return read_len; 12667 12668 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12669 memcpy(data + read_len, desc[i].data, copy_len); 12670 read_len += copy_len; 12671 } 12672 12673 return read_len; 12674 } 12675 12676 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12677 u32 len, u8 *data) 12678 { 12679 struct hclge_vport *vport = hclge_get_vport(handle); 12680 struct hclge_dev *hdev = vport->back; 12681 u32 read_len = 0; 12682 u16 data_len; 12683 12684 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12685 return -EOPNOTSUPP; 12686 12687 if (!hclge_module_existed(hdev)) 12688 return -ENXIO; 12689 12690 while (read_len < len) { 12691 data_len = hclge_get_sfp_eeprom_info(hdev, 12692 offset + read_len, 12693 len - read_len, 12694 data + read_len); 12695 if (!data_len) 12696 return -EIO; 12697 12698 read_len += data_len; 12699 } 12700 12701 return 0; 12702 } 12703 12704 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12705 u32 *status_code) 12706 { 12707 struct hclge_vport *vport = hclge_get_vport(handle); 12708 struct hclge_dev *hdev = vport->back; 12709 struct hclge_desc desc; 12710 int ret; 12711 12712 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12713 return -EOPNOTSUPP; 12714 12715 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12716 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12717 if (ret) { 12718 dev_err(&hdev->pdev->dev, 12719 "failed to query link diagnosis info, ret = %d\n", ret); 12720 return ret; 12721 } 12722 12723 *status_code = le32_to_cpu(desc.data[0]); 12724 return 0; 12725 } 12726 12727 /* After disable sriov, VF still has some config and info need clean, 12728 * which configed by PF. 12729 */ 12730 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12731 { 12732 struct hclge_dev *hdev = vport->back; 12733 struct hclge_vlan_info vlan_info; 12734 int ret; 12735 12736 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12737 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12738 vport->need_notify = 0; 12739 vport->mps = 0; 12740 12741 /* after disable sriov, clean VF rate configured by PF */ 12742 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12743 if (ret) 12744 dev_err(&hdev->pdev->dev, 12745 "failed to clean vf%d rate config, ret = %d\n", 12746 vfid, ret); 12747 12748 vlan_info.vlan_tag = 0; 12749 vlan_info.qos = 0; 12750 vlan_info.vlan_proto = ETH_P_8021Q; 12751 ret = hclge_update_port_base_vlan_cfg(vport, 12752 HNAE3_PORT_BASE_VLAN_DISABLE, 12753 &vlan_info); 12754 if (ret) 12755 dev_err(&hdev->pdev->dev, 12756 "failed to clean vf%d port base vlan, ret = %d\n", 12757 vfid, ret); 12758 12759 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12760 if (ret) 12761 dev_err(&hdev->pdev->dev, 12762 "failed to clean vf%d spoof config, ret = %d\n", 12763 vfid, ret); 12764 12765 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12766 } 12767 12768 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12769 { 12770 struct hclge_dev *hdev = ae_dev->priv; 12771 struct hclge_vport *vport; 12772 int i; 12773 12774 for (i = 0; i < num_vfs; i++) { 12775 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12776 12777 hclge_clear_vport_vf_info(vport, i); 12778 } 12779 } 12780 12781 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12782 u8 *priority) 12783 { 12784 struct hclge_vport *vport = hclge_get_vport(h); 12785 12786 if (dscp >= HNAE3_MAX_DSCP) 12787 return -EINVAL; 12788 12789 if (tc_mode) 12790 *tc_mode = vport->nic.kinfo.tc_map_mode; 12791 if (priority) 12792 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12793 vport->nic.kinfo.dscp_prio[dscp]; 12794 12795 return 0; 12796 } 12797 12798 static const struct hnae3_ae_ops hclge_ops = { 12799 .init_ae_dev = hclge_init_ae_dev, 12800 .uninit_ae_dev = hclge_uninit_ae_dev, 12801 .reset_prepare = hclge_reset_prepare_general, 12802 .reset_done = hclge_reset_done, 12803 .init_client_instance = hclge_init_client_instance, 12804 .uninit_client_instance = hclge_uninit_client_instance, 12805 .map_ring_to_vector = hclge_map_ring_to_vector, 12806 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12807 .get_vector = hclge_get_vector, 12808 .put_vector = hclge_put_vector, 12809 .set_promisc_mode = hclge_set_promisc_mode, 12810 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12811 .set_loopback = hclge_set_loopback, 12812 .start = hclge_ae_start, 12813 .stop = hclge_ae_stop, 12814 .client_start = hclge_client_start, 12815 .client_stop = hclge_client_stop, 12816 .get_status = hclge_get_status, 12817 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12818 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12819 .get_media_type = hclge_get_media_type, 12820 .check_port_speed = hclge_check_port_speed, 12821 .get_fec_stats = hclge_get_fec_stats, 12822 .get_fec = hclge_get_fec, 12823 .set_fec = hclge_set_fec, 12824 .get_rss_key_size = hclge_comm_get_rss_key_size, 12825 .get_rss = hclge_get_rss, 12826 .set_rss = hclge_set_rss, 12827 .set_rss_tuple = hclge_set_rss_tuple, 12828 .get_rss_tuple = hclge_get_rss_tuple, 12829 .get_tc_size = hclge_get_tc_size, 12830 .get_mac_addr = hclge_get_mac_addr, 12831 .set_mac_addr = hclge_set_mac_addr, 12832 .do_ioctl = hclge_do_ioctl, 12833 .add_uc_addr = hclge_add_uc_addr, 12834 .rm_uc_addr = hclge_rm_uc_addr, 12835 .add_mc_addr = hclge_add_mc_addr, 12836 .rm_mc_addr = hclge_rm_mc_addr, 12837 .set_autoneg = hclge_set_autoneg, 12838 .get_autoneg = hclge_get_autoneg, 12839 .restart_autoneg = hclge_restart_autoneg, 12840 .halt_autoneg = hclge_halt_autoneg, 12841 .get_pauseparam = hclge_get_pauseparam, 12842 .set_pauseparam = hclge_set_pauseparam, 12843 .set_mtu = hclge_set_mtu, 12844 .reset_queue = hclge_reset_tqp, 12845 .get_stats = hclge_get_stats, 12846 .get_mac_stats = hclge_get_mac_stat, 12847 .update_stats = hclge_update_stats, 12848 .get_strings = hclge_get_strings, 12849 .get_sset_count = hclge_get_sset_count, 12850 .get_fw_version = hclge_get_fw_version, 12851 .get_mdix_mode = hclge_get_mdix_mode, 12852 .enable_vlan_filter = hclge_enable_vlan_filter, 12853 .set_vlan_filter = hclge_set_vlan_filter, 12854 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12855 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12856 .reset_event = hclge_reset_event, 12857 .get_reset_level = hclge_get_reset_level, 12858 .set_default_reset_request = hclge_set_def_reset_request, 12859 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12860 .set_channels = hclge_set_channels, 12861 .get_channels = hclge_get_channels, 12862 .get_regs_len = hclge_get_regs_len, 12863 .get_regs = hclge_get_regs, 12864 .set_led_id = hclge_set_led_id, 12865 .get_link_mode = hclge_get_link_mode, 12866 .add_fd_entry = hclge_add_fd_entry, 12867 .del_fd_entry = hclge_del_fd_entry, 12868 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12869 .get_fd_rule_info = hclge_get_fd_rule_info, 12870 .get_fd_all_rules = hclge_get_all_rules, 12871 .enable_fd = hclge_enable_fd, 12872 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12873 .dbg_get_read_func = hclge_dbg_get_read_func, 12874 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12875 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12876 .ae_dev_resetting = hclge_ae_dev_resetting, 12877 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12878 .set_gro_en = hclge_gro_en, 12879 .get_global_queue_id = hclge_covert_handle_qid_global, 12880 .set_timer_task = hclge_set_timer_task, 12881 .mac_connect_phy = hclge_mac_connect_phy, 12882 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12883 .get_vf_config = hclge_get_vf_config, 12884 .set_vf_link_state = hclge_set_vf_link_state, 12885 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12886 .set_vf_trust = hclge_set_vf_trust, 12887 .set_vf_rate = hclge_set_vf_rate, 12888 .set_vf_mac = hclge_set_vf_mac, 12889 .get_module_eeprom = hclge_get_module_eeprom, 12890 .get_cmdq_stat = hclge_get_cmdq_stat, 12891 .add_cls_flower = hclge_add_cls_flower, 12892 .del_cls_flower = hclge_del_cls_flower, 12893 .cls_flower_active = hclge_is_cls_flower_active, 12894 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12895 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12896 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12897 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12898 .get_ts_info = hclge_ptp_get_ts_info, 12899 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12900 .clean_vf_config = hclge_clean_vport_config, 12901 .get_dscp_prio = hclge_get_dscp_prio, 12902 .get_wol = hclge_get_wol, 12903 .set_wol = hclge_set_wol, 12904 }; 12905 12906 static struct hnae3_ae_algo ae_algo = { 12907 .ops = &hclge_ops, 12908 .pdev_id_table = ae_algo_pci_tbl, 12909 }; 12910 12911 static int __init hclge_init(void) 12912 { 12913 pr_debug("%s is initializing\n", HCLGE_NAME); 12914 12915 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, 12916 HCLGE_NAME); 12917 if (!hclge_wq) { 12918 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12919 return -ENOMEM; 12920 } 12921 12922 hnae3_register_ae_algo(&ae_algo); 12923 12924 return 0; 12925 } 12926 12927 static void __exit hclge_exit(void) 12928 { 12929 hnae3_acquire_unload_lock(); 12930 hnae3_unregister_ae_algo_prepare(&ae_algo); 12931 hnae3_unregister_ae_algo(&ae_algo); 12932 destroy_workqueue(hclge_wq); 12933 hnae3_release_unload_lock(); 12934 } 12935 module_init(hclge_init); 12936 module_exit(hclge_exit); 12937 12938 MODULE_LICENSE("GPL"); 12939 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12940 MODULE_DESCRIPTION("HCLGE Driver"); 12941 MODULE_VERSION(HCLGE_MOD_VERSION); 12942