1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 17 #include <net/rtnetlink.h> 18 19 #include "hclge_cmd.h" 20 #include "hclge_dcb.h" 21 #include "hclge_main.h" 22 #include "hclge_mbx.h" 23 #include "hclge_mdio.h" 24 #include "hclge_regs.h" 25 #include "hclge_tm.h" 26 #include "hclge_err.h" 27 #include "hnae3.h" 28 #include "hclge_devlink.h" 29 #include "hclge_comm_cmd.h" 30 31 #include "hclge_trace.h" 32 33 #define HCLGE_NAME "hclge" 34 35 #define HCLGE_BUF_SIZE_UNIT 256U 36 #define HCLGE_BUF_MUL_BY 2 37 #define HCLGE_BUF_DIV_BY 2 38 #define NEED_RESERVE_TC_NUM 2 39 #define BUF_MAX_PERCENT 100 40 #define BUF_RESERVE_PERCENT 90 41 42 #define HCLGE_RESET_MAX_FAIL_CNT 5 43 #define HCLGE_RESET_SYNC_TIME 100 44 #define HCLGE_PF_RESET_SYNC_TIME 20 45 #define HCLGE_PF_RESET_SYNC_CNT 1500 46 47 #define HCLGE_LINK_STATUS_MS 10 48 49 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 50 static int hclge_init_vlan_config(struct hclge_dev *hdev); 51 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 52 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 53 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 54 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 55 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 56 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 57 unsigned long *addr); 58 static int hclge_set_default_loopback(struct hclge_dev *hdev); 59 60 static void hclge_sync_mac_table(struct hclge_dev *hdev); 61 static void hclge_restore_hw_table(struct hclge_dev *hdev); 62 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 63 static void hclge_sync_fd_table(struct hclge_dev *hdev); 64 static void hclge_update_fec_stats(struct hclge_dev *hdev); 65 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 66 int wait_cnt); 67 static int hclge_update_port_info(struct hclge_dev *hdev); 68 69 static struct hnae3_ae_algo ae_algo; 70 71 static struct workqueue_struct *hclge_wq; 72 73 static const struct pci_device_id ae_algo_pci_tbl[] = { 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 79 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 82 /* required last entry */ 83 {0, } 84 }; 85 86 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 87 88 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 89 "External Loopback test", 90 "App Loopback test", 91 "Serdes serial Loopback test", 92 "Serdes parallel Loopback test", 93 "Phy Loopback test" 94 }; 95 96 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 97 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 98 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 99 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 100 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 101 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 102 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 103 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 104 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 105 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 106 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 107 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 108 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 109 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 110 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 111 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 112 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 113 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 114 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 115 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 116 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 117 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 119 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 120 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 121 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 123 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 125 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 127 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 129 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 131 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 133 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 135 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 137 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 138 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 139 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 140 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 141 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 142 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 143 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 144 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 145 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 147 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 149 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 151 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 153 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 154 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 155 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 156 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 157 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 158 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 159 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 160 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 161 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 163 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 164 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 165 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 167 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 168 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 169 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 171 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 172 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 173 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 174 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 175 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 176 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 177 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 178 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 179 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 180 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 181 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 182 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 183 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 184 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 185 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 186 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 187 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 188 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 189 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 190 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 191 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 192 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 193 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 194 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 195 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 196 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 197 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 198 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 199 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 200 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 201 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 202 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 203 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 204 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 205 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 206 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 207 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 208 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 209 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 210 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 211 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 212 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 213 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 214 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 215 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 216 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 217 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 218 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 219 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 220 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 221 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 222 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 223 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 224 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 225 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 226 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 227 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 229 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 230 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 231 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 232 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 233 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 235 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 236 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 237 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 238 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 239 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 240 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 241 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 242 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 243 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 244 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 245 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 247 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 249 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 251 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 253 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 255 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 257 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 259 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 261 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 263 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 265 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 267 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 268 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 269 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 270 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 271 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 272 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 273 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 274 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 275 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 276 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 277 278 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 280 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 282 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 284 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 286 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 288 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 290 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 291 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 292 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 293 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 294 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 295 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 296 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 298 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 300 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 302 }; 303 304 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 305 { 306 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 307 .ethter_type = cpu_to_le16(ETH_P_LLDP), 308 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 309 .i_port_bitmap = 0x1, 310 }, 311 }; 312 313 static const struct key_info meta_data_key_info[] = { 314 { PACKET_TYPE_ID, 6 }, 315 { IP_FRAGEMENT, 1 }, 316 { ROCE_TYPE, 1 }, 317 { NEXT_KEY, 5 }, 318 { VLAN_NUMBER, 2 }, 319 { SRC_VPORT, 12 }, 320 { DST_VPORT, 12 }, 321 { TUNNEL_PACKET, 1 }, 322 }; 323 324 static const struct key_info tuple_key_info[] = { 325 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 326 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 327 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 328 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 329 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 330 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 331 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 332 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 333 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 334 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 335 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 336 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 337 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 338 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 339 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 340 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 341 { INNER_DST_MAC, 48, KEY_OPT_MAC, 342 offsetof(struct hclge_fd_rule, tuples.dst_mac), 343 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 344 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 345 offsetof(struct hclge_fd_rule, tuples.src_mac), 346 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 347 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 348 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 349 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 350 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 351 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 352 offsetof(struct hclge_fd_rule, tuples.ether_proto), 353 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 354 { INNER_L2_RSV, 16, KEY_OPT_LE16, 355 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 356 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 357 { INNER_IP_TOS, 8, KEY_OPT_U8, 358 offsetof(struct hclge_fd_rule, tuples.ip_tos), 359 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 360 { INNER_IP_PROTO, 8, KEY_OPT_U8, 361 offsetof(struct hclge_fd_rule, tuples.ip_proto), 362 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 363 { INNER_SRC_IP, 32, KEY_OPT_IP, 364 offsetof(struct hclge_fd_rule, tuples.src_ip), 365 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 366 { INNER_DST_IP, 32, KEY_OPT_IP, 367 offsetof(struct hclge_fd_rule, tuples.dst_ip), 368 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 369 { INNER_L3_RSV, 16, KEY_OPT_LE16, 370 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 371 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 372 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 373 offsetof(struct hclge_fd_rule, tuples.src_port), 374 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 375 { INNER_DST_PORT, 16, KEY_OPT_LE16, 376 offsetof(struct hclge_fd_rule, tuples.dst_port), 377 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 378 { INNER_L4_RSV, 32, KEY_OPT_LE32, 379 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 380 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 381 }; 382 383 /** 384 * hclge_cmd_send - send command to command queue 385 * @hw: pointer to the hw struct 386 * @desc: prefilled descriptor for describing the command 387 * @num : the number of descriptors to be sent 388 * 389 * This is the main send command for command queue, it 390 * sends the queue, cleans the queue, etc 391 **/ 392 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 393 { 394 return hclge_comm_cmd_send(&hw->hw, desc, num); 395 } 396 397 static void hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 398 int num, bool is_special) 399 { 400 int i; 401 402 trace_hclge_pf_cmd_send(hw, desc, 0, num); 403 404 if (!is_special) { 405 for (i = 1; i < num; i++) 406 trace_hclge_pf_cmd_send(hw, &desc[i], i, num); 407 } else { 408 for (i = 1; i < num; i++) 409 trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i], 410 i, num); 411 } 412 } 413 414 static void hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, 415 int num, bool is_special) 416 { 417 int i; 418 419 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 420 return; 421 422 trace_hclge_pf_cmd_get(hw, desc, 0, num); 423 424 if (!is_special) { 425 for (i = 1; i < num; i++) 426 trace_hclge_pf_cmd_get(hw, &desc[i], i, num); 427 } else { 428 for (i = 1; i < num; i++) 429 trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i], 430 i, num); 431 } 432 } 433 434 static const struct hclge_comm_cmq_ops hclge_cmq_ops = { 435 .trace_cmd_send = hclge_trace_cmd_send, 436 .trace_cmd_get = hclge_trace_cmd_get, 437 }; 438 439 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 440 { 441 #define HCLGE_MAC_CMD_NUM 21 442 443 u64 *data = (u64 *)(&hdev->mac_stats); 444 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 445 __le64 *desc_data; 446 u32 data_size; 447 int ret; 448 u32 i; 449 450 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 451 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 452 if (ret) { 453 dev_err(&hdev->pdev->dev, 454 "Get MAC pkt stats fail, status = %d.\n", ret); 455 456 return ret; 457 } 458 459 /* The first desc has a 64-bit header, so data size need to minus 1 */ 460 data_size = sizeof(desc) / (sizeof(u64)) - 1; 461 462 desc_data = (__le64 *)(&desc[0].data[0]); 463 for (i = 0; i < data_size; i++) { 464 /* data memory is continuous becase only the first desc has a 465 * header in this command 466 */ 467 *data += le64_to_cpu(*desc_data); 468 data++; 469 desc_data++; 470 } 471 472 return 0; 473 } 474 475 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 476 { 477 #define HCLGE_REG_NUM_PER_DESC 4 478 479 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 480 u64 *data = (u64 *)(&hdev->mac_stats); 481 struct hclge_desc *desc; 482 __le64 *desc_data; 483 u32 data_size; 484 u32 desc_num; 485 int ret; 486 u32 i; 487 488 /* The first desc has a 64-bit header, so need to consider it */ 489 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 490 491 /* This may be called inside atomic sections, 492 * so GFP_ATOMIC is more suitalbe here 493 */ 494 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 495 if (!desc) 496 return -ENOMEM; 497 498 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 499 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 500 if (ret) { 501 kfree(desc); 502 return ret; 503 } 504 505 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 506 507 desc_data = (__le64 *)(&desc[0].data[0]); 508 for (i = 0; i < data_size; i++) { 509 /* data memory is continuous becase only the first desc has a 510 * header in this command 511 */ 512 *data += le64_to_cpu(*desc_data); 513 data++; 514 desc_data++; 515 } 516 517 kfree(desc); 518 519 return 0; 520 } 521 522 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 523 { 524 struct hclge_desc desc; 525 int ret; 526 527 /* Driver needs total register number of both valid registers and 528 * reserved registers, but the old firmware only returns number 529 * of valid registers in device V2. To be compatible with these 530 * devices, driver uses a fixed value. 531 */ 532 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 533 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 534 return 0; 535 } 536 537 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 538 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 539 if (ret) { 540 dev_err(&hdev->pdev->dev, 541 "failed to query mac statistic reg number, ret = %d\n", 542 ret); 543 return ret; 544 } 545 546 *reg_num = le32_to_cpu(desc.data[0]); 547 if (*reg_num == 0) { 548 dev_err(&hdev->pdev->dev, 549 "mac statistic reg number is invalid!\n"); 550 return -ENODATA; 551 } 552 553 return 0; 554 } 555 556 int hclge_mac_update_stats(struct hclge_dev *hdev) 557 { 558 /* The firmware supports the new statistics acquisition method */ 559 if (hdev->ae_dev->dev_specs.mac_stats_num) 560 return hclge_mac_update_stats_complete(hdev); 561 else 562 return hclge_mac_update_stats_defective(hdev); 563 } 564 565 static int hclge_comm_get_count(struct hclge_dev *hdev, 566 const struct hclge_comm_stats_str strs[], 567 u32 size) 568 { 569 int count = 0; 570 u32 i; 571 572 for (i = 0; i < size; i++) 573 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 574 count++; 575 576 return count; 577 } 578 579 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 580 const struct hclge_comm_stats_str strs[], 581 int size, u64 *data) 582 { 583 u64 *buf = data; 584 u32 i; 585 586 for (i = 0; i < size; i++) { 587 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 588 continue; 589 590 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 591 buf++; 592 } 593 594 return buf; 595 } 596 597 static void hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 598 const struct hclge_comm_stats_str strs[], 599 int size, u8 **data) 600 { 601 u32 i; 602 603 if (stringset != ETH_SS_STATS) 604 return; 605 606 for (i = 0; i < size; i++) { 607 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 608 continue; 609 610 ethtool_puts(data, strs[i].desc); 611 } 612 } 613 614 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 615 { 616 struct hnae3_handle *handle; 617 int status; 618 619 handle = &hdev->vport[0].nic; 620 if (handle->client) { 621 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 622 if (status) { 623 dev_err(&hdev->pdev->dev, 624 "Update TQPS stats fail, status = %d.\n", 625 status); 626 } 627 } 628 629 hclge_update_fec_stats(hdev); 630 631 status = hclge_mac_update_stats(hdev); 632 if (status) 633 dev_err(&hdev->pdev->dev, 634 "Update MAC stats fail, status = %d.\n", status); 635 } 636 637 static void hclge_update_stats(struct hnae3_handle *handle) 638 { 639 struct hclge_vport *vport = hclge_get_vport(handle); 640 struct hclge_dev *hdev = vport->back; 641 int status; 642 643 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 644 return; 645 646 status = hclge_mac_update_stats(hdev); 647 if (status) 648 dev_err(&hdev->pdev->dev, 649 "Update MAC stats fail, status = %d.\n", 650 status); 651 652 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 653 if (status) 654 dev_err(&hdev->pdev->dev, 655 "Update TQPS stats fail, status = %d.\n", 656 status); 657 658 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 659 } 660 661 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 662 { 663 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 664 HNAE3_SUPPORT_PHY_LOOPBACK | \ 665 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 666 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 667 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 668 669 struct hclge_vport *vport = hclge_get_vport(handle); 670 struct hclge_dev *hdev = vport->back; 671 int count = 0; 672 673 /* Loopback test support rules: 674 * mac: only GE mode support 675 * serdes: all mac mode will support include GE/XGE/LGE/CGE 676 * phy: only support when phy device exist on board 677 */ 678 if (stringset == ETH_SS_TEST) { 679 /* clear loopback bit flags at first */ 680 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 681 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 682 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 683 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 684 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 685 count += 1; 686 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 687 } 688 689 if (hdev->ae_dev->dev_specs.hilink_version != 690 HCLGE_HILINK_H60) { 691 count += 1; 692 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 693 } 694 695 count += 1; 696 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 697 count += 1; 698 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 699 700 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 701 hdev->hw.mac.phydev->drv->set_loopback) || 702 hnae3_dev_phy_imp_supported(hdev)) { 703 count += 1; 704 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 705 } 706 } else if (stringset == ETH_SS_STATS) { 707 count = hclge_comm_get_count(hdev, g_mac_stats_string, 708 ARRAY_SIZE(g_mac_stats_string)) + 709 hclge_comm_tqps_get_sset_count(handle); 710 } 711 712 return count; 713 } 714 715 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 716 u8 **data) 717 { 718 struct hclge_vport *vport = hclge_get_vport(handle); 719 struct hclge_dev *hdev = vport->back; 720 const char *str; 721 int size; 722 723 if (stringset == ETH_SS_STATS) { 724 size = ARRAY_SIZE(g_mac_stats_string); 725 hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 726 size, data); 727 hclge_comm_tqps_get_strings(handle, data); 728 } else if (stringset == ETH_SS_TEST) { 729 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 730 str = hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL]; 731 ethtool_puts(data, str); 732 } 733 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 734 str = hns3_nic_test_strs[HNAE3_LOOP_APP]; 735 ethtool_puts(data, str); 736 } 737 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 738 str = hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES]; 739 ethtool_puts(data, str); 740 } 741 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 742 str = hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES]; 743 ethtool_puts(data, str); 744 } 745 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 746 str = hns3_nic_test_strs[HNAE3_LOOP_PHY]; 747 ethtool_puts(data, str); 748 } 749 } 750 } 751 752 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 753 { 754 struct hclge_vport *vport = hclge_get_vport(handle); 755 struct hclge_dev *hdev = vport->back; 756 u64 *p; 757 758 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 759 ARRAY_SIZE(g_mac_stats_string), data); 760 p = hclge_comm_tqps_get_stats(handle, p); 761 } 762 763 static void hclge_get_mac_stat(struct hnae3_handle *handle, 764 struct hns3_mac_stats *mac_stats) 765 { 766 struct hclge_vport *vport = hclge_get_vport(handle); 767 struct hclge_dev *hdev = vport->back; 768 769 hclge_update_stats(handle); 770 771 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 772 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 773 } 774 775 static int hclge_parse_func_status(struct hclge_dev *hdev, 776 struct hclge_func_status_cmd *status) 777 { 778 #define HCLGE_MAC_ID_MASK 0xF 779 780 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 781 return -EINVAL; 782 783 /* Set the pf to main pf */ 784 if (status->pf_state & HCLGE_PF_STATE_MAIN) 785 hdev->flag |= HCLGE_FLAG_MAIN; 786 else 787 hdev->flag &= ~HCLGE_FLAG_MAIN; 788 789 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 790 return 0; 791 } 792 793 static int hclge_query_function_status(struct hclge_dev *hdev) 794 { 795 #define HCLGE_QUERY_MAX_CNT 5 796 797 struct hclge_func_status_cmd *req; 798 struct hclge_desc desc; 799 int timeout = 0; 800 int ret; 801 802 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 803 req = (struct hclge_func_status_cmd *)desc.data; 804 805 do { 806 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 807 if (ret) { 808 dev_err(&hdev->pdev->dev, 809 "query function status failed %d.\n", ret); 810 return ret; 811 } 812 813 /* Check pf reset is done */ 814 if (req->pf_state) 815 break; 816 usleep_range(1000, 2000); 817 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 818 819 return hclge_parse_func_status(hdev, req); 820 } 821 822 static int hclge_query_pf_resource(struct hclge_dev *hdev) 823 { 824 struct hclge_pf_res_cmd *req; 825 struct hclge_desc desc; 826 int ret; 827 828 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 829 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 830 if (ret) { 831 dev_err(&hdev->pdev->dev, 832 "query pf resource failed %d.\n", ret); 833 return ret; 834 } 835 836 req = (struct hclge_pf_res_cmd *)desc.data; 837 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 838 le16_to_cpu(req->ext_tqp_num); 839 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 840 841 if (req->tx_buf_size) 842 hdev->tx_buf_size = 843 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 844 else 845 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 846 847 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 848 849 if (req->dv_buf_size) 850 hdev->dv_buf_size = 851 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 852 else 853 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 854 855 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 856 857 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 858 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 859 dev_err(&hdev->pdev->dev, 860 "only %u msi resources available, not enough for pf(min:2).\n", 861 hdev->num_nic_msi); 862 return -EINVAL; 863 } 864 865 if (hnae3_dev_roce_supported(hdev)) { 866 hdev->num_roce_msi = 867 le16_to_cpu(req->pf_intr_vector_number_roce); 868 869 /* PF should have NIC vectors and Roce vectors, 870 * NIC vectors are queued before Roce vectors. 871 */ 872 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 873 } else { 874 hdev->num_msi = hdev->num_nic_msi; 875 } 876 877 return 0; 878 } 879 880 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 881 { 882 switch (speed_cmd) { 883 case HCLGE_FW_MAC_SPEED_10M: 884 *speed = HCLGE_MAC_SPEED_10M; 885 break; 886 case HCLGE_FW_MAC_SPEED_100M: 887 *speed = HCLGE_MAC_SPEED_100M; 888 break; 889 case HCLGE_FW_MAC_SPEED_1G: 890 *speed = HCLGE_MAC_SPEED_1G; 891 break; 892 case HCLGE_FW_MAC_SPEED_10G: 893 *speed = HCLGE_MAC_SPEED_10G; 894 break; 895 case HCLGE_FW_MAC_SPEED_25G: 896 *speed = HCLGE_MAC_SPEED_25G; 897 break; 898 case HCLGE_FW_MAC_SPEED_40G: 899 *speed = HCLGE_MAC_SPEED_40G; 900 break; 901 case HCLGE_FW_MAC_SPEED_50G: 902 *speed = HCLGE_MAC_SPEED_50G; 903 break; 904 case HCLGE_FW_MAC_SPEED_100G: 905 *speed = HCLGE_MAC_SPEED_100G; 906 break; 907 case HCLGE_FW_MAC_SPEED_200G: 908 *speed = HCLGE_MAC_SPEED_200G; 909 break; 910 default: 911 return -EINVAL; 912 } 913 914 return 0; 915 } 916 917 static const struct hclge_speed_bit_map speed_bit_map[] = { 918 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 919 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 920 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 921 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 922 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 923 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 924 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS}, 925 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS}, 926 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS}, 927 }; 928 929 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 930 { 931 u16 i; 932 933 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 934 if (speed == speed_bit_map[i].speed) { 935 *speed_bit = speed_bit_map[i].speed_bit; 936 return 0; 937 } 938 } 939 940 return -EINVAL; 941 } 942 943 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 944 { 945 struct hclge_vport *vport = hclge_get_vport(handle); 946 struct hclge_dev *hdev = vport->back; 947 u32 speed_ability = hdev->hw.mac.speed_ability; 948 u32 speed_bit = 0; 949 int ret; 950 951 ret = hclge_get_speed_bit(speed, &speed_bit); 952 if (ret) 953 return ret; 954 955 if (speed_bit & speed_ability) 956 return 0; 957 958 return -EINVAL; 959 } 960 961 static void hclge_update_fec_support(struct hclge_mac *mac) 962 { 963 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 964 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 965 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 966 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 967 968 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 969 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 970 mac->supported); 971 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 972 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 973 mac->supported); 974 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 975 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 976 mac->supported); 977 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 978 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 979 mac->supported); 980 } 981 982 static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = { 983 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT}, 984 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT}, 985 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT}, 986 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT}, 987 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT}, 988 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT}, 989 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT}, 990 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 991 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 992 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 993 }; 994 995 static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = { 996 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT}, 997 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT}, 998 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT}, 999 {HCLGE_SUPPORT_100G_R4_BIT, 1000 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT}, 1001 {HCLGE_SUPPORT_100G_R2_BIT, 1002 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT}, 1003 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1004 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 1005 {HCLGE_SUPPORT_200G_R4_BIT, 1006 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 1007 }; 1008 1009 static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = { 1010 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT}, 1011 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT}, 1012 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT}, 1013 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT}, 1014 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT}, 1015 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT}, 1016 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT}, 1017 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1018 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 1019 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 1020 }; 1021 1022 static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = { 1023 {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, 1024 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, 1025 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT}, 1026 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT}, 1027 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT}, 1028 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT}, 1029 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT}, 1030 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT}, 1031 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 1032 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 1033 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 1034 }; 1035 1036 static void hclge_convert_setting_sr(u16 speed_ability, 1037 unsigned long *link_mode) 1038 { 1039 int i; 1040 1041 for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) { 1042 if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit) 1043 linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode, 1044 link_mode); 1045 } 1046 } 1047 1048 static void hclge_convert_setting_lr(u16 speed_ability, 1049 unsigned long *link_mode) 1050 { 1051 int i; 1052 1053 for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) { 1054 if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit) 1055 linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode, 1056 link_mode); 1057 } 1058 } 1059 1060 static void hclge_convert_setting_cr(u16 speed_ability, 1061 unsigned long *link_mode) 1062 { 1063 int i; 1064 1065 for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) { 1066 if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit) 1067 linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode, 1068 link_mode); 1069 } 1070 } 1071 1072 static void hclge_convert_setting_kr(u16 speed_ability, 1073 unsigned long *link_mode) 1074 { 1075 int i; 1076 1077 for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) { 1078 if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit) 1079 linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode, 1080 link_mode); 1081 } 1082 } 1083 1084 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1085 { 1086 /* If firmware has reported fec_ability, don't need to convert by speed */ 1087 if (mac->fec_ability) 1088 goto out; 1089 1090 switch (mac->speed) { 1091 case HCLGE_MAC_SPEED_10G: 1092 case HCLGE_MAC_SPEED_40G: 1093 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1094 BIT(HNAE3_FEC_NONE); 1095 break; 1096 case HCLGE_MAC_SPEED_25G: 1097 case HCLGE_MAC_SPEED_50G: 1098 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1099 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1100 break; 1101 case HCLGE_MAC_SPEED_100G: 1102 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1103 BIT(HNAE3_FEC_NONE); 1104 break; 1105 case HCLGE_MAC_SPEED_200G: 1106 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1107 BIT(HNAE3_FEC_LLRS); 1108 break; 1109 default: 1110 mac->fec_ability = 0; 1111 break; 1112 } 1113 1114 out: 1115 hclge_update_fec_support(mac); 1116 } 1117 1118 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1119 u16 speed_ability) 1120 { 1121 struct hclge_mac *mac = &hdev->hw.mac; 1122 1123 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1124 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1125 mac->supported); 1126 1127 hclge_convert_setting_sr(speed_ability, mac->supported); 1128 hclge_convert_setting_lr(speed_ability, mac->supported); 1129 hclge_convert_setting_cr(speed_ability, mac->supported); 1130 if (hnae3_dev_fec_supported(hdev)) 1131 hclge_convert_setting_fec(mac); 1132 1133 if (hnae3_dev_pause_supported(hdev)) 1134 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1135 1136 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1137 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1138 } 1139 1140 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1141 u16 speed_ability) 1142 { 1143 struct hclge_mac *mac = &hdev->hw.mac; 1144 1145 hclge_convert_setting_kr(speed_ability, mac->supported); 1146 if (hnae3_dev_fec_supported(hdev)) 1147 hclge_convert_setting_fec(mac); 1148 1149 if (hnae3_dev_pause_supported(hdev)) 1150 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1151 1152 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1153 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1154 } 1155 1156 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1157 u16 speed_ability) 1158 { 1159 unsigned long *supported = hdev->hw.mac.supported; 1160 1161 /* default to support all speed for GE port */ 1162 if (!speed_ability) 1163 speed_ability = HCLGE_SUPPORT_GE; 1164 1165 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1166 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1167 supported); 1168 1169 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1170 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1171 supported); 1172 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1173 supported); 1174 } 1175 1176 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1177 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1178 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1179 } 1180 1181 if (hnae3_dev_pause_supported(hdev)) { 1182 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1183 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1184 } 1185 1186 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1187 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1188 } 1189 1190 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1191 { 1192 u8 media_type = hdev->hw.mac.media_type; 1193 1194 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1195 hclge_parse_fiber_link_mode(hdev, speed_ability); 1196 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1197 hclge_parse_copper_link_mode(hdev, speed_ability); 1198 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1199 hclge_parse_backplane_link_mode(hdev, speed_ability); 1200 } 1201 1202 static u32 hclge_get_max_speed(u16 speed_ability) 1203 { 1204 if (speed_ability & HCLGE_SUPPORT_200G_BITS) 1205 return HCLGE_MAC_SPEED_200G; 1206 1207 if (speed_ability & HCLGE_SUPPORT_100G_BITS) 1208 return HCLGE_MAC_SPEED_100G; 1209 1210 if (speed_ability & HCLGE_SUPPORT_50G_BITS) 1211 return HCLGE_MAC_SPEED_50G; 1212 1213 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1214 return HCLGE_MAC_SPEED_40G; 1215 1216 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1217 return HCLGE_MAC_SPEED_25G; 1218 1219 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1220 return HCLGE_MAC_SPEED_10G; 1221 1222 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1223 return HCLGE_MAC_SPEED_1G; 1224 1225 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1226 return HCLGE_MAC_SPEED_100M; 1227 1228 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1229 return HCLGE_MAC_SPEED_10M; 1230 1231 return HCLGE_MAC_SPEED_1G; 1232 } 1233 1234 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1235 { 1236 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1237 #define SPEED_ABILITY_EXT_SHIFT 8 1238 1239 struct hclge_cfg_param_cmd *req; 1240 u64 mac_addr_tmp_high; 1241 u16 speed_ability_ext; 1242 u64 mac_addr_tmp; 1243 unsigned int i; 1244 1245 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1246 1247 /* get the configuration */ 1248 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1249 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1250 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1251 HCLGE_CFG_TQP_DESC_N_M, 1252 HCLGE_CFG_TQP_DESC_N_S); 1253 1254 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1255 HCLGE_CFG_PHY_ADDR_M, 1256 HCLGE_CFG_PHY_ADDR_S); 1257 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1258 HCLGE_CFG_MEDIA_TP_M, 1259 HCLGE_CFG_MEDIA_TP_S); 1260 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1261 HCLGE_CFG_RX_BUF_LEN_M, 1262 HCLGE_CFG_RX_BUF_LEN_S); 1263 /* get mac_address */ 1264 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1265 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1266 HCLGE_CFG_MAC_ADDR_H_M, 1267 HCLGE_CFG_MAC_ADDR_H_S); 1268 1269 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1270 1271 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1272 HCLGE_CFG_DEFAULT_SPEED_M, 1273 HCLGE_CFG_DEFAULT_SPEED_S); 1274 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1275 HCLGE_CFG_RSS_SIZE_M, 1276 HCLGE_CFG_RSS_SIZE_S); 1277 1278 for (i = 0; i < ETH_ALEN; i++) 1279 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1280 1281 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1282 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1283 1284 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1285 HCLGE_CFG_SPEED_ABILITY_M, 1286 HCLGE_CFG_SPEED_ABILITY_S); 1287 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1288 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1289 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1290 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1291 1292 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1293 HCLGE_CFG_VLAN_FLTR_CAP_M, 1294 HCLGE_CFG_VLAN_FLTR_CAP_S); 1295 1296 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1297 HCLGE_CFG_UMV_TBL_SPACE_M, 1298 HCLGE_CFG_UMV_TBL_SPACE_S); 1299 1300 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1301 HCLGE_CFG_PF_RSS_SIZE_M, 1302 HCLGE_CFG_PF_RSS_SIZE_S); 1303 1304 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1305 * power of 2, instead of reading out directly. This would 1306 * be more flexible for future changes and expansions. 1307 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1308 * it does not make sense if PF's field is 0. In this case, PF and VF 1309 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1310 */ 1311 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1312 1U << cfg->pf_rss_size_max : 1313 cfg->vf_rss_size_max; 1314 1315 /* The unit of the tx spare buffer size queried from configuration 1316 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1317 * needed here. 1318 */ 1319 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1320 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1321 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1322 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1323 } 1324 1325 /* hclge_get_cfg: query the static parameter from flash 1326 * @hdev: pointer to struct hclge_dev 1327 * @hcfg: the config structure to be getted 1328 */ 1329 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1330 { 1331 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1332 struct hclge_cfg_param_cmd *req; 1333 unsigned int i; 1334 int ret; 1335 1336 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1337 u32 offset = 0; 1338 1339 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1340 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1341 true); 1342 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1343 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1344 /* Len should be united by 4 bytes when send to hardware */ 1345 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1346 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1347 req->offset = cpu_to_le32(offset); 1348 } 1349 1350 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1351 if (ret) { 1352 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1353 return ret; 1354 } 1355 1356 hclge_parse_cfg(hcfg, desc); 1357 1358 return 0; 1359 } 1360 1361 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1362 { 1363 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1364 1365 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1366 1367 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1368 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1369 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1370 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1371 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1372 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1373 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1374 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1375 ae_dev->dev_specs.tnl_num = 0; 1376 } 1377 1378 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1379 struct hclge_desc *desc) 1380 { 1381 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1382 struct hclge_dev_specs_0_cmd *req0; 1383 struct hclge_dev_specs_1_cmd *req1; 1384 1385 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1386 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1387 1388 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1389 ae_dev->dev_specs.rss_ind_tbl_size = 1390 le16_to_cpu(req0->rss_ind_tbl_size); 1391 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1392 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1393 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1394 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1395 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1396 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1397 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1398 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1399 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1400 ae_dev->dev_specs.hilink_version = req1->hilink_version; 1401 } 1402 1403 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1404 { 1405 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1406 1407 if (!dev_specs->max_non_tso_bd_num) 1408 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1409 if (!dev_specs->rss_ind_tbl_size) 1410 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1411 if (!dev_specs->rss_key_size) 1412 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1413 if (!dev_specs->max_tm_rate) 1414 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1415 if (!dev_specs->max_qset_num) 1416 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1417 if (!dev_specs->max_int_gl) 1418 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1419 if (!dev_specs->max_frm_size) 1420 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1421 if (!dev_specs->umv_size) 1422 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1423 } 1424 1425 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1426 { 1427 u32 reg_num = 0; 1428 int ret; 1429 1430 ret = hclge_mac_query_reg_num(hdev, ®_num); 1431 if (ret && ret != -EOPNOTSUPP) 1432 return ret; 1433 1434 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1435 return 0; 1436 } 1437 1438 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1439 { 1440 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1441 int ret; 1442 int i; 1443 1444 ret = hclge_query_mac_stats_num(hdev); 1445 if (ret) 1446 return ret; 1447 1448 /* set default specifications as devices lower than version V3 do not 1449 * support querying specifications from firmware. 1450 */ 1451 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1452 hclge_set_default_dev_specs(hdev); 1453 return 0; 1454 } 1455 1456 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1457 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1458 true); 1459 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1460 } 1461 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1462 1463 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1464 if (ret) 1465 return ret; 1466 1467 hclge_parse_dev_specs(hdev, desc); 1468 hclge_check_dev_specs(hdev); 1469 1470 return 0; 1471 } 1472 1473 static int hclge_get_cap(struct hclge_dev *hdev) 1474 { 1475 int ret; 1476 1477 ret = hclge_query_function_status(hdev); 1478 if (ret) { 1479 dev_err(&hdev->pdev->dev, 1480 "query function status error %d.\n", ret); 1481 return ret; 1482 } 1483 1484 /* get pf resource */ 1485 return hclge_query_pf_resource(hdev); 1486 } 1487 1488 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1489 { 1490 #define HCLGE_MIN_TX_DESC 64 1491 #define HCLGE_MIN_RX_DESC 64 1492 1493 if (!is_kdump_kernel()) 1494 return; 1495 1496 dev_info(&hdev->pdev->dev, 1497 "Running kdump kernel. Using minimal resources\n"); 1498 1499 /* minimal queue pairs equals to the number of vports */ 1500 hdev->num_tqps = hdev->num_req_vfs + 1; 1501 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1502 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1503 } 1504 1505 static void hclge_init_tc_config(struct hclge_dev *hdev) 1506 { 1507 unsigned int i; 1508 1509 if (hdev->tc_max > HNAE3_MAX_TC || 1510 hdev->tc_max < 1) { 1511 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1512 hdev->tc_max); 1513 hdev->tc_max = 1; 1514 } 1515 1516 /* Dev does not support DCB */ 1517 if (!hnae3_dev_dcb_supported(hdev)) { 1518 hdev->tc_max = 1; 1519 hdev->pfc_max = 0; 1520 } else { 1521 hdev->pfc_max = hdev->tc_max; 1522 } 1523 1524 hdev->tm_info.num_tc = 1; 1525 1526 /* Currently not support uncontiuous tc */ 1527 for (i = 0; i < hdev->tm_info.num_tc; i++) 1528 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1529 1530 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1531 } 1532 1533 static int hclge_configure(struct hclge_dev *hdev) 1534 { 1535 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1536 struct hclge_cfg cfg; 1537 int ret; 1538 1539 ret = hclge_get_cfg(hdev, &cfg); 1540 if (ret) 1541 return ret; 1542 1543 hdev->base_tqp_pid = 0; 1544 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1545 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1546 hdev->rx_buf_len = cfg.rx_buf_len; 1547 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1548 hdev->hw.mac.media_type = cfg.media_type; 1549 hdev->hw.mac.phy_addr = cfg.phy_addr; 1550 hdev->num_tx_desc = cfg.tqp_desc_num; 1551 hdev->num_rx_desc = cfg.tqp_desc_num; 1552 hdev->tm_info.num_pg = 1; 1553 hdev->tc_max = cfg.tc_num; 1554 hdev->tm_info.hw_pfc_map = 0; 1555 if (cfg.umv_space) 1556 hdev->wanted_umv_size = cfg.umv_space; 1557 else 1558 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1559 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1560 hdev->gro_en = true; 1561 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1562 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1563 1564 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1565 hdev->fd_en = true; 1566 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1567 } 1568 1569 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1570 if (ret) { 1571 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1572 cfg.default_speed, ret); 1573 return ret; 1574 } 1575 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1576 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1577 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1578 1579 hclge_parse_link_mode(hdev, cfg.speed_ability); 1580 1581 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1582 1583 hclge_init_tc_config(hdev); 1584 hclge_init_kdump_kernel_config(hdev); 1585 1586 return ret; 1587 } 1588 1589 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1590 u16 tso_mss_max) 1591 { 1592 struct hclge_cfg_tso_status_cmd *req; 1593 struct hclge_desc desc; 1594 1595 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1596 1597 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1598 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1599 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1600 1601 return hclge_cmd_send(&hdev->hw, &desc, 1); 1602 } 1603 1604 static int hclge_config_gro(struct hclge_dev *hdev) 1605 { 1606 struct hclge_cfg_gro_status_cmd *req; 1607 struct hclge_desc desc; 1608 int ret; 1609 1610 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1611 return 0; 1612 1613 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1614 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1615 1616 req->gro_en = hdev->gro_en ? 1 : 0; 1617 1618 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1619 if (ret) 1620 dev_err(&hdev->pdev->dev, 1621 "GRO hardware config cmd failed, ret = %d\n", ret); 1622 1623 return ret; 1624 } 1625 1626 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1627 { 1628 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1629 struct hclge_comm_tqp *tqp; 1630 int i; 1631 1632 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1633 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1634 if (!hdev->htqp) 1635 return -ENOMEM; 1636 1637 tqp = hdev->htqp; 1638 1639 for (i = 0; i < hdev->num_tqps; i++) { 1640 tqp->dev = &hdev->pdev->dev; 1641 tqp->index = i; 1642 1643 tqp->q.ae_algo = &ae_algo; 1644 tqp->q.buf_size = hdev->rx_buf_len; 1645 tqp->q.tx_desc_num = hdev->num_tx_desc; 1646 tqp->q.rx_desc_num = hdev->num_rx_desc; 1647 1648 /* need an extended offset to configure queues >= 1649 * HCLGE_TQP_MAX_SIZE_DEV_V2 1650 */ 1651 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1652 tqp->q.io_base = hdev->hw.hw.io_base + 1653 HCLGE_TQP_REG_OFFSET + 1654 i * HCLGE_TQP_REG_SIZE; 1655 else 1656 tqp->q.io_base = hdev->hw.hw.io_base + 1657 HCLGE_TQP_REG_OFFSET + 1658 HCLGE_TQP_EXT_REG_OFFSET + 1659 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1660 HCLGE_TQP_REG_SIZE; 1661 1662 /* when device supports tx push and has device memory, 1663 * the queue can execute push mode or doorbell mode on 1664 * device memory. 1665 */ 1666 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1667 tqp->q.mem_base = hdev->hw.hw.mem_base + 1668 HCLGE_TQP_MEM_OFFSET(hdev, i); 1669 1670 tqp++; 1671 } 1672 1673 return 0; 1674 } 1675 1676 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1677 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1678 { 1679 struct hclge_tqp_map_cmd *req; 1680 struct hclge_desc desc; 1681 int ret; 1682 1683 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1684 1685 req = (struct hclge_tqp_map_cmd *)desc.data; 1686 req->tqp_id = cpu_to_le16(tqp_pid); 1687 req->tqp_vf = func_id; 1688 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1689 if (!is_pf) 1690 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1691 req->tqp_vid = cpu_to_le16(tqp_vid); 1692 1693 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1694 if (ret) 1695 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1696 1697 return ret; 1698 } 1699 1700 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1701 { 1702 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1703 struct hclge_dev *hdev = vport->back; 1704 int i, alloced; 1705 1706 for (i = 0, alloced = 0; i < hdev->num_tqps && 1707 alloced < num_tqps; i++) { 1708 if (!hdev->htqp[i].alloced) { 1709 hdev->htqp[i].q.handle = &vport->nic; 1710 hdev->htqp[i].q.tqp_index = alloced; 1711 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1712 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1713 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1714 hdev->htqp[i].alloced = true; 1715 alloced++; 1716 } 1717 } 1718 vport->alloc_tqps = alloced; 1719 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1720 vport->alloc_tqps / hdev->tm_info.num_tc); 1721 1722 /* ensure one to one mapping between irq and queue at default */ 1723 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1724 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1725 1726 return 0; 1727 } 1728 1729 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1730 u16 num_tx_desc, u16 num_rx_desc) 1731 1732 { 1733 struct hnae3_handle *nic = &vport->nic; 1734 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1735 struct hclge_dev *hdev = vport->back; 1736 int ret; 1737 1738 kinfo->num_tx_desc = num_tx_desc; 1739 kinfo->num_rx_desc = num_rx_desc; 1740 1741 kinfo->rx_buf_len = hdev->rx_buf_len; 1742 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1743 1744 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1745 sizeof(struct hnae3_queue *), GFP_KERNEL); 1746 if (!kinfo->tqp) 1747 return -ENOMEM; 1748 1749 ret = hclge_assign_tqp(vport, num_tqps); 1750 if (ret) 1751 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1752 1753 return ret; 1754 } 1755 1756 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1757 struct hclge_vport *vport) 1758 { 1759 struct hnae3_handle *nic = &vport->nic; 1760 struct hnae3_knic_private_info *kinfo; 1761 u16 i; 1762 1763 kinfo = &nic->kinfo; 1764 for (i = 0; i < vport->alloc_tqps; i++) { 1765 struct hclge_comm_tqp *q = 1766 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1767 bool is_pf; 1768 int ret; 1769 1770 is_pf = !(vport->vport_id); 1771 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1772 i, is_pf); 1773 if (ret) 1774 return ret; 1775 } 1776 1777 return 0; 1778 } 1779 1780 static int hclge_map_tqp(struct hclge_dev *hdev) 1781 { 1782 struct hclge_vport *vport = hdev->vport; 1783 u16 i, num_vport; 1784 1785 num_vport = hdev->num_req_vfs + 1; 1786 for (i = 0; i < num_vport; i++) { 1787 int ret; 1788 1789 ret = hclge_map_tqp_to_vport(hdev, vport); 1790 if (ret) 1791 return ret; 1792 1793 vport++; 1794 } 1795 1796 return 0; 1797 } 1798 1799 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1800 { 1801 struct hnae3_handle *nic = &vport->nic; 1802 struct hclge_dev *hdev = vport->back; 1803 int ret; 1804 1805 nic->pdev = hdev->pdev; 1806 nic->ae_algo = &ae_algo; 1807 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1808 MAX_NUMNODES); 1809 nic->kinfo.io_base = hdev->hw.hw.io_base; 1810 1811 ret = hclge_knic_setup(vport, num_tqps, 1812 hdev->num_tx_desc, hdev->num_rx_desc); 1813 if (ret) 1814 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1815 1816 return ret; 1817 } 1818 1819 static int hclge_alloc_vport(struct hclge_dev *hdev) 1820 { 1821 struct pci_dev *pdev = hdev->pdev; 1822 struct hclge_vport *vport; 1823 u32 tqp_main_vport; 1824 u32 tqp_per_vport; 1825 int num_vport, i; 1826 int ret; 1827 1828 /* We need to alloc a vport for main NIC of PF */ 1829 num_vport = hdev->num_req_vfs + 1; 1830 1831 if (hdev->num_tqps < num_vport) { 1832 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1833 hdev->num_tqps, num_vport); 1834 return -EINVAL; 1835 } 1836 1837 /* Alloc the same number of TQPs for every vport */ 1838 tqp_per_vport = hdev->num_tqps / num_vport; 1839 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1840 1841 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1842 GFP_KERNEL); 1843 if (!vport) 1844 return -ENOMEM; 1845 1846 hdev->vport = vport; 1847 hdev->num_alloc_vport = num_vport; 1848 1849 if (IS_ENABLED(CONFIG_PCI_IOV)) 1850 hdev->num_alloc_vfs = hdev->num_req_vfs; 1851 1852 for (i = 0; i < num_vport; i++) { 1853 vport->back = hdev; 1854 vport->vport_id = i; 1855 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1856 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1857 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1858 vport->port_base_vlan_cfg.tbl_sta = true; 1859 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1860 vport->req_vlan_fltr_en = true; 1861 INIT_LIST_HEAD(&vport->vlan_list); 1862 INIT_LIST_HEAD(&vport->uc_mac_list); 1863 INIT_LIST_HEAD(&vport->mc_mac_list); 1864 spin_lock_init(&vport->mac_list_lock); 1865 1866 if (i == 0) 1867 ret = hclge_vport_setup(vport, tqp_main_vport); 1868 else 1869 ret = hclge_vport_setup(vport, tqp_per_vport); 1870 if (ret) { 1871 dev_err(&pdev->dev, 1872 "vport setup failed for vport %d, %d\n", 1873 i, ret); 1874 return ret; 1875 } 1876 1877 vport++; 1878 } 1879 1880 return 0; 1881 } 1882 1883 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1884 struct hclge_pkt_buf_alloc *buf_alloc) 1885 { 1886 /* TX buffer size is unit by 128 byte */ 1887 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1888 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1889 struct hclge_tx_buff_alloc_cmd *req; 1890 struct hclge_desc desc; 1891 int ret; 1892 u8 i; 1893 1894 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1895 1896 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1897 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1898 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1899 1900 req->tx_pkt_buff[i] = 1901 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1902 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1903 } 1904 1905 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1906 if (ret) 1907 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1908 ret); 1909 1910 return ret; 1911 } 1912 1913 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1914 struct hclge_pkt_buf_alloc *buf_alloc) 1915 { 1916 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1917 1918 if (ret) 1919 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1920 1921 return ret; 1922 } 1923 1924 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1925 { 1926 unsigned int i; 1927 u32 cnt = 0; 1928 1929 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1930 if (hdev->hw_tc_map & BIT(i)) 1931 cnt++; 1932 return cnt; 1933 } 1934 1935 /* Get the number of pfc enabled TCs, which have private buffer */ 1936 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1937 struct hclge_pkt_buf_alloc *buf_alloc) 1938 { 1939 struct hclge_priv_buf *priv; 1940 unsigned int i; 1941 int cnt = 0; 1942 1943 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1944 priv = &buf_alloc->priv_buf[i]; 1945 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1946 priv->enable) 1947 cnt++; 1948 } 1949 1950 return cnt; 1951 } 1952 1953 /* Get the number of pfc disabled TCs, which have private buffer */ 1954 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1955 struct hclge_pkt_buf_alloc *buf_alloc) 1956 { 1957 struct hclge_priv_buf *priv; 1958 unsigned int i; 1959 int cnt = 0; 1960 1961 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1962 priv = &buf_alloc->priv_buf[i]; 1963 if (hdev->hw_tc_map & BIT(i) && 1964 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1965 priv->enable) 1966 cnt++; 1967 } 1968 1969 return cnt; 1970 } 1971 1972 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1973 { 1974 struct hclge_priv_buf *priv; 1975 u32 rx_priv = 0; 1976 int i; 1977 1978 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1979 priv = &buf_alloc->priv_buf[i]; 1980 if (priv->enable) 1981 rx_priv += priv->buf_size; 1982 } 1983 return rx_priv; 1984 } 1985 1986 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1987 { 1988 u32 i, total_tx_size = 0; 1989 1990 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1991 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1992 1993 return total_tx_size; 1994 } 1995 1996 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1997 struct hclge_pkt_buf_alloc *buf_alloc, 1998 u32 rx_all) 1999 { 2000 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2001 u32 tc_num = hclge_get_tc_num(hdev); 2002 u32 shared_buf, aligned_mps; 2003 u32 rx_priv; 2004 int i; 2005 2006 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2007 2008 if (hnae3_dev_dcb_supported(hdev)) 2009 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2010 hdev->dv_buf_size; 2011 else 2012 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2013 + hdev->dv_buf_size; 2014 2015 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2016 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2017 HCLGE_BUF_SIZE_UNIT); 2018 2019 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2020 if (rx_all < rx_priv + shared_std) 2021 return false; 2022 2023 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2024 buf_alloc->s_buf.buf_size = shared_buf; 2025 if (hnae3_dev_dcb_supported(hdev)) { 2026 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2027 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2028 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2029 HCLGE_BUF_SIZE_UNIT); 2030 } else { 2031 buf_alloc->s_buf.self.high = aligned_mps + 2032 HCLGE_NON_DCB_ADDITIONAL_BUF; 2033 buf_alloc->s_buf.self.low = aligned_mps; 2034 } 2035 2036 if (hnae3_dev_dcb_supported(hdev)) { 2037 hi_thrd = shared_buf - hdev->dv_buf_size; 2038 2039 if (tc_num <= NEED_RESERVE_TC_NUM) 2040 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2041 / BUF_MAX_PERCENT; 2042 2043 if (tc_num) 2044 hi_thrd = hi_thrd / tc_num; 2045 2046 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2047 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2048 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2049 } else { 2050 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2051 lo_thrd = aligned_mps; 2052 } 2053 2054 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2055 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2056 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2057 } 2058 2059 return true; 2060 } 2061 2062 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2063 struct hclge_pkt_buf_alloc *buf_alloc) 2064 { 2065 u32 i, total_size; 2066 2067 total_size = hdev->pkt_buf_size; 2068 2069 /* alloc tx buffer for all enabled tc */ 2070 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2071 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2072 2073 if (hdev->hw_tc_map & BIT(i)) { 2074 if (total_size < hdev->tx_buf_size) 2075 return -ENOMEM; 2076 2077 priv->tx_buf_size = hdev->tx_buf_size; 2078 } else { 2079 priv->tx_buf_size = 0; 2080 } 2081 2082 total_size -= priv->tx_buf_size; 2083 } 2084 2085 return 0; 2086 } 2087 2088 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2089 struct hclge_pkt_buf_alloc *buf_alloc) 2090 { 2091 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2092 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2093 unsigned int i; 2094 2095 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2096 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2097 2098 priv->enable = 0; 2099 priv->wl.low = 0; 2100 priv->wl.high = 0; 2101 priv->buf_size = 0; 2102 2103 if (!(hdev->hw_tc_map & BIT(i))) 2104 continue; 2105 2106 priv->enable = 1; 2107 2108 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2109 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2110 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2111 HCLGE_BUF_SIZE_UNIT); 2112 } else { 2113 priv->wl.low = 0; 2114 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2115 aligned_mps; 2116 } 2117 2118 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2119 } 2120 2121 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2122 } 2123 2124 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2125 struct hclge_pkt_buf_alloc *buf_alloc) 2126 { 2127 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2128 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2129 int i; 2130 2131 /* let the last to be cleared first */ 2132 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2133 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2134 unsigned int mask = BIT((unsigned int)i); 2135 2136 if (hdev->hw_tc_map & mask && 2137 !(hdev->tm_info.hw_pfc_map & mask)) { 2138 /* Clear the no pfc TC private buffer */ 2139 priv->wl.low = 0; 2140 priv->wl.high = 0; 2141 priv->buf_size = 0; 2142 priv->enable = 0; 2143 no_pfc_priv_num--; 2144 } 2145 2146 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2147 no_pfc_priv_num == 0) 2148 break; 2149 } 2150 2151 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2152 } 2153 2154 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2155 struct hclge_pkt_buf_alloc *buf_alloc) 2156 { 2157 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2158 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2159 int i; 2160 2161 /* let the last to be cleared first */ 2162 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2163 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2164 unsigned int mask = BIT((unsigned int)i); 2165 2166 if (hdev->hw_tc_map & mask && 2167 hdev->tm_info.hw_pfc_map & mask) { 2168 /* Reduce the number of pfc TC with private buffer */ 2169 priv->wl.low = 0; 2170 priv->enable = 0; 2171 priv->wl.high = 0; 2172 priv->buf_size = 0; 2173 pfc_priv_num--; 2174 } 2175 2176 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2177 pfc_priv_num == 0) 2178 break; 2179 } 2180 2181 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2182 } 2183 2184 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2185 struct hclge_pkt_buf_alloc *buf_alloc) 2186 { 2187 #define COMPENSATE_BUFFER 0x3C00 2188 #define COMPENSATE_HALF_MPS_NUM 5 2189 #define PRIV_WL_GAP 0x1800 2190 2191 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2192 u32 tc_num = hclge_get_tc_num(hdev); 2193 u32 half_mps = hdev->mps >> 1; 2194 u32 min_rx_priv; 2195 unsigned int i; 2196 2197 if (tc_num) 2198 rx_priv = rx_priv / tc_num; 2199 2200 if (tc_num <= NEED_RESERVE_TC_NUM) 2201 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2202 2203 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2204 COMPENSATE_HALF_MPS_NUM * half_mps; 2205 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2206 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2207 if (rx_priv < min_rx_priv) 2208 return false; 2209 2210 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2211 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2212 2213 priv->enable = 0; 2214 priv->wl.low = 0; 2215 priv->wl.high = 0; 2216 priv->buf_size = 0; 2217 2218 if (!(hdev->hw_tc_map & BIT(i))) 2219 continue; 2220 2221 priv->enable = 1; 2222 priv->buf_size = rx_priv; 2223 priv->wl.high = rx_priv - hdev->dv_buf_size; 2224 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2225 } 2226 2227 buf_alloc->s_buf.buf_size = 0; 2228 2229 return true; 2230 } 2231 2232 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2233 * @hdev: pointer to struct hclge_dev 2234 * @buf_alloc: pointer to buffer calculation data 2235 * @return: 0: calculate successful, negative: fail 2236 */ 2237 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2238 struct hclge_pkt_buf_alloc *buf_alloc) 2239 { 2240 /* When DCB is not supported, rx private buffer is not allocated. */ 2241 if (!hnae3_dev_dcb_supported(hdev)) { 2242 u32 rx_all = hdev->pkt_buf_size; 2243 2244 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2245 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2246 return -ENOMEM; 2247 2248 return 0; 2249 } 2250 2251 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2252 return 0; 2253 2254 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2255 return 0; 2256 2257 /* try to decrease the buffer size */ 2258 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2259 return 0; 2260 2261 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2262 return 0; 2263 2264 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2265 return 0; 2266 2267 return -ENOMEM; 2268 } 2269 2270 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2271 struct hclge_pkt_buf_alloc *buf_alloc) 2272 { 2273 struct hclge_rx_priv_buff_cmd *req; 2274 struct hclge_desc desc; 2275 int ret; 2276 int i; 2277 2278 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2279 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2280 2281 /* Alloc private buffer TCs */ 2282 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2283 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2284 2285 req->buf_num[i] = 2286 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2287 req->buf_num[i] |= 2288 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2289 } 2290 2291 req->shared_buf = 2292 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2293 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2294 2295 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2296 if (ret) 2297 dev_err(&hdev->pdev->dev, 2298 "rx private buffer alloc cmd failed %d\n", ret); 2299 2300 return ret; 2301 } 2302 2303 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2304 struct hclge_pkt_buf_alloc *buf_alloc) 2305 { 2306 struct hclge_rx_priv_wl_buf *req; 2307 struct hclge_priv_buf *priv; 2308 struct hclge_desc desc[2]; 2309 int i, j; 2310 int ret; 2311 2312 for (i = 0; i < 2; i++) { 2313 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2314 false); 2315 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2316 2317 /* The first descriptor set the NEXT bit to 1 */ 2318 if (i == 0) 2319 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2320 else 2321 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2322 2323 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2324 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2325 2326 priv = &buf_alloc->priv_buf[idx]; 2327 req->tc_wl[j].high = 2328 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2329 req->tc_wl[j].high |= 2330 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2331 req->tc_wl[j].low = 2332 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2333 req->tc_wl[j].low |= 2334 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2335 } 2336 } 2337 2338 /* Send 2 descriptor at one time */ 2339 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2340 if (ret) 2341 dev_err(&hdev->pdev->dev, 2342 "rx private waterline config cmd failed %d\n", 2343 ret); 2344 return ret; 2345 } 2346 2347 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2348 struct hclge_pkt_buf_alloc *buf_alloc) 2349 { 2350 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2351 struct hclge_rx_com_thrd *req; 2352 struct hclge_desc desc[2]; 2353 struct hclge_tc_thrd *tc; 2354 int i, j; 2355 int ret; 2356 2357 for (i = 0; i < 2; i++) { 2358 hclge_cmd_setup_basic_desc(&desc[i], 2359 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2360 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2361 2362 /* The first descriptor set the NEXT bit to 1 */ 2363 if (i == 0) 2364 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2365 else 2366 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2367 2368 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2369 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2370 2371 req->com_thrd[j].high = 2372 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2373 req->com_thrd[j].high |= 2374 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2375 req->com_thrd[j].low = 2376 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2377 req->com_thrd[j].low |= 2378 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2379 } 2380 } 2381 2382 /* Send 2 descriptors at one time */ 2383 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2384 if (ret) 2385 dev_err(&hdev->pdev->dev, 2386 "common threshold config cmd failed %d\n", ret); 2387 return ret; 2388 } 2389 2390 static int hclge_common_wl_config(struct hclge_dev *hdev, 2391 struct hclge_pkt_buf_alloc *buf_alloc) 2392 { 2393 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2394 struct hclge_rx_com_wl *req; 2395 struct hclge_desc desc; 2396 int ret; 2397 2398 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2399 2400 req = (struct hclge_rx_com_wl *)desc.data; 2401 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2402 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2403 2404 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2405 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2406 2407 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2408 if (ret) 2409 dev_err(&hdev->pdev->dev, 2410 "common waterline config cmd failed %d\n", ret); 2411 2412 return ret; 2413 } 2414 2415 int hclge_buffer_alloc(struct hclge_dev *hdev) 2416 { 2417 struct hclge_pkt_buf_alloc *pkt_buf; 2418 int ret; 2419 2420 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2421 if (!pkt_buf) 2422 return -ENOMEM; 2423 2424 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2425 if (ret) { 2426 dev_err(&hdev->pdev->dev, 2427 "could not calc tx buffer size for all TCs %d\n", ret); 2428 goto out; 2429 } 2430 2431 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2432 if (ret) { 2433 dev_err(&hdev->pdev->dev, 2434 "could not alloc tx buffers %d\n", ret); 2435 goto out; 2436 } 2437 2438 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2439 if (ret) { 2440 dev_err(&hdev->pdev->dev, 2441 "could not calc rx priv buffer size for all TCs %d\n", 2442 ret); 2443 goto out; 2444 } 2445 2446 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2447 if (ret) { 2448 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2449 ret); 2450 goto out; 2451 } 2452 2453 if (hnae3_dev_dcb_supported(hdev)) { 2454 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2455 if (ret) { 2456 dev_err(&hdev->pdev->dev, 2457 "could not configure rx private waterline %d\n", 2458 ret); 2459 goto out; 2460 } 2461 2462 ret = hclge_common_thrd_config(hdev, pkt_buf); 2463 if (ret) { 2464 dev_err(&hdev->pdev->dev, 2465 "could not configure common threshold %d\n", 2466 ret); 2467 goto out; 2468 } 2469 } 2470 2471 ret = hclge_common_wl_config(hdev, pkt_buf); 2472 if (ret) 2473 dev_err(&hdev->pdev->dev, 2474 "could not configure common waterline %d\n", ret); 2475 2476 out: 2477 kfree(pkt_buf); 2478 return ret; 2479 } 2480 2481 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2482 { 2483 struct hnae3_handle *roce = &vport->roce; 2484 struct hnae3_handle *nic = &vport->nic; 2485 struct hclge_dev *hdev = vport->back; 2486 2487 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2488 2489 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2490 return -EINVAL; 2491 2492 roce->rinfo.base_vector = hdev->num_nic_msi; 2493 2494 roce->rinfo.netdev = nic->kinfo.netdev; 2495 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2496 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2497 2498 roce->pdev = nic->pdev; 2499 roce->ae_algo = nic->ae_algo; 2500 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2501 MAX_NUMNODES); 2502 2503 return 0; 2504 } 2505 2506 static int hclge_init_msi(struct hclge_dev *hdev) 2507 { 2508 struct pci_dev *pdev = hdev->pdev; 2509 int vectors; 2510 int i; 2511 2512 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2513 hdev->num_msi, 2514 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2515 if (vectors < 0) { 2516 dev_err(&pdev->dev, 2517 "failed(%d) to allocate MSI/MSI-X vectors\n", 2518 vectors); 2519 return vectors; 2520 } 2521 if (vectors < hdev->num_msi) 2522 dev_warn(&hdev->pdev->dev, 2523 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2524 hdev->num_msi, vectors); 2525 2526 hdev->num_msi = vectors; 2527 hdev->num_msi_left = vectors; 2528 2529 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2530 sizeof(u16), GFP_KERNEL); 2531 if (!hdev->vector_status) { 2532 pci_free_irq_vectors(pdev); 2533 return -ENOMEM; 2534 } 2535 2536 for (i = 0; i < hdev->num_msi; i++) 2537 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2538 2539 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2540 sizeof(int), GFP_KERNEL); 2541 if (!hdev->vector_irq) { 2542 pci_free_irq_vectors(pdev); 2543 return -ENOMEM; 2544 } 2545 2546 return 0; 2547 } 2548 2549 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2550 { 2551 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2552 duplex = HCLGE_MAC_FULL; 2553 2554 return duplex; 2555 } 2556 2557 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2558 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2559 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2560 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2561 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2562 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2563 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2564 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2565 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2566 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2567 }; 2568 2569 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2570 { 2571 u16 i; 2572 2573 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2574 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2575 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2576 return 0; 2577 } 2578 } 2579 2580 return -EINVAL; 2581 } 2582 2583 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2584 u8 duplex, u8 lane_num) 2585 { 2586 struct hclge_config_mac_speed_dup_cmd *req; 2587 struct hclge_desc desc; 2588 u32 speed_fw; 2589 int ret; 2590 2591 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2592 2593 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2594 2595 if (duplex) 2596 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2597 2598 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2599 if (ret) { 2600 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2601 return ret; 2602 } 2603 2604 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2605 speed_fw); 2606 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2607 1); 2608 req->lane_num = lane_num; 2609 2610 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2611 if (ret) { 2612 dev_err(&hdev->pdev->dev, 2613 "mac speed/duplex config cmd failed %d.\n", ret); 2614 return ret; 2615 } 2616 2617 return 0; 2618 } 2619 2620 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2621 { 2622 struct hclge_mac *mac = &hdev->hw.mac; 2623 int ret; 2624 2625 duplex = hclge_check_speed_dup(duplex, speed); 2626 if (!mac->support_autoneg && mac->speed == speed && 2627 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2628 return 0; 2629 2630 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2631 if (ret) 2632 return ret; 2633 2634 hdev->hw.mac.speed = speed; 2635 hdev->hw.mac.duplex = duplex; 2636 if (!lane_num) 2637 hdev->hw.mac.lane_num = lane_num; 2638 2639 return 0; 2640 } 2641 2642 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2643 u8 duplex, u8 lane_num) 2644 { 2645 struct hclge_vport *vport = hclge_get_vport(handle); 2646 struct hclge_dev *hdev = vport->back; 2647 int ret; 2648 2649 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2650 2651 if (ret) 2652 return ret; 2653 2654 hdev->hw.mac.req_speed = speed; 2655 hdev->hw.mac.req_duplex = duplex; 2656 2657 return 0; 2658 } 2659 2660 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2661 { 2662 struct hclge_config_auto_neg_cmd *req; 2663 struct hclge_desc desc; 2664 u32 flag = 0; 2665 int ret; 2666 2667 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2668 2669 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2670 if (enable) 2671 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2672 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2673 2674 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2675 if (ret) 2676 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2677 ret); 2678 2679 return ret; 2680 } 2681 2682 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2683 { 2684 struct hclge_vport *vport = hclge_get_vport(handle); 2685 struct hclge_dev *hdev = vport->back; 2686 2687 if (!hdev->hw.mac.support_autoneg) { 2688 if (enable) { 2689 dev_err(&hdev->pdev->dev, 2690 "autoneg is not supported by current port\n"); 2691 return -EOPNOTSUPP; 2692 } else { 2693 return 0; 2694 } 2695 } 2696 2697 return hclge_set_autoneg_en(hdev, enable); 2698 } 2699 2700 static int hclge_get_autoneg(struct hnae3_handle *handle) 2701 { 2702 struct hclge_vport *vport = hclge_get_vport(handle); 2703 struct hclge_dev *hdev = vport->back; 2704 struct phy_device *phydev = hdev->hw.mac.phydev; 2705 2706 if (phydev) 2707 return phydev->autoneg; 2708 2709 return hdev->hw.mac.autoneg; 2710 } 2711 2712 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2713 { 2714 struct hclge_vport *vport = hclge_get_vport(handle); 2715 struct hclge_dev *hdev = vport->back; 2716 int ret; 2717 2718 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2719 2720 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2721 if (ret) 2722 return ret; 2723 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2724 } 2725 2726 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2727 { 2728 struct hclge_vport *vport = hclge_get_vport(handle); 2729 struct hclge_dev *hdev = vport->back; 2730 2731 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2732 return hclge_set_autoneg_en(hdev, !halt); 2733 2734 return 0; 2735 } 2736 2737 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2738 struct hclge_desc *desc, u32 desc_len) 2739 { 2740 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2741 u32 desc_index = 0; 2742 u32 data_index = 0; 2743 u32 i; 2744 2745 for (i = 0; i < lane_size; i++) { 2746 if (data_index >= HCLGE_DESC_DATA_LEN) { 2747 desc_index++; 2748 data_index = 0; 2749 } 2750 2751 if (desc_index >= desc_len) 2752 return; 2753 2754 hdev->fec_stats.per_lanes[i] += 2755 le32_to_cpu(desc[desc_index].data[data_index]); 2756 data_index++; 2757 } 2758 } 2759 2760 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2761 struct hclge_desc *desc, u32 desc_len) 2762 { 2763 struct hclge_query_fec_stats_cmd *req; 2764 2765 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2766 2767 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2768 hdev->fec_stats.rs_corr_blocks += 2769 le32_to_cpu(req->rs_fec_corr_blocks); 2770 hdev->fec_stats.rs_uncorr_blocks += 2771 le32_to_cpu(req->rs_fec_uncorr_blocks); 2772 hdev->fec_stats.rs_error_blocks += 2773 le32_to_cpu(req->rs_fec_error_blocks); 2774 hdev->fec_stats.base_r_corr_blocks += 2775 le32_to_cpu(req->base_r_fec_corr_blocks); 2776 hdev->fec_stats.base_r_uncorr_blocks += 2777 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2778 2779 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2780 } 2781 2782 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2783 { 2784 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2785 int ret; 2786 u32 i; 2787 2788 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2789 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2790 true); 2791 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2792 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2793 } 2794 2795 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2796 if (ret) 2797 return ret; 2798 2799 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2800 2801 return 0; 2802 } 2803 2804 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2805 { 2806 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2807 int ret; 2808 2809 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2810 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2811 return; 2812 2813 ret = hclge_update_fec_stats_hw(hdev); 2814 if (ret) 2815 dev_err(&hdev->pdev->dev, 2816 "failed to update fec stats, ret = %d\n", ret); 2817 2818 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2819 } 2820 2821 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2822 struct ethtool_fec_stats *fec_stats) 2823 { 2824 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2825 fec_stats->uncorrectable_blocks.total = 2826 hdev->fec_stats.rs_uncorr_blocks; 2827 } 2828 2829 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2830 struct ethtool_fec_stats *fec_stats) 2831 { 2832 u32 i; 2833 2834 if (hdev->fec_stats.base_r_lane_num == 0 || 2835 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2836 dev_err(&hdev->pdev->dev, 2837 "fec stats lane number(%llu) is invalid\n", 2838 hdev->fec_stats.base_r_lane_num); 2839 return; 2840 } 2841 2842 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2843 fec_stats->corrected_blocks.lanes[i] = 2844 hdev->fec_stats.base_r_corr_per_lanes[i]; 2845 fec_stats->uncorrectable_blocks.lanes[i] = 2846 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2847 } 2848 } 2849 2850 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2851 struct ethtool_fec_stats *fec_stats) 2852 { 2853 u32 fec_mode = hdev->hw.mac.fec_mode; 2854 2855 switch (fec_mode) { 2856 case BIT(HNAE3_FEC_RS): 2857 case BIT(HNAE3_FEC_LLRS): 2858 hclge_get_fec_stats_total(hdev, fec_stats); 2859 break; 2860 case BIT(HNAE3_FEC_BASER): 2861 hclge_get_fec_stats_lanes(hdev, fec_stats); 2862 break; 2863 default: 2864 dev_err(&hdev->pdev->dev, 2865 "fec stats is not supported by current fec mode(0x%x)\n", 2866 fec_mode); 2867 break; 2868 } 2869 } 2870 2871 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2872 struct ethtool_fec_stats *fec_stats) 2873 { 2874 struct hclge_vport *vport = hclge_get_vport(handle); 2875 struct hclge_dev *hdev = vport->back; 2876 u32 fec_mode = hdev->hw.mac.fec_mode; 2877 2878 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2879 fec_mode == BIT(HNAE3_FEC_AUTO) || 2880 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2881 return; 2882 2883 hclge_update_fec_stats(hdev); 2884 2885 hclge_comm_get_fec_stats(hdev, fec_stats); 2886 } 2887 2888 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2889 { 2890 struct hclge_config_fec_cmd *req; 2891 struct hclge_desc desc; 2892 int ret; 2893 2894 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2895 2896 req = (struct hclge_config_fec_cmd *)desc.data; 2897 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2898 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2899 if (fec_mode & BIT(HNAE3_FEC_RS)) 2900 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2901 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2902 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2903 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2904 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2905 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2906 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2907 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2908 2909 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2910 if (ret) 2911 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2912 2913 return ret; 2914 } 2915 2916 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2917 { 2918 struct hclge_vport *vport = hclge_get_vport(handle); 2919 struct hclge_dev *hdev = vport->back; 2920 struct hclge_mac *mac = &hdev->hw.mac; 2921 int ret; 2922 2923 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2924 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2925 return -EINVAL; 2926 } 2927 2928 ret = hclge_set_fec_hw(hdev, fec_mode); 2929 if (ret) 2930 return ret; 2931 2932 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2933 return 0; 2934 } 2935 2936 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2937 u8 *fec_mode) 2938 { 2939 struct hclge_vport *vport = hclge_get_vport(handle); 2940 struct hclge_dev *hdev = vport->back; 2941 struct hclge_mac *mac = &hdev->hw.mac; 2942 2943 if (fec_ability) 2944 *fec_ability = mac->fec_ability; 2945 if (fec_mode) 2946 *fec_mode = mac->fec_mode; 2947 } 2948 2949 static int hclge_mac_init(struct hclge_dev *hdev) 2950 { 2951 struct hclge_mac *mac = &hdev->hw.mac; 2952 int ret; 2953 2954 hdev->support_sfp_query = true; 2955 2956 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2957 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2958 2959 if (hdev->hw.mac.support_autoneg) { 2960 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2961 if (ret) 2962 return ret; 2963 } 2964 2965 if (!hdev->hw.mac.autoneg) { 2966 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed, 2967 hdev->hw.mac.req_duplex, 2968 hdev->hw.mac.lane_num); 2969 if (ret) 2970 return ret; 2971 } 2972 2973 mac->link = 0; 2974 2975 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2976 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2977 if (ret) 2978 return ret; 2979 } 2980 2981 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2982 if (ret) { 2983 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2984 return ret; 2985 } 2986 2987 ret = hclge_set_default_loopback(hdev); 2988 if (ret) 2989 return ret; 2990 2991 ret = hclge_buffer_alloc(hdev); 2992 if (ret) 2993 dev_err(&hdev->pdev->dev, 2994 "allocate buffer fail, ret=%d\n", ret); 2995 2996 return ret; 2997 } 2998 2999 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 3000 { 3001 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3002 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 3003 hdev->last_mbx_scheduled = jiffies; 3004 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3005 } 3006 } 3007 3008 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 3009 { 3010 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3011 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 3012 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 3013 hdev->last_rst_scheduled = jiffies; 3014 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3015 } 3016 } 3017 3018 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 3019 { 3020 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3021 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 3022 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3023 } 3024 3025 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 3026 { 3027 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3028 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 3029 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 3030 } 3031 3032 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 3033 { 3034 struct hclge_link_status_cmd *req; 3035 struct hclge_desc desc; 3036 int ret; 3037 3038 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 3039 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3040 if (ret) { 3041 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 3042 ret); 3043 return ret; 3044 } 3045 3046 req = (struct hclge_link_status_cmd *)desc.data; 3047 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3048 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3049 3050 return 0; 3051 } 3052 3053 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3054 { 3055 struct phy_device *phydev = hdev->hw.mac.phydev; 3056 3057 *link_status = HCLGE_LINK_STATUS_DOWN; 3058 3059 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3060 return 0; 3061 3062 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3063 return 0; 3064 3065 return hclge_get_mac_link_status(hdev, link_status); 3066 } 3067 3068 static void hclge_push_link_status(struct hclge_dev *hdev) 3069 { 3070 struct hclge_vport *vport; 3071 int ret; 3072 u16 i; 3073 3074 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3075 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3076 3077 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3078 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3079 continue; 3080 3081 ret = hclge_push_vf_link_status(vport); 3082 if (ret) { 3083 dev_err(&hdev->pdev->dev, 3084 "failed to push link status to vf%u, ret = %d\n", 3085 i, ret); 3086 } 3087 } 3088 } 3089 3090 static void hclge_update_link_status(struct hclge_dev *hdev) 3091 { 3092 struct hnae3_handle *handle = &hdev->vport[0].nic; 3093 struct hnae3_client *client = hdev->nic_client; 3094 int state; 3095 int ret; 3096 3097 if (!client) 3098 return; 3099 3100 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3101 return; 3102 3103 ret = hclge_get_mac_phy_link(hdev, &state); 3104 if (ret) { 3105 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3106 return; 3107 } 3108 3109 if (state != hdev->hw.mac.link) { 3110 hdev->hw.mac.link = state; 3111 if (state == HCLGE_LINK_STATUS_UP) 3112 hclge_update_port_info(hdev); 3113 3114 client->ops->link_status_change(handle, state); 3115 hclge_config_mac_tnl_int(hdev, state); 3116 3117 if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) { 3118 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3119 struct hnae3_client *rclient = hdev->roce_client; 3120 3121 if (rclient && rclient->ops->link_status_change) 3122 rclient->ops->link_status_change(rhandle, 3123 state); 3124 } 3125 3126 hclge_push_link_status(hdev); 3127 } 3128 3129 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3130 } 3131 3132 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3133 { 3134 u32 speed_ability; 3135 3136 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3137 return; 3138 3139 switch (mac->module_type) { 3140 case HNAE3_MODULE_TYPE_FIBRE_LR: 3141 hclge_convert_setting_lr(speed_ability, mac->advertising); 3142 break; 3143 case HNAE3_MODULE_TYPE_FIBRE_SR: 3144 case HNAE3_MODULE_TYPE_AOC: 3145 hclge_convert_setting_sr(speed_ability, mac->advertising); 3146 break; 3147 case HNAE3_MODULE_TYPE_CR: 3148 hclge_convert_setting_cr(speed_ability, mac->advertising); 3149 break; 3150 case HNAE3_MODULE_TYPE_KR: 3151 hclge_convert_setting_kr(speed_ability, mac->advertising); 3152 break; 3153 default: 3154 break; 3155 } 3156 } 3157 3158 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3159 { 3160 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3161 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3162 mac->advertising); 3163 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3164 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3165 mac->advertising); 3166 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3167 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3168 mac->advertising); 3169 else 3170 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3171 mac->advertising); 3172 } 3173 3174 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3175 { 3176 struct hclge_mac *mac = &hdev->hw.mac; 3177 bool rx_en, tx_en; 3178 3179 switch (hdev->fc_mode_last_time) { 3180 case HCLGE_FC_RX_PAUSE: 3181 rx_en = true; 3182 tx_en = false; 3183 break; 3184 case HCLGE_FC_TX_PAUSE: 3185 rx_en = false; 3186 tx_en = true; 3187 break; 3188 case HCLGE_FC_FULL: 3189 rx_en = true; 3190 tx_en = true; 3191 break; 3192 default: 3193 rx_en = false; 3194 tx_en = false; 3195 break; 3196 } 3197 3198 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3199 } 3200 3201 static void hclge_update_advertising(struct hclge_dev *hdev) 3202 { 3203 struct hclge_mac *mac = &hdev->hw.mac; 3204 3205 linkmode_zero(mac->advertising); 3206 hclge_update_speed_advertising(mac); 3207 hclge_update_fec_advertising(mac); 3208 hclge_update_pause_advertising(hdev); 3209 } 3210 3211 static void hclge_update_port_capability(struct hclge_dev *hdev, 3212 struct hclge_mac *mac) 3213 { 3214 if (hnae3_dev_fec_supported(hdev)) 3215 hclge_convert_setting_fec(mac); 3216 3217 /* firmware can not identify back plane type, the media type 3218 * read from configuration can help deal it 3219 */ 3220 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3221 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3222 mac->module_type = HNAE3_MODULE_TYPE_KR; 3223 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3224 mac->module_type = HNAE3_MODULE_TYPE_TP; 3225 3226 if (mac->support_autoneg) { 3227 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3228 linkmode_copy(mac->advertising, mac->supported); 3229 } else { 3230 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3231 mac->supported); 3232 hclge_update_advertising(hdev); 3233 } 3234 } 3235 3236 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3237 { 3238 struct hclge_sfp_info_cmd *resp; 3239 struct hclge_desc desc; 3240 int ret; 3241 3242 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3243 resp = (struct hclge_sfp_info_cmd *)desc.data; 3244 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3245 if (ret == -EOPNOTSUPP) { 3246 dev_warn(&hdev->pdev->dev, 3247 "IMP do not support get SFP speed %d\n", ret); 3248 return ret; 3249 } else if (ret) { 3250 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3251 return ret; 3252 } 3253 3254 *speed = le32_to_cpu(resp->speed); 3255 3256 return 0; 3257 } 3258 3259 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3260 { 3261 struct hclge_sfp_info_cmd *resp; 3262 struct hclge_desc desc; 3263 int ret; 3264 3265 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3266 resp = (struct hclge_sfp_info_cmd *)desc.data; 3267 3268 resp->query_type = QUERY_ACTIVE_SPEED; 3269 3270 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3271 if (ret == -EOPNOTSUPP) { 3272 dev_warn(&hdev->pdev->dev, 3273 "IMP does not support get SFP info %d\n", ret); 3274 return ret; 3275 } else if (ret) { 3276 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3277 return ret; 3278 } 3279 3280 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3281 * set to mac->speed. 3282 */ 3283 if (!le32_to_cpu(resp->speed)) 3284 return 0; 3285 3286 mac->speed = le32_to_cpu(resp->speed); 3287 /* if resp->speed_ability is 0, it means it's an old version 3288 * firmware, do not update these params 3289 */ 3290 if (resp->speed_ability) { 3291 mac->module_type = le32_to_cpu(resp->module_type); 3292 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3293 mac->autoneg = resp->autoneg; 3294 mac->support_autoneg = resp->autoneg_ability; 3295 mac->speed_type = QUERY_ACTIVE_SPEED; 3296 mac->lane_num = resp->lane_num; 3297 if (!resp->active_fec) 3298 mac->fec_mode = 0; 3299 else 3300 mac->fec_mode = BIT(resp->active_fec); 3301 mac->fec_ability = resp->fec_ability; 3302 } else { 3303 mac->speed_type = QUERY_SFP_SPEED; 3304 } 3305 3306 return 0; 3307 } 3308 3309 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3310 struct ethtool_link_ksettings *cmd) 3311 { 3312 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3313 struct hclge_vport *vport = hclge_get_vport(handle); 3314 struct hclge_phy_link_ksetting_0_cmd *req0; 3315 struct hclge_phy_link_ksetting_1_cmd *req1; 3316 u32 supported, advertising, lp_advertising; 3317 struct hclge_dev *hdev = vport->back; 3318 int ret; 3319 3320 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3321 true); 3322 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3323 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3324 true); 3325 3326 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3327 if (ret) { 3328 dev_err(&hdev->pdev->dev, 3329 "failed to get phy link ksetting, ret = %d.\n", ret); 3330 return ret; 3331 } 3332 3333 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3334 cmd->base.autoneg = req0->autoneg; 3335 cmd->base.speed = le32_to_cpu(req0->speed); 3336 cmd->base.duplex = req0->duplex; 3337 cmd->base.port = req0->port; 3338 cmd->base.transceiver = req0->transceiver; 3339 cmd->base.phy_address = req0->phy_address; 3340 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3341 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3342 supported = le32_to_cpu(req0->supported); 3343 advertising = le32_to_cpu(req0->advertising); 3344 lp_advertising = le32_to_cpu(req0->lp_advertising); 3345 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3346 supported); 3347 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3348 advertising); 3349 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3350 lp_advertising); 3351 3352 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3353 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3354 cmd->base.master_slave_state = req1->master_slave_state; 3355 3356 return 0; 3357 } 3358 3359 static int 3360 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3361 const struct ethtool_link_ksettings *cmd) 3362 { 3363 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3364 struct hclge_vport *vport = hclge_get_vport(handle); 3365 struct hclge_phy_link_ksetting_0_cmd *req0; 3366 struct hclge_phy_link_ksetting_1_cmd *req1; 3367 struct hclge_dev *hdev = vport->back; 3368 u32 advertising; 3369 int ret; 3370 3371 if (cmd->base.autoneg == AUTONEG_DISABLE && 3372 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3373 (cmd->base.duplex != DUPLEX_HALF && 3374 cmd->base.duplex != DUPLEX_FULL))) 3375 return -EINVAL; 3376 3377 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3378 false); 3379 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3380 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3381 false); 3382 3383 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3384 req0->autoneg = cmd->base.autoneg; 3385 req0->speed = cpu_to_le32(cmd->base.speed); 3386 req0->duplex = cmd->base.duplex; 3387 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3388 cmd->link_modes.advertising); 3389 req0->advertising = cpu_to_le32(advertising); 3390 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3391 3392 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3393 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3394 3395 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3396 if (ret) { 3397 dev_err(&hdev->pdev->dev, 3398 "failed to set phy link ksettings, ret = %d.\n", ret); 3399 return ret; 3400 } 3401 3402 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3403 hdev->hw.mac.req_speed = cmd->base.speed; 3404 hdev->hw.mac.req_duplex = cmd->base.duplex; 3405 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3406 3407 return 0; 3408 } 3409 3410 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3411 { 3412 struct ethtool_link_ksettings cmd; 3413 int ret; 3414 3415 if (!hnae3_dev_phy_imp_supported(hdev)) 3416 return 0; 3417 3418 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3419 if (ret) 3420 return ret; 3421 3422 hdev->hw.mac.autoneg = cmd.base.autoneg; 3423 hdev->hw.mac.speed = cmd.base.speed; 3424 hdev->hw.mac.duplex = cmd.base.duplex; 3425 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3426 3427 return 0; 3428 } 3429 3430 static int hclge_tp_port_init(struct hclge_dev *hdev) 3431 { 3432 struct ethtool_link_ksettings cmd; 3433 3434 if (!hnae3_dev_phy_imp_supported(hdev)) 3435 return 0; 3436 3437 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3438 cmd.base.speed = hdev->hw.mac.req_speed; 3439 cmd.base.duplex = hdev->hw.mac.req_duplex; 3440 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3441 3442 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3443 } 3444 3445 static int hclge_update_port_info(struct hclge_dev *hdev) 3446 { 3447 struct hclge_mac *mac = &hdev->hw.mac; 3448 int speed; 3449 int ret; 3450 3451 /* get the port info from SFP cmd if not copper port */ 3452 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3453 return hclge_update_tp_port_info(hdev); 3454 3455 /* if IMP does not support get SFP/qSFP info, return directly */ 3456 if (!hdev->support_sfp_query) 3457 return 0; 3458 3459 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3460 speed = mac->speed; 3461 ret = hclge_get_sfp_info(hdev, mac); 3462 } else { 3463 speed = HCLGE_MAC_SPEED_UNKNOWN; 3464 ret = hclge_get_sfp_speed(hdev, &speed); 3465 } 3466 3467 if (ret == -EOPNOTSUPP) { 3468 hdev->support_sfp_query = false; 3469 return ret; 3470 } else if (ret) { 3471 return ret; 3472 } 3473 3474 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3475 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3476 hclge_update_port_capability(hdev, mac); 3477 if (mac->speed != speed) 3478 (void)hclge_tm_port_shaper_cfg(hdev); 3479 return 0; 3480 } 3481 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3482 HCLGE_MAC_FULL, mac->lane_num); 3483 } else { 3484 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3485 return 0; /* do nothing if no SFP */ 3486 3487 /* must config full duplex for SFP */ 3488 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3489 } 3490 } 3491 3492 static int hclge_get_status(struct hnae3_handle *handle) 3493 { 3494 struct hclge_vport *vport = hclge_get_vport(handle); 3495 struct hclge_dev *hdev = vport->back; 3496 3497 hclge_update_link_status(hdev); 3498 3499 return hdev->hw.mac.link; 3500 } 3501 3502 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3503 { 3504 if (!pci_num_vf(hdev->pdev)) { 3505 dev_err(&hdev->pdev->dev, 3506 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3507 return NULL; 3508 } 3509 3510 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3511 dev_err(&hdev->pdev->dev, 3512 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3513 vf, pci_num_vf(hdev->pdev)); 3514 return NULL; 3515 } 3516 3517 /* VF start from 1 in vport */ 3518 vf += HCLGE_VF_VPORT_START_NUM; 3519 return &hdev->vport[vf]; 3520 } 3521 3522 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3523 struct ifla_vf_info *ivf) 3524 { 3525 struct hclge_vport *vport = hclge_get_vport(handle); 3526 struct hclge_dev *hdev = vport->back; 3527 3528 vport = hclge_get_vf_vport(hdev, vf); 3529 if (!vport) 3530 return -EINVAL; 3531 3532 ivf->vf = vf; 3533 ivf->linkstate = vport->vf_info.link_state; 3534 ivf->spoofchk = vport->vf_info.spoofchk; 3535 ivf->trusted = vport->vf_info.trusted; 3536 ivf->min_tx_rate = 0; 3537 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3538 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3539 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3540 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3541 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3542 3543 return 0; 3544 } 3545 3546 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3547 int link_state) 3548 { 3549 struct hclge_vport *vport = hclge_get_vport(handle); 3550 struct hclge_dev *hdev = vport->back; 3551 int link_state_old; 3552 int ret; 3553 3554 vport = hclge_get_vf_vport(hdev, vf); 3555 if (!vport) 3556 return -EINVAL; 3557 3558 link_state_old = vport->vf_info.link_state; 3559 vport->vf_info.link_state = link_state; 3560 3561 /* return success directly if the VF is unalive, VF will 3562 * query link state itself when it starts work. 3563 */ 3564 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3565 return 0; 3566 3567 ret = hclge_push_vf_link_status(vport); 3568 if (ret) { 3569 vport->vf_info.link_state = link_state_old; 3570 dev_err(&hdev->pdev->dev, 3571 "failed to push vf%d link status, ret = %d\n", vf, ret); 3572 } 3573 3574 return ret; 3575 } 3576 3577 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3578 { 3579 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3580 3581 /* fetch the events from their corresponding regs */ 3582 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3583 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3584 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3585 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3586 3587 /* Assumption: If by any chance reset and mailbox events are reported 3588 * together then we will only process reset event in this go and will 3589 * defer the processing of the mailbox events. Since, we would have not 3590 * cleared RX CMDQ event this time we would receive again another 3591 * interrupt from H/W just for the mailbox. 3592 * 3593 * check for vector0 reset event sources 3594 */ 3595 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3596 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3597 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3598 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3599 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3600 hdev->rst_stats.imp_rst_cnt++; 3601 return HCLGE_VECTOR0_EVENT_RST; 3602 } 3603 3604 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3605 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3606 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3607 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3608 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3609 hdev->rst_stats.global_rst_cnt++; 3610 return HCLGE_VECTOR0_EVENT_RST; 3611 } 3612 3613 /* check for vector0 msix event and hardware error event source */ 3614 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3615 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3616 return HCLGE_VECTOR0_EVENT_ERR; 3617 3618 /* check for vector0 ptp event source */ 3619 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3620 *clearval = msix_src_reg; 3621 return HCLGE_VECTOR0_EVENT_PTP; 3622 } 3623 3624 /* check for vector0 mailbox(=CMDQ RX) event source */ 3625 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3626 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3627 *clearval = cmdq_src_reg; 3628 return HCLGE_VECTOR0_EVENT_MBX; 3629 } 3630 3631 /* print other vector0 event source */ 3632 dev_info(&hdev->pdev->dev, 3633 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3634 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3635 3636 return HCLGE_VECTOR0_EVENT_OTHER; 3637 } 3638 3639 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3640 u32 regclr) 3641 { 3642 #define HCLGE_IMP_RESET_DELAY 5 3643 3644 switch (event_type) { 3645 case HCLGE_VECTOR0_EVENT_PTP: 3646 case HCLGE_VECTOR0_EVENT_RST: 3647 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3648 mdelay(HCLGE_IMP_RESET_DELAY); 3649 3650 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3651 break; 3652 case HCLGE_VECTOR0_EVENT_MBX: 3653 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3654 break; 3655 default: 3656 break; 3657 } 3658 } 3659 3660 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3661 { 3662 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3663 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3664 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3665 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3666 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3667 } 3668 3669 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3670 { 3671 writel(enable ? 1 : 0, vector->addr); 3672 } 3673 3674 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3675 { 3676 struct hclge_dev *hdev = data; 3677 unsigned long flags; 3678 u32 clearval = 0; 3679 u32 event_cause; 3680 3681 hclge_enable_vector(&hdev->misc_vector, false); 3682 event_cause = hclge_check_event_cause(hdev, &clearval); 3683 3684 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3685 switch (event_cause) { 3686 case HCLGE_VECTOR0_EVENT_ERR: 3687 hclge_errhand_task_schedule(hdev); 3688 break; 3689 case HCLGE_VECTOR0_EVENT_RST: 3690 hclge_reset_task_schedule(hdev); 3691 break; 3692 case HCLGE_VECTOR0_EVENT_PTP: 3693 spin_lock_irqsave(&hdev->ptp->lock, flags); 3694 hclge_ptp_clean_tx_hwts(hdev); 3695 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3696 break; 3697 case HCLGE_VECTOR0_EVENT_MBX: 3698 /* If we are here then, 3699 * 1. Either we are not handling any mbx task and we are not 3700 * scheduled as well 3701 * OR 3702 * 2. We could be handling a mbx task but nothing more is 3703 * scheduled. 3704 * In both cases, we should schedule mbx task as there are more 3705 * mbx messages reported by this interrupt. 3706 */ 3707 hclge_mbx_task_schedule(hdev); 3708 break; 3709 default: 3710 dev_warn(&hdev->pdev->dev, 3711 "received unknown or unhandled event of vector0\n"); 3712 break; 3713 } 3714 3715 hclge_clear_event_cause(hdev, event_cause, clearval); 3716 3717 /* Enable interrupt if it is not caused by reset event or error event */ 3718 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3719 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3720 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3721 hclge_enable_vector(&hdev->misc_vector, true); 3722 3723 return IRQ_HANDLED; 3724 } 3725 3726 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3727 { 3728 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3729 dev_warn(&hdev->pdev->dev, 3730 "vector(vector_id %d) has been freed.\n", vector_id); 3731 return; 3732 } 3733 3734 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3735 hdev->num_msi_left += 1; 3736 hdev->num_msi_used -= 1; 3737 } 3738 3739 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3740 { 3741 struct hclge_misc_vector *vector = &hdev->misc_vector; 3742 3743 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3744 3745 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3746 hdev->vector_status[0] = 0; 3747 3748 hdev->num_msi_left -= 1; 3749 hdev->num_msi_used += 1; 3750 } 3751 3752 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3753 { 3754 int ret; 3755 3756 hclge_get_misc_vector(hdev); 3757 3758 /* this would be explicitly freed in the end */ 3759 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3760 HCLGE_NAME, pci_name(hdev->pdev)); 3761 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3762 0, hdev->misc_vector.name, hdev); 3763 if (ret) { 3764 hclge_free_vector(hdev, 0); 3765 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3766 hdev->misc_vector.vector_irq); 3767 } 3768 3769 return ret; 3770 } 3771 3772 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3773 { 3774 free_irq(hdev->misc_vector.vector_irq, hdev); 3775 hclge_free_vector(hdev, 0); 3776 } 3777 3778 int hclge_notify_client(struct hclge_dev *hdev, 3779 enum hnae3_reset_notify_type type) 3780 { 3781 struct hnae3_handle *handle = &hdev->vport[0].nic; 3782 struct hnae3_client *client = hdev->nic_client; 3783 int ret; 3784 3785 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3786 return 0; 3787 3788 if (!client->ops->reset_notify) 3789 return -EOPNOTSUPP; 3790 3791 ret = client->ops->reset_notify(handle, type); 3792 if (ret) 3793 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3794 type, ret); 3795 3796 return ret; 3797 } 3798 3799 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3800 enum hnae3_reset_notify_type type) 3801 { 3802 struct hnae3_handle *handle = &hdev->vport[0].roce; 3803 struct hnae3_client *client = hdev->roce_client; 3804 int ret; 3805 3806 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3807 return 0; 3808 3809 if (!client->ops->reset_notify) 3810 return -EOPNOTSUPP; 3811 3812 ret = client->ops->reset_notify(handle, type); 3813 if (ret) 3814 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3815 type, ret); 3816 3817 return ret; 3818 } 3819 3820 static int hclge_reset_wait(struct hclge_dev *hdev) 3821 { 3822 #define HCLGE_RESET_WATI_MS 100 3823 #define HCLGE_RESET_WAIT_CNT 350 3824 3825 u32 val, reg, reg_bit; 3826 u32 cnt = 0; 3827 3828 switch (hdev->reset_type) { 3829 case HNAE3_IMP_RESET: 3830 reg = HCLGE_GLOBAL_RESET_REG; 3831 reg_bit = HCLGE_IMP_RESET_BIT; 3832 break; 3833 case HNAE3_GLOBAL_RESET: 3834 reg = HCLGE_GLOBAL_RESET_REG; 3835 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3836 break; 3837 case HNAE3_FUNC_RESET: 3838 reg = HCLGE_FUN_RST_ING; 3839 reg_bit = HCLGE_FUN_RST_ING_B; 3840 break; 3841 default: 3842 dev_err(&hdev->pdev->dev, 3843 "Wait for unsupported reset type: %d\n", 3844 hdev->reset_type); 3845 return -EINVAL; 3846 } 3847 3848 val = hclge_read_dev(&hdev->hw, reg); 3849 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3850 msleep(HCLGE_RESET_WATI_MS); 3851 val = hclge_read_dev(&hdev->hw, reg); 3852 cnt++; 3853 } 3854 3855 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3856 dev_warn(&hdev->pdev->dev, 3857 "Wait for reset timeout: %d\n", hdev->reset_type); 3858 return -EBUSY; 3859 } 3860 3861 return 0; 3862 } 3863 3864 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3865 { 3866 struct hclge_vf_rst_cmd *req; 3867 struct hclge_desc desc; 3868 3869 req = (struct hclge_vf_rst_cmd *)desc.data; 3870 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3871 req->dest_vfid = func_id; 3872 3873 if (reset) 3874 req->vf_rst = 0x1; 3875 3876 return hclge_cmd_send(&hdev->hw, &desc, 1); 3877 } 3878 3879 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3880 { 3881 int i; 3882 3883 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3884 struct hclge_vport *vport = &hdev->vport[i]; 3885 int ret; 3886 3887 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3888 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3889 if (ret) { 3890 dev_err(&hdev->pdev->dev, 3891 "set vf(%u) rst failed %d!\n", 3892 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3893 ret); 3894 return ret; 3895 } 3896 3897 if (!reset || 3898 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3899 continue; 3900 3901 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3902 hdev->reset_type == HNAE3_FUNC_RESET) { 3903 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3904 &vport->need_notify); 3905 continue; 3906 } 3907 3908 /* Inform VF to process the reset. 3909 * hclge_inform_reset_assert_to_vf may fail if VF 3910 * driver is not loaded. 3911 */ 3912 ret = hclge_inform_reset_assert_to_vf(vport); 3913 if (ret) 3914 dev_warn(&hdev->pdev->dev, 3915 "inform reset to vf(%u) failed %d!\n", 3916 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3917 ret); 3918 } 3919 3920 return 0; 3921 } 3922 3923 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3924 { 3925 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3926 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3927 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3928 return; 3929 3930 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3931 HCLGE_MBX_SCHED_TIMEOUT)) 3932 dev_warn(&hdev->pdev->dev, 3933 "mbx service task is scheduled after %ums on cpu%u!\n", 3934 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3935 smp_processor_id()); 3936 3937 hclge_mbx_handler(hdev); 3938 3939 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3940 } 3941 3942 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3943 { 3944 struct hclge_pf_rst_sync_cmd *req; 3945 struct hclge_desc desc; 3946 int cnt = 0; 3947 int ret; 3948 3949 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3950 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3951 3952 do { 3953 /* vf need to down netdev by mbx during PF or FLR reset */ 3954 hclge_mailbox_service_task(hdev); 3955 3956 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3957 /* for compatible with old firmware, wait 3958 * 100 ms for VF to stop IO 3959 */ 3960 if (ret == -EOPNOTSUPP) { 3961 msleep(HCLGE_RESET_SYNC_TIME); 3962 return; 3963 } else if (ret) { 3964 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3965 ret); 3966 return; 3967 } else if (req->all_vf_ready) { 3968 return; 3969 } 3970 msleep(HCLGE_PF_RESET_SYNC_TIME); 3971 hclge_comm_cmd_reuse_desc(&desc, true); 3972 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3973 3974 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3975 } 3976 3977 void hclge_report_hw_error(struct hclge_dev *hdev, 3978 enum hnae3_hw_error_type type) 3979 { 3980 struct hnae3_client *client = hdev->nic_client; 3981 3982 if (!client || !client->ops->process_hw_error || 3983 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3984 return; 3985 3986 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3987 } 3988 3989 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3990 { 3991 u32 reg_val; 3992 3993 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3994 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3995 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3996 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3997 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3998 } 3999 4000 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 4001 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 4002 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4003 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4004 } 4005 } 4006 4007 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4008 { 4009 struct hclge_desc desc; 4010 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4011 int ret; 4012 4013 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4014 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4015 req->fun_reset_vfid = func_id; 4016 4017 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4018 if (ret) 4019 dev_err(&hdev->pdev->dev, 4020 "send function reset cmd fail, status =%d\n", ret); 4021 4022 return ret; 4023 } 4024 4025 static void hclge_do_reset(struct hclge_dev *hdev) 4026 { 4027 struct hnae3_handle *handle = &hdev->vport[0].nic; 4028 struct pci_dev *pdev = hdev->pdev; 4029 u32 val; 4030 4031 if (hclge_get_hw_reset_stat(handle)) { 4032 dev_info(&pdev->dev, "hardware reset not finish\n"); 4033 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4034 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4035 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4036 return; 4037 } 4038 4039 switch (hdev->reset_type) { 4040 case HNAE3_IMP_RESET: 4041 dev_info(&pdev->dev, "IMP reset requested\n"); 4042 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4043 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4044 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4045 break; 4046 case HNAE3_GLOBAL_RESET: 4047 dev_info(&pdev->dev, "global reset requested\n"); 4048 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4049 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4050 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4051 break; 4052 case HNAE3_FUNC_RESET: 4053 dev_info(&pdev->dev, "PF reset requested\n"); 4054 /* schedule again to check later */ 4055 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4056 hclge_reset_task_schedule(hdev); 4057 break; 4058 default: 4059 dev_warn(&pdev->dev, 4060 "unsupported reset type: %d\n", hdev->reset_type); 4061 break; 4062 } 4063 } 4064 4065 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4066 unsigned long *addr) 4067 { 4068 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4069 struct hclge_dev *hdev = ae_dev->priv; 4070 4071 /* return the highest priority reset level amongst all */ 4072 if (test_bit(HNAE3_IMP_RESET, addr)) { 4073 rst_level = HNAE3_IMP_RESET; 4074 clear_bit(HNAE3_IMP_RESET, addr); 4075 clear_bit(HNAE3_GLOBAL_RESET, addr); 4076 clear_bit(HNAE3_FUNC_RESET, addr); 4077 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4078 rst_level = HNAE3_GLOBAL_RESET; 4079 clear_bit(HNAE3_GLOBAL_RESET, addr); 4080 clear_bit(HNAE3_FUNC_RESET, addr); 4081 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4082 rst_level = HNAE3_FUNC_RESET; 4083 clear_bit(HNAE3_FUNC_RESET, addr); 4084 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4085 rst_level = HNAE3_FLR_RESET; 4086 clear_bit(HNAE3_FLR_RESET, addr); 4087 } 4088 4089 if (hdev->reset_type != HNAE3_NONE_RESET && 4090 rst_level < hdev->reset_type) 4091 return HNAE3_NONE_RESET; 4092 4093 return rst_level; 4094 } 4095 4096 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4097 { 4098 u32 clearval = 0; 4099 4100 switch (hdev->reset_type) { 4101 case HNAE3_IMP_RESET: 4102 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4103 break; 4104 case HNAE3_GLOBAL_RESET: 4105 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4106 break; 4107 default: 4108 break; 4109 } 4110 4111 if (!clearval) 4112 return; 4113 4114 /* For revision 0x20, the reset interrupt source 4115 * can only be cleared after hardware reset done 4116 */ 4117 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4118 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4119 clearval); 4120 4121 hclge_enable_vector(&hdev->misc_vector, true); 4122 } 4123 4124 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4125 { 4126 u32 reg_val; 4127 4128 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4129 if (enable) 4130 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4131 else 4132 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4133 4134 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4135 } 4136 4137 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4138 { 4139 int ret; 4140 4141 ret = hclge_set_all_vf_rst(hdev, true); 4142 if (ret) 4143 return ret; 4144 4145 hclge_func_reset_sync_vf(hdev); 4146 4147 return 0; 4148 } 4149 4150 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4151 { 4152 u32 reg_val; 4153 int ret = 0; 4154 4155 switch (hdev->reset_type) { 4156 case HNAE3_FUNC_RESET: 4157 ret = hclge_func_reset_notify_vf(hdev); 4158 if (ret) 4159 return ret; 4160 4161 ret = hclge_func_reset_cmd(hdev, 0); 4162 if (ret) { 4163 dev_err(&hdev->pdev->dev, 4164 "asserting function reset fail %d!\n", ret); 4165 return ret; 4166 } 4167 4168 /* After performaning pf reset, it is not necessary to do the 4169 * mailbox handling or send any command to firmware, because 4170 * any mailbox handling or command to firmware is only valid 4171 * after hclge_comm_cmd_init is called. 4172 */ 4173 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4174 hdev->rst_stats.pf_rst_cnt++; 4175 break; 4176 case HNAE3_FLR_RESET: 4177 ret = hclge_func_reset_notify_vf(hdev); 4178 if (ret) 4179 return ret; 4180 break; 4181 case HNAE3_IMP_RESET: 4182 hclge_handle_imp_error(hdev); 4183 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4184 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4185 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4186 break; 4187 default: 4188 break; 4189 } 4190 4191 /* inform hardware that preparatory work is done */ 4192 msleep(HCLGE_RESET_SYNC_TIME); 4193 hclge_reset_handshake(hdev, true); 4194 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4195 4196 return ret; 4197 } 4198 4199 static void hclge_show_rst_info(struct hclge_dev *hdev) 4200 { 4201 char *buf; 4202 4203 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4204 if (!buf) 4205 return; 4206 4207 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4208 4209 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4210 4211 kfree(buf); 4212 } 4213 4214 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4215 { 4216 #define MAX_RESET_FAIL_CNT 5 4217 4218 if (hdev->reset_pending) { 4219 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4220 hdev->reset_pending); 4221 return true; 4222 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4223 HCLGE_RESET_INT_M) { 4224 dev_info(&hdev->pdev->dev, 4225 "reset failed because new reset interrupt\n"); 4226 hclge_clear_reset_cause(hdev); 4227 return false; 4228 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4229 hdev->rst_stats.reset_fail_cnt++; 4230 set_bit(hdev->reset_type, &hdev->reset_pending); 4231 dev_info(&hdev->pdev->dev, 4232 "re-schedule reset task(%u)\n", 4233 hdev->rst_stats.reset_fail_cnt); 4234 return true; 4235 } 4236 4237 hclge_clear_reset_cause(hdev); 4238 4239 /* recover the handshake status when reset fail */ 4240 hclge_reset_handshake(hdev, true); 4241 4242 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4243 4244 hclge_show_rst_info(hdev); 4245 4246 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4247 4248 return false; 4249 } 4250 4251 static void hclge_update_reset_level(struct hclge_dev *hdev) 4252 { 4253 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4254 enum hnae3_reset_type reset_level; 4255 4256 /* reset request will not be set during reset, so clear 4257 * pending reset request to avoid unnecessary reset 4258 * caused by the same reason. 4259 */ 4260 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4261 4262 /* if default_reset_request has a higher level reset request, 4263 * it should be handled as soon as possible. since some errors 4264 * need this kind of reset to fix. 4265 */ 4266 reset_level = hclge_get_reset_level(ae_dev, 4267 &hdev->default_reset_request); 4268 if (reset_level != HNAE3_NONE_RESET) 4269 set_bit(reset_level, &hdev->reset_request); 4270 } 4271 4272 static int hclge_set_rst_done(struct hclge_dev *hdev) 4273 { 4274 struct hclge_pf_rst_done_cmd *req; 4275 struct hclge_desc desc; 4276 int ret; 4277 4278 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4279 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4280 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4281 4282 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4283 /* To be compatible with the old firmware, which does not support 4284 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4285 * return success 4286 */ 4287 if (ret == -EOPNOTSUPP) { 4288 dev_warn(&hdev->pdev->dev, 4289 "current firmware does not support command(0x%x)!\n", 4290 HCLGE_OPC_PF_RST_DONE); 4291 return 0; 4292 } else if (ret) { 4293 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4294 ret); 4295 } 4296 4297 return ret; 4298 } 4299 4300 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4301 { 4302 int ret = 0; 4303 4304 switch (hdev->reset_type) { 4305 case HNAE3_FUNC_RESET: 4306 case HNAE3_FLR_RESET: 4307 ret = hclge_set_all_vf_rst(hdev, false); 4308 break; 4309 case HNAE3_GLOBAL_RESET: 4310 case HNAE3_IMP_RESET: 4311 ret = hclge_set_rst_done(hdev); 4312 break; 4313 default: 4314 break; 4315 } 4316 4317 /* clear up the handshake status after re-initialize done */ 4318 hclge_reset_handshake(hdev, false); 4319 4320 return ret; 4321 } 4322 4323 static int hclge_reset_stack(struct hclge_dev *hdev) 4324 { 4325 int ret; 4326 4327 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4328 if (ret) 4329 return ret; 4330 4331 ret = hclge_reset_ae_dev(hdev->ae_dev); 4332 if (ret) 4333 return ret; 4334 4335 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4336 } 4337 4338 static int hclge_reset_prepare(struct hclge_dev *hdev) 4339 { 4340 int ret; 4341 4342 hdev->rst_stats.reset_cnt++; 4343 /* perform reset of the stack & ae device for a client */ 4344 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4345 if (ret) 4346 return ret; 4347 4348 rtnl_lock(); 4349 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4350 rtnl_unlock(); 4351 if (ret) 4352 return ret; 4353 4354 return hclge_reset_prepare_wait(hdev); 4355 } 4356 4357 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4358 { 4359 int ret; 4360 4361 hdev->rst_stats.hw_reset_done_cnt++; 4362 4363 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4364 if (ret) 4365 return ret; 4366 4367 rtnl_lock(); 4368 ret = hclge_reset_stack(hdev); 4369 rtnl_unlock(); 4370 if (ret) 4371 return ret; 4372 4373 hclge_clear_reset_cause(hdev); 4374 4375 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4376 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4377 * times 4378 */ 4379 if (ret && 4380 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4381 return ret; 4382 4383 ret = hclge_reset_prepare_up(hdev); 4384 if (ret) 4385 return ret; 4386 4387 rtnl_lock(); 4388 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4389 rtnl_unlock(); 4390 if (ret) 4391 return ret; 4392 4393 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4394 if (ret) 4395 return ret; 4396 4397 hdev->last_reset_time = jiffies; 4398 hdev->rst_stats.reset_fail_cnt = 0; 4399 hdev->rst_stats.reset_done_cnt++; 4400 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4401 4402 hclge_update_reset_level(hdev); 4403 4404 return 0; 4405 } 4406 4407 static void hclge_reset(struct hclge_dev *hdev) 4408 { 4409 if (hclge_reset_prepare(hdev)) 4410 goto err_reset; 4411 4412 if (hclge_reset_wait(hdev)) 4413 goto err_reset; 4414 4415 if (hclge_reset_rebuild(hdev)) 4416 goto err_reset; 4417 4418 return; 4419 4420 err_reset: 4421 if (hclge_reset_err_handle(hdev)) 4422 hclge_reset_task_schedule(hdev); 4423 } 4424 4425 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4426 { 4427 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4428 struct hclge_dev *hdev = ae_dev->priv; 4429 4430 /* We might end up getting called broadly because of 2 below cases: 4431 * 1. Recoverable error was conveyed through APEI and only way to bring 4432 * normalcy is to reset. 4433 * 2. A new reset request from the stack due to timeout 4434 * 4435 * check if this is a new reset request and we are not here just because 4436 * last reset attempt did not succeed and watchdog hit us again. We will 4437 * know this if last reset request did not occur very recently (watchdog 4438 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4439 * In case of new request we reset the "reset level" to PF reset. 4440 * And if it is a repeat reset request of the most recent one then we 4441 * want to make sure we throttle the reset request. Therefore, we will 4442 * not allow it again before 3*HZ times. 4443 */ 4444 4445 if (time_before(jiffies, (hdev->last_reset_time + 4446 HCLGE_RESET_INTERVAL))) { 4447 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4448 return; 4449 } 4450 4451 if (hdev->default_reset_request) { 4452 hdev->reset_level = 4453 hclge_get_reset_level(ae_dev, 4454 &hdev->default_reset_request); 4455 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4456 hdev->reset_level = HNAE3_FUNC_RESET; 4457 } 4458 4459 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4460 hdev->reset_level); 4461 4462 /* request reset & schedule reset task */ 4463 set_bit(hdev->reset_level, &hdev->reset_request); 4464 hclge_reset_task_schedule(hdev); 4465 4466 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4467 hdev->reset_level++; 4468 } 4469 4470 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4471 enum hnae3_reset_type rst_type) 4472 { 4473 struct hclge_dev *hdev = ae_dev->priv; 4474 4475 set_bit(rst_type, &hdev->default_reset_request); 4476 } 4477 4478 static void hclge_reset_timer(struct timer_list *t) 4479 { 4480 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4481 4482 /* if default_reset_request has no value, it means that this reset 4483 * request has already be handled, so just return here 4484 */ 4485 if (!hdev->default_reset_request) 4486 return; 4487 4488 dev_info(&hdev->pdev->dev, 4489 "triggering reset in reset timer\n"); 4490 hclge_reset_event(hdev->pdev, NULL); 4491 } 4492 4493 static void hclge_reset_subtask(struct hclge_dev *hdev) 4494 { 4495 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4496 4497 /* check if there is any ongoing reset in the hardware. This status can 4498 * be checked from reset_pending. If there is then, we need to wait for 4499 * hardware to complete reset. 4500 * a. If we are able to figure out in reasonable time that hardware 4501 * has fully resetted then, we can proceed with driver, client 4502 * reset. 4503 * b. else, we can come back later to check this status so re-sched 4504 * now. 4505 */ 4506 hdev->last_reset_time = jiffies; 4507 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4508 if (hdev->reset_type != HNAE3_NONE_RESET) 4509 hclge_reset(hdev); 4510 4511 /* check if we got any *new* reset requests to be honored */ 4512 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4513 if (hdev->reset_type != HNAE3_NONE_RESET) 4514 hclge_do_reset(hdev); 4515 4516 hdev->reset_type = HNAE3_NONE_RESET; 4517 } 4518 4519 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4520 { 4521 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4522 enum hnae3_reset_type reset_type; 4523 4524 if (ae_dev->hw_err_reset_req) { 4525 reset_type = hclge_get_reset_level(ae_dev, 4526 &ae_dev->hw_err_reset_req); 4527 hclge_set_def_reset_request(ae_dev, reset_type); 4528 } 4529 4530 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4531 ae_dev->ops->reset_event(hdev->pdev, NULL); 4532 4533 /* enable interrupt after error handling complete */ 4534 hclge_enable_vector(&hdev->misc_vector, true); 4535 } 4536 4537 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4538 { 4539 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4540 4541 ae_dev->hw_err_reset_req = 0; 4542 4543 if (hclge_find_error_source(hdev)) { 4544 hclge_handle_error_info_log(ae_dev); 4545 hclge_handle_mac_tnl(hdev); 4546 hclge_handle_vf_queue_err_ras(hdev); 4547 } 4548 4549 hclge_handle_err_reset_request(hdev); 4550 } 4551 4552 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4553 { 4554 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4555 struct device *dev = &hdev->pdev->dev; 4556 u32 msix_sts_reg; 4557 4558 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4559 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4560 if (hclge_handle_hw_msix_error 4561 (hdev, &hdev->default_reset_request)) 4562 dev_info(dev, "received msix interrupt 0x%x\n", 4563 msix_sts_reg); 4564 } 4565 4566 hclge_handle_hw_ras_error(ae_dev); 4567 4568 hclge_handle_err_reset_request(hdev); 4569 } 4570 4571 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4572 { 4573 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4574 return; 4575 4576 if (hnae3_dev_ras_imp_supported(hdev)) 4577 hclge_handle_err_recovery(hdev); 4578 else 4579 hclge_misc_err_recovery(hdev); 4580 } 4581 4582 static void hclge_reset_service_task(struct hclge_dev *hdev) 4583 { 4584 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4585 return; 4586 4587 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4588 HCLGE_RESET_SCHED_TIMEOUT)) 4589 dev_warn(&hdev->pdev->dev, 4590 "reset service task is scheduled after %ums on cpu%u!\n", 4591 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4592 smp_processor_id()); 4593 4594 down(&hdev->reset_sem); 4595 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4596 4597 hclge_reset_subtask(hdev); 4598 4599 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4600 up(&hdev->reset_sem); 4601 } 4602 4603 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4604 { 4605 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4606 4607 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4608 int i; 4609 4610 /* start from vport 1 for PF is always alive */ 4611 for (i = 1; i < hdev->num_alloc_vport; i++) { 4612 struct hclge_vport *vport = &hdev->vport[i]; 4613 4614 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4615 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4616 continue; 4617 if (time_after(jiffies, vport->last_active_jiffies + 4618 alive_time)) { 4619 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4620 dev_warn(&hdev->pdev->dev, 4621 "VF %u heartbeat timeout\n", 4622 i - HCLGE_VF_VPORT_START_NUM); 4623 } 4624 } 4625 } 4626 4627 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4628 { 4629 unsigned long delta = round_jiffies_relative(HZ); 4630 4631 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4632 return; 4633 4634 /* Always handle the link updating to make sure link state is 4635 * updated when it is triggered by mbx. 4636 */ 4637 hclge_update_link_status(hdev); 4638 hclge_sync_mac_table(hdev); 4639 hclge_sync_promisc_mode(hdev); 4640 hclge_sync_fd_table(hdev); 4641 4642 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4643 delta = jiffies - hdev->last_serv_processed; 4644 4645 if (delta < round_jiffies_relative(HZ)) { 4646 delta = round_jiffies_relative(HZ) - delta; 4647 goto out; 4648 } 4649 } 4650 4651 hdev->serv_processed_cnt++; 4652 hclge_update_vport_alive(hdev); 4653 4654 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4655 hdev->last_serv_processed = jiffies; 4656 goto out; 4657 } 4658 4659 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4660 hclge_update_stats_for_all(hdev); 4661 4662 hclge_update_port_info(hdev); 4663 hclge_sync_vlan_filter(hdev); 4664 4665 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4666 hclge_rfs_filter_expire(hdev); 4667 4668 hdev->last_serv_processed = jiffies; 4669 4670 out: 4671 hclge_task_schedule(hdev, delta); 4672 } 4673 4674 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4675 { 4676 unsigned long flags; 4677 4678 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4679 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4680 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4681 return; 4682 4683 /* to prevent concurrence with the irq handler */ 4684 spin_lock_irqsave(&hdev->ptp->lock, flags); 4685 4686 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4687 * handler may handle it just before spin_lock_irqsave(). 4688 */ 4689 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4690 hclge_ptp_clean_tx_hwts(hdev); 4691 4692 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4693 } 4694 4695 static void hclge_service_task(struct work_struct *work) 4696 { 4697 struct hclge_dev *hdev = 4698 container_of(work, struct hclge_dev, service_task.work); 4699 4700 hclge_errhand_service_task(hdev); 4701 hclge_reset_service_task(hdev); 4702 hclge_ptp_service_task(hdev); 4703 hclge_mailbox_service_task(hdev); 4704 hclge_periodic_service_task(hdev); 4705 4706 /* Handle error recovery, reset and mbx again in case periodical task 4707 * delays the handling by calling hclge_task_schedule() in 4708 * hclge_periodic_service_task(). 4709 */ 4710 hclge_errhand_service_task(hdev); 4711 hclge_reset_service_task(hdev); 4712 hclge_mailbox_service_task(hdev); 4713 } 4714 4715 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4716 { 4717 /* VF handle has no client */ 4718 if (!handle->client) 4719 return container_of(handle, struct hclge_vport, nic); 4720 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4721 return container_of(handle, struct hclge_vport, roce); 4722 else 4723 return container_of(handle, struct hclge_vport, nic); 4724 } 4725 4726 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4727 struct hnae3_vector_info *vector_info) 4728 { 4729 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4730 4731 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4732 4733 /* need an extend offset to config vector >= 64 */ 4734 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4735 vector_info->io_addr = hdev->hw.hw.io_base + 4736 HCLGE_VECTOR_REG_BASE + 4737 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4738 else 4739 vector_info->io_addr = hdev->hw.hw.io_base + 4740 HCLGE_VECTOR_EXT_REG_BASE + 4741 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4742 HCLGE_VECTOR_REG_OFFSET_H + 4743 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4744 HCLGE_VECTOR_REG_OFFSET; 4745 4746 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4747 hdev->vector_irq[idx] = vector_info->vector; 4748 } 4749 4750 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4751 struct hnae3_vector_info *vector_info) 4752 { 4753 struct hclge_vport *vport = hclge_get_vport(handle); 4754 struct hnae3_vector_info *vector = vector_info; 4755 struct hclge_dev *hdev = vport->back; 4756 int alloc = 0; 4757 u16 i = 0; 4758 u16 j; 4759 4760 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4761 vector_num = min(hdev->num_msi_left, vector_num); 4762 4763 for (j = 0; j < vector_num; j++) { 4764 while (++i < hdev->num_nic_msi) { 4765 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4766 hclge_get_vector_info(hdev, i, vector); 4767 vector++; 4768 alloc++; 4769 4770 break; 4771 } 4772 } 4773 } 4774 hdev->num_msi_left -= alloc; 4775 hdev->num_msi_used += alloc; 4776 4777 return alloc; 4778 } 4779 4780 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4781 { 4782 int i; 4783 4784 for (i = 0; i < hdev->num_msi; i++) 4785 if (vector == hdev->vector_irq[i]) 4786 return i; 4787 4788 return -EINVAL; 4789 } 4790 4791 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4792 { 4793 struct hclge_vport *vport = hclge_get_vport(handle); 4794 struct hclge_dev *hdev = vport->back; 4795 int vector_id; 4796 4797 vector_id = hclge_get_vector_index(hdev, vector); 4798 if (vector_id < 0) { 4799 dev_err(&hdev->pdev->dev, 4800 "Get vector index fail. vector = %d\n", vector); 4801 return vector_id; 4802 } 4803 4804 hclge_free_vector(hdev, vector_id); 4805 4806 return 0; 4807 } 4808 4809 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4810 u8 *key, u8 *hfunc) 4811 { 4812 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4813 struct hclge_vport *vport = hclge_get_vport(handle); 4814 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4815 4816 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4817 4818 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4819 ae_dev->dev_specs.rss_ind_tbl_size); 4820 4821 return 0; 4822 } 4823 4824 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4825 const u8 *key, const u8 hfunc) 4826 { 4827 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4828 struct hclge_vport *vport = hclge_get_vport(handle); 4829 struct hclge_dev *hdev = vport->back; 4830 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4831 int ret, i; 4832 4833 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4834 if (ret) { 4835 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4836 return ret; 4837 } 4838 4839 /* Update the shadow RSS table with user specified qids */ 4840 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4841 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4842 4843 /* Update the hardware */ 4844 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4845 rss_cfg->rss_indirection_tbl); 4846 } 4847 4848 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4849 struct ethtool_rxnfc *nfc) 4850 { 4851 struct hclge_vport *vport = hclge_get_vport(handle); 4852 struct hclge_dev *hdev = vport->back; 4853 int ret; 4854 4855 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4856 &hdev->rss_cfg, nfc); 4857 if (ret) { 4858 dev_err(&hdev->pdev->dev, 4859 "failed to set rss tuple, ret = %d.\n", ret); 4860 return ret; 4861 } 4862 4863 return 0; 4864 } 4865 4866 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4867 struct ethtool_rxnfc *nfc) 4868 { 4869 struct hclge_vport *vport = hclge_get_vport(handle); 4870 u8 tuple_sets; 4871 int ret; 4872 4873 nfc->data = 0; 4874 4875 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4876 &tuple_sets); 4877 if (ret || !tuple_sets) 4878 return ret; 4879 4880 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4881 4882 return 0; 4883 } 4884 4885 static int hclge_get_tc_size(struct hnae3_handle *handle) 4886 { 4887 struct hclge_vport *vport = hclge_get_vport(handle); 4888 struct hclge_dev *hdev = vport->back; 4889 4890 return hdev->pf_rss_size_max; 4891 } 4892 4893 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4894 { 4895 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4896 struct hclge_vport *vport = hdev->vport; 4897 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4898 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4899 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4900 struct hnae3_tc_info *tc_info; 4901 u16 roundup_size; 4902 u16 rss_size; 4903 int i; 4904 4905 tc_info = &vport->nic.kinfo.tc_info; 4906 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4907 rss_size = tc_info->tqp_count[i]; 4908 tc_valid[i] = 0; 4909 4910 if (!(hdev->hw_tc_map & BIT(i))) 4911 continue; 4912 4913 /* tc_size set to hardware is the log2 of roundup power of two 4914 * of rss_size, the acutal queue size is limited by indirection 4915 * table. 4916 */ 4917 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4918 rss_size == 0) { 4919 dev_err(&hdev->pdev->dev, 4920 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4921 rss_size); 4922 return -EINVAL; 4923 } 4924 4925 roundup_size = roundup_pow_of_two(rss_size); 4926 roundup_size = ilog2(roundup_size); 4927 4928 tc_valid[i] = 1; 4929 tc_size[i] = roundup_size; 4930 tc_offset[i] = tc_info->tqp_offset[i]; 4931 } 4932 4933 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4934 tc_size); 4935 } 4936 4937 int hclge_rss_init_hw(struct hclge_dev *hdev) 4938 { 4939 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4940 u8 *key = hdev->rss_cfg.rss_hash_key; 4941 u8 hfunc = hdev->rss_cfg.rss_algo; 4942 int ret; 4943 4944 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4945 rss_indir); 4946 if (ret) 4947 return ret; 4948 4949 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4950 if (ret) 4951 return ret; 4952 4953 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4954 if (ret) 4955 return ret; 4956 4957 return hclge_init_rss_tc_mode(hdev); 4958 } 4959 4960 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4961 int vector_id, bool en, 4962 struct hnae3_ring_chain_node *ring_chain) 4963 { 4964 struct hclge_dev *hdev = vport->back; 4965 struct hnae3_ring_chain_node *node; 4966 struct hclge_desc desc; 4967 struct hclge_ctrl_vector_chain_cmd *req = 4968 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4969 enum hclge_comm_cmd_status status; 4970 enum hclge_opcode_type op; 4971 u16 tqp_type_and_id; 4972 int i; 4973 4974 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4975 hclge_cmd_setup_basic_desc(&desc, op, false); 4976 req->int_vector_id_l = hnae3_get_field(vector_id, 4977 HCLGE_VECTOR_ID_L_M, 4978 HCLGE_VECTOR_ID_L_S); 4979 req->int_vector_id_h = hnae3_get_field(vector_id, 4980 HCLGE_VECTOR_ID_H_M, 4981 HCLGE_VECTOR_ID_H_S); 4982 4983 i = 0; 4984 for (node = ring_chain; node; node = node->next) { 4985 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4986 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4987 HCLGE_INT_TYPE_S, 4988 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4989 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4990 HCLGE_TQP_ID_S, node->tqp_index); 4991 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4992 HCLGE_INT_GL_IDX_S, 4993 hnae3_get_field(node->int_gl_idx, 4994 HNAE3_RING_GL_IDX_M, 4995 HNAE3_RING_GL_IDX_S)); 4996 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4997 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4998 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4999 req->vfid = vport->vport_id; 5000 5001 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5002 if (status) { 5003 dev_err(&hdev->pdev->dev, 5004 "Map TQP fail, status is %d.\n", 5005 status); 5006 return -EIO; 5007 } 5008 i = 0; 5009 5010 hclge_cmd_setup_basic_desc(&desc, 5011 op, 5012 false); 5013 req->int_vector_id_l = 5014 hnae3_get_field(vector_id, 5015 HCLGE_VECTOR_ID_L_M, 5016 HCLGE_VECTOR_ID_L_S); 5017 req->int_vector_id_h = 5018 hnae3_get_field(vector_id, 5019 HCLGE_VECTOR_ID_H_M, 5020 HCLGE_VECTOR_ID_H_S); 5021 } 5022 } 5023 5024 if (i > 0) { 5025 req->int_cause_num = i; 5026 req->vfid = vport->vport_id; 5027 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5028 if (status) { 5029 dev_err(&hdev->pdev->dev, 5030 "Map TQP fail, status is %d.\n", status); 5031 return -EIO; 5032 } 5033 } 5034 5035 return 0; 5036 } 5037 5038 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5039 struct hnae3_ring_chain_node *ring_chain) 5040 { 5041 struct hclge_vport *vport = hclge_get_vport(handle); 5042 struct hclge_dev *hdev = vport->back; 5043 int vector_id; 5044 5045 vector_id = hclge_get_vector_index(hdev, vector); 5046 if (vector_id < 0) { 5047 dev_err(&hdev->pdev->dev, 5048 "failed to get vector index. vector=%d\n", vector); 5049 return vector_id; 5050 } 5051 5052 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5053 } 5054 5055 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5056 struct hnae3_ring_chain_node *ring_chain) 5057 { 5058 struct hclge_vport *vport = hclge_get_vport(handle); 5059 struct hclge_dev *hdev = vport->back; 5060 int vector_id, ret; 5061 5062 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5063 return 0; 5064 5065 vector_id = hclge_get_vector_index(hdev, vector); 5066 if (vector_id < 0) { 5067 dev_err(&handle->pdev->dev, 5068 "Get vector index fail. ret =%d\n", vector_id); 5069 return vector_id; 5070 } 5071 5072 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5073 if (ret) 5074 dev_err(&handle->pdev->dev, 5075 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5076 vector_id, ret); 5077 5078 return ret; 5079 } 5080 5081 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5082 bool en_uc, bool en_mc, bool en_bc) 5083 { 5084 struct hclge_vport *vport = &hdev->vport[vf_id]; 5085 struct hnae3_handle *handle = &vport->nic; 5086 struct hclge_promisc_cfg_cmd *req; 5087 struct hclge_desc desc; 5088 bool uc_tx_en = en_uc; 5089 u8 promisc_cfg = 0; 5090 int ret; 5091 5092 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5093 5094 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5095 req->vf_id = vf_id; 5096 5097 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5098 uc_tx_en = false; 5099 5100 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5101 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5102 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5103 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5104 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5105 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5106 req->extend_promisc = promisc_cfg; 5107 5108 /* to be compatible with DEVICE_VERSION_V1/2 */ 5109 promisc_cfg = 0; 5110 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5111 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5112 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5113 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5114 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5115 req->promisc = promisc_cfg; 5116 5117 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5118 if (ret) 5119 dev_err(&hdev->pdev->dev, 5120 "failed to set vport %u promisc mode, ret = %d.\n", 5121 vf_id, ret); 5122 5123 return ret; 5124 } 5125 5126 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5127 bool en_mc_pmc, bool en_bc_pmc) 5128 { 5129 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5130 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5131 } 5132 5133 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5134 bool en_mc_pmc) 5135 { 5136 struct hclge_vport *vport = hclge_get_vport(handle); 5137 struct hclge_dev *hdev = vport->back; 5138 bool en_bc_pmc = true; 5139 5140 /* For device whose version below V2, if broadcast promisc enabled, 5141 * vlan filter is always bypassed. So broadcast promisc should be 5142 * disabled until user enable promisc mode 5143 */ 5144 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5145 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5146 5147 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5148 en_bc_pmc); 5149 } 5150 5151 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5152 { 5153 struct hclge_vport *vport = hclge_get_vport(handle); 5154 5155 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5156 } 5157 5158 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5159 { 5160 if (hlist_empty(&hdev->fd_rule_list)) 5161 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5162 } 5163 5164 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5165 { 5166 if (!test_bit(location, hdev->fd_bmap)) { 5167 set_bit(location, hdev->fd_bmap); 5168 hdev->hclge_fd_rule_num++; 5169 } 5170 } 5171 5172 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5173 { 5174 if (test_bit(location, hdev->fd_bmap)) { 5175 clear_bit(location, hdev->fd_bmap); 5176 hdev->hclge_fd_rule_num--; 5177 } 5178 } 5179 5180 static void hclge_fd_free_node(struct hclge_dev *hdev, 5181 struct hclge_fd_rule *rule) 5182 { 5183 hlist_del(&rule->rule_node); 5184 kfree(rule); 5185 hclge_sync_fd_state(hdev); 5186 } 5187 5188 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5189 struct hclge_fd_rule *old_rule, 5190 struct hclge_fd_rule *new_rule, 5191 enum HCLGE_FD_NODE_STATE state) 5192 { 5193 switch (state) { 5194 case HCLGE_FD_TO_ADD: 5195 case HCLGE_FD_ACTIVE: 5196 /* 1) if the new state is TO_ADD, just replace the old rule 5197 * with the same location, no matter its state, because the 5198 * new rule will be configured to the hardware. 5199 * 2) if the new state is ACTIVE, it means the new rule 5200 * has been configured to the hardware, so just replace 5201 * the old rule node with the same location. 5202 * 3) for it doesn't add a new node to the list, so it's 5203 * unnecessary to update the rule number and fd_bmap. 5204 */ 5205 new_rule->rule_node.next = old_rule->rule_node.next; 5206 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5207 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5208 kfree(new_rule); 5209 break; 5210 case HCLGE_FD_DELETED: 5211 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5212 hclge_fd_free_node(hdev, old_rule); 5213 break; 5214 case HCLGE_FD_TO_DEL: 5215 /* if new request is TO_DEL, and old rule is existent 5216 * 1) the state of old rule is TO_DEL, we need do nothing, 5217 * because we delete rule by location, other rule content 5218 * is unncessary. 5219 * 2) the state of old rule is ACTIVE, we need to change its 5220 * state to TO_DEL, so the rule will be deleted when periodic 5221 * task being scheduled. 5222 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5223 * been added to hardware, so we just delete the rule node from 5224 * fd_rule_list directly. 5225 */ 5226 if (old_rule->state == HCLGE_FD_TO_ADD) { 5227 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5228 hclge_fd_free_node(hdev, old_rule); 5229 return; 5230 } 5231 old_rule->state = HCLGE_FD_TO_DEL; 5232 break; 5233 } 5234 } 5235 5236 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5237 u16 location, 5238 struct hclge_fd_rule **parent) 5239 { 5240 struct hclge_fd_rule *rule; 5241 struct hlist_node *node; 5242 5243 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5244 if (rule->location == location) 5245 return rule; 5246 else if (rule->location > location) 5247 return NULL; 5248 /* record the parent node, use to keep the nodes in fd_rule_list 5249 * in ascend order. 5250 */ 5251 *parent = rule; 5252 } 5253 5254 return NULL; 5255 } 5256 5257 /* insert fd rule node in ascend order according to rule->location */ 5258 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5259 struct hclge_fd_rule *rule, 5260 struct hclge_fd_rule *parent) 5261 { 5262 INIT_HLIST_NODE(&rule->rule_node); 5263 5264 if (parent) 5265 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5266 else 5267 hlist_add_head(&rule->rule_node, hlist); 5268 } 5269 5270 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5271 struct hclge_fd_user_def_cfg *cfg) 5272 { 5273 struct hclge_fd_user_def_cfg_cmd *req; 5274 struct hclge_desc desc; 5275 u16 data = 0; 5276 int ret; 5277 5278 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5279 5280 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5281 5282 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5283 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5284 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5285 req->ol2_cfg = cpu_to_le16(data); 5286 5287 data = 0; 5288 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5289 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5290 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5291 req->ol3_cfg = cpu_to_le16(data); 5292 5293 data = 0; 5294 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5295 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5296 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5297 req->ol4_cfg = cpu_to_le16(data); 5298 5299 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5300 if (ret) 5301 dev_err(&hdev->pdev->dev, 5302 "failed to set fd user def data, ret= %d\n", ret); 5303 return ret; 5304 } 5305 5306 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5307 { 5308 int ret; 5309 5310 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5311 return; 5312 5313 if (!locked) 5314 spin_lock_bh(&hdev->fd_rule_lock); 5315 5316 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5317 if (ret) 5318 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5319 5320 if (!locked) 5321 spin_unlock_bh(&hdev->fd_rule_lock); 5322 } 5323 5324 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5325 struct hclge_fd_rule *rule) 5326 { 5327 struct hlist_head *hlist = &hdev->fd_rule_list; 5328 struct hclge_fd_rule *fd_rule, *parent = NULL; 5329 struct hclge_fd_user_def_info *info, *old_info; 5330 struct hclge_fd_user_def_cfg *cfg; 5331 5332 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5333 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5334 return 0; 5335 5336 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5337 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5338 info = &rule->ep.user_def; 5339 5340 if (!cfg->ref_cnt || cfg->offset == info->offset) 5341 return 0; 5342 5343 if (cfg->ref_cnt > 1) 5344 goto error; 5345 5346 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5347 if (fd_rule) { 5348 old_info = &fd_rule->ep.user_def; 5349 if (info->layer == old_info->layer) 5350 return 0; 5351 } 5352 5353 error: 5354 dev_err(&hdev->pdev->dev, 5355 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5356 info->layer + 1); 5357 return -ENOSPC; 5358 } 5359 5360 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5361 struct hclge_fd_rule *rule) 5362 { 5363 struct hclge_fd_user_def_cfg *cfg; 5364 5365 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5366 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5367 return; 5368 5369 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5370 if (!cfg->ref_cnt) { 5371 cfg->offset = rule->ep.user_def.offset; 5372 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5373 } 5374 cfg->ref_cnt++; 5375 } 5376 5377 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5378 struct hclge_fd_rule *rule) 5379 { 5380 struct hclge_fd_user_def_cfg *cfg; 5381 5382 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5383 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5384 return; 5385 5386 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5387 if (!cfg->ref_cnt) 5388 return; 5389 5390 cfg->ref_cnt--; 5391 if (!cfg->ref_cnt) { 5392 cfg->offset = 0; 5393 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5394 } 5395 } 5396 5397 static void hclge_update_fd_list(struct hclge_dev *hdev, 5398 enum HCLGE_FD_NODE_STATE state, u16 location, 5399 struct hclge_fd_rule *new_rule) 5400 { 5401 struct hlist_head *hlist = &hdev->fd_rule_list; 5402 struct hclge_fd_rule *fd_rule, *parent = NULL; 5403 5404 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5405 if (fd_rule) { 5406 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5407 if (state == HCLGE_FD_ACTIVE) 5408 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5409 hclge_sync_fd_user_def_cfg(hdev, true); 5410 5411 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5412 return; 5413 } 5414 5415 /* it's unlikely to fail here, because we have checked the rule 5416 * exist before. 5417 */ 5418 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5419 dev_warn(&hdev->pdev->dev, 5420 "failed to delete fd rule %u, it's inexistent\n", 5421 location); 5422 return; 5423 } 5424 5425 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5426 hclge_sync_fd_user_def_cfg(hdev, true); 5427 5428 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5429 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5430 5431 if (state == HCLGE_FD_TO_ADD) { 5432 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5433 hclge_task_schedule(hdev, 0); 5434 } 5435 } 5436 5437 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5438 { 5439 struct hclge_get_fd_mode_cmd *req; 5440 struct hclge_desc desc; 5441 int ret; 5442 5443 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5444 5445 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5446 5447 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5448 if (ret) { 5449 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5450 return ret; 5451 } 5452 5453 *fd_mode = req->mode; 5454 5455 return ret; 5456 } 5457 5458 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5459 u32 *stage1_entry_num, 5460 u32 *stage2_entry_num, 5461 u16 *stage1_counter_num, 5462 u16 *stage2_counter_num) 5463 { 5464 struct hclge_get_fd_allocation_cmd *req; 5465 struct hclge_desc desc; 5466 int ret; 5467 5468 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5469 5470 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5471 5472 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5473 if (ret) { 5474 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5475 ret); 5476 return ret; 5477 } 5478 5479 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5480 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5481 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5482 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5483 5484 return ret; 5485 } 5486 5487 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5488 enum HCLGE_FD_STAGE stage_num) 5489 { 5490 struct hclge_set_fd_key_config_cmd *req; 5491 struct hclge_fd_key_cfg *stage; 5492 struct hclge_desc desc; 5493 int ret; 5494 5495 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5496 5497 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5498 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5499 req->stage = stage_num; 5500 req->key_select = stage->key_sel; 5501 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5502 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5503 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5504 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5505 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5506 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5507 5508 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5509 if (ret) 5510 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5511 5512 return ret; 5513 } 5514 5515 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5516 { 5517 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5518 5519 spin_lock_bh(&hdev->fd_rule_lock); 5520 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5521 spin_unlock_bh(&hdev->fd_rule_lock); 5522 5523 hclge_fd_set_user_def_cmd(hdev, cfg); 5524 } 5525 5526 static int hclge_init_fd_config(struct hclge_dev *hdev) 5527 { 5528 #define LOW_2_WORDS 0x03 5529 struct hclge_fd_key_cfg *key_cfg; 5530 int ret; 5531 5532 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5533 return 0; 5534 5535 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5536 if (ret) 5537 return ret; 5538 5539 switch (hdev->fd_cfg.fd_mode) { 5540 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5541 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5542 break; 5543 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5544 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5545 break; 5546 default: 5547 dev_err(&hdev->pdev->dev, 5548 "Unsupported flow director mode %u\n", 5549 hdev->fd_cfg.fd_mode); 5550 return -EOPNOTSUPP; 5551 } 5552 5553 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5554 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5555 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5556 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5557 key_cfg->outer_sipv6_word_en = 0; 5558 key_cfg->outer_dipv6_word_en = 0; 5559 5560 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5561 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5562 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5563 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5564 5565 /* If use max 400bit key, we can support tuples for ether type */ 5566 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5567 key_cfg->tuple_active |= 5568 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5569 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5570 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5571 } 5572 5573 /* roce_type is used to filter roce frames 5574 * dst_vport is used to specify the rule 5575 */ 5576 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5577 5578 ret = hclge_get_fd_allocation(hdev, 5579 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5580 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5581 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5582 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5583 if (ret) 5584 return ret; 5585 5586 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5587 } 5588 5589 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5590 int loc, u8 *key, bool is_add) 5591 { 5592 struct hclge_fd_tcam_config_1_cmd *req1; 5593 struct hclge_fd_tcam_config_2_cmd *req2; 5594 struct hclge_fd_tcam_config_3_cmd *req3; 5595 struct hclge_desc desc[3]; 5596 int ret; 5597 5598 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5599 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5600 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5601 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5602 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5603 5604 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5605 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5606 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5607 5608 req1->stage = stage; 5609 req1->xy_sel = sel_x ? 1 : 0; 5610 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5611 req1->index = cpu_to_le32(loc); 5612 req1->entry_vld = sel_x ? is_add : 0; 5613 5614 if (key) { 5615 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5616 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5617 sizeof(req2->tcam_data)); 5618 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5619 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5620 } 5621 5622 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5623 if (ret) 5624 dev_err(&hdev->pdev->dev, 5625 "config tcam key fail, ret=%d\n", 5626 ret); 5627 5628 return ret; 5629 } 5630 5631 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5632 struct hclge_fd_ad_data *action) 5633 { 5634 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5635 struct hclge_fd_ad_config_cmd *req; 5636 struct hclge_desc desc; 5637 u64 ad_data = 0; 5638 int ret; 5639 5640 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5641 5642 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5643 req->index = cpu_to_le32(loc); 5644 req->stage = stage; 5645 5646 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5647 action->write_rule_id_to_bd); 5648 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5649 action->rule_id); 5650 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5651 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5652 action->override_tc); 5653 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5654 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5655 } 5656 ad_data <<= 32; 5657 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5658 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5659 action->forward_to_direct_queue); 5660 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5661 action->queue_id); 5662 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5663 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5664 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5665 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5666 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5667 action->counter_id); 5668 5669 req->ad_data = cpu_to_le64(ad_data); 5670 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5671 if (ret) 5672 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5673 5674 return ret; 5675 } 5676 5677 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5678 struct hclge_fd_rule *rule) 5679 { 5680 int offset, moffset, ip_offset; 5681 enum HCLGE_FD_KEY_OPT key_opt; 5682 u16 tmp_x_s, tmp_y_s; 5683 u32 tmp_x_l, tmp_y_l; 5684 u8 *p = (u8 *)rule; 5685 int i; 5686 5687 if (rule->unused_tuple & BIT(tuple_bit)) 5688 return true; 5689 5690 key_opt = tuple_key_info[tuple_bit].key_opt; 5691 offset = tuple_key_info[tuple_bit].offset; 5692 moffset = tuple_key_info[tuple_bit].moffset; 5693 5694 switch (key_opt) { 5695 case KEY_OPT_U8: 5696 calc_x(*key_x, p[offset], p[moffset]); 5697 calc_y(*key_y, p[offset], p[moffset]); 5698 5699 return true; 5700 case KEY_OPT_LE16: 5701 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5702 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5703 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5704 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5705 5706 return true; 5707 case KEY_OPT_LE32: 5708 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5709 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5710 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5711 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5712 5713 return true; 5714 case KEY_OPT_MAC: 5715 for (i = 0; i < ETH_ALEN; i++) { 5716 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5717 p[moffset + i]); 5718 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5719 p[moffset + i]); 5720 } 5721 5722 return true; 5723 case KEY_OPT_IP: 5724 ip_offset = IPV4_INDEX * sizeof(u32); 5725 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5726 *(u32 *)(&p[moffset + ip_offset])); 5727 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5728 *(u32 *)(&p[moffset + ip_offset])); 5729 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5730 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5731 5732 return true; 5733 default: 5734 return false; 5735 } 5736 } 5737 5738 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5739 u8 vf_id, u8 network_port_id) 5740 { 5741 u32 port_number = 0; 5742 5743 if (port_type == HOST_PORT) { 5744 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5745 pf_id); 5746 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5747 vf_id); 5748 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5749 } else { 5750 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5751 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5752 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5753 } 5754 5755 return port_number; 5756 } 5757 5758 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5759 __le32 *key_x, __le32 *key_y, 5760 struct hclge_fd_rule *rule) 5761 { 5762 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5763 u8 cur_pos = 0, tuple_size, shift_bits; 5764 unsigned int i; 5765 5766 for (i = 0; i < MAX_META_DATA; i++) { 5767 tuple_size = meta_data_key_info[i].key_length; 5768 tuple_bit = key_cfg->meta_data_active & BIT(i); 5769 5770 switch (tuple_bit) { 5771 case BIT(ROCE_TYPE): 5772 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5773 cur_pos += tuple_size; 5774 break; 5775 case BIT(DST_VPORT): 5776 port_number = hclge_get_port_number(HOST_PORT, 0, 5777 rule->vf_id, 0); 5778 hnae3_set_field(meta_data, 5779 GENMASK(cur_pos + tuple_size, cur_pos), 5780 cur_pos, port_number); 5781 cur_pos += tuple_size; 5782 break; 5783 default: 5784 break; 5785 } 5786 } 5787 5788 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5789 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5790 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5791 5792 *key_x = cpu_to_le32(tmp_x << shift_bits); 5793 *key_y = cpu_to_le32(tmp_y << shift_bits); 5794 } 5795 5796 /* A complete key is combined with meta data key and tuple key. 5797 * Meta data key is stored at the MSB region, and tuple key is stored at 5798 * the LSB region, unused bits will be filled 0. 5799 */ 5800 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5801 struct hclge_fd_rule *rule) 5802 { 5803 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5804 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5805 u8 *cur_key_x, *cur_key_y; 5806 u8 meta_data_region; 5807 u8 tuple_size; 5808 int ret; 5809 u32 i; 5810 5811 memset(key_x, 0, sizeof(key_x)); 5812 memset(key_y, 0, sizeof(key_y)); 5813 cur_key_x = key_x; 5814 cur_key_y = key_y; 5815 5816 for (i = 0; i < MAX_TUPLE; i++) { 5817 bool tuple_valid; 5818 5819 tuple_size = tuple_key_info[i].key_length / 8; 5820 if (!(key_cfg->tuple_active & BIT(i))) 5821 continue; 5822 5823 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5824 cur_key_y, rule); 5825 if (tuple_valid) { 5826 cur_key_x += tuple_size; 5827 cur_key_y += tuple_size; 5828 } 5829 } 5830 5831 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5832 MAX_META_DATA_LENGTH / 8; 5833 5834 hclge_fd_convert_meta_data(key_cfg, 5835 (__le32 *)(key_x + meta_data_region), 5836 (__le32 *)(key_y + meta_data_region), 5837 rule); 5838 5839 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5840 true); 5841 if (ret) { 5842 dev_err(&hdev->pdev->dev, 5843 "fd key_y config fail, loc=%u, ret=%d\n", 5844 rule->queue_id, ret); 5845 return ret; 5846 } 5847 5848 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5849 true); 5850 if (ret) 5851 dev_err(&hdev->pdev->dev, 5852 "fd key_x config fail, loc=%u, ret=%d\n", 5853 rule->queue_id, ret); 5854 return ret; 5855 } 5856 5857 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5858 struct hclge_fd_rule *rule) 5859 { 5860 struct hclge_vport *vport = hdev->vport; 5861 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5862 struct hclge_fd_ad_data ad_data; 5863 5864 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5865 ad_data.ad_id = rule->location; 5866 5867 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5868 ad_data.drop_packet = true; 5869 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5870 ad_data.override_tc = true; 5871 ad_data.queue_id = 5872 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5873 ad_data.tc_size = 5874 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5875 } else { 5876 ad_data.forward_to_direct_queue = true; 5877 ad_data.queue_id = rule->queue_id; 5878 } 5879 5880 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5881 ad_data.use_counter = true; 5882 ad_data.counter_id = rule->vf_id % 5883 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5884 } else { 5885 ad_data.use_counter = false; 5886 ad_data.counter_id = 0; 5887 } 5888 5889 ad_data.use_next_stage = false; 5890 ad_data.next_input_key = 0; 5891 5892 ad_data.write_rule_id_to_bd = true; 5893 ad_data.rule_id = rule->location; 5894 5895 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5896 } 5897 5898 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5899 u32 *unused_tuple) 5900 { 5901 if (!spec || !unused_tuple) 5902 return -EINVAL; 5903 5904 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5905 5906 if (!spec->ip4src) 5907 *unused_tuple |= BIT(INNER_SRC_IP); 5908 5909 if (!spec->ip4dst) 5910 *unused_tuple |= BIT(INNER_DST_IP); 5911 5912 if (!spec->psrc) 5913 *unused_tuple |= BIT(INNER_SRC_PORT); 5914 5915 if (!spec->pdst) 5916 *unused_tuple |= BIT(INNER_DST_PORT); 5917 5918 if (!spec->tos) 5919 *unused_tuple |= BIT(INNER_IP_TOS); 5920 5921 return 0; 5922 } 5923 5924 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5925 u32 *unused_tuple) 5926 { 5927 if (!spec || !unused_tuple) 5928 return -EINVAL; 5929 5930 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5931 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5932 5933 if (!spec->ip4src) 5934 *unused_tuple |= BIT(INNER_SRC_IP); 5935 5936 if (!spec->ip4dst) 5937 *unused_tuple |= BIT(INNER_DST_IP); 5938 5939 if (!spec->tos) 5940 *unused_tuple |= BIT(INNER_IP_TOS); 5941 5942 if (!spec->proto) 5943 *unused_tuple |= BIT(INNER_IP_PROTO); 5944 5945 if (spec->l4_4_bytes) 5946 return -EOPNOTSUPP; 5947 5948 if (spec->ip_ver != ETH_RX_NFC_IP4) 5949 return -EOPNOTSUPP; 5950 5951 return 0; 5952 } 5953 5954 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5955 u32 *unused_tuple) 5956 { 5957 if (!spec || !unused_tuple) 5958 return -EINVAL; 5959 5960 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5961 5962 /* check whether src/dst ip address used */ 5963 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5964 *unused_tuple |= BIT(INNER_SRC_IP); 5965 5966 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5967 *unused_tuple |= BIT(INNER_DST_IP); 5968 5969 if (!spec->psrc) 5970 *unused_tuple |= BIT(INNER_SRC_PORT); 5971 5972 if (!spec->pdst) 5973 *unused_tuple |= BIT(INNER_DST_PORT); 5974 5975 if (!spec->tclass) 5976 *unused_tuple |= BIT(INNER_IP_TOS); 5977 5978 return 0; 5979 } 5980 5981 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5982 u32 *unused_tuple) 5983 { 5984 if (!spec || !unused_tuple) 5985 return -EINVAL; 5986 5987 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5988 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5989 5990 /* check whether src/dst ip address used */ 5991 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5992 *unused_tuple |= BIT(INNER_SRC_IP); 5993 5994 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5995 *unused_tuple |= BIT(INNER_DST_IP); 5996 5997 if (!spec->l4_proto) 5998 *unused_tuple |= BIT(INNER_IP_PROTO); 5999 6000 if (!spec->tclass) 6001 *unused_tuple |= BIT(INNER_IP_TOS); 6002 6003 if (spec->l4_4_bytes) 6004 return -EOPNOTSUPP; 6005 6006 return 0; 6007 } 6008 6009 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 6010 { 6011 if (!spec || !unused_tuple) 6012 return -EINVAL; 6013 6014 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 6015 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 6016 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 6017 6018 if (is_zero_ether_addr(spec->h_source)) 6019 *unused_tuple |= BIT(INNER_SRC_MAC); 6020 6021 if (is_zero_ether_addr(spec->h_dest)) 6022 *unused_tuple |= BIT(INNER_DST_MAC); 6023 6024 if (!spec->h_proto) 6025 *unused_tuple |= BIT(INNER_ETH_TYPE); 6026 6027 return 0; 6028 } 6029 6030 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 6031 struct ethtool_rx_flow_spec *fs, 6032 u32 *unused_tuple) 6033 { 6034 if (fs->flow_type & FLOW_EXT) { 6035 if (fs->h_ext.vlan_etype) { 6036 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 6037 return -EOPNOTSUPP; 6038 } 6039 6040 if (!fs->h_ext.vlan_tci) 6041 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6042 6043 if (fs->m_ext.vlan_tci && 6044 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 6045 dev_err(&hdev->pdev->dev, 6046 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6047 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6048 return -EINVAL; 6049 } 6050 } else { 6051 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6052 } 6053 6054 if (fs->flow_type & FLOW_MAC_EXT) { 6055 if (hdev->fd_cfg.fd_mode != 6056 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6057 dev_err(&hdev->pdev->dev, 6058 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6059 return -EOPNOTSUPP; 6060 } 6061 6062 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6063 *unused_tuple |= BIT(INNER_DST_MAC); 6064 else 6065 *unused_tuple &= ~BIT(INNER_DST_MAC); 6066 } 6067 6068 return 0; 6069 } 6070 6071 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6072 struct hclge_fd_user_def_info *info) 6073 { 6074 switch (flow_type) { 6075 case ETHER_FLOW: 6076 info->layer = HCLGE_FD_USER_DEF_L2; 6077 *unused_tuple &= ~BIT(INNER_L2_RSV); 6078 break; 6079 case IP_USER_FLOW: 6080 case IPV6_USER_FLOW: 6081 info->layer = HCLGE_FD_USER_DEF_L3; 6082 *unused_tuple &= ~BIT(INNER_L3_RSV); 6083 break; 6084 case TCP_V4_FLOW: 6085 case UDP_V4_FLOW: 6086 case TCP_V6_FLOW: 6087 case UDP_V6_FLOW: 6088 info->layer = HCLGE_FD_USER_DEF_L4; 6089 *unused_tuple &= ~BIT(INNER_L4_RSV); 6090 break; 6091 default: 6092 return -EOPNOTSUPP; 6093 } 6094 6095 return 0; 6096 } 6097 6098 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6099 { 6100 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6101 } 6102 6103 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6104 struct ethtool_rx_flow_spec *fs, 6105 u32 *unused_tuple, 6106 struct hclge_fd_user_def_info *info) 6107 { 6108 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6109 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6110 u16 data, offset, data_mask, offset_mask; 6111 int ret; 6112 6113 info->layer = HCLGE_FD_USER_DEF_NONE; 6114 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6115 6116 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6117 return 0; 6118 6119 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6120 * for data, and bit32~47 is used for offset. 6121 */ 6122 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6123 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6124 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6125 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6126 6127 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6128 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6129 return -EOPNOTSUPP; 6130 } 6131 6132 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6133 dev_err(&hdev->pdev->dev, 6134 "user-def offset[%u] should be no more than %u\n", 6135 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6136 return -EINVAL; 6137 } 6138 6139 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6140 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6141 return -EINVAL; 6142 } 6143 6144 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6145 if (ret) { 6146 dev_err(&hdev->pdev->dev, 6147 "unsupported flow type for user-def bytes, ret = %d\n", 6148 ret); 6149 return ret; 6150 } 6151 6152 info->data = data; 6153 info->data_mask = data_mask; 6154 info->offset = offset; 6155 6156 return 0; 6157 } 6158 6159 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6160 struct ethtool_rx_flow_spec *fs, 6161 u32 *unused_tuple, 6162 struct hclge_fd_user_def_info *info) 6163 { 6164 u32 flow_type; 6165 int ret; 6166 6167 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6168 dev_err(&hdev->pdev->dev, 6169 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6170 fs->location, 6171 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6172 return -EINVAL; 6173 } 6174 6175 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6176 if (ret) 6177 return ret; 6178 6179 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6180 switch (flow_type) { 6181 case SCTP_V4_FLOW: 6182 case TCP_V4_FLOW: 6183 case UDP_V4_FLOW: 6184 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6185 unused_tuple); 6186 break; 6187 case IP_USER_FLOW: 6188 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6189 unused_tuple); 6190 break; 6191 case SCTP_V6_FLOW: 6192 case TCP_V6_FLOW: 6193 case UDP_V6_FLOW: 6194 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6195 unused_tuple); 6196 break; 6197 case IPV6_USER_FLOW: 6198 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6199 unused_tuple); 6200 break; 6201 case ETHER_FLOW: 6202 if (hdev->fd_cfg.fd_mode != 6203 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6204 dev_err(&hdev->pdev->dev, 6205 "ETHER_FLOW is not supported in current fd mode!\n"); 6206 return -EOPNOTSUPP; 6207 } 6208 6209 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6210 unused_tuple); 6211 break; 6212 default: 6213 dev_err(&hdev->pdev->dev, 6214 "unsupported protocol type, protocol type = %#x\n", 6215 flow_type); 6216 return -EOPNOTSUPP; 6217 } 6218 6219 if (ret) { 6220 dev_err(&hdev->pdev->dev, 6221 "failed to check flow union tuple, ret = %d\n", 6222 ret); 6223 return ret; 6224 } 6225 6226 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6227 } 6228 6229 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6230 struct hclge_fd_rule *rule, u8 ip_proto) 6231 { 6232 rule->tuples.src_ip[IPV4_INDEX] = 6233 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6234 rule->tuples_mask.src_ip[IPV4_INDEX] = 6235 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6236 6237 rule->tuples.dst_ip[IPV4_INDEX] = 6238 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6239 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6240 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6241 6242 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6243 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6244 6245 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6246 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6247 6248 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6249 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6250 6251 rule->tuples.ether_proto = ETH_P_IP; 6252 rule->tuples_mask.ether_proto = 0xFFFF; 6253 6254 rule->tuples.ip_proto = ip_proto; 6255 rule->tuples_mask.ip_proto = 0xFF; 6256 } 6257 6258 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6259 struct hclge_fd_rule *rule) 6260 { 6261 rule->tuples.src_ip[IPV4_INDEX] = 6262 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6263 rule->tuples_mask.src_ip[IPV4_INDEX] = 6264 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6265 6266 rule->tuples.dst_ip[IPV4_INDEX] = 6267 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6268 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6269 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6270 6271 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6272 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6273 6274 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6275 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6276 6277 rule->tuples.ether_proto = ETH_P_IP; 6278 rule->tuples_mask.ether_proto = 0xFFFF; 6279 } 6280 6281 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6282 struct hclge_fd_rule *rule, u8 ip_proto) 6283 { 6284 ipv6_addr_be32_to_cpu(rule->tuples.src_ip, 6285 fs->h_u.tcp_ip6_spec.ip6src); 6286 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, 6287 fs->m_u.tcp_ip6_spec.ip6src); 6288 6289 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, 6290 fs->h_u.tcp_ip6_spec.ip6dst); 6291 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, 6292 fs->m_u.tcp_ip6_spec.ip6dst); 6293 6294 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6295 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6296 6297 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6298 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6299 6300 rule->tuples.ether_proto = ETH_P_IPV6; 6301 rule->tuples_mask.ether_proto = 0xFFFF; 6302 6303 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6304 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6305 6306 rule->tuples.ip_proto = ip_proto; 6307 rule->tuples_mask.ip_proto = 0xFF; 6308 } 6309 6310 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6311 struct hclge_fd_rule *rule) 6312 { 6313 ipv6_addr_be32_to_cpu(rule->tuples.src_ip, 6314 fs->h_u.usr_ip6_spec.ip6src); 6315 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, 6316 fs->m_u.usr_ip6_spec.ip6src); 6317 6318 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, 6319 fs->h_u.usr_ip6_spec.ip6dst); 6320 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, 6321 fs->m_u.usr_ip6_spec.ip6dst); 6322 6323 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6324 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6325 6326 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6327 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6328 6329 rule->tuples.ether_proto = ETH_P_IPV6; 6330 rule->tuples_mask.ether_proto = 0xFFFF; 6331 } 6332 6333 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6334 struct hclge_fd_rule *rule) 6335 { 6336 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6337 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6338 6339 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6340 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6341 6342 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6343 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6344 } 6345 6346 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6347 struct hclge_fd_rule *rule) 6348 { 6349 switch (info->layer) { 6350 case HCLGE_FD_USER_DEF_L2: 6351 rule->tuples.l2_user_def = info->data; 6352 rule->tuples_mask.l2_user_def = info->data_mask; 6353 break; 6354 case HCLGE_FD_USER_DEF_L3: 6355 rule->tuples.l3_user_def = info->data; 6356 rule->tuples_mask.l3_user_def = info->data_mask; 6357 break; 6358 case HCLGE_FD_USER_DEF_L4: 6359 rule->tuples.l4_user_def = (u32)info->data << 16; 6360 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6361 break; 6362 default: 6363 break; 6364 } 6365 6366 rule->ep.user_def = *info; 6367 } 6368 6369 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6370 struct hclge_fd_rule *rule, 6371 struct hclge_fd_user_def_info *info) 6372 { 6373 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6374 6375 switch (flow_type) { 6376 case SCTP_V4_FLOW: 6377 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6378 break; 6379 case TCP_V4_FLOW: 6380 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6381 break; 6382 case UDP_V4_FLOW: 6383 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6384 break; 6385 case IP_USER_FLOW: 6386 hclge_fd_get_ip4_tuple(fs, rule); 6387 break; 6388 case SCTP_V6_FLOW: 6389 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6390 break; 6391 case TCP_V6_FLOW: 6392 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6393 break; 6394 case UDP_V6_FLOW: 6395 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6396 break; 6397 case IPV6_USER_FLOW: 6398 hclge_fd_get_ip6_tuple(fs, rule); 6399 break; 6400 case ETHER_FLOW: 6401 hclge_fd_get_ether_tuple(fs, rule); 6402 break; 6403 default: 6404 return -EOPNOTSUPP; 6405 } 6406 6407 if (fs->flow_type & FLOW_EXT) { 6408 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6409 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6410 hclge_fd_get_user_def_tuple(info, rule); 6411 } 6412 6413 if (fs->flow_type & FLOW_MAC_EXT) { 6414 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6415 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6416 } 6417 6418 return 0; 6419 } 6420 6421 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6422 struct hclge_fd_rule *rule) 6423 { 6424 int ret; 6425 6426 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6427 if (ret) 6428 return ret; 6429 6430 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6431 } 6432 6433 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6434 struct hclge_fd_rule *rule) 6435 { 6436 int ret; 6437 6438 spin_lock_bh(&hdev->fd_rule_lock); 6439 6440 if (hdev->fd_active_type != rule->rule_type && 6441 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6442 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6443 dev_err(&hdev->pdev->dev, 6444 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6445 rule->rule_type, hdev->fd_active_type); 6446 spin_unlock_bh(&hdev->fd_rule_lock); 6447 return -EINVAL; 6448 } 6449 6450 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6451 if (ret) 6452 goto out; 6453 6454 ret = hclge_clear_arfs_rules(hdev); 6455 if (ret) 6456 goto out; 6457 6458 ret = hclge_fd_config_rule(hdev, rule); 6459 if (ret) 6460 goto out; 6461 6462 rule->state = HCLGE_FD_ACTIVE; 6463 hdev->fd_active_type = rule->rule_type; 6464 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6465 6466 out: 6467 spin_unlock_bh(&hdev->fd_rule_lock); 6468 return ret; 6469 } 6470 6471 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6472 { 6473 struct hclge_vport *vport = hclge_get_vport(handle); 6474 struct hclge_dev *hdev = vport->back; 6475 6476 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6477 } 6478 6479 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6480 u16 *vport_id, u8 *action, u16 *queue_id) 6481 { 6482 struct hclge_vport *vport = hdev->vport; 6483 6484 if (ring_cookie == RX_CLS_FLOW_DISC) { 6485 *action = HCLGE_FD_ACTION_DROP_PACKET; 6486 } else { 6487 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6488 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6489 u16 tqps; 6490 6491 /* To keep consistent with user's configuration, minus 1 when 6492 * printing 'vf', because vf id from ethtool is added 1 for vf. 6493 */ 6494 if (vf > hdev->num_req_vfs) { 6495 dev_err(&hdev->pdev->dev, 6496 "Error: vf id (%u) should be less than %u\n", 6497 vf - 1U, hdev->num_req_vfs); 6498 return -EINVAL; 6499 } 6500 6501 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6502 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6503 6504 if (ring >= tqps) { 6505 dev_err(&hdev->pdev->dev, 6506 "Error: queue id (%u) > max tqp num (%u)\n", 6507 ring, tqps - 1U); 6508 return -EINVAL; 6509 } 6510 6511 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6512 *queue_id = ring; 6513 } 6514 6515 return 0; 6516 } 6517 6518 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6519 struct ethtool_rxnfc *cmd) 6520 { 6521 struct hclge_vport *vport = hclge_get_vport(handle); 6522 struct hclge_dev *hdev = vport->back; 6523 struct hclge_fd_user_def_info info; 6524 u16 dst_vport_id = 0, q_index = 0; 6525 struct ethtool_rx_flow_spec *fs; 6526 struct hclge_fd_rule *rule; 6527 u32 unused = 0; 6528 u8 action; 6529 int ret; 6530 6531 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6532 dev_err(&hdev->pdev->dev, 6533 "flow table director is not supported\n"); 6534 return -EOPNOTSUPP; 6535 } 6536 6537 if (!hdev->fd_en) { 6538 dev_err(&hdev->pdev->dev, 6539 "please enable flow director first\n"); 6540 return -EOPNOTSUPP; 6541 } 6542 6543 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6544 6545 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6546 if (ret) 6547 return ret; 6548 6549 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6550 &action, &q_index); 6551 if (ret) 6552 return ret; 6553 6554 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6555 if (!rule) 6556 return -ENOMEM; 6557 6558 ret = hclge_fd_get_tuple(fs, rule, &info); 6559 if (ret) { 6560 kfree(rule); 6561 return ret; 6562 } 6563 6564 rule->flow_type = fs->flow_type; 6565 rule->location = fs->location; 6566 rule->unused_tuple = unused; 6567 rule->vf_id = dst_vport_id; 6568 rule->queue_id = q_index; 6569 rule->action = action; 6570 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6571 6572 ret = hclge_add_fd_entry_common(hdev, rule); 6573 if (ret) 6574 kfree(rule); 6575 6576 return ret; 6577 } 6578 6579 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6580 struct ethtool_rxnfc *cmd) 6581 { 6582 struct hclge_vport *vport = hclge_get_vport(handle); 6583 struct hclge_dev *hdev = vport->back; 6584 struct ethtool_rx_flow_spec *fs; 6585 int ret; 6586 6587 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6588 return -EOPNOTSUPP; 6589 6590 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6591 6592 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6593 return -EINVAL; 6594 6595 spin_lock_bh(&hdev->fd_rule_lock); 6596 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6597 !test_bit(fs->location, hdev->fd_bmap)) { 6598 dev_err(&hdev->pdev->dev, 6599 "Delete fail, rule %u is inexistent\n", fs->location); 6600 spin_unlock_bh(&hdev->fd_rule_lock); 6601 return -ENOENT; 6602 } 6603 6604 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6605 NULL, false); 6606 if (ret) 6607 goto out; 6608 6609 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6610 6611 out: 6612 spin_unlock_bh(&hdev->fd_rule_lock); 6613 return ret; 6614 } 6615 6616 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6617 bool clear_list) 6618 { 6619 struct hclge_fd_rule *rule; 6620 struct hlist_node *node; 6621 u16 location; 6622 6623 spin_lock_bh(&hdev->fd_rule_lock); 6624 6625 for_each_set_bit(location, hdev->fd_bmap, 6626 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6627 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6628 NULL, false); 6629 6630 if (clear_list) { 6631 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6632 rule_node) { 6633 hlist_del(&rule->rule_node); 6634 kfree(rule); 6635 } 6636 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6637 hdev->hclge_fd_rule_num = 0; 6638 bitmap_zero(hdev->fd_bmap, 6639 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6640 } 6641 6642 spin_unlock_bh(&hdev->fd_rule_lock); 6643 } 6644 6645 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6646 { 6647 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6648 return; 6649 6650 hclge_clear_fd_rules_in_list(hdev, true); 6651 hclge_fd_disable_user_def(hdev); 6652 } 6653 6654 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6655 { 6656 struct hclge_vport *vport = hclge_get_vport(handle); 6657 struct hclge_dev *hdev = vport->back; 6658 struct hclge_fd_rule *rule; 6659 struct hlist_node *node; 6660 6661 /* Return ok here, because reset error handling will check this 6662 * return value. If error is returned here, the reset process will 6663 * fail. 6664 */ 6665 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6666 return 0; 6667 6668 /* if fd is disabled, should not restore it when reset */ 6669 if (!hdev->fd_en) 6670 return 0; 6671 6672 spin_lock_bh(&hdev->fd_rule_lock); 6673 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6674 if (rule->state == HCLGE_FD_ACTIVE) 6675 rule->state = HCLGE_FD_TO_ADD; 6676 } 6677 spin_unlock_bh(&hdev->fd_rule_lock); 6678 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6679 6680 return 0; 6681 } 6682 6683 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6684 struct ethtool_rxnfc *cmd) 6685 { 6686 struct hclge_vport *vport = hclge_get_vport(handle); 6687 struct hclge_dev *hdev = vport->back; 6688 6689 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6690 return -EOPNOTSUPP; 6691 6692 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6693 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6694 6695 return 0; 6696 } 6697 6698 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6699 struct ethtool_tcpip4_spec *spec, 6700 struct ethtool_tcpip4_spec *spec_mask) 6701 { 6702 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6703 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6704 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6705 6706 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6707 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6708 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6709 6710 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6711 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6712 0 : cpu_to_be16(rule->tuples_mask.src_port); 6713 6714 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6715 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6716 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6717 6718 spec->tos = rule->tuples.ip_tos; 6719 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6720 0 : rule->tuples_mask.ip_tos; 6721 } 6722 6723 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6724 struct ethtool_usrip4_spec *spec, 6725 struct ethtool_usrip4_spec *spec_mask) 6726 { 6727 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6728 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6729 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6730 6731 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6732 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6733 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6734 6735 spec->tos = rule->tuples.ip_tos; 6736 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6737 0 : rule->tuples_mask.ip_tos; 6738 6739 spec->proto = rule->tuples.ip_proto; 6740 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6741 0 : rule->tuples_mask.ip_proto; 6742 6743 spec->ip_ver = ETH_RX_NFC_IP4; 6744 } 6745 6746 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6747 struct ethtool_tcpip6_spec *spec, 6748 struct ethtool_tcpip6_spec *spec_mask) 6749 { 6750 ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip); 6751 ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip); 6752 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6753 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6754 else 6755 ipv6_addr_cpu_to_be32(spec_mask->ip6src, 6756 rule->tuples_mask.src_ip); 6757 6758 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6759 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6760 else 6761 ipv6_addr_cpu_to_be32(spec_mask->ip6dst, 6762 rule->tuples_mask.dst_ip); 6763 6764 spec->tclass = rule->tuples.ip_tos; 6765 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6766 0 : rule->tuples_mask.ip_tos; 6767 6768 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6769 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6770 0 : cpu_to_be16(rule->tuples_mask.src_port); 6771 6772 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6773 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6774 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6775 } 6776 6777 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6778 struct ethtool_usrip6_spec *spec, 6779 struct ethtool_usrip6_spec *spec_mask) 6780 { 6781 ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip); 6782 ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip); 6783 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6784 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6785 else 6786 ipv6_addr_cpu_to_be32(spec_mask->ip6src, 6787 rule->tuples_mask.src_ip); 6788 6789 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6790 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6791 else 6792 ipv6_addr_cpu_to_be32(spec_mask->ip6dst, 6793 rule->tuples_mask.dst_ip); 6794 6795 spec->tclass = rule->tuples.ip_tos; 6796 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6797 0 : rule->tuples_mask.ip_tos; 6798 6799 spec->l4_proto = rule->tuples.ip_proto; 6800 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6801 0 : rule->tuples_mask.ip_proto; 6802 } 6803 6804 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6805 struct ethhdr *spec, 6806 struct ethhdr *spec_mask) 6807 { 6808 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6809 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6810 6811 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6812 eth_zero_addr(spec_mask->h_source); 6813 else 6814 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6815 6816 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6817 eth_zero_addr(spec_mask->h_dest); 6818 else 6819 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6820 6821 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6822 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6823 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6824 } 6825 6826 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6827 struct hclge_fd_rule *rule) 6828 { 6829 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6830 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6831 fs->h_ext.data[0] = 0; 6832 fs->h_ext.data[1] = 0; 6833 fs->m_ext.data[0] = 0; 6834 fs->m_ext.data[1] = 0; 6835 } else { 6836 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6837 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6838 fs->m_ext.data[0] = 6839 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6840 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6841 } 6842 } 6843 6844 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6845 struct hclge_fd_rule *rule) 6846 { 6847 if (fs->flow_type & FLOW_EXT) { 6848 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6849 fs->m_ext.vlan_tci = 6850 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6851 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6852 6853 hclge_fd_get_user_def_info(fs, rule); 6854 } 6855 6856 if (fs->flow_type & FLOW_MAC_EXT) { 6857 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6858 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6859 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6860 else 6861 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6862 rule->tuples_mask.dst_mac); 6863 } 6864 } 6865 6866 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6867 u16 location) 6868 { 6869 struct hclge_fd_rule *rule = NULL; 6870 struct hlist_node *node2; 6871 6872 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6873 if (rule->location == location) 6874 return rule; 6875 else if (rule->location > location) 6876 return NULL; 6877 } 6878 6879 return NULL; 6880 } 6881 6882 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6883 struct hclge_fd_rule *rule) 6884 { 6885 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6886 fs->ring_cookie = RX_CLS_FLOW_DISC; 6887 } else { 6888 u64 vf_id; 6889 6890 fs->ring_cookie = rule->queue_id; 6891 vf_id = rule->vf_id; 6892 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6893 fs->ring_cookie |= vf_id; 6894 } 6895 } 6896 6897 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6898 struct ethtool_rxnfc *cmd) 6899 { 6900 struct hclge_vport *vport = hclge_get_vport(handle); 6901 struct hclge_fd_rule *rule = NULL; 6902 struct hclge_dev *hdev = vport->back; 6903 struct ethtool_rx_flow_spec *fs; 6904 6905 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6906 return -EOPNOTSUPP; 6907 6908 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6909 6910 spin_lock_bh(&hdev->fd_rule_lock); 6911 6912 rule = hclge_get_fd_rule(hdev, fs->location); 6913 if (!rule) { 6914 spin_unlock_bh(&hdev->fd_rule_lock); 6915 return -ENOENT; 6916 } 6917 6918 fs->flow_type = rule->flow_type; 6919 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6920 case SCTP_V4_FLOW: 6921 case TCP_V4_FLOW: 6922 case UDP_V4_FLOW: 6923 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6924 &fs->m_u.tcp_ip4_spec); 6925 break; 6926 case IP_USER_FLOW: 6927 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6928 &fs->m_u.usr_ip4_spec); 6929 break; 6930 case SCTP_V6_FLOW: 6931 case TCP_V6_FLOW: 6932 case UDP_V6_FLOW: 6933 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6934 &fs->m_u.tcp_ip6_spec); 6935 break; 6936 case IPV6_USER_FLOW: 6937 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6938 &fs->m_u.usr_ip6_spec); 6939 break; 6940 /* The flow type of fd rule has been checked before adding in to rule 6941 * list. As other flow types have been handled, it must be ETHER_FLOW 6942 * for the default case 6943 */ 6944 default: 6945 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6946 &fs->m_u.ether_spec); 6947 break; 6948 } 6949 6950 hclge_fd_get_ext_info(fs, rule); 6951 6952 hclge_fd_get_ring_cookie(fs, rule); 6953 6954 spin_unlock_bh(&hdev->fd_rule_lock); 6955 6956 return 0; 6957 } 6958 6959 static int hclge_get_all_rules(struct hnae3_handle *handle, 6960 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6961 { 6962 struct hclge_vport *vport = hclge_get_vport(handle); 6963 struct hclge_dev *hdev = vport->back; 6964 struct hclge_fd_rule *rule; 6965 struct hlist_node *node2; 6966 int cnt = 0; 6967 6968 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6969 return -EOPNOTSUPP; 6970 6971 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6972 6973 spin_lock_bh(&hdev->fd_rule_lock); 6974 hlist_for_each_entry_safe(rule, node2, 6975 &hdev->fd_rule_list, rule_node) { 6976 if (cnt == cmd->rule_cnt) { 6977 spin_unlock_bh(&hdev->fd_rule_lock); 6978 return -EMSGSIZE; 6979 } 6980 6981 if (rule->state == HCLGE_FD_TO_DEL) 6982 continue; 6983 6984 rule_locs[cnt] = rule->location; 6985 cnt++; 6986 } 6987 6988 spin_unlock_bh(&hdev->fd_rule_lock); 6989 6990 cmd->rule_cnt = cnt; 6991 6992 return 0; 6993 } 6994 6995 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 6996 struct hclge_fd_rule_tuples *tuples) 6997 { 6998 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 6999 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 7000 7001 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 7002 tuples->ip_proto = fkeys->basic.ip_proto; 7003 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 7004 7005 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 7006 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 7007 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 7008 } else { 7009 int i; 7010 7011 for (i = 0; i < IPV6_ADDR_WORDS; i++) { 7012 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 7013 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 7014 } 7015 } 7016 } 7017 7018 /* traverse all rules, check whether an existed rule has the same tuples */ 7019 static struct hclge_fd_rule * 7020 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 7021 const struct hclge_fd_rule_tuples *tuples) 7022 { 7023 struct hclge_fd_rule *rule = NULL; 7024 struct hlist_node *node; 7025 7026 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7027 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 7028 return rule; 7029 } 7030 7031 return NULL; 7032 } 7033 7034 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 7035 struct hclge_fd_rule *rule) 7036 { 7037 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 7038 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 7039 BIT(INNER_SRC_PORT); 7040 rule->action = 0; 7041 rule->vf_id = 0; 7042 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 7043 rule->state = HCLGE_FD_TO_ADD; 7044 if (tuples->ether_proto == ETH_P_IP) { 7045 if (tuples->ip_proto == IPPROTO_TCP) 7046 rule->flow_type = TCP_V4_FLOW; 7047 else 7048 rule->flow_type = UDP_V4_FLOW; 7049 } else { 7050 if (tuples->ip_proto == IPPROTO_TCP) 7051 rule->flow_type = TCP_V6_FLOW; 7052 else 7053 rule->flow_type = UDP_V6_FLOW; 7054 } 7055 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7056 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7057 } 7058 7059 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7060 u16 flow_id, struct flow_keys *fkeys) 7061 { 7062 struct hclge_vport *vport = hclge_get_vport(handle); 7063 struct hclge_fd_rule_tuples new_tuples = {}; 7064 struct hclge_dev *hdev = vport->back; 7065 struct hclge_fd_rule *rule; 7066 u16 bit_id; 7067 7068 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7069 return -EOPNOTSUPP; 7070 7071 /* when there is already fd rule existed add by user, 7072 * arfs should not work 7073 */ 7074 spin_lock_bh(&hdev->fd_rule_lock); 7075 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7076 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7077 spin_unlock_bh(&hdev->fd_rule_lock); 7078 return -EOPNOTSUPP; 7079 } 7080 7081 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7082 7083 /* check is there flow director filter existed for this flow, 7084 * if not, create a new filter for it; 7085 * if filter exist with different queue id, modify the filter; 7086 * if filter exist with same queue id, do nothing 7087 */ 7088 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7089 if (!rule) { 7090 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7091 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7092 spin_unlock_bh(&hdev->fd_rule_lock); 7093 return -ENOSPC; 7094 } 7095 7096 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7097 if (!rule) { 7098 spin_unlock_bh(&hdev->fd_rule_lock); 7099 return -ENOMEM; 7100 } 7101 7102 rule->location = bit_id; 7103 rule->arfs.flow_id = flow_id; 7104 rule->queue_id = queue_id; 7105 hclge_fd_build_arfs_rule(&new_tuples, rule); 7106 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7107 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7108 } else if (rule->queue_id != queue_id) { 7109 rule->queue_id = queue_id; 7110 rule->state = HCLGE_FD_TO_ADD; 7111 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7112 hclge_task_schedule(hdev, 0); 7113 } 7114 spin_unlock_bh(&hdev->fd_rule_lock); 7115 return rule->location; 7116 } 7117 7118 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7119 { 7120 #ifdef CONFIG_RFS_ACCEL 7121 struct hnae3_handle *handle = &hdev->vport[0].nic; 7122 struct hclge_fd_rule *rule; 7123 struct hlist_node *node; 7124 7125 spin_lock_bh(&hdev->fd_rule_lock); 7126 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7127 spin_unlock_bh(&hdev->fd_rule_lock); 7128 return; 7129 } 7130 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7131 if (rule->state != HCLGE_FD_ACTIVE) 7132 continue; 7133 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7134 rule->arfs.flow_id, rule->location)) { 7135 rule->state = HCLGE_FD_TO_DEL; 7136 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7137 } 7138 } 7139 spin_unlock_bh(&hdev->fd_rule_lock); 7140 #endif 7141 } 7142 7143 /* make sure being called after lock up with fd_rule_lock */ 7144 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7145 { 7146 #ifdef CONFIG_RFS_ACCEL 7147 struct hclge_fd_rule *rule; 7148 struct hlist_node *node; 7149 int ret; 7150 7151 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7152 return 0; 7153 7154 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7155 switch (rule->state) { 7156 case HCLGE_FD_TO_DEL: 7157 case HCLGE_FD_ACTIVE: 7158 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7159 rule->location, NULL, false); 7160 if (ret) 7161 return ret; 7162 fallthrough; 7163 case HCLGE_FD_TO_ADD: 7164 hclge_fd_dec_rule_cnt(hdev, rule->location); 7165 hlist_del(&rule->rule_node); 7166 kfree(rule); 7167 break; 7168 default: 7169 break; 7170 } 7171 } 7172 hclge_sync_fd_state(hdev); 7173 7174 #endif 7175 return 0; 7176 } 7177 7178 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7179 struct hclge_fd_rule *rule) 7180 { 7181 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7182 struct flow_match_basic match; 7183 u16 ethtype_key, ethtype_mask; 7184 7185 flow_rule_match_basic(flow, &match); 7186 ethtype_key = ntohs(match.key->n_proto); 7187 ethtype_mask = ntohs(match.mask->n_proto); 7188 7189 if (ethtype_key == ETH_P_ALL) { 7190 ethtype_key = 0; 7191 ethtype_mask = 0; 7192 } 7193 rule->tuples.ether_proto = ethtype_key; 7194 rule->tuples_mask.ether_proto = ethtype_mask; 7195 rule->tuples.ip_proto = match.key->ip_proto; 7196 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7197 } else { 7198 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7199 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7200 } 7201 } 7202 7203 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7204 struct hclge_fd_rule *rule) 7205 { 7206 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7207 struct flow_match_eth_addrs match; 7208 7209 flow_rule_match_eth_addrs(flow, &match); 7210 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7211 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7212 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7213 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7214 } else { 7215 rule->unused_tuple |= BIT(INNER_DST_MAC); 7216 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7217 } 7218 } 7219 7220 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7221 struct hclge_fd_rule *rule) 7222 { 7223 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7224 struct flow_match_vlan match; 7225 7226 flow_rule_match_vlan(flow, &match); 7227 rule->tuples.vlan_tag1 = match.key->vlan_id | 7228 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7229 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7230 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7231 } else { 7232 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7233 } 7234 } 7235 7236 static int hclge_get_cls_key_ip(const struct flow_rule *flow, 7237 struct hclge_fd_rule *rule, 7238 struct netlink_ext_ack *extack) 7239 { 7240 u16 addr_type = 0; 7241 7242 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7243 struct flow_match_control match; 7244 7245 flow_rule_match_control(flow, &match); 7246 addr_type = match.key->addr_type; 7247 7248 if (flow_rule_has_control_flags(match.mask->flags, extack)) 7249 return -EOPNOTSUPP; 7250 } 7251 7252 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7253 struct flow_match_ipv4_addrs match; 7254 7255 flow_rule_match_ipv4_addrs(flow, &match); 7256 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7257 rule->tuples_mask.src_ip[IPV4_INDEX] = 7258 be32_to_cpu(match.mask->src); 7259 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7260 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7261 be32_to_cpu(match.mask->dst); 7262 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7263 struct flow_match_ipv6_addrs match; 7264 7265 flow_rule_match_ipv6_addrs(flow, &match); 7266 ipv6_addr_be32_to_cpu(rule->tuples.src_ip, 7267 match.key->src.s6_addr32); 7268 ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, 7269 match.mask->src.s6_addr32); 7270 ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, 7271 match.key->dst.s6_addr32); 7272 ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, 7273 match.mask->dst.s6_addr32); 7274 } else { 7275 rule->unused_tuple |= BIT(INNER_SRC_IP); 7276 rule->unused_tuple |= BIT(INNER_DST_IP); 7277 } 7278 7279 return 0; 7280 } 7281 7282 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7283 struct hclge_fd_rule *rule) 7284 { 7285 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7286 struct flow_match_ports match; 7287 7288 flow_rule_match_ports(flow, &match); 7289 7290 rule->tuples.src_port = be16_to_cpu(match.key->src); 7291 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7292 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7293 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7294 } else { 7295 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7296 rule->unused_tuple |= BIT(INNER_DST_PORT); 7297 } 7298 } 7299 7300 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7301 struct flow_cls_offload *cls_flower, 7302 struct hclge_fd_rule *rule) 7303 { 7304 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7305 struct netlink_ext_ack *extack = cls_flower->common.extack; 7306 struct flow_dissector *dissector = flow->match.dissector; 7307 int ret; 7308 7309 if (dissector->used_keys & 7310 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 7311 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 7312 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7313 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 7314 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7315 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7316 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) { 7317 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n", 7318 dissector->used_keys); 7319 return -EOPNOTSUPP; 7320 } 7321 7322 hclge_get_cls_key_basic(flow, rule); 7323 hclge_get_cls_key_mac(flow, rule); 7324 hclge_get_cls_key_vlan(flow, rule); 7325 7326 ret = hclge_get_cls_key_ip(flow, rule, extack); 7327 if (ret) 7328 return ret; 7329 7330 hclge_get_cls_key_port(flow, rule); 7331 7332 return 0; 7333 } 7334 7335 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7336 struct flow_cls_offload *cls_flower, int tc) 7337 { 7338 u32 prio = cls_flower->common.prio; 7339 7340 if (tc < 0 || tc > hdev->tc_max) { 7341 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7342 return -EINVAL; 7343 } 7344 7345 if (prio == 0 || 7346 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7347 dev_err(&hdev->pdev->dev, 7348 "prio %u should be in range[1, %u]\n", 7349 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7350 return -EINVAL; 7351 } 7352 7353 if (test_bit(prio - 1, hdev->fd_bmap)) { 7354 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7355 return -EINVAL; 7356 } 7357 return 0; 7358 } 7359 7360 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7361 struct flow_cls_offload *cls_flower, 7362 int tc) 7363 { 7364 struct hclge_vport *vport = hclge_get_vport(handle); 7365 struct hclge_dev *hdev = vport->back; 7366 struct hclge_fd_rule *rule; 7367 int ret; 7368 7369 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7370 dev_err(&hdev->pdev->dev, 7371 "cls flower is not supported\n"); 7372 return -EOPNOTSUPP; 7373 } 7374 7375 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7376 if (ret) { 7377 dev_err(&hdev->pdev->dev, 7378 "failed to check cls flower params, ret = %d\n", ret); 7379 return ret; 7380 } 7381 7382 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7383 if (!rule) 7384 return -ENOMEM; 7385 7386 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7387 if (ret) { 7388 kfree(rule); 7389 return ret; 7390 } 7391 7392 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7393 rule->cls_flower.tc = tc; 7394 rule->location = cls_flower->common.prio - 1; 7395 rule->vf_id = 0; 7396 rule->cls_flower.cookie = cls_flower->cookie; 7397 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7398 7399 ret = hclge_add_fd_entry_common(hdev, rule); 7400 if (ret) 7401 kfree(rule); 7402 7403 return ret; 7404 } 7405 7406 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7407 unsigned long cookie) 7408 { 7409 struct hclge_fd_rule *rule; 7410 struct hlist_node *node; 7411 7412 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7413 if (rule->cls_flower.cookie == cookie) 7414 return rule; 7415 } 7416 7417 return NULL; 7418 } 7419 7420 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7421 struct flow_cls_offload *cls_flower) 7422 { 7423 struct hclge_vport *vport = hclge_get_vport(handle); 7424 struct hclge_dev *hdev = vport->back; 7425 struct hclge_fd_rule *rule; 7426 int ret; 7427 7428 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7429 return -EOPNOTSUPP; 7430 7431 spin_lock_bh(&hdev->fd_rule_lock); 7432 7433 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7434 if (!rule) { 7435 spin_unlock_bh(&hdev->fd_rule_lock); 7436 return -EINVAL; 7437 } 7438 7439 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7440 NULL, false); 7441 if (ret) { 7442 /* if tcam config fail, set rule state to TO_DEL, 7443 * so the rule will be deleted when periodic 7444 * task being scheduled. 7445 */ 7446 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL); 7447 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7448 spin_unlock_bh(&hdev->fd_rule_lock); 7449 return ret; 7450 } 7451 7452 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7453 spin_unlock_bh(&hdev->fd_rule_lock); 7454 7455 return 0; 7456 } 7457 7458 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7459 { 7460 struct hclge_fd_rule *rule; 7461 struct hlist_node *node; 7462 int ret = 0; 7463 7464 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7465 return; 7466 7467 spin_lock_bh(&hdev->fd_rule_lock); 7468 7469 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7470 switch (rule->state) { 7471 case HCLGE_FD_TO_ADD: 7472 ret = hclge_fd_config_rule(hdev, rule); 7473 if (ret) 7474 goto out; 7475 rule->state = HCLGE_FD_ACTIVE; 7476 break; 7477 case HCLGE_FD_TO_DEL: 7478 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7479 rule->location, NULL, false); 7480 if (ret) 7481 goto out; 7482 hclge_fd_dec_rule_cnt(hdev, rule->location); 7483 hclge_fd_free_node(hdev, rule); 7484 break; 7485 default: 7486 break; 7487 } 7488 } 7489 7490 out: 7491 if (ret) 7492 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7493 7494 spin_unlock_bh(&hdev->fd_rule_lock); 7495 } 7496 7497 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7498 { 7499 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7500 return; 7501 7502 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7503 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7504 7505 hclge_clear_fd_rules_in_list(hdev, clear_list); 7506 } 7507 7508 hclge_sync_fd_user_def_cfg(hdev, false); 7509 7510 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7511 } 7512 7513 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7514 { 7515 struct hclge_vport *vport = hclge_get_vport(handle); 7516 struct hclge_dev *hdev = vport->back; 7517 7518 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7519 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7520 } 7521 7522 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7523 { 7524 struct hclge_vport *vport = hclge_get_vport(handle); 7525 struct hclge_dev *hdev = vport->back; 7526 7527 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7528 } 7529 7530 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7531 { 7532 struct hclge_vport *vport = hclge_get_vport(handle); 7533 struct hclge_dev *hdev = vport->back; 7534 7535 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7536 } 7537 7538 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7539 { 7540 struct hclge_vport *vport = hclge_get_vport(handle); 7541 struct hclge_dev *hdev = vport->back; 7542 7543 return hdev->rst_stats.hw_reset_done_cnt; 7544 } 7545 7546 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7547 { 7548 struct hclge_vport *vport = hclge_get_vport(handle); 7549 struct hclge_dev *hdev = vport->back; 7550 7551 hdev->fd_en = enable; 7552 7553 if (!enable) 7554 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7555 else 7556 hclge_restore_fd_entries(handle); 7557 7558 hclge_task_schedule(hdev, 0); 7559 } 7560 7561 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7562 { 7563 #define HCLGE_LINK_STATUS_WAIT_CNT 3 7564 7565 struct hclge_desc desc; 7566 struct hclge_config_mac_mode_cmd *req = 7567 (struct hclge_config_mac_mode_cmd *)desc.data; 7568 u32 loop_en = 0; 7569 int ret; 7570 7571 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7572 7573 if (enable) { 7574 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7575 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7576 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7577 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7578 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7579 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7580 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7581 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7582 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7583 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7584 } 7585 7586 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7587 7588 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7589 if (ret) { 7590 dev_err(&hdev->pdev->dev, 7591 "mac enable fail, ret =%d.\n", ret); 7592 return; 7593 } 7594 7595 if (!enable) 7596 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7597 HCLGE_LINK_STATUS_WAIT_CNT); 7598 } 7599 7600 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7601 u8 switch_param, u8 param_mask) 7602 { 7603 struct hclge_mac_vlan_switch_cmd *req; 7604 struct hclge_desc desc; 7605 u32 func_id; 7606 int ret; 7607 7608 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7609 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7610 7611 /* read current config parameter */ 7612 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7613 true); 7614 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7615 req->func_id = cpu_to_le32(func_id); 7616 7617 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7618 if (ret) { 7619 dev_err(&hdev->pdev->dev, 7620 "read mac vlan switch parameter fail, ret = %d\n", ret); 7621 return ret; 7622 } 7623 7624 /* modify and write new config parameter */ 7625 hclge_comm_cmd_reuse_desc(&desc, false); 7626 req->switch_param = (req->switch_param & param_mask) | switch_param; 7627 req->param_mask = param_mask; 7628 7629 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7630 if (ret) 7631 dev_err(&hdev->pdev->dev, 7632 "set mac vlan switch parameter fail, ret = %d\n", ret); 7633 return ret; 7634 } 7635 7636 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7637 int link_ret) 7638 { 7639 #define HCLGE_PHY_LINK_STATUS_NUM 200 7640 7641 struct phy_device *phydev = hdev->hw.mac.phydev; 7642 int i = 0; 7643 int ret; 7644 7645 do { 7646 ret = phy_read_status(phydev); 7647 if (ret) { 7648 dev_err(&hdev->pdev->dev, 7649 "phy update link status fail, ret = %d\n", ret); 7650 return; 7651 } 7652 7653 if (phydev->link == link_ret) 7654 break; 7655 7656 msleep(HCLGE_LINK_STATUS_MS); 7657 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7658 } 7659 7660 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7661 int wait_cnt) 7662 { 7663 int link_status; 7664 int i = 0; 7665 int ret; 7666 7667 do { 7668 ret = hclge_get_mac_link_status(hdev, &link_status); 7669 if (ret) 7670 return ret; 7671 if (link_status == link_ret) 7672 return 0; 7673 7674 msleep(HCLGE_LINK_STATUS_MS); 7675 } while (++i < wait_cnt); 7676 return -EBUSY; 7677 } 7678 7679 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7680 bool is_phy) 7681 { 7682 #define HCLGE_MAC_LINK_STATUS_NUM 100 7683 7684 int link_ret; 7685 7686 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7687 7688 if (is_phy) 7689 hclge_phy_link_status_wait(hdev, link_ret); 7690 7691 return hclge_mac_link_status_wait(hdev, link_ret, 7692 HCLGE_MAC_LINK_STATUS_NUM); 7693 } 7694 7695 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7696 { 7697 struct hclge_config_mac_mode_cmd *req; 7698 struct hclge_desc desc; 7699 u32 loop_en; 7700 int ret; 7701 7702 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7703 /* 1 Read out the MAC mode config at first */ 7704 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7705 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7706 if (ret) { 7707 dev_err(&hdev->pdev->dev, 7708 "mac loopback get fail, ret =%d.\n", ret); 7709 return ret; 7710 } 7711 7712 /* 2 Then setup the loopback flag */ 7713 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7714 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7715 7716 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7717 7718 /* 3 Config mac work mode with loopback flag 7719 * and its original configure parameters 7720 */ 7721 hclge_comm_cmd_reuse_desc(&desc, false); 7722 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7723 if (ret) 7724 dev_err(&hdev->pdev->dev, 7725 "mac loopback set fail, ret =%d.\n", ret); 7726 return ret; 7727 } 7728 7729 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7730 enum hnae3_loop loop_mode) 7731 { 7732 struct hclge_common_lb_cmd *req; 7733 struct hclge_desc desc; 7734 u8 loop_mode_b; 7735 int ret; 7736 7737 req = (struct hclge_common_lb_cmd *)desc.data; 7738 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7739 7740 switch (loop_mode) { 7741 case HNAE3_LOOP_SERIAL_SERDES: 7742 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7743 break; 7744 case HNAE3_LOOP_PARALLEL_SERDES: 7745 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7746 break; 7747 case HNAE3_LOOP_PHY: 7748 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7749 break; 7750 default: 7751 dev_err(&hdev->pdev->dev, 7752 "unsupported loopback mode %d\n", loop_mode); 7753 return -ENOTSUPP; 7754 } 7755 7756 req->mask = loop_mode_b; 7757 if (en) 7758 req->enable = loop_mode_b; 7759 7760 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7761 if (ret) 7762 dev_err(&hdev->pdev->dev, 7763 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7764 loop_mode, ret); 7765 7766 return ret; 7767 } 7768 7769 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7770 { 7771 #define HCLGE_COMMON_LB_RETRY_MS 10 7772 #define HCLGE_COMMON_LB_RETRY_NUM 100 7773 7774 struct hclge_common_lb_cmd *req; 7775 struct hclge_desc desc; 7776 u32 i = 0; 7777 int ret; 7778 7779 req = (struct hclge_common_lb_cmd *)desc.data; 7780 7781 do { 7782 msleep(HCLGE_COMMON_LB_RETRY_MS); 7783 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7784 true); 7785 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7786 if (ret) { 7787 dev_err(&hdev->pdev->dev, 7788 "failed to get loopback done status, ret = %d\n", 7789 ret); 7790 return ret; 7791 } 7792 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7793 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7794 7795 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7796 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7797 return -EBUSY; 7798 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7799 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7800 return -EIO; 7801 } 7802 7803 return 0; 7804 } 7805 7806 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7807 enum hnae3_loop loop_mode) 7808 { 7809 int ret; 7810 7811 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7812 if (ret) 7813 return ret; 7814 7815 return hclge_cfg_common_loopback_wait(hdev); 7816 } 7817 7818 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7819 enum hnae3_loop loop_mode) 7820 { 7821 int ret; 7822 7823 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7824 if (ret) 7825 return ret; 7826 7827 hclge_cfg_mac_mode(hdev, en); 7828 7829 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7830 if (ret) 7831 dev_err(&hdev->pdev->dev, 7832 "serdes loopback config mac mode timeout\n"); 7833 7834 return ret; 7835 } 7836 7837 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7838 struct phy_device *phydev) 7839 { 7840 int ret; 7841 7842 if (!phydev->suspended) { 7843 ret = phy_suspend(phydev); 7844 if (ret) 7845 return ret; 7846 } 7847 7848 ret = phy_resume(phydev); 7849 if (ret) 7850 return ret; 7851 7852 return phy_loopback(phydev, true); 7853 } 7854 7855 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7856 struct phy_device *phydev) 7857 { 7858 int ret; 7859 7860 ret = phy_loopback(phydev, false); 7861 if (ret) 7862 return ret; 7863 7864 return phy_suspend(phydev); 7865 } 7866 7867 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7868 { 7869 struct phy_device *phydev = hdev->hw.mac.phydev; 7870 int ret; 7871 7872 if (!phydev) { 7873 if (hnae3_dev_phy_imp_supported(hdev)) 7874 return hclge_set_common_loopback(hdev, en, 7875 HNAE3_LOOP_PHY); 7876 return -ENOTSUPP; 7877 } 7878 7879 if (en) 7880 ret = hclge_enable_phy_loopback(hdev, phydev); 7881 else 7882 ret = hclge_disable_phy_loopback(hdev, phydev); 7883 if (ret) { 7884 dev_err(&hdev->pdev->dev, 7885 "set phy loopback fail, ret = %d\n", ret); 7886 return ret; 7887 } 7888 7889 hclge_cfg_mac_mode(hdev, en); 7890 7891 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7892 if (ret) 7893 dev_err(&hdev->pdev->dev, 7894 "phy loopback config mac mode timeout\n"); 7895 7896 return ret; 7897 } 7898 7899 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7900 u16 stream_id, bool enable) 7901 { 7902 struct hclge_desc desc; 7903 struct hclge_cfg_com_tqp_queue_cmd *req = 7904 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7905 7906 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7907 req->tqp_id = cpu_to_le16(tqp_id); 7908 req->stream_id = cpu_to_le16(stream_id); 7909 if (enable) 7910 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7911 7912 return hclge_cmd_send(&hdev->hw, &desc, 1); 7913 } 7914 7915 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7916 { 7917 struct hclge_vport *vport = hclge_get_vport(handle); 7918 struct hclge_dev *hdev = vport->back; 7919 int ret; 7920 u16 i; 7921 7922 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7923 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7924 if (ret) 7925 return ret; 7926 } 7927 return 0; 7928 } 7929 7930 static int hclge_set_loopback(struct hnae3_handle *handle, 7931 enum hnae3_loop loop_mode, bool en) 7932 { 7933 struct hclge_vport *vport = hclge_get_vport(handle); 7934 struct hclge_dev *hdev = vport->back; 7935 int ret = 0; 7936 7937 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7938 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7939 * the same, the packets are looped back in the SSU. If SSU loopback 7940 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7941 */ 7942 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7943 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7944 7945 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7946 HCLGE_SWITCH_ALW_LPBK_MASK); 7947 if (ret) 7948 return ret; 7949 } 7950 7951 switch (loop_mode) { 7952 case HNAE3_LOOP_APP: 7953 ret = hclge_set_app_loopback(hdev, en); 7954 break; 7955 case HNAE3_LOOP_SERIAL_SERDES: 7956 case HNAE3_LOOP_PARALLEL_SERDES: 7957 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7958 break; 7959 case HNAE3_LOOP_PHY: 7960 ret = hclge_set_phy_loopback(hdev, en); 7961 break; 7962 case HNAE3_LOOP_EXTERNAL: 7963 break; 7964 default: 7965 ret = -ENOTSUPP; 7966 dev_err(&hdev->pdev->dev, 7967 "loop_mode %d is not supported\n", loop_mode); 7968 break; 7969 } 7970 7971 if (ret) 7972 return ret; 7973 7974 ret = hclge_tqp_enable(handle, en); 7975 if (ret) 7976 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7977 en ? "enable" : "disable", ret); 7978 7979 return ret; 7980 } 7981 7982 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7983 { 7984 int ret; 7985 7986 ret = hclge_set_app_loopback(hdev, false); 7987 if (ret) 7988 return ret; 7989 7990 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7991 if (ret) 7992 return ret; 7993 7994 return hclge_cfg_common_loopback(hdev, false, 7995 HNAE3_LOOP_PARALLEL_SERDES); 7996 } 7997 7998 static void hclge_flush_link_update(struct hclge_dev *hdev) 7999 { 8000 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 8001 8002 unsigned long last = hdev->serv_processed_cnt; 8003 int i = 0; 8004 8005 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 8006 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 8007 last == hdev->serv_processed_cnt) 8008 usleep_range(1, 1); 8009 } 8010 8011 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 8012 { 8013 struct hclge_vport *vport = hclge_get_vport(handle); 8014 struct hclge_dev *hdev = vport->back; 8015 8016 if (enable) { 8017 hclge_task_schedule(hdev, 0); 8018 } else { 8019 /* Set the DOWN flag here to disable link updating */ 8020 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8021 8022 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 8023 hclge_flush_link_update(hdev); 8024 } 8025 } 8026 8027 static int hclge_ae_start(struct hnae3_handle *handle) 8028 { 8029 struct hclge_vport *vport = hclge_get_vport(handle); 8030 struct hclge_dev *hdev = vport->back; 8031 8032 /* mac enable */ 8033 hclge_cfg_mac_mode(hdev, true); 8034 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 8035 hdev->hw.mac.link = 0; 8036 8037 /* reset tqp stats */ 8038 hclge_comm_reset_tqp_stats(handle); 8039 8040 hclge_mac_start_phy(hdev); 8041 8042 return 0; 8043 } 8044 8045 static void hclge_ae_stop(struct hnae3_handle *handle) 8046 { 8047 struct hclge_vport *vport = hclge_get_vport(handle); 8048 struct hclge_dev *hdev = vport->back; 8049 8050 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8051 spin_lock_bh(&hdev->fd_rule_lock); 8052 hclge_clear_arfs_rules(hdev); 8053 spin_unlock_bh(&hdev->fd_rule_lock); 8054 8055 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8056 * so it only need to stop phy here. 8057 */ 8058 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 8059 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 8060 HCLGE_PFC_DISABLE); 8061 if (hdev->reset_type != HNAE3_FUNC_RESET && 8062 hdev->reset_type != HNAE3_FLR_RESET) { 8063 hclge_mac_stop_phy(hdev); 8064 hclge_update_link_status(hdev); 8065 return; 8066 } 8067 } 8068 8069 hclge_reset_tqp(handle); 8070 8071 hclge_config_mac_tnl_int(hdev, false); 8072 8073 /* Mac disable */ 8074 hclge_cfg_mac_mode(hdev, false); 8075 8076 hclge_mac_stop_phy(hdev); 8077 8078 /* reset tqp stats */ 8079 hclge_comm_reset_tqp_stats(handle); 8080 hclge_update_link_status(hdev); 8081 } 8082 8083 int hclge_vport_start(struct hclge_vport *vport) 8084 { 8085 struct hclge_dev *hdev = vport->back; 8086 8087 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8088 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8089 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8090 vport->last_active_jiffies = jiffies; 8091 vport->need_notify = 0; 8092 8093 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8094 if (vport->vport_id) { 8095 hclge_restore_mac_table_common(vport); 8096 hclge_restore_vport_vlan_table(vport); 8097 } else { 8098 hclge_restore_hw_table(hdev); 8099 } 8100 } 8101 8102 clear_bit(vport->vport_id, hdev->vport_config_block); 8103 8104 return 0; 8105 } 8106 8107 void hclge_vport_stop(struct hclge_vport *vport) 8108 { 8109 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8110 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8111 vport->need_notify = 0; 8112 } 8113 8114 static int hclge_client_start(struct hnae3_handle *handle) 8115 { 8116 struct hclge_vport *vport = hclge_get_vport(handle); 8117 8118 return hclge_vport_start(vport); 8119 } 8120 8121 static void hclge_client_stop(struct hnae3_handle *handle) 8122 { 8123 struct hclge_vport *vport = hclge_get_vport(handle); 8124 8125 hclge_vport_stop(vport); 8126 } 8127 8128 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8129 u16 cmdq_resp, u8 resp_code, 8130 enum hclge_mac_vlan_tbl_opcode op) 8131 { 8132 struct hclge_dev *hdev = vport->back; 8133 8134 if (cmdq_resp) { 8135 dev_err(&hdev->pdev->dev, 8136 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8137 cmdq_resp); 8138 return -EIO; 8139 } 8140 8141 if (op == HCLGE_MAC_VLAN_ADD) { 8142 if (!resp_code || resp_code == 1) 8143 return 0; 8144 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8145 resp_code == HCLGE_ADD_MC_OVERFLOW) 8146 return -ENOSPC; 8147 8148 dev_err(&hdev->pdev->dev, 8149 "add mac addr failed for undefined, code=%u.\n", 8150 resp_code); 8151 return -EIO; 8152 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8153 if (!resp_code) { 8154 return 0; 8155 } else if (resp_code == 1) { 8156 dev_dbg(&hdev->pdev->dev, 8157 "remove mac addr failed for miss.\n"); 8158 return -ENOENT; 8159 } 8160 8161 dev_err(&hdev->pdev->dev, 8162 "remove mac addr failed for undefined, code=%u.\n", 8163 resp_code); 8164 return -EIO; 8165 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8166 if (!resp_code) { 8167 return 0; 8168 } else if (resp_code == 1) { 8169 dev_dbg(&hdev->pdev->dev, 8170 "lookup mac addr failed for miss.\n"); 8171 return -ENOENT; 8172 } 8173 8174 dev_err(&hdev->pdev->dev, 8175 "lookup mac addr failed for undefined, code=%u.\n", 8176 resp_code); 8177 return -EIO; 8178 } 8179 8180 dev_err(&hdev->pdev->dev, 8181 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8182 8183 return -EINVAL; 8184 } 8185 8186 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8187 { 8188 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8189 8190 unsigned int word_num; 8191 unsigned int bit_num; 8192 8193 if (vfid > 255 || vfid < 0) 8194 return -EIO; 8195 8196 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8197 word_num = vfid / 32; 8198 bit_num = vfid % 32; 8199 if (clr) 8200 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8201 else 8202 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8203 } else { 8204 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8205 bit_num = vfid % 32; 8206 if (clr) 8207 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8208 else 8209 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8210 } 8211 8212 return 0; 8213 } 8214 8215 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8216 { 8217 #define HCLGE_DESC_NUMBER 3 8218 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8219 int i, j; 8220 8221 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8222 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8223 if (desc[i].data[j]) 8224 return false; 8225 8226 return true; 8227 } 8228 8229 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8230 const u8 *addr, bool is_mc) 8231 { 8232 const unsigned char *mac_addr = addr; 8233 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8234 (mac_addr[0]) | (mac_addr[1] << 8); 8235 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8236 8237 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8238 if (is_mc) { 8239 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8240 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8241 } 8242 8243 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8244 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8245 } 8246 8247 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8248 struct hclge_mac_vlan_tbl_entry_cmd *req) 8249 { 8250 struct hclge_dev *hdev = vport->back; 8251 struct hclge_desc desc; 8252 u8 resp_code; 8253 u16 retval; 8254 int ret; 8255 8256 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8257 8258 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8259 8260 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8261 if (ret) { 8262 dev_err(&hdev->pdev->dev, 8263 "del mac addr failed for cmd_send, ret =%d.\n", 8264 ret); 8265 return ret; 8266 } 8267 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8268 retval = le16_to_cpu(desc.retval); 8269 8270 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8271 HCLGE_MAC_VLAN_REMOVE); 8272 } 8273 8274 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8275 struct hclge_mac_vlan_tbl_entry_cmd *req, 8276 struct hclge_desc *desc, 8277 bool is_mc) 8278 { 8279 struct hclge_dev *hdev = vport->back; 8280 u8 resp_code; 8281 u16 retval; 8282 int ret; 8283 8284 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8285 if (is_mc) { 8286 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8287 memcpy(desc[0].data, 8288 req, 8289 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8290 hclge_cmd_setup_basic_desc(&desc[1], 8291 HCLGE_OPC_MAC_VLAN_ADD, 8292 true); 8293 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8294 hclge_cmd_setup_basic_desc(&desc[2], 8295 HCLGE_OPC_MAC_VLAN_ADD, 8296 true); 8297 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8298 } else { 8299 memcpy(desc[0].data, 8300 req, 8301 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8302 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8303 } 8304 if (ret) { 8305 dev_err(&hdev->pdev->dev, 8306 "lookup mac addr failed for cmd_send, ret =%d.\n", 8307 ret); 8308 return ret; 8309 } 8310 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8311 retval = le16_to_cpu(desc[0].retval); 8312 8313 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8314 HCLGE_MAC_VLAN_LKUP); 8315 } 8316 8317 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8318 struct hclge_mac_vlan_tbl_entry_cmd *req, 8319 struct hclge_desc *mc_desc) 8320 { 8321 struct hclge_dev *hdev = vport->back; 8322 int cfg_status; 8323 u8 resp_code; 8324 u16 retval; 8325 int ret; 8326 8327 if (!mc_desc) { 8328 struct hclge_desc desc; 8329 8330 hclge_cmd_setup_basic_desc(&desc, 8331 HCLGE_OPC_MAC_VLAN_ADD, 8332 false); 8333 memcpy(desc.data, req, 8334 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8335 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8336 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8337 retval = le16_to_cpu(desc.retval); 8338 8339 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8340 resp_code, 8341 HCLGE_MAC_VLAN_ADD); 8342 } else { 8343 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8344 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8345 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8346 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8347 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8348 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8349 memcpy(mc_desc[0].data, req, 8350 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8351 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8352 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8353 retval = le16_to_cpu(mc_desc[0].retval); 8354 8355 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8356 resp_code, 8357 HCLGE_MAC_VLAN_ADD); 8358 } 8359 8360 if (ret) { 8361 dev_err(&hdev->pdev->dev, 8362 "add mac addr failed for cmd_send, ret =%d.\n", 8363 ret); 8364 return ret; 8365 } 8366 8367 return cfg_status; 8368 } 8369 8370 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8371 u16 *allocated_size) 8372 { 8373 struct hclge_umv_spc_alc_cmd *req; 8374 struct hclge_desc desc; 8375 int ret; 8376 8377 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8378 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8379 8380 req->space_size = cpu_to_le32(space_size); 8381 8382 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8383 if (ret) { 8384 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8385 ret); 8386 return ret; 8387 } 8388 8389 *allocated_size = le32_to_cpu(desc.data[1]); 8390 8391 return 0; 8392 } 8393 8394 static int hclge_init_umv_space(struct hclge_dev *hdev) 8395 { 8396 u16 allocated_size = 0; 8397 int ret; 8398 8399 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8400 if (ret) 8401 return ret; 8402 8403 if (allocated_size < hdev->wanted_umv_size) 8404 dev_warn(&hdev->pdev->dev, 8405 "failed to alloc umv space, want %u, get %u\n", 8406 hdev->wanted_umv_size, allocated_size); 8407 8408 hdev->max_umv_size = allocated_size; 8409 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8410 hdev->share_umv_size = hdev->priv_umv_size + 8411 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8412 8413 if (hdev->ae_dev->dev_specs.mc_mac_size) 8414 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8415 8416 return 0; 8417 } 8418 8419 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8420 { 8421 struct hclge_vport *vport; 8422 int i; 8423 8424 for (i = 0; i < hdev->num_alloc_vport; i++) { 8425 vport = &hdev->vport[i]; 8426 vport->used_umv_num = 0; 8427 } 8428 8429 mutex_lock(&hdev->vport_lock); 8430 hdev->share_umv_size = hdev->priv_umv_size + 8431 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8432 mutex_unlock(&hdev->vport_lock); 8433 8434 hdev->used_mc_mac_num = 0; 8435 } 8436 8437 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8438 { 8439 struct hclge_dev *hdev = vport->back; 8440 bool is_full; 8441 8442 if (need_lock) 8443 mutex_lock(&hdev->vport_lock); 8444 8445 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8446 hdev->share_umv_size == 0); 8447 8448 if (need_lock) 8449 mutex_unlock(&hdev->vport_lock); 8450 8451 return is_full; 8452 } 8453 8454 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8455 { 8456 struct hclge_dev *hdev = vport->back; 8457 8458 if (is_free) { 8459 if (vport->used_umv_num > hdev->priv_umv_size) 8460 hdev->share_umv_size++; 8461 8462 if (vport->used_umv_num > 0) 8463 vport->used_umv_num--; 8464 } else { 8465 if (vport->used_umv_num >= hdev->priv_umv_size && 8466 hdev->share_umv_size > 0) 8467 hdev->share_umv_size--; 8468 vport->used_umv_num++; 8469 } 8470 } 8471 8472 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8473 const u8 *mac_addr) 8474 { 8475 struct hclge_mac_node *mac_node, *tmp; 8476 8477 list_for_each_entry_safe(mac_node, tmp, list, node) 8478 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8479 return mac_node; 8480 8481 return NULL; 8482 } 8483 8484 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8485 enum HCLGE_MAC_NODE_STATE state) 8486 { 8487 switch (state) { 8488 /* from set_rx_mode or tmp_add_list */ 8489 case HCLGE_MAC_TO_ADD: 8490 if (mac_node->state == HCLGE_MAC_TO_DEL) 8491 mac_node->state = HCLGE_MAC_ACTIVE; 8492 break; 8493 /* only from set_rx_mode */ 8494 case HCLGE_MAC_TO_DEL: 8495 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8496 list_del(&mac_node->node); 8497 kfree(mac_node); 8498 } else { 8499 mac_node->state = HCLGE_MAC_TO_DEL; 8500 } 8501 break; 8502 /* only from tmp_add_list, the mac_node->state won't be 8503 * ACTIVE. 8504 */ 8505 case HCLGE_MAC_ACTIVE: 8506 if (mac_node->state == HCLGE_MAC_TO_ADD) 8507 mac_node->state = HCLGE_MAC_ACTIVE; 8508 8509 break; 8510 } 8511 } 8512 8513 int hclge_update_mac_list(struct hclge_vport *vport, 8514 enum HCLGE_MAC_NODE_STATE state, 8515 enum HCLGE_MAC_ADDR_TYPE mac_type, 8516 const unsigned char *addr) 8517 { 8518 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8519 struct hclge_dev *hdev = vport->back; 8520 struct hclge_mac_node *mac_node; 8521 struct list_head *list; 8522 8523 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8524 &vport->uc_mac_list : &vport->mc_mac_list; 8525 8526 spin_lock_bh(&vport->mac_list_lock); 8527 8528 /* if the mac addr is already in the mac list, no need to add a new 8529 * one into it, just check the mac addr state, convert it to a new 8530 * state, or just remove it, or do nothing. 8531 */ 8532 mac_node = hclge_find_mac_node(list, addr); 8533 if (mac_node) { 8534 hclge_update_mac_node(mac_node, state); 8535 spin_unlock_bh(&vport->mac_list_lock); 8536 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8537 return 0; 8538 } 8539 8540 /* if this address is never added, unnecessary to delete */ 8541 if (state == HCLGE_MAC_TO_DEL) { 8542 spin_unlock_bh(&vport->mac_list_lock); 8543 hnae3_format_mac_addr(format_mac_addr, addr); 8544 dev_err(&hdev->pdev->dev, 8545 "failed to delete address %s from mac list\n", 8546 format_mac_addr); 8547 return -ENOENT; 8548 } 8549 8550 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8551 if (!mac_node) { 8552 spin_unlock_bh(&vport->mac_list_lock); 8553 return -ENOMEM; 8554 } 8555 8556 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8557 8558 mac_node->state = state; 8559 ether_addr_copy(mac_node->mac_addr, addr); 8560 list_add_tail(&mac_node->node, list); 8561 8562 spin_unlock_bh(&vport->mac_list_lock); 8563 8564 return 0; 8565 } 8566 8567 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8568 const unsigned char *addr) 8569 { 8570 struct hclge_vport *vport = hclge_get_vport(handle); 8571 8572 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8573 addr); 8574 } 8575 8576 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8577 const unsigned char *addr) 8578 { 8579 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8580 struct hclge_dev *hdev = vport->back; 8581 struct hclge_mac_vlan_tbl_entry_cmd req; 8582 struct hclge_desc desc; 8583 u16 egress_port = 0; 8584 int ret; 8585 8586 /* mac addr check */ 8587 if (is_zero_ether_addr(addr) || 8588 is_broadcast_ether_addr(addr) || 8589 is_multicast_ether_addr(addr)) { 8590 hnae3_format_mac_addr(format_mac_addr, addr); 8591 dev_err(&hdev->pdev->dev, 8592 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8593 format_mac_addr, is_zero_ether_addr(addr), 8594 is_broadcast_ether_addr(addr), 8595 is_multicast_ether_addr(addr)); 8596 return -EINVAL; 8597 } 8598 8599 memset(&req, 0, sizeof(req)); 8600 8601 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8602 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8603 8604 req.egress_port = cpu_to_le16(egress_port); 8605 8606 hclge_prepare_mac_addr(&req, addr, false); 8607 8608 /* Lookup the mac address in the mac_vlan table, and add 8609 * it if the entry is inexistent. Repeated unicast entry 8610 * is not allowed in the mac vlan table. 8611 */ 8612 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8613 if (ret == -ENOENT) { 8614 mutex_lock(&hdev->vport_lock); 8615 if (!hclge_is_umv_space_full(vport, false)) { 8616 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8617 if (!ret) 8618 hclge_update_umv_space(vport, false); 8619 mutex_unlock(&hdev->vport_lock); 8620 return ret; 8621 } 8622 mutex_unlock(&hdev->vport_lock); 8623 8624 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8625 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8626 hdev->priv_umv_size); 8627 8628 return -ENOSPC; 8629 } 8630 8631 /* check if we just hit the duplicate */ 8632 if (!ret) 8633 return -EEXIST; 8634 8635 return ret; 8636 } 8637 8638 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8639 const unsigned char *addr) 8640 { 8641 struct hclge_vport *vport = hclge_get_vport(handle); 8642 8643 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8644 addr); 8645 } 8646 8647 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8648 const unsigned char *addr) 8649 { 8650 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8651 struct hclge_dev *hdev = vport->back; 8652 struct hclge_mac_vlan_tbl_entry_cmd req; 8653 int ret; 8654 8655 /* mac addr check */ 8656 if (is_zero_ether_addr(addr) || 8657 is_broadcast_ether_addr(addr) || 8658 is_multicast_ether_addr(addr)) { 8659 hnae3_format_mac_addr(format_mac_addr, addr); 8660 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8661 format_mac_addr); 8662 return -EINVAL; 8663 } 8664 8665 memset(&req, 0, sizeof(req)); 8666 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8667 hclge_prepare_mac_addr(&req, addr, false); 8668 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8669 if (!ret || ret == -ENOENT) { 8670 mutex_lock(&hdev->vport_lock); 8671 hclge_update_umv_space(vport, true); 8672 mutex_unlock(&hdev->vport_lock); 8673 return 0; 8674 } 8675 8676 return ret; 8677 } 8678 8679 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8680 const unsigned char *addr) 8681 { 8682 struct hclge_vport *vport = hclge_get_vport(handle); 8683 8684 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8685 addr); 8686 } 8687 8688 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8689 const unsigned char *addr) 8690 { 8691 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8692 struct hclge_dev *hdev = vport->back; 8693 struct hclge_mac_vlan_tbl_entry_cmd req; 8694 struct hclge_desc desc[3]; 8695 bool is_new_addr = false; 8696 int status; 8697 8698 /* mac addr check */ 8699 if (!is_multicast_ether_addr(addr)) { 8700 hnae3_format_mac_addr(format_mac_addr, addr); 8701 dev_err(&hdev->pdev->dev, 8702 "Add mc mac err! invalid mac:%s.\n", 8703 format_mac_addr); 8704 return -EINVAL; 8705 } 8706 memset(&req, 0, sizeof(req)); 8707 hclge_prepare_mac_addr(&req, addr, true); 8708 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8709 if (status) { 8710 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8711 hdev->used_mc_mac_num >= 8712 hdev->ae_dev->dev_specs.mc_mac_size) 8713 goto err_no_space; 8714 8715 is_new_addr = true; 8716 8717 /* This mac addr do not exist, add new entry for it */ 8718 memset(desc[0].data, 0, sizeof(desc[0].data)); 8719 memset(desc[1].data, 0, sizeof(desc[0].data)); 8720 memset(desc[2].data, 0, sizeof(desc[0].data)); 8721 } 8722 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8723 if (status) 8724 return status; 8725 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8726 if (status == -ENOSPC) 8727 goto err_no_space; 8728 else if (!status && is_new_addr) 8729 hdev->used_mc_mac_num++; 8730 8731 return status; 8732 8733 err_no_space: 8734 /* if already overflow, not to print each time */ 8735 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8736 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8737 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8738 } 8739 8740 return -ENOSPC; 8741 } 8742 8743 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8744 const unsigned char *addr) 8745 { 8746 struct hclge_vport *vport = hclge_get_vport(handle); 8747 8748 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8749 addr); 8750 } 8751 8752 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8753 const unsigned char *addr) 8754 { 8755 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8756 struct hclge_dev *hdev = vport->back; 8757 struct hclge_mac_vlan_tbl_entry_cmd req; 8758 enum hclge_comm_cmd_status status; 8759 struct hclge_desc desc[3]; 8760 8761 /* mac addr check */ 8762 if (!is_multicast_ether_addr(addr)) { 8763 hnae3_format_mac_addr(format_mac_addr, addr); 8764 dev_dbg(&hdev->pdev->dev, 8765 "Remove mc mac err! invalid mac:%s.\n", 8766 format_mac_addr); 8767 return -EINVAL; 8768 } 8769 8770 memset(&req, 0, sizeof(req)); 8771 hclge_prepare_mac_addr(&req, addr, true); 8772 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8773 if (!status) { 8774 /* This mac addr exist, remove this handle's VFID for it */ 8775 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8776 if (status) 8777 return status; 8778 8779 if (hclge_is_all_function_id_zero(desc)) { 8780 /* All the vfid is zero, so need to delete this entry */ 8781 status = hclge_remove_mac_vlan_tbl(vport, &req); 8782 if (!status) 8783 hdev->used_mc_mac_num--; 8784 } else { 8785 /* Not all the vfid is zero, update the vfid */ 8786 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8787 } 8788 } else if (status == -ENOENT) { 8789 status = 0; 8790 } 8791 8792 return status; 8793 } 8794 8795 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8796 struct list_head *list, 8797 enum HCLGE_MAC_ADDR_TYPE mac_type) 8798 { 8799 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8800 struct hclge_mac_node *mac_node, *tmp; 8801 int ret; 8802 8803 if (mac_type == HCLGE_MAC_ADDR_UC) 8804 sync = hclge_add_uc_addr_common; 8805 else 8806 sync = hclge_add_mc_addr_common; 8807 8808 list_for_each_entry_safe(mac_node, tmp, list, node) { 8809 ret = sync(vport, mac_node->mac_addr); 8810 if (!ret) { 8811 mac_node->state = HCLGE_MAC_ACTIVE; 8812 } else { 8813 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8814 &vport->state); 8815 8816 /* If one unicast mac address is existing in hardware, 8817 * we need to try whether other unicast mac addresses 8818 * are new addresses that can be added. 8819 * Multicast mac address can be reusable, even though 8820 * there is no space to add new multicast mac address, 8821 * we should check whether other mac addresses are 8822 * existing in hardware for reuse. 8823 */ 8824 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8825 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8826 break; 8827 } 8828 } 8829 } 8830 8831 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8832 struct list_head *list, 8833 enum HCLGE_MAC_ADDR_TYPE mac_type) 8834 { 8835 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8836 struct hclge_mac_node *mac_node, *tmp; 8837 int ret; 8838 8839 if (mac_type == HCLGE_MAC_ADDR_UC) 8840 unsync = hclge_rm_uc_addr_common; 8841 else 8842 unsync = hclge_rm_mc_addr_common; 8843 8844 list_for_each_entry_safe(mac_node, tmp, list, node) { 8845 ret = unsync(vport, mac_node->mac_addr); 8846 if (!ret || ret == -ENOENT) { 8847 list_del(&mac_node->node); 8848 kfree(mac_node); 8849 } else { 8850 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8851 &vport->state); 8852 break; 8853 } 8854 } 8855 } 8856 8857 static bool hclge_sync_from_add_list(struct list_head *add_list, 8858 struct list_head *mac_list) 8859 { 8860 struct hclge_mac_node *mac_node, *tmp, *new_node; 8861 bool all_added = true; 8862 8863 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8864 if (mac_node->state == HCLGE_MAC_TO_ADD) 8865 all_added = false; 8866 8867 /* if the mac address from tmp_add_list is not in the 8868 * uc/mc_mac_list, it means have received a TO_DEL request 8869 * during the time window of adding the mac address into mac 8870 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8871 * then it will be removed at next time. else it must be TO_ADD, 8872 * this address hasn't been added into mac table, 8873 * so just remove the mac node. 8874 */ 8875 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8876 if (new_node) { 8877 hclge_update_mac_node(new_node, mac_node->state); 8878 list_del(&mac_node->node); 8879 kfree(mac_node); 8880 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8881 mac_node->state = HCLGE_MAC_TO_DEL; 8882 list_move_tail(&mac_node->node, mac_list); 8883 } else { 8884 list_del(&mac_node->node); 8885 kfree(mac_node); 8886 } 8887 } 8888 8889 return all_added; 8890 } 8891 8892 static void hclge_sync_from_del_list(struct list_head *del_list, 8893 struct list_head *mac_list) 8894 { 8895 struct hclge_mac_node *mac_node, *tmp, *new_node; 8896 8897 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8898 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8899 if (new_node) { 8900 /* If the mac addr exists in the mac list, it means 8901 * received a new TO_ADD request during the time window 8902 * of configuring the mac address. For the mac node 8903 * state is TO_ADD, and the address is already in the 8904 * in the hardware(due to delete fail), so we just need 8905 * to change the mac node state to ACTIVE. 8906 */ 8907 new_node->state = HCLGE_MAC_ACTIVE; 8908 list_del(&mac_node->node); 8909 kfree(mac_node); 8910 } else { 8911 list_move_tail(&mac_node->node, mac_list); 8912 } 8913 } 8914 } 8915 8916 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8917 enum HCLGE_MAC_ADDR_TYPE mac_type, 8918 bool is_all_added) 8919 { 8920 if (mac_type == HCLGE_MAC_ADDR_UC) { 8921 if (is_all_added) 8922 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8923 else if (hclge_is_umv_space_full(vport, true)) 8924 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8925 } else { 8926 if (is_all_added) 8927 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8928 else 8929 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8930 } 8931 } 8932 8933 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8934 enum HCLGE_MAC_ADDR_TYPE mac_type) 8935 { 8936 struct hclge_mac_node *mac_node, *tmp, *new_node; 8937 struct list_head tmp_add_list, tmp_del_list; 8938 struct list_head *list; 8939 bool all_added; 8940 8941 INIT_LIST_HEAD(&tmp_add_list); 8942 INIT_LIST_HEAD(&tmp_del_list); 8943 8944 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8945 * we can add/delete these mac addr outside the spin lock 8946 */ 8947 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8948 &vport->uc_mac_list : &vport->mc_mac_list; 8949 8950 spin_lock_bh(&vport->mac_list_lock); 8951 8952 list_for_each_entry_safe(mac_node, tmp, list, node) { 8953 switch (mac_node->state) { 8954 case HCLGE_MAC_TO_DEL: 8955 list_move_tail(&mac_node->node, &tmp_del_list); 8956 break; 8957 case HCLGE_MAC_TO_ADD: 8958 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8959 if (!new_node) 8960 goto stop_traverse; 8961 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8962 new_node->state = mac_node->state; 8963 list_add_tail(&new_node->node, &tmp_add_list); 8964 break; 8965 default: 8966 break; 8967 } 8968 } 8969 8970 stop_traverse: 8971 spin_unlock_bh(&vport->mac_list_lock); 8972 8973 /* delete first, in order to get max mac table space for adding */ 8974 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8975 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8976 8977 /* if some mac addresses were added/deleted fail, move back to the 8978 * mac_list, and retry at next time. 8979 */ 8980 spin_lock_bh(&vport->mac_list_lock); 8981 8982 hclge_sync_from_del_list(&tmp_del_list, list); 8983 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8984 8985 spin_unlock_bh(&vport->mac_list_lock); 8986 8987 hclge_update_overflow_flags(vport, mac_type, all_added); 8988 } 8989 8990 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8991 { 8992 struct hclge_dev *hdev = vport->back; 8993 8994 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8995 return false; 8996 8997 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8998 return true; 8999 9000 return false; 9001 } 9002 9003 static void hclge_sync_mac_table(struct hclge_dev *hdev) 9004 { 9005 int i; 9006 9007 for (i = 0; i < hdev->num_alloc_vport; i++) { 9008 struct hclge_vport *vport = &hdev->vport[i]; 9009 9010 if (!hclge_need_sync_mac_table(vport)) 9011 continue; 9012 9013 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 9014 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 9015 } 9016 } 9017 9018 static void hclge_build_del_list(struct list_head *list, 9019 bool is_del_list, 9020 struct list_head *tmp_del_list) 9021 { 9022 struct hclge_mac_node *mac_cfg, *tmp; 9023 9024 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 9025 switch (mac_cfg->state) { 9026 case HCLGE_MAC_TO_DEL: 9027 case HCLGE_MAC_ACTIVE: 9028 list_move_tail(&mac_cfg->node, tmp_del_list); 9029 break; 9030 case HCLGE_MAC_TO_ADD: 9031 if (is_del_list) { 9032 list_del(&mac_cfg->node); 9033 kfree(mac_cfg); 9034 } 9035 break; 9036 } 9037 } 9038 } 9039 9040 static void hclge_unsync_del_list(struct hclge_vport *vport, 9041 int (*unsync)(struct hclge_vport *vport, 9042 const unsigned char *addr), 9043 bool is_del_list, 9044 struct list_head *tmp_del_list) 9045 { 9046 struct hclge_mac_node *mac_cfg, *tmp; 9047 int ret; 9048 9049 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 9050 ret = unsync(vport, mac_cfg->mac_addr); 9051 if (!ret || ret == -ENOENT) { 9052 /* clear all mac addr from hardware, but remain these 9053 * mac addr in the mac list, and restore them after 9054 * vf reset finished. 9055 */ 9056 if (!is_del_list && 9057 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9058 mac_cfg->state = HCLGE_MAC_TO_ADD; 9059 } else { 9060 list_del(&mac_cfg->node); 9061 kfree(mac_cfg); 9062 } 9063 } else if (is_del_list) { 9064 mac_cfg->state = HCLGE_MAC_TO_DEL; 9065 } 9066 } 9067 } 9068 9069 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9070 enum HCLGE_MAC_ADDR_TYPE mac_type) 9071 { 9072 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9073 struct hclge_dev *hdev = vport->back; 9074 struct list_head tmp_del_list, *list; 9075 9076 if (mac_type == HCLGE_MAC_ADDR_UC) { 9077 list = &vport->uc_mac_list; 9078 unsync = hclge_rm_uc_addr_common; 9079 } else { 9080 list = &vport->mc_mac_list; 9081 unsync = hclge_rm_mc_addr_common; 9082 } 9083 9084 INIT_LIST_HEAD(&tmp_del_list); 9085 9086 if (!is_del_list) 9087 set_bit(vport->vport_id, hdev->vport_config_block); 9088 9089 spin_lock_bh(&vport->mac_list_lock); 9090 9091 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9092 9093 spin_unlock_bh(&vport->mac_list_lock); 9094 9095 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9096 9097 spin_lock_bh(&vport->mac_list_lock); 9098 9099 hclge_sync_from_del_list(&tmp_del_list, list); 9100 9101 spin_unlock_bh(&vport->mac_list_lock); 9102 } 9103 9104 /* remove all mac address when uninitailize */ 9105 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9106 enum HCLGE_MAC_ADDR_TYPE mac_type) 9107 { 9108 struct hclge_mac_node *mac_node, *tmp; 9109 struct hclge_dev *hdev = vport->back; 9110 struct list_head tmp_del_list, *list; 9111 9112 INIT_LIST_HEAD(&tmp_del_list); 9113 9114 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9115 &vport->uc_mac_list : &vport->mc_mac_list; 9116 9117 spin_lock_bh(&vport->mac_list_lock); 9118 9119 list_for_each_entry_safe(mac_node, tmp, list, node) { 9120 switch (mac_node->state) { 9121 case HCLGE_MAC_TO_DEL: 9122 case HCLGE_MAC_ACTIVE: 9123 list_move_tail(&mac_node->node, &tmp_del_list); 9124 break; 9125 case HCLGE_MAC_TO_ADD: 9126 list_del(&mac_node->node); 9127 kfree(mac_node); 9128 break; 9129 } 9130 } 9131 9132 spin_unlock_bh(&vport->mac_list_lock); 9133 9134 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9135 9136 if (!list_empty(&tmp_del_list)) 9137 dev_warn(&hdev->pdev->dev, 9138 "uninit %s mac list for vport %u not completely.\n", 9139 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9140 vport->vport_id); 9141 9142 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9143 list_del(&mac_node->node); 9144 kfree(mac_node); 9145 } 9146 } 9147 9148 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9149 { 9150 struct hclge_vport *vport; 9151 int i; 9152 9153 for (i = 0; i < hdev->num_alloc_vport; i++) { 9154 vport = &hdev->vport[i]; 9155 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9156 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9157 } 9158 } 9159 9160 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9161 u16 cmdq_resp, u8 resp_code) 9162 { 9163 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9164 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9165 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9166 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9167 9168 int return_status; 9169 9170 if (cmdq_resp) { 9171 dev_err(&hdev->pdev->dev, 9172 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9173 cmdq_resp); 9174 return -EIO; 9175 } 9176 9177 switch (resp_code) { 9178 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9179 case HCLGE_ETHERTYPE_ALREADY_ADD: 9180 return_status = 0; 9181 break; 9182 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9183 dev_err(&hdev->pdev->dev, 9184 "add mac ethertype failed for manager table overflow.\n"); 9185 return_status = -EIO; 9186 break; 9187 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9188 dev_err(&hdev->pdev->dev, 9189 "add mac ethertype failed for key conflict.\n"); 9190 return_status = -EIO; 9191 break; 9192 default: 9193 dev_err(&hdev->pdev->dev, 9194 "add mac ethertype failed for undefined, code=%u.\n", 9195 resp_code); 9196 return_status = -EIO; 9197 } 9198 9199 return return_status; 9200 } 9201 9202 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9203 u8 *mac_addr) 9204 { 9205 struct hclge_vport *vport = hclge_get_vport(handle); 9206 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9207 struct hclge_dev *hdev = vport->back; 9208 9209 vport = hclge_get_vf_vport(hdev, vf); 9210 if (!vport) 9211 return -EINVAL; 9212 9213 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9214 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9215 dev_info(&hdev->pdev->dev, 9216 "Specified MAC(=%s) is same as before, no change committed!\n", 9217 format_mac_addr); 9218 return 0; 9219 } 9220 9221 ether_addr_copy(vport->vf_info.mac, mac_addr); 9222 9223 /* there is a timewindow for PF to know VF unalive, it may 9224 * cause send mailbox fail, but it doesn't matter, VF will 9225 * query it when reinit. 9226 */ 9227 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9228 dev_info(&hdev->pdev->dev, 9229 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9230 vf, format_mac_addr); 9231 (void)hclge_inform_reset_assert_to_vf(vport); 9232 return 0; 9233 } 9234 9235 dev_info(&hdev->pdev->dev, 9236 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9237 vf, format_mac_addr); 9238 return 0; 9239 } 9240 9241 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9242 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9243 { 9244 struct hclge_desc desc; 9245 u8 resp_code; 9246 u16 retval; 9247 int ret; 9248 9249 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9250 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9251 9252 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9253 if (ret) { 9254 dev_err(&hdev->pdev->dev, 9255 "add mac ethertype failed for cmd_send, ret =%d.\n", 9256 ret); 9257 return ret; 9258 } 9259 9260 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9261 retval = le16_to_cpu(desc.retval); 9262 9263 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9264 } 9265 9266 static int init_mgr_tbl(struct hclge_dev *hdev) 9267 { 9268 int ret; 9269 int i; 9270 9271 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9272 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9273 if (ret) { 9274 dev_err(&hdev->pdev->dev, 9275 "add mac ethertype failed, ret =%d.\n", 9276 ret); 9277 return ret; 9278 } 9279 } 9280 9281 return 0; 9282 } 9283 9284 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9285 { 9286 struct hclge_vport *vport = hclge_get_vport(handle); 9287 struct hclge_dev *hdev = vport->back; 9288 9289 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9290 } 9291 9292 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9293 const u8 *old_addr, const u8 *new_addr) 9294 { 9295 struct list_head *list = &vport->uc_mac_list; 9296 struct hclge_mac_node *old_node, *new_node; 9297 9298 new_node = hclge_find_mac_node(list, new_addr); 9299 if (!new_node) { 9300 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9301 if (!new_node) 9302 return -ENOMEM; 9303 9304 new_node->state = HCLGE_MAC_TO_ADD; 9305 ether_addr_copy(new_node->mac_addr, new_addr); 9306 list_add(&new_node->node, list); 9307 } else { 9308 if (new_node->state == HCLGE_MAC_TO_DEL) 9309 new_node->state = HCLGE_MAC_ACTIVE; 9310 9311 /* make sure the new addr is in the list head, avoid dev 9312 * addr may be not re-added into mac table for the umv space 9313 * limitation after global/imp reset which will clear mac 9314 * table by hardware. 9315 */ 9316 list_move(&new_node->node, list); 9317 } 9318 9319 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9320 old_node = hclge_find_mac_node(list, old_addr); 9321 if (old_node) { 9322 if (old_node->state == HCLGE_MAC_TO_ADD) { 9323 list_del(&old_node->node); 9324 kfree(old_node); 9325 } else { 9326 old_node->state = HCLGE_MAC_TO_DEL; 9327 } 9328 } 9329 } 9330 9331 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9332 9333 return 0; 9334 } 9335 9336 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9337 bool is_first) 9338 { 9339 const unsigned char *new_addr = (const unsigned char *)p; 9340 struct hclge_vport *vport = hclge_get_vport(handle); 9341 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9342 struct hclge_dev *hdev = vport->back; 9343 unsigned char *old_addr = NULL; 9344 int ret; 9345 9346 /* mac addr check */ 9347 if (is_zero_ether_addr(new_addr) || 9348 is_broadcast_ether_addr(new_addr) || 9349 is_multicast_ether_addr(new_addr)) { 9350 hnae3_format_mac_addr(format_mac_addr, new_addr); 9351 dev_err(&hdev->pdev->dev, 9352 "change uc mac err! invalid mac: %s.\n", 9353 format_mac_addr); 9354 return -EINVAL; 9355 } 9356 9357 ret = hclge_pause_addr_cfg(hdev, new_addr); 9358 if (ret) { 9359 dev_err(&hdev->pdev->dev, 9360 "failed to configure mac pause address, ret = %d\n", 9361 ret); 9362 return ret; 9363 } 9364 9365 if (!is_first) 9366 old_addr = hdev->hw.mac.mac_addr; 9367 9368 spin_lock_bh(&vport->mac_list_lock); 9369 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9370 if (ret) { 9371 hnae3_format_mac_addr(format_mac_addr, new_addr); 9372 dev_err(&hdev->pdev->dev, 9373 "failed to change the mac addr:%s, ret = %d\n", 9374 format_mac_addr, ret); 9375 spin_unlock_bh(&vport->mac_list_lock); 9376 9377 if (!is_first) 9378 hclge_pause_addr_cfg(hdev, old_addr); 9379 9380 return ret; 9381 } 9382 /* we must update dev addr with spin lock protect, preventing dev addr 9383 * being removed by set_rx_mode path. 9384 */ 9385 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9386 spin_unlock_bh(&vport->mac_list_lock); 9387 9388 hclge_task_schedule(hdev, 0); 9389 9390 return 0; 9391 } 9392 9393 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9394 { 9395 struct mii_ioctl_data *data = if_mii(ifr); 9396 9397 if (!hnae3_dev_phy_imp_supported(hdev)) 9398 return -EOPNOTSUPP; 9399 9400 switch (cmd) { 9401 case SIOCGMIIPHY: 9402 data->phy_id = hdev->hw.mac.phy_addr; 9403 /* this command reads phy id and register at the same time */ 9404 fallthrough; 9405 case SIOCGMIIREG: 9406 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9407 return 0; 9408 9409 case SIOCSMIIREG: 9410 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9411 default: 9412 return -EOPNOTSUPP; 9413 } 9414 } 9415 9416 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9417 int cmd) 9418 { 9419 struct hclge_vport *vport = hclge_get_vport(handle); 9420 struct hclge_dev *hdev = vport->back; 9421 9422 switch (cmd) { 9423 case SIOCGHWTSTAMP: 9424 return hclge_ptp_get_cfg(hdev, ifr); 9425 case SIOCSHWTSTAMP: 9426 return hclge_ptp_set_cfg(hdev, ifr); 9427 default: 9428 if (!hdev->hw.mac.phydev) 9429 return hclge_mii_ioctl(hdev, ifr, cmd); 9430 } 9431 9432 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9433 } 9434 9435 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9436 bool bypass_en) 9437 { 9438 struct hclge_port_vlan_filter_bypass_cmd *req; 9439 struct hclge_desc desc; 9440 int ret; 9441 9442 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9443 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9444 req->vf_id = vf_id; 9445 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9446 bypass_en ? 1 : 0); 9447 9448 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9449 if (ret) 9450 dev_err(&hdev->pdev->dev, 9451 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9452 vf_id, ret); 9453 9454 return ret; 9455 } 9456 9457 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9458 u8 fe_type, bool filter_en, u8 vf_id) 9459 { 9460 struct hclge_vlan_filter_ctrl_cmd *req; 9461 struct hclge_desc desc; 9462 int ret; 9463 9464 /* read current vlan filter parameter */ 9465 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9466 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9467 req->vlan_type = vlan_type; 9468 req->vf_id = vf_id; 9469 9470 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9471 if (ret) { 9472 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9473 vf_id, ret); 9474 return ret; 9475 } 9476 9477 /* modify and write new config parameter */ 9478 hclge_comm_cmd_reuse_desc(&desc, false); 9479 req->vlan_fe = filter_en ? 9480 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9481 9482 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9483 if (ret) 9484 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9485 vf_id, ret); 9486 9487 return ret; 9488 } 9489 9490 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9491 { 9492 struct hclge_dev *hdev = vport->back; 9493 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9494 int ret; 9495 9496 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9497 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9498 HCLGE_FILTER_FE_EGRESS_V1_B, 9499 enable, vport->vport_id); 9500 9501 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9502 HCLGE_FILTER_FE_EGRESS, enable, 9503 vport->vport_id); 9504 if (ret) 9505 return ret; 9506 9507 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9508 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9509 !enable); 9510 } else if (!vport->vport_id) { 9511 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9512 enable = false; 9513 9514 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9515 HCLGE_FILTER_FE_INGRESS, 9516 enable, 0); 9517 } 9518 9519 return ret; 9520 } 9521 9522 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9523 { 9524 struct hnae3_handle *handle = &vport->nic; 9525 struct hclge_vport_vlan_cfg *vlan, *tmp; 9526 struct hclge_dev *hdev = vport->back; 9527 9528 if (vport->vport_id) { 9529 if (vport->port_base_vlan_cfg.state != 9530 HNAE3_PORT_BASE_VLAN_DISABLE) 9531 return true; 9532 9533 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9534 return false; 9535 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9536 return false; 9537 } 9538 9539 if (!vport->req_vlan_fltr_en) 9540 return false; 9541 9542 /* compatible with former device, always enable vlan filter */ 9543 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9544 return true; 9545 9546 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9547 if (vlan->vlan_id != 0) 9548 return true; 9549 9550 return false; 9551 } 9552 9553 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9554 { 9555 struct hclge_dev *hdev = vport->back; 9556 bool need_en; 9557 int ret; 9558 9559 mutex_lock(&hdev->vport_lock); 9560 9561 vport->req_vlan_fltr_en = request_en; 9562 9563 need_en = hclge_need_enable_vport_vlan_filter(vport); 9564 if (need_en == vport->cur_vlan_fltr_en) { 9565 mutex_unlock(&hdev->vport_lock); 9566 return 0; 9567 } 9568 9569 ret = hclge_set_vport_vlan_filter(vport, need_en); 9570 if (ret) { 9571 mutex_unlock(&hdev->vport_lock); 9572 return ret; 9573 } 9574 9575 vport->cur_vlan_fltr_en = need_en; 9576 9577 mutex_unlock(&hdev->vport_lock); 9578 9579 return 0; 9580 } 9581 9582 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9583 { 9584 struct hclge_vport *vport = hclge_get_vport(handle); 9585 9586 return hclge_enable_vport_vlan_filter(vport, enable); 9587 } 9588 9589 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9590 bool is_kill, u16 vlan, 9591 struct hclge_desc *desc) 9592 { 9593 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9594 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9595 u8 vf_byte_val; 9596 u8 vf_byte_off; 9597 int ret; 9598 9599 hclge_cmd_setup_basic_desc(&desc[0], 9600 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9601 hclge_cmd_setup_basic_desc(&desc[1], 9602 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9603 9604 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9605 9606 vf_byte_off = vfid / 8; 9607 vf_byte_val = 1 << (vfid % 8); 9608 9609 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9610 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9611 9612 req0->vlan_id = cpu_to_le16(vlan); 9613 req0->vlan_cfg = is_kill; 9614 9615 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9616 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9617 else 9618 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9619 9620 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9621 if (ret) { 9622 dev_err(&hdev->pdev->dev, 9623 "Send vf vlan command fail, ret =%d.\n", 9624 ret); 9625 return ret; 9626 } 9627 9628 return 0; 9629 } 9630 9631 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9632 bool is_kill, struct hclge_desc *desc) 9633 { 9634 struct hclge_vlan_filter_vf_cfg_cmd *req; 9635 9636 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9637 9638 if (!is_kill) { 9639 #define HCLGE_VF_VLAN_NO_ENTRY 2 9640 if (!req->resp_code || req->resp_code == 1) 9641 return 0; 9642 9643 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9644 set_bit(vfid, hdev->vf_vlan_full); 9645 dev_warn(&hdev->pdev->dev, 9646 "vf vlan table is full, vf vlan filter is disabled\n"); 9647 return 0; 9648 } 9649 9650 dev_err(&hdev->pdev->dev, 9651 "Add vf vlan filter fail, ret =%u.\n", 9652 req->resp_code); 9653 } else { 9654 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9655 if (!req->resp_code) 9656 return 0; 9657 9658 /* vf vlan filter is disabled when vf vlan table is full, 9659 * then new vlan id will not be added into vf vlan table. 9660 * Just return 0 without warning, avoid massive verbose 9661 * print logs when unload. 9662 */ 9663 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9664 return 0; 9665 9666 dev_err(&hdev->pdev->dev, 9667 "Kill vf vlan filter fail, ret =%u.\n", 9668 req->resp_code); 9669 } 9670 9671 return -EIO; 9672 } 9673 9674 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9675 bool is_kill, u16 vlan) 9676 { 9677 struct hclge_vport *vport = &hdev->vport[vfid]; 9678 struct hclge_desc desc[2]; 9679 int ret; 9680 9681 /* if vf vlan table is full, firmware will close vf vlan filter, it 9682 * is unable and unnecessary to add new vlan id to vf vlan filter. 9683 * If spoof check is enable, and vf vlan is full, it shouldn't add 9684 * new vlan, because tx packets with these vlan id will be dropped. 9685 */ 9686 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9687 if (vport->vf_info.spoofchk && vlan) { 9688 dev_err(&hdev->pdev->dev, 9689 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9690 return -EPERM; 9691 } 9692 return 0; 9693 } 9694 9695 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9696 if (ret) 9697 return ret; 9698 9699 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9700 } 9701 9702 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9703 u16 vlan_id, bool is_kill) 9704 { 9705 struct hclge_vlan_filter_pf_cfg_cmd *req; 9706 struct hclge_desc desc; 9707 u8 vlan_offset_byte_val; 9708 u8 vlan_offset_byte; 9709 u8 vlan_offset_160; 9710 int ret; 9711 9712 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9713 9714 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9715 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9716 HCLGE_VLAN_BYTE_SIZE; 9717 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9718 9719 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9720 req->vlan_offset = vlan_offset_160; 9721 req->vlan_cfg = is_kill; 9722 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9723 9724 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9725 if (ret) 9726 dev_err(&hdev->pdev->dev, 9727 "port vlan command, send fail, ret =%d.\n", ret); 9728 return ret; 9729 } 9730 9731 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9732 u16 vlan_id, bool is_kill) 9733 { 9734 /* vlan 0 may be added twice when 8021q module is enabled */ 9735 if (!is_kill && !vlan_id && 9736 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9737 return false; 9738 9739 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9740 dev_warn(&hdev->pdev->dev, 9741 "Add port vlan failed, vport %u is already in vlan %u\n", 9742 vport_id, vlan_id); 9743 return false; 9744 } 9745 9746 if (is_kill && 9747 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9748 dev_warn(&hdev->pdev->dev, 9749 "Delete port vlan failed, vport %u is not in vlan %u\n", 9750 vport_id, vlan_id); 9751 return false; 9752 } 9753 9754 return true; 9755 } 9756 9757 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9758 u16 vport_id, u16 vlan_id, 9759 bool is_kill) 9760 { 9761 u16 vport_idx, vport_num = 0; 9762 int ret; 9763 9764 if (is_kill && !vlan_id) 9765 return 0; 9766 9767 if (vlan_id >= VLAN_N_VID) 9768 return -EINVAL; 9769 9770 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9771 if (ret) { 9772 dev_err(&hdev->pdev->dev, 9773 "Set %u vport vlan filter config fail, ret =%d.\n", 9774 vport_id, ret); 9775 return ret; 9776 } 9777 9778 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9779 return 0; 9780 9781 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9782 vport_num++; 9783 9784 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9785 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9786 is_kill); 9787 9788 return ret; 9789 } 9790 9791 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9792 { 9793 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9794 struct hclge_vport_vtag_tx_cfg_cmd *req; 9795 struct hclge_dev *hdev = vport->back; 9796 struct hclge_desc desc; 9797 u16 bmap_index; 9798 int status; 9799 9800 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9801 9802 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9803 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9804 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9805 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9806 vcfg->accept_tag1 ? 1 : 0); 9807 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9808 vcfg->accept_untag1 ? 1 : 0); 9809 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9810 vcfg->accept_tag2 ? 1 : 0); 9811 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9812 vcfg->accept_untag2 ? 1 : 0); 9813 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9814 vcfg->insert_tag1_en ? 1 : 0); 9815 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9816 vcfg->insert_tag2_en ? 1 : 0); 9817 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9818 vcfg->tag_shift_mode_en ? 1 : 0); 9819 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9820 9821 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9822 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9823 HCLGE_VF_NUM_PER_BYTE; 9824 req->vf_bitmap[bmap_index] = 9825 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9826 9827 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9828 if (status) 9829 dev_err(&hdev->pdev->dev, 9830 "Send port txvlan cfg command fail, ret =%d\n", 9831 status); 9832 9833 return status; 9834 } 9835 9836 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9837 { 9838 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9839 struct hclge_vport_vtag_rx_cfg_cmd *req; 9840 struct hclge_dev *hdev = vport->back; 9841 struct hclge_desc desc; 9842 u16 bmap_index; 9843 int status; 9844 9845 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9846 9847 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9848 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9849 vcfg->strip_tag1_en ? 1 : 0); 9850 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9851 vcfg->strip_tag2_en ? 1 : 0); 9852 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9853 vcfg->vlan1_vlan_prionly ? 1 : 0); 9854 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9855 vcfg->vlan2_vlan_prionly ? 1 : 0); 9856 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9857 vcfg->strip_tag1_discard_en ? 1 : 0); 9858 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9859 vcfg->strip_tag2_discard_en ? 1 : 0); 9860 9861 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9862 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9863 HCLGE_VF_NUM_PER_BYTE; 9864 req->vf_bitmap[bmap_index] = 9865 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9866 9867 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9868 if (status) 9869 dev_err(&hdev->pdev->dev, 9870 "Send port rxvlan cfg command fail, ret =%d\n", 9871 status); 9872 9873 return status; 9874 } 9875 9876 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9877 u16 port_base_vlan_state, 9878 u16 vlan_tag, u8 qos) 9879 { 9880 int ret; 9881 9882 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9883 vport->txvlan_cfg.accept_tag1 = true; 9884 vport->txvlan_cfg.insert_tag1_en = false; 9885 vport->txvlan_cfg.default_tag1 = 0; 9886 } else { 9887 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9888 9889 vport->txvlan_cfg.accept_tag1 = 9890 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9891 vport->txvlan_cfg.insert_tag1_en = true; 9892 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9893 vlan_tag; 9894 } 9895 9896 vport->txvlan_cfg.accept_untag1 = true; 9897 9898 /* accept_tag2 and accept_untag2 are not supported on 9899 * pdev revision(0x20), new revision support them, 9900 * this two fields can not be configured by user. 9901 */ 9902 vport->txvlan_cfg.accept_tag2 = true; 9903 vport->txvlan_cfg.accept_untag2 = true; 9904 vport->txvlan_cfg.insert_tag2_en = false; 9905 vport->txvlan_cfg.default_tag2 = 0; 9906 vport->txvlan_cfg.tag_shift_mode_en = true; 9907 9908 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9909 vport->rxvlan_cfg.strip_tag1_en = false; 9910 vport->rxvlan_cfg.strip_tag2_en = 9911 vport->rxvlan_cfg.rx_vlan_offload_en; 9912 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9913 } else { 9914 vport->rxvlan_cfg.strip_tag1_en = 9915 vport->rxvlan_cfg.rx_vlan_offload_en; 9916 vport->rxvlan_cfg.strip_tag2_en = true; 9917 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9918 } 9919 9920 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9921 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9922 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9923 9924 ret = hclge_set_vlan_tx_offload_cfg(vport); 9925 if (ret) 9926 return ret; 9927 9928 return hclge_set_vlan_rx_offload_cfg(vport); 9929 } 9930 9931 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9932 { 9933 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9934 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9935 struct hclge_desc desc; 9936 int status; 9937 9938 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9939 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9940 rx_req->ot_fst_vlan_type = 9941 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9942 rx_req->ot_sec_vlan_type = 9943 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9944 rx_req->in_fst_vlan_type = 9945 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9946 rx_req->in_sec_vlan_type = 9947 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9948 9949 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9950 if (status) { 9951 dev_err(&hdev->pdev->dev, 9952 "Send rxvlan protocol type command fail, ret =%d\n", 9953 status); 9954 return status; 9955 } 9956 9957 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9958 9959 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9960 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9961 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9962 9963 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9964 if (status) 9965 dev_err(&hdev->pdev->dev, 9966 "Send txvlan protocol type command fail, ret =%d\n", 9967 status); 9968 9969 return status; 9970 } 9971 9972 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9973 { 9974 struct hclge_vport *vport; 9975 bool enable = true; 9976 int ret; 9977 int i; 9978 9979 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9980 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9981 HCLGE_FILTER_FE_EGRESS_V1_B, 9982 true, 0); 9983 9984 /* for revision 0x21, vf vlan filter is per function */ 9985 for (i = 0; i < hdev->num_alloc_vport; i++) { 9986 vport = &hdev->vport[i]; 9987 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9988 HCLGE_FILTER_FE_EGRESS, true, 9989 vport->vport_id); 9990 if (ret) 9991 return ret; 9992 vport->cur_vlan_fltr_en = true; 9993 } 9994 9995 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 9996 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 9997 enable = false; 9998 9999 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 10000 HCLGE_FILTER_FE_INGRESS, enable, 0); 10001 } 10002 10003 static int hclge_init_vlan_type(struct hclge_dev *hdev) 10004 { 10005 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 10006 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 10007 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 10008 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 10009 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 10010 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 10011 10012 return hclge_set_vlan_protocol_type(hdev); 10013 } 10014 10015 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 10016 { 10017 struct hclge_port_base_vlan_config *cfg; 10018 struct hclge_vport *vport; 10019 int ret; 10020 int i; 10021 10022 for (i = 0; i < hdev->num_alloc_vport; i++) { 10023 vport = &hdev->vport[i]; 10024 cfg = &vport->port_base_vlan_cfg; 10025 10026 ret = hclge_vlan_offload_cfg(vport, cfg->state, 10027 cfg->vlan_info.vlan_tag, 10028 cfg->vlan_info.qos); 10029 if (ret) 10030 return ret; 10031 } 10032 return 0; 10033 } 10034 10035 static int hclge_init_vlan_config(struct hclge_dev *hdev) 10036 { 10037 struct hnae3_handle *handle = &hdev->vport[0].nic; 10038 int ret; 10039 10040 ret = hclge_init_vlan_filter(hdev); 10041 if (ret) 10042 return ret; 10043 10044 ret = hclge_init_vlan_type(hdev); 10045 if (ret) 10046 return ret; 10047 10048 ret = hclge_init_vport_vlan_offload(hdev); 10049 if (ret) 10050 return ret; 10051 10052 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 10053 } 10054 10055 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10056 bool writen_to_tbl) 10057 { 10058 struct hclge_vport_vlan_cfg *vlan, *tmp; 10059 struct hclge_dev *hdev = vport->back; 10060 10061 mutex_lock(&hdev->vport_lock); 10062 10063 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10064 if (vlan->vlan_id == vlan_id) { 10065 mutex_unlock(&hdev->vport_lock); 10066 return; 10067 } 10068 } 10069 10070 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10071 if (!vlan) { 10072 mutex_unlock(&hdev->vport_lock); 10073 return; 10074 } 10075 10076 vlan->hd_tbl_status = writen_to_tbl; 10077 vlan->vlan_id = vlan_id; 10078 10079 list_add_tail(&vlan->node, &vport->vlan_list); 10080 mutex_unlock(&hdev->vport_lock); 10081 } 10082 10083 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10084 { 10085 struct hclge_vport_vlan_cfg *vlan, *tmp; 10086 struct hclge_dev *hdev = vport->back; 10087 int ret; 10088 10089 mutex_lock(&hdev->vport_lock); 10090 10091 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10092 if (!vlan->hd_tbl_status) { 10093 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10094 vport->vport_id, 10095 vlan->vlan_id, false); 10096 if (ret) { 10097 dev_err(&hdev->pdev->dev, 10098 "restore vport vlan list failed, ret=%d\n", 10099 ret); 10100 10101 mutex_unlock(&hdev->vport_lock); 10102 return ret; 10103 } 10104 } 10105 vlan->hd_tbl_status = true; 10106 } 10107 10108 mutex_unlock(&hdev->vport_lock); 10109 10110 return 0; 10111 } 10112 10113 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10114 bool is_write_tbl) 10115 { 10116 struct hclge_vport_vlan_cfg *vlan, *tmp; 10117 struct hclge_dev *hdev = vport->back; 10118 10119 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10120 if (vlan->vlan_id == vlan_id) { 10121 if (is_write_tbl && vlan->hd_tbl_status) 10122 hclge_set_vlan_filter_hw(hdev, 10123 htons(ETH_P_8021Q), 10124 vport->vport_id, 10125 vlan_id, 10126 true); 10127 10128 list_del(&vlan->node); 10129 kfree(vlan); 10130 break; 10131 } 10132 } 10133 } 10134 10135 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10136 { 10137 struct hclge_vport_vlan_cfg *vlan, *tmp; 10138 struct hclge_dev *hdev = vport->back; 10139 10140 mutex_lock(&hdev->vport_lock); 10141 10142 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10143 if (vlan->hd_tbl_status) 10144 hclge_set_vlan_filter_hw(hdev, 10145 htons(ETH_P_8021Q), 10146 vport->vport_id, 10147 vlan->vlan_id, 10148 true); 10149 10150 vlan->hd_tbl_status = false; 10151 if (is_del_list) { 10152 list_del(&vlan->node); 10153 kfree(vlan); 10154 } 10155 } 10156 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10157 mutex_unlock(&hdev->vport_lock); 10158 } 10159 10160 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10161 { 10162 struct hclge_vport_vlan_cfg *vlan, *tmp; 10163 struct hclge_vport *vport; 10164 int i; 10165 10166 mutex_lock(&hdev->vport_lock); 10167 10168 for (i = 0; i < hdev->num_alloc_vport; i++) { 10169 vport = &hdev->vport[i]; 10170 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10171 list_del(&vlan->node); 10172 kfree(vlan); 10173 } 10174 } 10175 10176 mutex_unlock(&hdev->vport_lock); 10177 } 10178 10179 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10180 { 10181 struct hclge_vlan_info *vlan_info; 10182 struct hclge_vport *vport; 10183 u16 vlan_proto; 10184 u16 vlan_id; 10185 u16 state; 10186 int vf_id; 10187 int ret; 10188 10189 /* PF should restore all vfs port base vlan */ 10190 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10191 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10192 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10193 &vport->port_base_vlan_cfg.vlan_info : 10194 &vport->port_base_vlan_cfg.old_vlan_info; 10195 10196 vlan_id = vlan_info->vlan_tag; 10197 vlan_proto = vlan_info->vlan_proto; 10198 state = vport->port_base_vlan_cfg.state; 10199 10200 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10201 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10202 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10203 vport->vport_id, 10204 vlan_id, false); 10205 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10206 } 10207 } 10208 } 10209 10210 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10211 { 10212 struct hclge_vport_vlan_cfg *vlan, *tmp; 10213 struct hclge_dev *hdev = vport->back; 10214 int ret; 10215 10216 mutex_lock(&hdev->vport_lock); 10217 10218 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10219 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10220 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10221 vport->vport_id, 10222 vlan->vlan_id, false); 10223 if (ret) 10224 break; 10225 vlan->hd_tbl_status = true; 10226 } 10227 } 10228 10229 mutex_unlock(&hdev->vport_lock); 10230 } 10231 10232 /* For global reset and imp reset, hardware will clear the mac table, 10233 * so we change the mac address state from ACTIVE to TO_ADD, then they 10234 * can be restored in the service task after reset complete. Furtherly, 10235 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10236 * be restored after reset, so just remove these mac nodes from mac_list. 10237 */ 10238 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10239 { 10240 struct hclge_mac_node *mac_node, *tmp; 10241 10242 list_for_each_entry_safe(mac_node, tmp, list, node) { 10243 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10244 mac_node->state = HCLGE_MAC_TO_ADD; 10245 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10246 list_del(&mac_node->node); 10247 kfree(mac_node); 10248 } 10249 } 10250 } 10251 10252 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10253 { 10254 spin_lock_bh(&vport->mac_list_lock); 10255 10256 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10257 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10258 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10259 10260 spin_unlock_bh(&vport->mac_list_lock); 10261 } 10262 10263 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10264 { 10265 struct hclge_vport *vport = &hdev->vport[0]; 10266 struct hnae3_handle *handle = &vport->nic; 10267 10268 hclge_restore_mac_table_common(vport); 10269 hclge_restore_vport_port_base_vlan_config(hdev); 10270 hclge_restore_vport_vlan_table(vport); 10271 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10272 hclge_restore_fd_entries(handle); 10273 } 10274 10275 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10276 { 10277 struct hclge_vport *vport = hclge_get_vport(handle); 10278 10279 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10280 vport->rxvlan_cfg.strip_tag1_en = false; 10281 vport->rxvlan_cfg.strip_tag2_en = enable; 10282 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10283 } else { 10284 vport->rxvlan_cfg.strip_tag1_en = enable; 10285 vport->rxvlan_cfg.strip_tag2_en = true; 10286 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10287 } 10288 10289 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10290 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10291 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10292 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10293 10294 return hclge_set_vlan_rx_offload_cfg(vport); 10295 } 10296 10297 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10298 { 10299 struct hclge_dev *hdev = vport->back; 10300 10301 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10302 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10303 } 10304 10305 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10306 u16 port_base_vlan_state, 10307 struct hclge_vlan_info *new_info, 10308 struct hclge_vlan_info *old_info) 10309 { 10310 struct hclge_dev *hdev = vport->back; 10311 int ret; 10312 10313 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10314 hclge_rm_vport_all_vlan_table(vport, false); 10315 /* force clear VLAN 0 */ 10316 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10317 if (ret) 10318 return ret; 10319 return hclge_set_vlan_filter_hw(hdev, 10320 htons(new_info->vlan_proto), 10321 vport->vport_id, 10322 new_info->vlan_tag, 10323 false); 10324 } 10325 10326 vport->port_base_vlan_cfg.tbl_sta = false; 10327 10328 /* force add VLAN 0 */ 10329 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10330 if (ret) 10331 return ret; 10332 10333 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10334 vport->vport_id, old_info->vlan_tag, 10335 true); 10336 if (ret) 10337 return ret; 10338 10339 return hclge_add_vport_all_vlan_table(vport); 10340 } 10341 10342 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10343 const struct hclge_vlan_info *old_cfg) 10344 { 10345 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10346 return true; 10347 10348 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10349 return true; 10350 10351 return false; 10352 } 10353 10354 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10355 struct hclge_vlan_info *new_info, 10356 struct hclge_vlan_info *old_info) 10357 { 10358 struct hclge_dev *hdev = vport->back; 10359 int ret; 10360 10361 /* add new VLAN tag */ 10362 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10363 vport->vport_id, new_info->vlan_tag, 10364 false); 10365 if (ret) 10366 return ret; 10367 10368 vport->port_base_vlan_cfg.tbl_sta = false; 10369 /* remove old VLAN tag */ 10370 if (old_info->vlan_tag == 0) 10371 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10372 true, 0); 10373 else 10374 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10375 vport->vport_id, 10376 old_info->vlan_tag, true); 10377 if (ret) 10378 dev_err(&hdev->pdev->dev, 10379 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10380 vport->vport_id, old_info->vlan_tag, ret); 10381 10382 return ret; 10383 } 10384 10385 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10386 struct hclge_vlan_info *vlan_info) 10387 { 10388 struct hnae3_handle *nic = &vport->nic; 10389 struct hclge_vlan_info *old_vlan_info; 10390 int ret; 10391 10392 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10393 10394 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10395 vlan_info->qos); 10396 if (ret) 10397 return ret; 10398 10399 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10400 goto out; 10401 10402 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10403 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10404 old_vlan_info); 10405 else 10406 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10407 old_vlan_info); 10408 if (ret) 10409 return ret; 10410 10411 out: 10412 vport->port_base_vlan_cfg.state = state; 10413 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10414 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10415 else 10416 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10417 10418 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10419 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10420 vport->port_base_vlan_cfg.tbl_sta = true; 10421 hclge_set_vport_vlan_fltr_change(vport); 10422 10423 return 0; 10424 } 10425 10426 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10427 enum hnae3_port_base_vlan_state state, 10428 u16 vlan, u8 qos) 10429 { 10430 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10431 if (!vlan && !qos) 10432 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10433 10434 return HNAE3_PORT_BASE_VLAN_ENABLE; 10435 } 10436 10437 if (!vlan && !qos) 10438 return HNAE3_PORT_BASE_VLAN_DISABLE; 10439 10440 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10441 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10442 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10443 10444 return HNAE3_PORT_BASE_VLAN_MODIFY; 10445 } 10446 10447 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10448 u16 vlan, u8 qos, __be16 proto) 10449 { 10450 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10451 struct hclge_vport *vport = hclge_get_vport(handle); 10452 struct hclge_dev *hdev = vport->back; 10453 struct hclge_vlan_info vlan_info; 10454 u16 state; 10455 int ret; 10456 10457 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10458 return -EOPNOTSUPP; 10459 10460 vport = hclge_get_vf_vport(hdev, vfid); 10461 if (!vport) 10462 return -EINVAL; 10463 10464 /* qos is a 3 bits value, so can not be bigger than 7 */ 10465 if (vlan > VLAN_N_VID - 1 || qos > 7) 10466 return -EINVAL; 10467 if (proto != htons(ETH_P_8021Q)) 10468 return -EPROTONOSUPPORT; 10469 10470 state = hclge_get_port_base_vlan_state(vport, 10471 vport->port_base_vlan_cfg.state, 10472 vlan, qos); 10473 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10474 return 0; 10475 10476 vlan_info.vlan_tag = vlan; 10477 vlan_info.qos = qos; 10478 vlan_info.vlan_proto = ntohs(proto); 10479 10480 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10481 if (ret) { 10482 dev_err(&hdev->pdev->dev, 10483 "failed to update port base vlan for vf %d, ret = %d\n", 10484 vfid, ret); 10485 return ret; 10486 } 10487 10488 /* there is a timewindow for PF to know VF unalive, it may 10489 * cause send mailbox fail, but it doesn't matter, VF will 10490 * query it when reinit. 10491 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10492 * VLAN state. 10493 */ 10494 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10495 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10496 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10497 vport->vport_id, 10498 state, 10499 &vlan_info); 10500 else 10501 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10502 &vport->need_notify); 10503 } 10504 return 0; 10505 } 10506 10507 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10508 { 10509 struct hclge_vlan_info *vlan_info; 10510 struct hclge_vport *vport; 10511 int ret; 10512 int vf; 10513 10514 /* clear port base vlan for all vf */ 10515 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10516 vport = &hdev->vport[vf]; 10517 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10518 10519 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10520 vport->vport_id, 10521 vlan_info->vlan_tag, true); 10522 if (ret) 10523 dev_err(&hdev->pdev->dev, 10524 "failed to clear vf vlan for vf%d, ret = %d\n", 10525 vf - HCLGE_VF_VPORT_START_NUM, ret); 10526 } 10527 } 10528 10529 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10530 u16 vlan_id, bool is_kill) 10531 { 10532 struct hclge_vport *vport = hclge_get_vport(handle); 10533 struct hclge_dev *hdev = vport->back; 10534 bool writen_to_tbl = false; 10535 int ret = 0; 10536 10537 /* When device is resetting or reset failed, firmware is unable to 10538 * handle mailbox. Just record the vlan id, and remove it after 10539 * reset finished. 10540 */ 10541 mutex_lock(&hdev->vport_lock); 10542 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10543 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10544 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10545 mutex_unlock(&hdev->vport_lock); 10546 return -EBUSY; 10547 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 10548 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10549 } 10550 mutex_unlock(&hdev->vport_lock); 10551 10552 /* when port base vlan enabled, we use port base vlan as the vlan 10553 * filter entry. In this case, we don't update vlan filter table 10554 * when user add new vlan or remove exist vlan, just update the vport 10555 * vlan list. The vlan id in vlan list will be writen in vlan filter 10556 * table until port base vlan disabled 10557 */ 10558 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10559 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10560 vlan_id, is_kill); 10561 writen_to_tbl = true; 10562 } 10563 10564 if (!ret) { 10565 if (!is_kill) { 10566 hclge_add_vport_vlan_table(vport, vlan_id, 10567 writen_to_tbl); 10568 } else if (is_kill && vlan_id != 0) { 10569 mutex_lock(&hdev->vport_lock); 10570 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10571 mutex_unlock(&hdev->vport_lock); 10572 } 10573 } else if (is_kill) { 10574 /* when remove hw vlan filter failed, record the vlan id, 10575 * and try to remove it from hw later, to be consistence 10576 * with stack 10577 */ 10578 mutex_lock(&hdev->vport_lock); 10579 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10580 mutex_unlock(&hdev->vport_lock); 10581 } 10582 10583 hclge_set_vport_vlan_fltr_change(vport); 10584 10585 return ret; 10586 } 10587 10588 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10589 { 10590 struct hclge_vport *vport; 10591 int ret; 10592 u16 i; 10593 10594 for (i = 0; i < hdev->num_alloc_vport; i++) { 10595 vport = &hdev->vport[i]; 10596 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10597 &vport->state)) 10598 continue; 10599 10600 ret = hclge_enable_vport_vlan_filter(vport, 10601 vport->req_vlan_fltr_en); 10602 if (ret) { 10603 dev_err(&hdev->pdev->dev, 10604 "failed to sync vlan filter state for vport%u, ret = %d\n", 10605 vport->vport_id, ret); 10606 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10607 &vport->state); 10608 return; 10609 } 10610 } 10611 } 10612 10613 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10614 { 10615 #define HCLGE_MAX_SYNC_COUNT 60 10616 10617 int i, ret, sync_cnt = 0; 10618 u16 vlan_id; 10619 10620 mutex_lock(&hdev->vport_lock); 10621 /* start from vport 1 for PF is always alive */ 10622 for (i = 0; i < hdev->num_alloc_vport; i++) { 10623 struct hclge_vport *vport = &hdev->vport[i]; 10624 10625 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10626 VLAN_N_VID); 10627 while (vlan_id != VLAN_N_VID) { 10628 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10629 vport->vport_id, vlan_id, 10630 true); 10631 if (ret && ret != -EINVAL) { 10632 mutex_unlock(&hdev->vport_lock); 10633 return; 10634 } 10635 10636 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10637 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10638 hclge_set_vport_vlan_fltr_change(vport); 10639 10640 sync_cnt++; 10641 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 10642 mutex_unlock(&hdev->vport_lock); 10643 return; 10644 } 10645 10646 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10647 VLAN_N_VID); 10648 } 10649 } 10650 mutex_unlock(&hdev->vport_lock); 10651 10652 hclge_sync_vlan_fltr_state(hdev); 10653 } 10654 10655 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10656 { 10657 struct hclge_config_max_frm_size_cmd *req; 10658 struct hclge_desc desc; 10659 10660 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10661 10662 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10663 req->max_frm_size = cpu_to_le16(new_mps); 10664 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10665 10666 return hclge_cmd_send(&hdev->hw, &desc, 1); 10667 } 10668 10669 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10670 { 10671 struct hclge_vport *vport = hclge_get_vport(handle); 10672 10673 return hclge_set_vport_mtu(vport, new_mtu); 10674 } 10675 10676 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10677 { 10678 struct hclge_dev *hdev = vport->back; 10679 int i, max_frm_size, ret; 10680 10681 /* HW supprt 2 layer vlan */ 10682 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10683 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10684 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10685 return -EINVAL; 10686 10687 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10688 mutex_lock(&hdev->vport_lock); 10689 /* VF's mps must fit within hdev->mps */ 10690 if (vport->vport_id && max_frm_size > hdev->mps) { 10691 mutex_unlock(&hdev->vport_lock); 10692 return -EINVAL; 10693 } else if (vport->vport_id) { 10694 vport->mps = max_frm_size; 10695 mutex_unlock(&hdev->vport_lock); 10696 return 0; 10697 } 10698 10699 /* PF's mps must be greater then VF's mps */ 10700 for (i = 1; i < hdev->num_alloc_vport; i++) 10701 if (max_frm_size < hdev->vport[i].mps) { 10702 dev_err(&hdev->pdev->dev, 10703 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10704 i, hdev->vport[i].mps); 10705 mutex_unlock(&hdev->vport_lock); 10706 return -EINVAL; 10707 } 10708 10709 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10710 10711 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10712 if (ret) { 10713 dev_err(&hdev->pdev->dev, 10714 "Change mtu fail, ret =%d\n", ret); 10715 goto out; 10716 } 10717 10718 hdev->mps = max_frm_size; 10719 vport->mps = max_frm_size; 10720 10721 ret = hclge_buffer_alloc(hdev); 10722 if (ret) 10723 dev_err(&hdev->pdev->dev, 10724 "Allocate buffer fail, ret =%d\n", ret); 10725 10726 out: 10727 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10728 mutex_unlock(&hdev->vport_lock); 10729 return ret; 10730 } 10731 10732 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10733 bool enable) 10734 { 10735 struct hclge_reset_tqp_queue_cmd *req; 10736 struct hclge_desc desc; 10737 int ret; 10738 10739 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10740 10741 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10742 req->tqp_id = cpu_to_le16(queue_id); 10743 if (enable) 10744 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10745 10746 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10747 if (ret) { 10748 dev_err(&hdev->pdev->dev, 10749 "Send tqp reset cmd error, status =%d\n", ret); 10750 return ret; 10751 } 10752 10753 return 0; 10754 } 10755 10756 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10757 u8 *reset_status) 10758 { 10759 struct hclge_reset_tqp_queue_cmd *req; 10760 struct hclge_desc desc; 10761 int ret; 10762 10763 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10764 10765 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10766 req->tqp_id = cpu_to_le16(queue_id); 10767 10768 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10769 if (ret) { 10770 dev_err(&hdev->pdev->dev, 10771 "Get reset status error, status =%d\n", ret); 10772 return ret; 10773 } 10774 10775 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10776 10777 return 0; 10778 } 10779 10780 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10781 { 10782 struct hclge_comm_tqp *tqp; 10783 struct hnae3_queue *queue; 10784 10785 queue = handle->kinfo.tqp[queue_id]; 10786 tqp = container_of(queue, struct hclge_comm_tqp, q); 10787 10788 return tqp->index; 10789 } 10790 10791 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10792 { 10793 struct hclge_vport *vport = hclge_get_vport(handle); 10794 struct hclge_dev *hdev = vport->back; 10795 u16 reset_try_times = 0; 10796 u8 reset_status; 10797 u16 queue_gid; 10798 int ret; 10799 u16 i; 10800 10801 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10802 queue_gid = hclge_covert_handle_qid_global(handle, i); 10803 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10804 if (ret) { 10805 dev_err(&hdev->pdev->dev, 10806 "failed to send reset tqp cmd, ret = %d\n", 10807 ret); 10808 return ret; 10809 } 10810 10811 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10812 ret = hclge_get_reset_status(hdev, queue_gid, 10813 &reset_status); 10814 if (ret) 10815 return ret; 10816 10817 if (reset_status) 10818 break; 10819 10820 /* Wait for tqp hw reset */ 10821 usleep_range(1000, 1200); 10822 } 10823 10824 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10825 dev_err(&hdev->pdev->dev, 10826 "wait for tqp hw reset timeout\n"); 10827 return -ETIME; 10828 } 10829 10830 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10831 if (ret) { 10832 dev_err(&hdev->pdev->dev, 10833 "failed to deassert soft reset, ret = %d\n", 10834 ret); 10835 return ret; 10836 } 10837 reset_try_times = 0; 10838 } 10839 return 0; 10840 } 10841 10842 static int hclge_reset_rcb(struct hnae3_handle *handle) 10843 { 10844 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10845 #define HCLGE_RESET_RCB_SUCCESS 1U 10846 10847 struct hclge_vport *vport = hclge_get_vport(handle); 10848 struct hclge_dev *hdev = vport->back; 10849 struct hclge_reset_cmd *req; 10850 struct hclge_desc desc; 10851 u8 return_status; 10852 u16 queue_gid; 10853 int ret; 10854 10855 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10856 10857 req = (struct hclge_reset_cmd *)desc.data; 10858 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10859 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10860 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10861 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10862 10863 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10864 if (ret) { 10865 dev_err(&hdev->pdev->dev, 10866 "failed to send rcb reset cmd, ret = %d\n", ret); 10867 return ret; 10868 } 10869 10870 return_status = req->fun_reset_rcb_return_status; 10871 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10872 return 0; 10873 10874 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10875 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10876 return_status); 10877 return -EIO; 10878 } 10879 10880 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10881 * again to reset all tqps 10882 */ 10883 return hclge_reset_tqp_cmd(handle); 10884 } 10885 10886 int hclge_reset_tqp(struct hnae3_handle *handle) 10887 { 10888 struct hclge_vport *vport = hclge_get_vport(handle); 10889 struct hclge_dev *hdev = vport->back; 10890 int ret; 10891 10892 /* only need to disable PF's tqp */ 10893 if (!vport->vport_id) { 10894 ret = hclge_tqp_enable(handle, false); 10895 if (ret) { 10896 dev_err(&hdev->pdev->dev, 10897 "failed to disable tqp, ret = %d\n", ret); 10898 return ret; 10899 } 10900 } 10901 10902 return hclge_reset_rcb(handle); 10903 } 10904 10905 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10906 { 10907 struct hclge_vport *vport = hclge_get_vport(handle); 10908 struct hclge_dev *hdev = vport->back; 10909 10910 return hdev->fw_version; 10911 } 10912 10913 int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version) 10914 { 10915 struct hclge_comm_query_scc_cmd *resp; 10916 struct hclge_desc desc; 10917 int ret; 10918 10919 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_SCC_VER, 1); 10920 resp = (struct hclge_comm_query_scc_cmd *)desc.data; 10921 10922 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10923 if (ret) 10924 return ret; 10925 10926 *scc_version = le32_to_cpu(resp->scc_version); 10927 10928 return 0; 10929 } 10930 10931 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10932 { 10933 struct phy_device *phydev = hdev->hw.mac.phydev; 10934 10935 if (!phydev) 10936 return; 10937 10938 phy_set_asym_pause(phydev, rx_en, tx_en); 10939 } 10940 10941 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10942 { 10943 int ret; 10944 10945 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10946 return 0; 10947 10948 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10949 if (ret) 10950 dev_err(&hdev->pdev->dev, 10951 "configure pauseparam error, ret = %d.\n", ret); 10952 10953 return ret; 10954 } 10955 10956 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10957 { 10958 struct phy_device *phydev = hdev->hw.mac.phydev; 10959 u16 remote_advertising = 0; 10960 u16 local_advertising; 10961 u32 rx_pause, tx_pause; 10962 u8 flowctl; 10963 10964 if (!phydev->link) 10965 return 0; 10966 10967 if (!phydev->autoneg) 10968 return hclge_mac_pause_setup_hw(hdev); 10969 10970 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10971 10972 if (phydev->pause) 10973 remote_advertising = LPA_PAUSE_CAP; 10974 10975 if (phydev->asym_pause) 10976 remote_advertising |= LPA_PAUSE_ASYM; 10977 10978 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10979 remote_advertising); 10980 tx_pause = flowctl & FLOW_CTRL_TX; 10981 rx_pause = flowctl & FLOW_CTRL_RX; 10982 10983 if (phydev->duplex == HCLGE_MAC_HALF) { 10984 tx_pause = 0; 10985 rx_pause = 0; 10986 } 10987 10988 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10989 } 10990 10991 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10992 u32 *rx_en, u32 *tx_en) 10993 { 10994 struct hclge_vport *vport = hclge_get_vport(handle); 10995 struct hclge_dev *hdev = vport->back; 10996 u8 media_type = hdev->hw.mac.media_type; 10997 10998 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10999 hclge_get_autoneg(handle) : 0; 11000 11001 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11002 *rx_en = 0; 11003 *tx_en = 0; 11004 return; 11005 } 11006 11007 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 11008 *rx_en = 1; 11009 *tx_en = 0; 11010 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 11011 *tx_en = 1; 11012 *rx_en = 0; 11013 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 11014 *rx_en = 1; 11015 *tx_en = 1; 11016 } else { 11017 *rx_en = 0; 11018 *tx_en = 0; 11019 } 11020 } 11021 11022 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 11023 u32 rx_en, u32 tx_en) 11024 { 11025 if (rx_en && tx_en) 11026 hdev->fc_mode_last_time = HCLGE_FC_FULL; 11027 else if (rx_en && !tx_en) 11028 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 11029 else if (!rx_en && tx_en) 11030 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 11031 else 11032 hdev->fc_mode_last_time = HCLGE_FC_NONE; 11033 11034 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 11035 } 11036 11037 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 11038 u32 rx_en, u32 tx_en) 11039 { 11040 struct hclge_vport *vport = hclge_get_vport(handle); 11041 struct hclge_dev *hdev = vport->back; 11042 struct phy_device *phydev = hdev->hw.mac.phydev; 11043 u32 fc_autoneg; 11044 11045 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 11046 fc_autoneg = hclge_get_autoneg(handle); 11047 if (auto_neg != fc_autoneg) { 11048 dev_info(&hdev->pdev->dev, 11049 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 11050 return -EOPNOTSUPP; 11051 } 11052 } 11053 11054 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11055 dev_info(&hdev->pdev->dev, 11056 "Priority flow control enabled. Cannot set link flow control.\n"); 11057 return -EOPNOTSUPP; 11058 } 11059 11060 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 11061 11062 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 11063 11064 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 11065 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 11066 11067 if (phydev) 11068 return phy_start_aneg(phydev); 11069 11070 return -EOPNOTSUPP; 11071 } 11072 11073 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 11074 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 11075 { 11076 struct hclge_vport *vport = hclge_get_vport(handle); 11077 struct hclge_dev *hdev = vport->back; 11078 11079 if (speed) 11080 *speed = hdev->hw.mac.speed; 11081 if (duplex) 11082 *duplex = hdev->hw.mac.duplex; 11083 if (auto_neg) 11084 *auto_neg = hdev->hw.mac.autoneg; 11085 if (lane_num) 11086 *lane_num = hdev->hw.mac.lane_num; 11087 } 11088 11089 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11090 u8 *module_type) 11091 { 11092 struct hclge_vport *vport = hclge_get_vport(handle); 11093 struct hclge_dev *hdev = vport->back; 11094 11095 /* When nic is down, the service task is not running, doesn't update 11096 * the port information per second. Query the port information before 11097 * return the media type, ensure getting the correct media information. 11098 */ 11099 hclge_update_port_info(hdev); 11100 11101 if (media_type) 11102 *media_type = hdev->hw.mac.media_type; 11103 11104 if (module_type) 11105 *module_type = hdev->hw.mac.module_type; 11106 } 11107 11108 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11109 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11110 { 11111 struct hclge_vport *vport = hclge_get_vport(handle); 11112 struct hclge_dev *hdev = vport->back; 11113 struct phy_device *phydev = hdev->hw.mac.phydev; 11114 int mdix_ctrl, mdix, is_resolved; 11115 unsigned int retval; 11116 11117 if (!phydev) { 11118 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11119 *tp_mdix = ETH_TP_MDI_INVALID; 11120 return; 11121 } 11122 11123 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11124 11125 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11126 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11127 HCLGE_PHY_MDIX_CTRL_S); 11128 11129 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11130 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11131 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11132 11133 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11134 11135 switch (mdix_ctrl) { 11136 case 0x0: 11137 *tp_mdix_ctrl = ETH_TP_MDI; 11138 break; 11139 case 0x1: 11140 *tp_mdix_ctrl = ETH_TP_MDI_X; 11141 break; 11142 case 0x3: 11143 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11144 break; 11145 default: 11146 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11147 break; 11148 } 11149 11150 if (!is_resolved) 11151 *tp_mdix = ETH_TP_MDI_INVALID; 11152 else if (mdix) 11153 *tp_mdix = ETH_TP_MDI_X; 11154 else 11155 *tp_mdix = ETH_TP_MDI; 11156 } 11157 11158 static void hclge_info_show(struct hclge_dev *hdev) 11159 { 11160 struct hnae3_handle *handle = &hdev->vport->nic; 11161 struct device *dev = &hdev->pdev->dev; 11162 11163 dev_info(dev, "PF info begin:\n"); 11164 11165 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11166 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11167 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11168 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11169 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11170 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11171 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11172 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11173 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11174 dev_info(dev, "This is %s PF\n", 11175 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11176 dev_info(dev, "DCB %s\n", 11177 handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable"); 11178 dev_info(dev, "MQPRIO %s\n", 11179 handle->kinfo.tc_info.mqprio_active ? "enable" : "disable"); 11180 dev_info(dev, "Default tx spare buffer size: %u\n", 11181 hdev->tx_spare_buf_size); 11182 11183 dev_info(dev, "PF info end.\n"); 11184 } 11185 11186 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11187 struct hclge_vport *vport) 11188 { 11189 struct hnae3_client *client = vport->nic.client; 11190 struct hclge_dev *hdev = ae_dev->priv; 11191 int rst_cnt = hdev->rst_stats.reset_cnt; 11192 int ret; 11193 11194 ret = client->ops->init_instance(&vport->nic); 11195 if (ret) 11196 return ret; 11197 11198 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11199 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11200 rst_cnt != hdev->rst_stats.reset_cnt) { 11201 ret = -EBUSY; 11202 goto init_nic_err; 11203 } 11204 11205 /* Enable nic hw error interrupts */ 11206 ret = hclge_config_nic_hw_error(hdev, true); 11207 if (ret) { 11208 dev_err(&ae_dev->pdev->dev, 11209 "fail(%d) to enable hw error interrupts\n", ret); 11210 goto init_nic_err; 11211 } 11212 11213 hnae3_set_client_init_flag(client, ae_dev, 1); 11214 11215 if (netif_msg_drv(&hdev->vport->nic)) 11216 hclge_info_show(hdev); 11217 11218 return ret; 11219 11220 init_nic_err: 11221 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11222 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11223 msleep(HCLGE_WAIT_RESET_DONE); 11224 11225 client->ops->uninit_instance(&vport->nic, 0); 11226 11227 return ret; 11228 } 11229 11230 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11231 struct hclge_vport *vport) 11232 { 11233 struct hclge_dev *hdev = ae_dev->priv; 11234 struct hnae3_client *client; 11235 int rst_cnt; 11236 int ret; 11237 11238 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11239 !hdev->nic_client) 11240 return 0; 11241 11242 client = hdev->roce_client; 11243 ret = hclge_init_roce_base_info(vport); 11244 if (ret) 11245 return ret; 11246 11247 rst_cnt = hdev->rst_stats.reset_cnt; 11248 ret = client->ops->init_instance(&vport->roce); 11249 if (ret) 11250 return ret; 11251 11252 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11253 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11254 rst_cnt != hdev->rst_stats.reset_cnt) { 11255 ret = -EBUSY; 11256 goto init_roce_err; 11257 } 11258 11259 /* Enable roce ras interrupts */ 11260 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11261 if (ret) { 11262 dev_err(&ae_dev->pdev->dev, 11263 "fail(%d) to enable roce ras interrupts\n", ret); 11264 goto init_roce_err; 11265 } 11266 11267 hnae3_set_client_init_flag(client, ae_dev, 1); 11268 11269 return 0; 11270 11271 init_roce_err: 11272 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11273 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11274 msleep(HCLGE_WAIT_RESET_DONE); 11275 11276 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11277 11278 return ret; 11279 } 11280 11281 static int hclge_init_client_instance(struct hnae3_client *client, 11282 struct hnae3_ae_dev *ae_dev) 11283 { 11284 struct hclge_dev *hdev = ae_dev->priv; 11285 struct hclge_vport *vport = &hdev->vport[0]; 11286 int ret; 11287 11288 switch (client->type) { 11289 case HNAE3_CLIENT_KNIC: 11290 hdev->nic_client = client; 11291 vport->nic.client = client; 11292 ret = hclge_init_nic_client_instance(ae_dev, vport); 11293 if (ret) 11294 goto clear_nic; 11295 11296 ret = hclge_init_roce_client_instance(ae_dev, vport); 11297 if (ret) 11298 goto clear_roce; 11299 11300 break; 11301 case HNAE3_CLIENT_ROCE: 11302 if (hnae3_dev_roce_supported(hdev)) { 11303 hdev->roce_client = client; 11304 vport->roce.client = client; 11305 } 11306 11307 ret = hclge_init_roce_client_instance(ae_dev, vport); 11308 if (ret) 11309 goto clear_roce; 11310 11311 break; 11312 default: 11313 return -EINVAL; 11314 } 11315 11316 return 0; 11317 11318 clear_nic: 11319 hdev->nic_client = NULL; 11320 vport->nic.client = NULL; 11321 return ret; 11322 clear_roce: 11323 hdev->roce_client = NULL; 11324 vport->roce.client = NULL; 11325 return ret; 11326 } 11327 11328 static bool hclge_uninit_need_wait(struct hclge_dev *hdev) 11329 { 11330 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11331 test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 11332 } 11333 11334 static void hclge_uninit_client_instance(struct hnae3_client *client, 11335 struct hnae3_ae_dev *ae_dev) 11336 { 11337 struct hclge_dev *hdev = ae_dev->priv; 11338 struct hclge_vport *vport = &hdev->vport[0]; 11339 11340 if (hdev->roce_client) { 11341 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11342 while (hclge_uninit_need_wait(hdev)) 11343 msleep(HCLGE_WAIT_RESET_DONE); 11344 11345 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11346 hdev->roce_client = NULL; 11347 vport->roce.client = NULL; 11348 } 11349 if (client->type == HNAE3_CLIENT_ROCE) 11350 return; 11351 if (hdev->nic_client && client->ops->uninit_instance) { 11352 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11353 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11354 msleep(HCLGE_WAIT_RESET_DONE); 11355 11356 client->ops->uninit_instance(&vport->nic, 0); 11357 hdev->nic_client = NULL; 11358 vport->nic.client = NULL; 11359 } 11360 } 11361 11362 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11363 { 11364 struct pci_dev *pdev = hdev->pdev; 11365 struct hclge_hw *hw = &hdev->hw; 11366 11367 /* for device does not have device memory, return directly */ 11368 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11369 return 0; 11370 11371 hw->hw.mem_base = 11372 devm_ioremap_wc(&pdev->dev, 11373 pci_resource_start(pdev, HCLGE_MEM_BAR), 11374 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11375 if (!hw->hw.mem_base) { 11376 dev_err(&pdev->dev, "failed to map device memory\n"); 11377 return -EFAULT; 11378 } 11379 11380 return 0; 11381 } 11382 11383 static int hclge_pci_init(struct hclge_dev *hdev) 11384 { 11385 struct pci_dev *pdev = hdev->pdev; 11386 struct hclge_hw *hw; 11387 int ret; 11388 11389 ret = pci_enable_device(pdev); 11390 if (ret) { 11391 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11392 return ret; 11393 } 11394 11395 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11396 if (ret) { 11397 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11398 if (ret) { 11399 dev_err(&pdev->dev, 11400 "can't set consistent PCI DMA"); 11401 goto err_disable_device; 11402 } 11403 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11404 } 11405 11406 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11407 if (ret) { 11408 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11409 goto err_disable_device; 11410 } 11411 11412 pci_set_master(pdev); 11413 hw = &hdev->hw; 11414 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11415 if (!hw->hw.io_base) { 11416 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11417 ret = -ENOMEM; 11418 goto err_release_regions; 11419 } 11420 11421 ret = hclge_dev_mem_map(hdev); 11422 if (ret) 11423 goto err_unmap_io_base; 11424 11425 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11426 11427 return 0; 11428 11429 err_unmap_io_base: 11430 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11431 err_release_regions: 11432 pci_release_regions(pdev); 11433 err_disable_device: 11434 pci_disable_device(pdev); 11435 11436 return ret; 11437 } 11438 11439 static void hclge_pci_uninit(struct hclge_dev *hdev) 11440 { 11441 struct pci_dev *pdev = hdev->pdev; 11442 11443 if (hdev->hw.hw.mem_base) 11444 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11445 11446 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11447 pci_free_irq_vectors(pdev); 11448 pci_release_regions(pdev); 11449 pci_disable_device(pdev); 11450 } 11451 11452 static void hclge_state_init(struct hclge_dev *hdev) 11453 { 11454 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11455 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11456 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11457 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11458 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11459 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11460 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11461 } 11462 11463 static void hclge_state_uninit(struct hclge_dev *hdev) 11464 { 11465 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11466 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11467 11468 if (hdev->reset_timer.function) 11469 del_timer_sync(&hdev->reset_timer); 11470 if (hdev->service_task.work.func) 11471 cancel_delayed_work_sync(&hdev->service_task); 11472 } 11473 11474 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11475 enum hnae3_reset_type rst_type) 11476 { 11477 #define HCLGE_RESET_RETRY_WAIT_MS 500 11478 #define HCLGE_RESET_RETRY_CNT 5 11479 11480 struct hclge_dev *hdev = ae_dev->priv; 11481 int retry_cnt = 0; 11482 int ret; 11483 11484 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11485 down(&hdev->reset_sem); 11486 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11487 hdev->reset_type = rst_type; 11488 ret = hclge_reset_prepare(hdev); 11489 if (!ret && !hdev->reset_pending) 11490 break; 11491 11492 dev_err(&hdev->pdev->dev, 11493 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11494 ret, hdev->reset_pending, retry_cnt); 11495 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11496 up(&hdev->reset_sem); 11497 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11498 } 11499 11500 /* disable misc vector before reset done */ 11501 hclge_enable_vector(&hdev->misc_vector, false); 11502 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11503 11504 if (hdev->reset_type == HNAE3_FLR_RESET) 11505 hdev->rst_stats.flr_rst_cnt++; 11506 } 11507 11508 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11509 { 11510 struct hclge_dev *hdev = ae_dev->priv; 11511 int ret; 11512 11513 hclge_enable_vector(&hdev->misc_vector, true); 11514 11515 ret = hclge_reset_rebuild(hdev); 11516 if (ret) 11517 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11518 11519 hdev->reset_type = HNAE3_NONE_RESET; 11520 if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11521 up(&hdev->reset_sem); 11522 } 11523 11524 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11525 { 11526 u16 i; 11527 11528 for (i = 0; i < hdev->num_alloc_vport; i++) { 11529 struct hclge_vport *vport = &hdev->vport[i]; 11530 int ret; 11531 11532 /* Send cmd to clear vport's FUNC_RST_ING */ 11533 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11534 if (ret) 11535 dev_warn(&hdev->pdev->dev, 11536 "clear vport(%u) rst failed %d!\n", 11537 vport->vport_id, ret); 11538 } 11539 } 11540 11541 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11542 { 11543 struct hclge_desc desc; 11544 int ret; 11545 11546 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11547 11548 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11549 /* This new command is only supported by new firmware, it will 11550 * fail with older firmware. Error value -EOPNOSUPP can only be 11551 * returned by older firmware running this command, to keep code 11552 * backward compatible we will override this value and return 11553 * success. 11554 */ 11555 if (ret && ret != -EOPNOTSUPP) { 11556 dev_err(&hdev->pdev->dev, 11557 "failed to clear hw resource, ret = %d\n", ret); 11558 return ret; 11559 } 11560 return 0; 11561 } 11562 11563 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11564 { 11565 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11566 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11567 } 11568 11569 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11570 { 11571 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11572 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11573 } 11574 11575 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11576 { 11577 struct hclge_vport *vport = hclge_get_vport(handle); 11578 11579 return &vport->back->hw.mac.wol; 11580 } 11581 11582 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11583 u32 *wol_supported) 11584 { 11585 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11586 struct hclge_desc desc; 11587 int ret; 11588 11589 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11590 true); 11591 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11592 11593 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11594 if (ret) { 11595 dev_err(&hdev->pdev->dev, 11596 "failed to query wol supported, ret = %d\n", ret); 11597 return ret; 11598 } 11599 11600 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11601 11602 return 0; 11603 } 11604 11605 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11606 struct hclge_wol_info *wol_info) 11607 { 11608 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11609 struct hclge_desc desc; 11610 int ret; 11611 11612 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11613 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11614 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11615 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11616 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11617 11618 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11619 if (ret) 11620 dev_err(&hdev->pdev->dev, 11621 "failed to set wol config, ret = %d\n", ret); 11622 11623 return ret; 11624 } 11625 11626 static int hclge_update_wol(struct hclge_dev *hdev) 11627 { 11628 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11629 11630 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11631 return 0; 11632 11633 return hclge_set_wol_cfg(hdev, wol_info); 11634 } 11635 11636 static int hclge_init_wol(struct hclge_dev *hdev) 11637 { 11638 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11639 int ret; 11640 11641 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11642 return 0; 11643 11644 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11645 ret = hclge_get_wol_supported_mode(hdev, 11646 &wol_info->wol_support_mode); 11647 if (ret) { 11648 wol_info->wol_support_mode = 0; 11649 return ret; 11650 } 11651 11652 return hclge_update_wol(hdev); 11653 } 11654 11655 static void hclge_get_wol(struct hnae3_handle *handle, 11656 struct ethtool_wolinfo *wol) 11657 { 11658 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11659 11660 wol->supported = wol_info->wol_support_mode; 11661 wol->wolopts = wol_info->wol_current_mode; 11662 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11663 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11664 } 11665 11666 static int hclge_set_wol(struct hnae3_handle *handle, 11667 struct ethtool_wolinfo *wol) 11668 { 11669 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11670 struct hclge_vport *vport = hclge_get_vport(handle); 11671 u32 wol_mode; 11672 int ret; 11673 11674 wol_mode = wol->wolopts; 11675 if (wol_mode & ~wol_info->wol_support_mode) 11676 return -EINVAL; 11677 11678 wol_info->wol_current_mode = wol_mode; 11679 if (wol_mode & WAKE_MAGICSECURE) { 11680 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11681 wol_info->wol_sopass_size = SOPASS_MAX; 11682 } else { 11683 wol_info->wol_sopass_size = 0; 11684 } 11685 11686 ret = hclge_set_wol_cfg(vport->back, wol_info); 11687 if (ret) 11688 wol_info->wol_current_mode = 0; 11689 11690 return ret; 11691 } 11692 11693 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11694 { 11695 struct pci_dev *pdev = ae_dev->pdev; 11696 struct hclge_dev *hdev; 11697 int ret; 11698 11699 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11700 if (!hdev) 11701 return -ENOMEM; 11702 11703 hdev->pdev = pdev; 11704 hdev->ae_dev = ae_dev; 11705 hdev->reset_type = HNAE3_NONE_RESET; 11706 hdev->reset_level = HNAE3_FUNC_RESET; 11707 ae_dev->priv = hdev; 11708 11709 /* HW supprt 2 layer vlan */ 11710 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11711 11712 mutex_init(&hdev->vport_lock); 11713 spin_lock_init(&hdev->fd_rule_lock); 11714 sema_init(&hdev->reset_sem, 1); 11715 11716 ret = hclge_pci_init(hdev); 11717 if (ret) 11718 goto out; 11719 11720 /* Firmware command queue initialize */ 11721 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11722 if (ret) 11723 goto err_pci_uninit; 11724 11725 /* Firmware command initialize */ 11726 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops); 11727 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11728 true, hdev->reset_pending); 11729 if (ret) 11730 goto err_cmd_uninit; 11731 11732 ret = hclge_clear_hw_resource(hdev); 11733 if (ret) 11734 goto err_cmd_uninit; 11735 11736 ret = hclge_get_cap(hdev); 11737 if (ret) 11738 goto err_cmd_uninit; 11739 11740 ret = hclge_query_dev_specs(hdev); 11741 if (ret) { 11742 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11743 ret); 11744 goto err_cmd_uninit; 11745 } 11746 11747 ret = hclge_configure(hdev); 11748 if (ret) { 11749 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11750 goto err_cmd_uninit; 11751 } 11752 11753 ret = hclge_init_msi(hdev); 11754 if (ret) { 11755 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11756 goto err_cmd_uninit; 11757 } 11758 11759 ret = hclge_misc_irq_init(hdev); 11760 if (ret) 11761 goto err_msi_uninit; 11762 11763 ret = hclge_alloc_tqps(hdev); 11764 if (ret) { 11765 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11766 goto err_msi_irq_uninit; 11767 } 11768 11769 ret = hclge_alloc_vport(hdev); 11770 if (ret) 11771 goto err_msi_irq_uninit; 11772 11773 ret = hclge_map_tqp(hdev); 11774 if (ret) 11775 goto err_msi_irq_uninit; 11776 11777 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11778 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 11779 if (hnae3_dev_phy_imp_supported(hdev)) 11780 ret = hclge_update_tp_port_info(hdev); 11781 else 11782 ret = hclge_mac_mdio_config(hdev); 11783 11784 if (ret) 11785 goto err_msi_irq_uninit; 11786 } 11787 11788 ret = hclge_init_umv_space(hdev); 11789 if (ret) 11790 goto err_mdiobus_unreg; 11791 11792 ret = hclge_mac_init(hdev); 11793 if (ret) { 11794 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11795 goto err_mdiobus_unreg; 11796 } 11797 11798 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11799 if (ret) { 11800 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11801 goto err_mdiobus_unreg; 11802 } 11803 11804 ret = hclge_config_gro(hdev); 11805 if (ret) 11806 goto err_mdiobus_unreg; 11807 11808 ret = hclge_init_vlan_config(hdev); 11809 if (ret) { 11810 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11811 goto err_mdiobus_unreg; 11812 } 11813 11814 ret = hclge_tm_schd_init(hdev); 11815 if (ret) { 11816 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11817 goto err_mdiobus_unreg; 11818 } 11819 11820 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11821 &hdev->rss_cfg); 11822 if (ret) { 11823 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11824 goto err_mdiobus_unreg; 11825 } 11826 11827 ret = hclge_rss_init_hw(hdev); 11828 if (ret) { 11829 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11830 goto err_mdiobus_unreg; 11831 } 11832 11833 ret = init_mgr_tbl(hdev); 11834 if (ret) { 11835 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11836 goto err_mdiobus_unreg; 11837 } 11838 11839 ret = hclge_init_fd_config(hdev); 11840 if (ret) { 11841 dev_err(&pdev->dev, 11842 "fd table init fail, ret=%d\n", ret); 11843 goto err_mdiobus_unreg; 11844 } 11845 11846 ret = hclge_ptp_init(hdev); 11847 if (ret) 11848 goto err_mdiobus_unreg; 11849 11850 ret = hclge_update_port_info(hdev); 11851 if (ret) 11852 goto err_ptp_uninit; 11853 11854 INIT_KFIFO(hdev->mac_tnl_log); 11855 11856 hclge_dcb_ops_set(hdev); 11857 11858 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11859 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11860 11861 hclge_clear_all_event_cause(hdev); 11862 hclge_clear_resetting_state(hdev); 11863 11864 /* Log and clear the hw errors those already occurred */ 11865 if (hnae3_dev_ras_imp_supported(hdev)) 11866 hclge_handle_occurred_error(hdev); 11867 else 11868 hclge_handle_all_hns_hw_errors(ae_dev); 11869 11870 /* request delayed reset for the error recovery because an immediate 11871 * global reset on a PF affecting pending initialization of other PFs 11872 */ 11873 if (ae_dev->hw_err_reset_req) { 11874 enum hnae3_reset_type reset_level; 11875 11876 reset_level = hclge_get_reset_level(ae_dev, 11877 &ae_dev->hw_err_reset_req); 11878 hclge_set_def_reset_request(ae_dev, reset_level); 11879 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11880 } 11881 11882 hclge_init_rxd_adv_layout(hdev); 11883 11884 /* Enable MISC vector(vector0) */ 11885 hclge_enable_vector(&hdev->misc_vector, true); 11886 11887 ret = hclge_init_wol(hdev); 11888 if (ret) 11889 dev_warn(&pdev->dev, 11890 "failed to wake on lan init, ret = %d\n", ret); 11891 11892 ret = hclge_devlink_init(hdev); 11893 if (ret) 11894 goto err_ptp_uninit; 11895 11896 hclge_state_init(hdev); 11897 hdev->last_reset_time = jiffies; 11898 11899 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11900 HCLGE_DRIVER_NAME); 11901 11902 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11903 return 0; 11904 11905 err_ptp_uninit: 11906 hclge_ptp_uninit(hdev); 11907 err_mdiobus_unreg: 11908 if (hdev->hw.mac.phydev) 11909 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11910 err_msi_irq_uninit: 11911 hclge_misc_irq_uninit(hdev); 11912 err_msi_uninit: 11913 pci_free_irq_vectors(pdev); 11914 err_cmd_uninit: 11915 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11916 err_pci_uninit: 11917 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11918 pci_release_regions(pdev); 11919 pci_disable_device(pdev); 11920 out: 11921 mutex_destroy(&hdev->vport_lock); 11922 return ret; 11923 } 11924 11925 static void hclge_stats_clear(struct hclge_dev *hdev) 11926 { 11927 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11928 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11929 } 11930 11931 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11932 { 11933 return hclge_config_switch_param(hdev, vf, enable, 11934 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11935 } 11936 11937 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11938 { 11939 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11940 HCLGE_FILTER_FE_NIC_INGRESS_B, 11941 enable, vf); 11942 } 11943 11944 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11945 { 11946 int ret; 11947 11948 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11949 if (ret) { 11950 dev_err(&hdev->pdev->dev, 11951 "Set vf %d mac spoof check %s failed, ret=%d\n", 11952 vf, enable ? "on" : "off", ret); 11953 return ret; 11954 } 11955 11956 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11957 if (ret) 11958 dev_err(&hdev->pdev->dev, 11959 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11960 vf, enable ? "on" : "off", ret); 11961 11962 return ret; 11963 } 11964 11965 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11966 bool enable) 11967 { 11968 struct hclge_vport *vport = hclge_get_vport(handle); 11969 struct hclge_dev *hdev = vport->back; 11970 u32 new_spoofchk = enable ? 1 : 0; 11971 int ret; 11972 11973 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11974 return -EOPNOTSUPP; 11975 11976 vport = hclge_get_vf_vport(hdev, vf); 11977 if (!vport) 11978 return -EINVAL; 11979 11980 if (vport->vf_info.spoofchk == new_spoofchk) 11981 return 0; 11982 11983 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11984 dev_warn(&hdev->pdev->dev, 11985 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11986 vf); 11987 else if (enable && hclge_is_umv_space_full(vport, true)) 11988 dev_warn(&hdev->pdev->dev, 11989 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11990 vf); 11991 11992 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11993 if (ret) 11994 return ret; 11995 11996 vport->vf_info.spoofchk = new_spoofchk; 11997 return 0; 11998 } 11999 12000 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 12001 { 12002 struct hclge_vport *vport = hdev->vport; 12003 int ret; 12004 int i; 12005 12006 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 12007 return 0; 12008 12009 /* resume the vf spoof check state after reset */ 12010 for (i = 0; i < hdev->num_alloc_vport; i++) { 12011 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 12012 vport->vf_info.spoofchk); 12013 if (ret) 12014 return ret; 12015 12016 vport++; 12017 } 12018 12019 return 0; 12020 } 12021 12022 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 12023 { 12024 struct hclge_vport *vport = hclge_get_vport(handle); 12025 struct hclge_dev *hdev = vport->back; 12026 u32 new_trusted = enable ? 1 : 0; 12027 12028 vport = hclge_get_vf_vport(hdev, vf); 12029 if (!vport) 12030 return -EINVAL; 12031 12032 if (vport->vf_info.trusted == new_trusted) 12033 return 0; 12034 12035 vport->vf_info.trusted = new_trusted; 12036 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12037 hclge_task_schedule(hdev, 0); 12038 12039 return 0; 12040 } 12041 12042 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 12043 { 12044 int ret; 12045 int vf; 12046 12047 /* reset vf rate to default value */ 12048 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 12049 struct hclge_vport *vport = &hdev->vport[vf]; 12050 12051 vport->vf_info.max_tx_rate = 0; 12052 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 12053 if (ret) 12054 dev_err(&hdev->pdev->dev, 12055 "vf%d failed to reset to default, ret=%d\n", 12056 vf - HCLGE_VF_VPORT_START_NUM, ret); 12057 } 12058 } 12059 12060 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 12061 int min_tx_rate, int max_tx_rate) 12062 { 12063 if (min_tx_rate != 0 || 12064 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 12065 dev_err(&hdev->pdev->dev, 12066 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 12067 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 12068 return -EINVAL; 12069 } 12070 12071 return 0; 12072 } 12073 12074 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 12075 int min_tx_rate, int max_tx_rate, bool force) 12076 { 12077 struct hclge_vport *vport = hclge_get_vport(handle); 12078 struct hclge_dev *hdev = vport->back; 12079 int ret; 12080 12081 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 12082 if (ret) 12083 return ret; 12084 12085 vport = hclge_get_vf_vport(hdev, vf); 12086 if (!vport) 12087 return -EINVAL; 12088 12089 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 12090 return 0; 12091 12092 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 12093 if (ret) 12094 return ret; 12095 12096 vport->vf_info.max_tx_rate = max_tx_rate; 12097 12098 return 0; 12099 } 12100 12101 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 12102 { 12103 struct hnae3_handle *handle = &hdev->vport->nic; 12104 struct hclge_vport *vport; 12105 int ret; 12106 int vf; 12107 12108 /* resume the vf max_tx_rate after reset */ 12109 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12110 vport = hclge_get_vf_vport(hdev, vf); 12111 if (!vport) 12112 return -EINVAL; 12113 12114 /* zero means max rate, after reset, firmware already set it to 12115 * max rate, so just continue. 12116 */ 12117 if (!vport->vf_info.max_tx_rate) 12118 continue; 12119 12120 ret = hclge_set_vf_rate(handle, vf, 0, 12121 vport->vf_info.max_tx_rate, true); 12122 if (ret) { 12123 dev_err(&hdev->pdev->dev, 12124 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12125 vf, vport->vf_info.max_tx_rate, ret); 12126 return ret; 12127 } 12128 } 12129 12130 return 0; 12131 } 12132 12133 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12134 { 12135 struct hclge_vport *vport = hdev->vport; 12136 int i; 12137 12138 for (i = 0; i < hdev->num_alloc_vport; i++) { 12139 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12140 vport++; 12141 } 12142 } 12143 12144 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12145 { 12146 struct hclge_dev *hdev = ae_dev->priv; 12147 struct pci_dev *pdev = ae_dev->pdev; 12148 int ret; 12149 12150 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12151 12152 hclge_stats_clear(hdev); 12153 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12154 * so here should not clean table in memory. 12155 */ 12156 if (hdev->reset_type == HNAE3_IMP_RESET || 12157 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12158 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12159 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12160 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12161 hclge_reset_umv_space(hdev); 12162 } 12163 12164 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12165 true, hdev->reset_pending); 12166 if (ret) { 12167 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12168 return ret; 12169 } 12170 12171 ret = hclge_map_tqp(hdev); 12172 if (ret) { 12173 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12174 return ret; 12175 } 12176 12177 ret = hclge_mac_init(hdev); 12178 if (ret) { 12179 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12180 return ret; 12181 } 12182 12183 ret = hclge_tp_port_init(hdev); 12184 if (ret) { 12185 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12186 ret); 12187 return ret; 12188 } 12189 12190 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12191 if (ret) { 12192 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12193 return ret; 12194 } 12195 12196 ret = hclge_config_gro(hdev); 12197 if (ret) 12198 return ret; 12199 12200 ret = hclge_init_vlan_config(hdev); 12201 if (ret) { 12202 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12203 return ret; 12204 } 12205 12206 hclge_reset_tc_config(hdev); 12207 12208 ret = hclge_tm_init_hw(hdev, true); 12209 if (ret) { 12210 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12211 return ret; 12212 } 12213 12214 ret = hclge_rss_init_hw(hdev); 12215 if (ret) { 12216 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12217 return ret; 12218 } 12219 12220 ret = init_mgr_tbl(hdev); 12221 if (ret) { 12222 dev_err(&pdev->dev, 12223 "failed to reinit manager table, ret = %d\n", ret); 12224 return ret; 12225 } 12226 12227 ret = hclge_init_fd_config(hdev); 12228 if (ret) { 12229 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12230 return ret; 12231 } 12232 12233 ret = hclge_ptp_init(hdev); 12234 if (ret) 12235 return ret; 12236 12237 /* Log and clear the hw errors those already occurred */ 12238 if (hnae3_dev_ras_imp_supported(hdev)) 12239 hclge_handle_occurred_error(hdev); 12240 else 12241 hclge_handle_all_hns_hw_errors(ae_dev); 12242 12243 /* Re-enable the hw error interrupts because 12244 * the interrupts get disabled on global reset. 12245 */ 12246 ret = hclge_config_nic_hw_error(hdev, true); 12247 if (ret) { 12248 dev_err(&pdev->dev, 12249 "fail(%d) to re-enable NIC hw error interrupts\n", 12250 ret); 12251 return ret; 12252 } 12253 12254 if (hdev->roce_client) { 12255 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12256 if (ret) { 12257 dev_err(&pdev->dev, 12258 "fail(%d) to re-enable roce ras interrupts\n", 12259 ret); 12260 return ret; 12261 } 12262 } 12263 12264 hclge_reset_vport_state(hdev); 12265 ret = hclge_reset_vport_spoofchk(hdev); 12266 if (ret) 12267 return ret; 12268 12269 ret = hclge_resume_vf_rate(hdev); 12270 if (ret) 12271 return ret; 12272 12273 hclge_init_rxd_adv_layout(hdev); 12274 12275 ret = hclge_update_wol(hdev); 12276 if (ret) 12277 dev_warn(&pdev->dev, 12278 "failed to update wol config, ret = %d\n", ret); 12279 12280 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12281 HCLGE_DRIVER_NAME); 12282 12283 return 0; 12284 } 12285 12286 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12287 { 12288 struct hclge_dev *hdev = ae_dev->priv; 12289 struct hclge_mac *mac = &hdev->hw.mac; 12290 12291 hclge_reset_vf_rate(hdev); 12292 hclge_clear_vf_vlan(hdev); 12293 hclge_state_uninit(hdev); 12294 hclge_ptp_uninit(hdev); 12295 hclge_uninit_rxd_adv_layout(hdev); 12296 hclge_uninit_mac_table(hdev); 12297 hclge_del_all_fd_entries(hdev); 12298 12299 if (mac->phydev) 12300 mdiobus_unregister(mac->mdio_bus); 12301 12302 /* Disable MISC vector(vector0) */ 12303 hclge_enable_vector(&hdev->misc_vector, false); 12304 synchronize_irq(hdev->misc_vector.vector_irq); 12305 12306 /* Disable all hw interrupts */ 12307 hclge_config_mac_tnl_int(hdev, false); 12308 hclge_config_nic_hw_error(hdev, false); 12309 hclge_config_rocee_ras_interrupt(hdev, false); 12310 12311 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12312 hclge_misc_irq_uninit(hdev); 12313 hclge_devlink_uninit(hdev); 12314 hclge_pci_uninit(hdev); 12315 hclge_uninit_vport_vlan_table(hdev); 12316 mutex_destroy(&hdev->vport_lock); 12317 ae_dev->priv = NULL; 12318 } 12319 12320 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12321 { 12322 struct hclge_vport *vport = hclge_get_vport(handle); 12323 struct hclge_dev *hdev = vport->back; 12324 12325 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12326 } 12327 12328 static void hclge_get_channels(struct hnae3_handle *handle, 12329 struct ethtool_channels *ch) 12330 { 12331 ch->max_combined = hclge_get_max_channels(handle); 12332 ch->other_count = 1; 12333 ch->max_other = 1; 12334 ch->combined_count = handle->kinfo.rss_size; 12335 } 12336 12337 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12338 u16 *alloc_tqps, u16 *max_rss_size) 12339 { 12340 struct hclge_vport *vport = hclge_get_vport(handle); 12341 struct hclge_dev *hdev = vport->back; 12342 12343 *alloc_tqps = vport->alloc_tqps; 12344 *max_rss_size = hdev->pf_rss_size_max; 12345 } 12346 12347 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12348 { 12349 struct hclge_vport *vport = hclge_get_vport(handle); 12350 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12351 struct hclge_dev *hdev = vport->back; 12352 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12353 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12354 u16 roundup_size; 12355 unsigned int i; 12356 12357 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12358 roundup_size = ilog2(roundup_size); 12359 /* Set the RSS TC mode according to the new RSS size */ 12360 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12361 tc_valid[i] = 0; 12362 12363 if (!(hdev->hw_tc_map & BIT(i))) 12364 continue; 12365 12366 tc_valid[i] = 1; 12367 tc_size[i] = roundup_size; 12368 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12369 } 12370 12371 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12372 tc_size); 12373 } 12374 12375 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12376 bool rxfh_configured) 12377 { 12378 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12379 struct hclge_vport *vport = hclge_get_vport(handle); 12380 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12381 struct hclge_dev *hdev = vport->back; 12382 u16 cur_rss_size = kinfo->rss_size; 12383 u16 cur_tqps = kinfo->num_tqps; 12384 u32 *rss_indir; 12385 unsigned int i; 12386 int ret; 12387 12388 kinfo->req_rss_size = new_tqps_num; 12389 12390 ret = hclge_tm_vport_map_update(hdev); 12391 if (ret) { 12392 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12393 return ret; 12394 } 12395 12396 ret = hclge_set_rss_tc_mode_cfg(handle); 12397 if (ret) 12398 return ret; 12399 12400 /* RSS indirection table has been configured by user */ 12401 if (rxfh_configured) 12402 goto out; 12403 12404 /* Reinitializes the rss indirect table according to the new RSS size */ 12405 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12406 GFP_KERNEL); 12407 if (!rss_indir) 12408 return -ENOMEM; 12409 12410 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12411 rss_indir[i] = i % kinfo->rss_size; 12412 12413 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12414 if (ret) 12415 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12416 ret); 12417 12418 kfree(rss_indir); 12419 12420 out: 12421 if (!ret) 12422 dev_info(&hdev->pdev->dev, 12423 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12424 cur_rss_size, kinfo->rss_size, 12425 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12426 12427 return ret; 12428 } 12429 12430 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12431 { 12432 struct hclge_set_led_state_cmd *req; 12433 struct hclge_desc desc; 12434 int ret; 12435 12436 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12437 12438 req = (struct hclge_set_led_state_cmd *)desc.data; 12439 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12440 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12441 12442 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12443 if (ret) 12444 dev_err(&hdev->pdev->dev, 12445 "Send set led state cmd error, ret =%d\n", ret); 12446 12447 return ret; 12448 } 12449 12450 enum hclge_led_status { 12451 HCLGE_LED_OFF, 12452 HCLGE_LED_ON, 12453 HCLGE_LED_NO_CHANGE = 0xFF, 12454 }; 12455 12456 static int hclge_set_led_id(struct hnae3_handle *handle, 12457 enum ethtool_phys_id_state status) 12458 { 12459 struct hclge_vport *vport = hclge_get_vport(handle); 12460 struct hclge_dev *hdev = vport->back; 12461 12462 switch (status) { 12463 case ETHTOOL_ID_ACTIVE: 12464 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12465 case ETHTOOL_ID_INACTIVE: 12466 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12467 default: 12468 return -EINVAL; 12469 } 12470 } 12471 12472 static void hclge_get_link_mode(struct hnae3_handle *handle, 12473 unsigned long *supported, 12474 unsigned long *advertising) 12475 { 12476 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12477 struct hclge_vport *vport = hclge_get_vport(handle); 12478 struct hclge_dev *hdev = vport->back; 12479 unsigned int idx = 0; 12480 12481 for (; idx < size; idx++) { 12482 supported[idx] = hdev->hw.mac.supported[idx]; 12483 advertising[idx] = hdev->hw.mac.advertising[idx]; 12484 } 12485 } 12486 12487 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12488 { 12489 struct hclge_vport *vport = hclge_get_vport(handle); 12490 struct hclge_dev *hdev = vport->back; 12491 bool gro_en_old = hdev->gro_en; 12492 int ret; 12493 12494 hdev->gro_en = enable; 12495 ret = hclge_config_gro(hdev); 12496 if (ret) 12497 hdev->gro_en = gro_en_old; 12498 12499 return ret; 12500 } 12501 12502 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12503 { 12504 struct hnae3_handle *handle = &vport->nic; 12505 struct hclge_dev *hdev = vport->back; 12506 bool uc_en = false; 12507 bool mc_en = false; 12508 u8 tmp_flags; 12509 bool bc_en; 12510 int ret; 12511 12512 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12513 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12514 vport->last_promisc_flags = vport->overflow_promisc_flags; 12515 } 12516 12517 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12518 &vport->state)) 12519 return 0; 12520 12521 /* for PF */ 12522 if (!vport->vport_id) { 12523 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12524 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12525 tmp_flags & HNAE3_MPE); 12526 if (!ret) 12527 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12528 &vport->state); 12529 else 12530 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12531 &vport->state); 12532 return ret; 12533 } 12534 12535 /* for VF */ 12536 if (vport->vf_info.trusted) { 12537 uc_en = vport->vf_info.request_uc_en > 0 || 12538 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12539 mc_en = vport->vf_info.request_mc_en > 0 || 12540 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12541 } 12542 bc_en = vport->vf_info.request_bc_en > 0; 12543 12544 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12545 mc_en, bc_en); 12546 if (ret) { 12547 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12548 return ret; 12549 } 12550 hclge_set_vport_vlan_fltr_change(vport); 12551 12552 return 0; 12553 } 12554 12555 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12556 { 12557 struct hclge_vport *vport; 12558 int ret; 12559 u16 i; 12560 12561 for (i = 0; i < hdev->num_alloc_vport; i++) { 12562 vport = &hdev->vport[i]; 12563 12564 ret = hclge_sync_vport_promisc_mode(vport); 12565 if (ret) 12566 return; 12567 } 12568 } 12569 12570 static bool hclge_module_existed(struct hclge_dev *hdev) 12571 { 12572 struct hclge_desc desc; 12573 u32 existed; 12574 int ret; 12575 12576 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12577 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12578 if (ret) { 12579 dev_err(&hdev->pdev->dev, 12580 "failed to get SFP exist state, ret = %d\n", ret); 12581 return false; 12582 } 12583 12584 existed = le32_to_cpu(desc.data[0]); 12585 12586 return existed != 0; 12587 } 12588 12589 /* need 6 bds(total 140 bytes) in one reading 12590 * return the number of bytes actually read, 0 means read failed. 12591 */ 12592 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12593 u32 len, u8 *data) 12594 { 12595 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12596 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12597 u16 read_len; 12598 u16 copy_len; 12599 int ret; 12600 int i; 12601 12602 /* setup all 6 bds to read module eeprom info. */ 12603 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12604 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12605 true); 12606 12607 /* bd0~bd4 need next flag */ 12608 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12609 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12610 } 12611 12612 /* setup bd0, this bd contains offset and read length. */ 12613 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12614 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12615 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12616 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12617 12618 ret = hclge_cmd_send(&hdev->hw, desc, i); 12619 if (ret) { 12620 dev_err(&hdev->pdev->dev, 12621 "failed to get SFP eeprom info, ret = %d\n", ret); 12622 return 0; 12623 } 12624 12625 /* copy sfp info from bd0 to out buffer. */ 12626 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12627 memcpy(data, sfp_info_bd0->data, copy_len); 12628 read_len = copy_len; 12629 12630 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12631 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12632 if (read_len >= len) 12633 return read_len; 12634 12635 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12636 memcpy(data + read_len, desc[i].data, copy_len); 12637 read_len += copy_len; 12638 } 12639 12640 return read_len; 12641 } 12642 12643 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12644 u32 len, u8 *data) 12645 { 12646 struct hclge_vport *vport = hclge_get_vport(handle); 12647 struct hclge_dev *hdev = vport->back; 12648 u32 read_len = 0; 12649 u16 data_len; 12650 12651 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12652 return -EOPNOTSUPP; 12653 12654 if (!hclge_module_existed(hdev)) 12655 return -ENXIO; 12656 12657 while (read_len < len) { 12658 data_len = hclge_get_sfp_eeprom_info(hdev, 12659 offset + read_len, 12660 len - read_len, 12661 data + read_len); 12662 if (!data_len) 12663 return -EIO; 12664 12665 read_len += data_len; 12666 } 12667 12668 return 0; 12669 } 12670 12671 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12672 u32 *status_code) 12673 { 12674 struct hclge_vport *vport = hclge_get_vport(handle); 12675 struct hclge_dev *hdev = vport->back; 12676 struct hclge_desc desc; 12677 int ret; 12678 12679 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12680 return -EOPNOTSUPP; 12681 12682 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12683 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12684 if (ret) { 12685 dev_err(&hdev->pdev->dev, 12686 "failed to query link diagnosis info, ret = %d\n", ret); 12687 return ret; 12688 } 12689 12690 *status_code = le32_to_cpu(desc.data[0]); 12691 return 0; 12692 } 12693 12694 /* After disable sriov, VF still has some config and info need clean, 12695 * which configed by PF. 12696 */ 12697 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12698 { 12699 struct hclge_dev *hdev = vport->back; 12700 struct hclge_vlan_info vlan_info; 12701 int ret; 12702 12703 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12704 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12705 vport->need_notify = 0; 12706 vport->mps = 0; 12707 12708 /* after disable sriov, clean VF rate configured by PF */ 12709 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12710 if (ret) 12711 dev_err(&hdev->pdev->dev, 12712 "failed to clean vf%d rate config, ret = %d\n", 12713 vfid, ret); 12714 12715 vlan_info.vlan_tag = 0; 12716 vlan_info.qos = 0; 12717 vlan_info.vlan_proto = ETH_P_8021Q; 12718 ret = hclge_update_port_base_vlan_cfg(vport, 12719 HNAE3_PORT_BASE_VLAN_DISABLE, 12720 &vlan_info); 12721 if (ret) 12722 dev_err(&hdev->pdev->dev, 12723 "failed to clean vf%d port base vlan, ret = %d\n", 12724 vfid, ret); 12725 12726 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12727 if (ret) 12728 dev_err(&hdev->pdev->dev, 12729 "failed to clean vf%d spoof config, ret = %d\n", 12730 vfid, ret); 12731 12732 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12733 } 12734 12735 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12736 { 12737 struct hclge_dev *hdev = ae_dev->priv; 12738 struct hclge_vport *vport; 12739 int i; 12740 12741 for (i = 0; i < num_vfs; i++) { 12742 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12743 12744 hclge_clear_vport_vf_info(vport, i); 12745 } 12746 } 12747 12748 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12749 u8 *priority) 12750 { 12751 struct hclge_vport *vport = hclge_get_vport(h); 12752 12753 if (dscp >= HNAE3_MAX_DSCP) 12754 return -EINVAL; 12755 12756 if (tc_mode) 12757 *tc_mode = vport->nic.kinfo.tc_map_mode; 12758 if (priority) 12759 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12760 vport->nic.kinfo.dscp_prio[dscp]; 12761 12762 return 0; 12763 } 12764 12765 static const struct hnae3_ae_ops hclge_ops = { 12766 .init_ae_dev = hclge_init_ae_dev, 12767 .uninit_ae_dev = hclge_uninit_ae_dev, 12768 .reset_prepare = hclge_reset_prepare_general, 12769 .reset_done = hclge_reset_done, 12770 .init_client_instance = hclge_init_client_instance, 12771 .uninit_client_instance = hclge_uninit_client_instance, 12772 .map_ring_to_vector = hclge_map_ring_to_vector, 12773 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12774 .get_vector = hclge_get_vector, 12775 .put_vector = hclge_put_vector, 12776 .set_promisc_mode = hclge_set_promisc_mode, 12777 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12778 .set_loopback = hclge_set_loopback, 12779 .start = hclge_ae_start, 12780 .stop = hclge_ae_stop, 12781 .client_start = hclge_client_start, 12782 .client_stop = hclge_client_stop, 12783 .get_status = hclge_get_status, 12784 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12785 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12786 .get_media_type = hclge_get_media_type, 12787 .check_port_speed = hclge_check_port_speed, 12788 .get_fec_stats = hclge_get_fec_stats, 12789 .get_fec = hclge_get_fec, 12790 .set_fec = hclge_set_fec, 12791 .get_rss_key_size = hclge_comm_get_rss_key_size, 12792 .get_rss = hclge_get_rss, 12793 .set_rss = hclge_set_rss, 12794 .set_rss_tuple = hclge_set_rss_tuple, 12795 .get_rss_tuple = hclge_get_rss_tuple, 12796 .get_tc_size = hclge_get_tc_size, 12797 .get_mac_addr = hclge_get_mac_addr, 12798 .set_mac_addr = hclge_set_mac_addr, 12799 .do_ioctl = hclge_do_ioctl, 12800 .add_uc_addr = hclge_add_uc_addr, 12801 .rm_uc_addr = hclge_rm_uc_addr, 12802 .add_mc_addr = hclge_add_mc_addr, 12803 .rm_mc_addr = hclge_rm_mc_addr, 12804 .set_autoneg = hclge_set_autoneg, 12805 .get_autoneg = hclge_get_autoneg, 12806 .restart_autoneg = hclge_restart_autoneg, 12807 .halt_autoneg = hclge_halt_autoneg, 12808 .get_pauseparam = hclge_get_pauseparam, 12809 .set_pauseparam = hclge_set_pauseparam, 12810 .set_mtu = hclge_set_mtu, 12811 .reset_queue = hclge_reset_tqp, 12812 .get_stats = hclge_get_stats, 12813 .get_mac_stats = hclge_get_mac_stat, 12814 .update_stats = hclge_update_stats, 12815 .get_strings = hclge_get_strings, 12816 .get_sset_count = hclge_get_sset_count, 12817 .get_fw_version = hclge_get_fw_version, 12818 .get_mdix_mode = hclge_get_mdix_mode, 12819 .enable_vlan_filter = hclge_enable_vlan_filter, 12820 .set_vlan_filter = hclge_set_vlan_filter, 12821 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12822 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12823 .reset_event = hclge_reset_event, 12824 .get_reset_level = hclge_get_reset_level, 12825 .set_default_reset_request = hclge_set_def_reset_request, 12826 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12827 .set_channels = hclge_set_channels, 12828 .get_channels = hclge_get_channels, 12829 .get_regs_len = hclge_get_regs_len, 12830 .get_regs = hclge_get_regs, 12831 .set_led_id = hclge_set_led_id, 12832 .get_link_mode = hclge_get_link_mode, 12833 .add_fd_entry = hclge_add_fd_entry, 12834 .del_fd_entry = hclge_del_fd_entry, 12835 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12836 .get_fd_rule_info = hclge_get_fd_rule_info, 12837 .get_fd_all_rules = hclge_get_all_rules, 12838 .enable_fd = hclge_enable_fd, 12839 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12840 .dbg_read_cmd = hclge_dbg_read_cmd, 12841 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12842 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12843 .ae_dev_resetting = hclge_ae_dev_resetting, 12844 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12845 .set_gro_en = hclge_gro_en, 12846 .get_global_queue_id = hclge_covert_handle_qid_global, 12847 .set_timer_task = hclge_set_timer_task, 12848 .mac_connect_phy = hclge_mac_connect_phy, 12849 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12850 .get_vf_config = hclge_get_vf_config, 12851 .set_vf_link_state = hclge_set_vf_link_state, 12852 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12853 .set_vf_trust = hclge_set_vf_trust, 12854 .set_vf_rate = hclge_set_vf_rate, 12855 .set_vf_mac = hclge_set_vf_mac, 12856 .get_module_eeprom = hclge_get_module_eeprom, 12857 .get_cmdq_stat = hclge_get_cmdq_stat, 12858 .add_cls_flower = hclge_add_cls_flower, 12859 .del_cls_flower = hclge_del_cls_flower, 12860 .cls_flower_active = hclge_is_cls_flower_active, 12861 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12862 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12863 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12864 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12865 .get_ts_info = hclge_ptp_get_ts_info, 12866 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12867 .clean_vf_config = hclge_clean_vport_config, 12868 .get_dscp_prio = hclge_get_dscp_prio, 12869 .get_wol = hclge_get_wol, 12870 .set_wol = hclge_set_wol, 12871 }; 12872 12873 static struct hnae3_ae_algo ae_algo = { 12874 .ops = &hclge_ops, 12875 .pdev_id_table = ae_algo_pci_tbl, 12876 }; 12877 12878 static int __init hclge_init(void) 12879 { 12880 pr_info("%s is initializing\n", HCLGE_NAME); 12881 12882 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 12883 if (!hclge_wq) { 12884 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12885 return -ENOMEM; 12886 } 12887 12888 hnae3_register_ae_algo(&ae_algo); 12889 12890 return 0; 12891 } 12892 12893 static void __exit hclge_exit(void) 12894 { 12895 hnae3_unregister_ae_algo_prepare(&ae_algo); 12896 hnae3_unregister_ae_algo(&ae_algo); 12897 destroy_workqueue(hclge_wq); 12898 } 12899 module_init(hclge_init); 12900 module_exit(hclge_exit); 12901 12902 MODULE_LICENSE("GPL"); 12903 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12904 MODULE_DESCRIPTION("HCLGE Driver"); 12905 MODULE_VERSION(HCLGE_MOD_VERSION); 12906