xref: /linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c (revision 031fba65fc202abf1f193e321be7a2c274fd88ba) 
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #include <linux/acpi.h>
5 #include <linux/device.h>
6 #include <linux/etherdevice.h>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/netdevice.h>
12 #include <linux/pci.h>
13 #include <linux/platform_device.h>
14 #include <linux/if_vlan.h>
15 #include <linux/crash_dump.h>
16 #include <net/ipv6.h>
17 #include <net/rtnetlink.h>
18 #include "hclge_cmd.h"
19 #include "hclge_dcb.h"
20 #include "hclge_main.h"
21 #include "hclge_mbx.h"
22 #include "hclge_mdio.h"
23 #include "hclge_regs.h"
24 #include "hclge_tm.h"
25 #include "hclge_err.h"
26 #include "hnae3.h"
27 #include "hclge_devlink.h"
28 #include "hclge_comm_cmd.h"
29 
30 #define HCLGE_NAME			"hclge"
31 
32 #define HCLGE_BUF_SIZE_UNIT	256U
33 #define HCLGE_BUF_MUL_BY	2
34 #define HCLGE_BUF_DIV_BY	2
35 #define NEED_RESERVE_TC_NUM	2
36 #define BUF_MAX_PERCENT		100
37 #define BUF_RESERVE_PERCENT	90
38 
39 #define HCLGE_RESET_MAX_FAIL_CNT	5
40 #define HCLGE_RESET_SYNC_TIME		100
41 #define HCLGE_PF_RESET_SYNC_TIME	20
42 #define HCLGE_PF_RESET_SYNC_CNT		1500
43 
44 #define HCLGE_LINK_STATUS_MS	10
45 
46 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
47 static int hclge_init_vlan_config(struct hclge_dev *hdev);
48 static void hclge_sync_vlan_filter(struct hclge_dev *hdev);
49 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
50 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle);
51 static void hclge_rfs_filter_expire(struct hclge_dev *hdev);
52 static int hclge_clear_arfs_rules(struct hclge_dev *hdev);
53 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
54 						   unsigned long *addr);
55 static int hclge_set_default_loopback(struct hclge_dev *hdev);
56 
57 static void hclge_sync_mac_table(struct hclge_dev *hdev);
58 static void hclge_restore_hw_table(struct hclge_dev *hdev);
59 static void hclge_sync_promisc_mode(struct hclge_dev *hdev);
60 static void hclge_sync_fd_table(struct hclge_dev *hdev);
61 static void hclge_update_fec_stats(struct hclge_dev *hdev);
62 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret,
63 				      int wait_cnt);
64 
65 static struct hnae3_ae_algo ae_algo;
66 
67 static struct workqueue_struct *hclge_wq;
68 
69 static const struct pci_device_id ae_algo_pci_tbl[] = {
70 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
71 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
72 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
73 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
74 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
75 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
76 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
77 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
78 	/* required last entry */
79 	{0, }
80 };
81 
82 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
83 
84 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
85 	"External Loopback test",
86 	"App      Loopback test",
87 	"Serdes   serial Loopback test",
88 	"Serdes   parallel Loopback test",
89 	"Phy      Loopback test"
90 };
91 
92 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
93 	{"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
94 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
95 	{"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
96 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
97 	{"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
98 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)},
99 	{"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
100 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)},
101 	{"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
102 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)},
103 	{"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
104 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)},
105 	{"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
106 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)},
107 	{"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
108 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
109 	{"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
110 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
111 	{"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
112 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
113 	{"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
114 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
115 	{"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
116 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
117 	{"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
118 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
119 	{"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
120 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
121 	{"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
122 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
123 	{"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
124 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)},
125 	{"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
126 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)},
127 	{"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
128 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)},
129 	{"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
130 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)},
131 	{"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
132 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)},
133 	{"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
134 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)},
135 	{"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
136 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)},
137 	{"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
138 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)},
139 	{"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
140 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)},
141 	{"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
142 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
143 	{"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
144 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
145 	{"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
146 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
147 	{"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
148 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
149 	{"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
150 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
151 	{"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
152 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
153 	{"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
154 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
155 	{"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
156 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
157 	{"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
158 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)},
159 	{"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
160 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)},
161 	{"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
162 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)},
163 	{"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
164 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)},
165 	{"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
166 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)},
167 	{"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
168 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)},
169 	{"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
170 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)},
171 	{"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
172 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)},
173 	{"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
174 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
175 	{"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
176 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
177 	{"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
178 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
179 	{"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
180 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
181 	{"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
182 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
183 	{"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
184 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
185 	{"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
186 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
187 	{"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
188 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
189 	{"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
190 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
191 	{"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
192 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
193 	{"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
194 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
195 	{"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
196 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
197 	{"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
198 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
199 	{"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
200 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
201 	{"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
202 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
203 	{"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
204 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
205 	{"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
206 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
207 	{"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
208 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
209 	{"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
210 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
211 	{"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
212 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
213 	{"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
214 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
215 	{"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
216 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
217 	{"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
218 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
219 	{"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
220 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
221 	{"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
222 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
223 	{"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
224 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
225 	{"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
226 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
227 	{"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
228 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
229 	{"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
230 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
231 	{"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
232 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
233 	{"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
234 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
235 	{"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
236 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
237 	{"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
238 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
239 	{"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
240 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
241 	{"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
242 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
243 	{"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
244 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
245 	{"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
246 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
247 	{"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
248 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
249 	{"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
250 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
251 	{"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
252 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
253 	{"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
254 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
255 	{"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
256 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
257 	{"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
258 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
259 	{"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
260 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
261 	{"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
262 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
263 	{"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
264 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
265 	{"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
266 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
267 	{"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
268 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
269 	{"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
270 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
271 	{"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
272 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
273 
274 	{"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
275 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
276 	{"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
277 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
278 	{"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
279 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
280 	{"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
281 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
282 	{"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
283 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
284 	{"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
285 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
286 	{"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
287 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
288 	{"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
289 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
290 	{"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
291 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
292 	{"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
293 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
294 	{"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
295 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
296 	{"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
297 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
298 };
299 
300 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
301 	{
302 		.flags = HCLGE_MAC_MGR_MASK_VLAN_B,
303 		.ethter_type = cpu_to_le16(ETH_P_LLDP),
304 		.mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e},
305 		.i_port_bitmap = 0x1,
306 	},
307 };
308 
309 static const struct key_info meta_data_key_info[] = {
310 	{ PACKET_TYPE_ID, 6 },
311 	{ IP_FRAGEMENT, 1 },
312 	{ ROCE_TYPE, 1 },
313 	{ NEXT_KEY, 5 },
314 	{ VLAN_NUMBER, 2 },
315 	{ SRC_VPORT, 12 },
316 	{ DST_VPORT, 12 },
317 	{ TUNNEL_PACKET, 1 },
318 };
319 
320 static const struct key_info tuple_key_info[] = {
321 	{ OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 },
322 	{ OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 },
323 	{ OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 },
324 	{ OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
325 	{ OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 },
326 	{ OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
327 	{ OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 },
328 	{ OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 },
329 	{ OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 },
330 	{ OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 },
331 	{ OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 },
332 	{ OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 },
333 	{ OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 },
334 	{ OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 },
335 	{ OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 },
336 	{ OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 },
337 	{ INNER_DST_MAC, 48, KEY_OPT_MAC,
338 	  offsetof(struct hclge_fd_rule, tuples.dst_mac),
339 	  offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) },
340 	{ INNER_SRC_MAC, 48, KEY_OPT_MAC,
341 	  offsetof(struct hclge_fd_rule, tuples.src_mac),
342 	  offsetof(struct hclge_fd_rule, tuples_mask.src_mac) },
343 	{ INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16,
344 	  offsetof(struct hclge_fd_rule, tuples.vlan_tag1),
345 	  offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) },
346 	{ INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
347 	{ INNER_ETH_TYPE, 16, KEY_OPT_LE16,
348 	  offsetof(struct hclge_fd_rule, tuples.ether_proto),
349 	  offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) },
350 	{ INNER_L2_RSV, 16, KEY_OPT_LE16,
351 	  offsetof(struct hclge_fd_rule, tuples.l2_user_def),
352 	  offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) },
353 	{ INNER_IP_TOS, 8, KEY_OPT_U8,
354 	  offsetof(struct hclge_fd_rule, tuples.ip_tos),
355 	  offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) },
356 	{ INNER_IP_PROTO, 8, KEY_OPT_U8,
357 	  offsetof(struct hclge_fd_rule, tuples.ip_proto),
358 	  offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) },
359 	{ INNER_SRC_IP, 32, KEY_OPT_IP,
360 	  offsetof(struct hclge_fd_rule, tuples.src_ip),
361 	  offsetof(struct hclge_fd_rule, tuples_mask.src_ip) },
362 	{ INNER_DST_IP, 32, KEY_OPT_IP,
363 	  offsetof(struct hclge_fd_rule, tuples.dst_ip),
364 	  offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) },
365 	{ INNER_L3_RSV, 16, KEY_OPT_LE16,
366 	  offsetof(struct hclge_fd_rule, tuples.l3_user_def),
367 	  offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) },
368 	{ INNER_SRC_PORT, 16, KEY_OPT_LE16,
369 	  offsetof(struct hclge_fd_rule, tuples.src_port),
370 	  offsetof(struct hclge_fd_rule, tuples_mask.src_port) },
371 	{ INNER_DST_PORT, 16, KEY_OPT_LE16,
372 	  offsetof(struct hclge_fd_rule, tuples.dst_port),
373 	  offsetof(struct hclge_fd_rule, tuples_mask.dst_port) },
374 	{ INNER_L4_RSV, 32, KEY_OPT_LE32,
375 	  offsetof(struct hclge_fd_rule, tuples.l4_user_def),
376 	  offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) },
377 };
378 
379 /**
380  * hclge_cmd_send - send command to command queue
381  * @hw: pointer to the hw struct
382  * @desc: prefilled descriptor for describing the command
383  * @num : the number of descriptors to be sent
384  *
385  * This is the main send command for command queue, it
386  * sends the queue, cleans the queue, etc
387  **/
388 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
389 {
390 	return hclge_comm_cmd_send(&hw->hw, desc, num);
391 }
392 
393 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
394 {
395 #define HCLGE_MAC_CMD_NUM 21
396 
397 	u64 *data = (u64 *)(&hdev->mac_stats);
398 	struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
399 	__le64 *desc_data;
400 	u32 data_size;
401 	int ret;
402 	u32 i;
403 
404 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
405 	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
406 	if (ret) {
407 		dev_err(&hdev->pdev->dev,
408 			"Get MAC pkt stats fail, status = %d.\n", ret);
409 
410 		return ret;
411 	}
412 
413 	/* The first desc has a 64-bit header, so data size need to minus 1 */
414 	data_size = sizeof(desc) / (sizeof(u64)) - 1;
415 
416 	desc_data = (__le64 *)(&desc[0].data[0]);
417 	for (i = 0; i < data_size; i++) {
418 		/* data memory is continuous becase only the first desc has a
419 		 * header in this command
420 		 */
421 		*data += le64_to_cpu(*desc_data);
422 		data++;
423 		desc_data++;
424 	}
425 
426 	return 0;
427 }
428 
429 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev)
430 {
431 #define HCLGE_REG_NUM_PER_DESC		4
432 
433 	u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num;
434 	u64 *data = (u64 *)(&hdev->mac_stats);
435 	struct hclge_desc *desc;
436 	__le64 *desc_data;
437 	u32 data_size;
438 	u32 desc_num;
439 	int ret;
440 	u32 i;
441 
442 	/* The first desc has a 64-bit header, so need to consider it */
443 	desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1;
444 
445 	/* This may be called inside atomic sections,
446 	 * so GFP_ATOMIC is more suitalbe here
447 	 */
448 	desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC);
449 	if (!desc)
450 		return -ENOMEM;
451 
452 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true);
453 	ret = hclge_cmd_send(&hdev->hw, desc, desc_num);
454 	if (ret) {
455 		kfree(desc);
456 		return ret;
457 	}
458 
459 	data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num);
460 
461 	desc_data = (__le64 *)(&desc[0].data[0]);
462 	for (i = 0; i < data_size; i++) {
463 		/* data memory is continuous becase only the first desc has a
464 		 * header in this command
465 		 */
466 		*data += le64_to_cpu(*desc_data);
467 		data++;
468 		desc_data++;
469 	}
470 
471 	kfree(desc);
472 
473 	return 0;
474 }
475 
476 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
477 {
478 	struct hclge_desc desc;
479 	int ret;
480 
481 	/* Driver needs total register number of both valid registers and
482 	 * reserved registers, but the old firmware only returns number
483 	 * of valid registers in device V2. To be compatible with these
484 	 * devices, driver uses a fixed value.
485 	 */
486 	if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
487 		*reg_num = HCLGE_MAC_STATS_MAX_NUM_V1;
488 		return 0;
489 	}
490 
491 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
492 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
493 	if (ret) {
494 		dev_err(&hdev->pdev->dev,
495 			"failed to query mac statistic reg number, ret = %d\n",
496 			ret);
497 		return ret;
498 	}
499 
500 	*reg_num = le32_to_cpu(desc.data[0]);
501 	if (*reg_num == 0) {
502 		dev_err(&hdev->pdev->dev,
503 			"mac statistic reg number is invalid!\n");
504 		return -ENODATA;
505 	}
506 
507 	return 0;
508 }
509 
510 int hclge_mac_update_stats(struct hclge_dev *hdev)
511 {
512 	/* The firmware supports the new statistics acquisition method */
513 	if (hdev->ae_dev->dev_specs.mac_stats_num)
514 		return hclge_mac_update_stats_complete(hdev);
515 	else
516 		return hclge_mac_update_stats_defective(hdev);
517 }
518 
519 static int hclge_comm_get_count(struct hclge_dev *hdev,
520 				const struct hclge_comm_stats_str strs[],
521 				u32 size)
522 {
523 	int count = 0;
524 	u32 i;
525 
526 	for (i = 0; i < size; i++)
527 		if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num)
528 			count++;
529 
530 	return count;
531 }
532 
533 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev,
534 				 const struct hclge_comm_stats_str strs[],
535 				 int size, u64 *data)
536 {
537 	u64 *buf = data;
538 	u32 i;
539 
540 	for (i = 0; i < size; i++) {
541 		if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
542 			continue;
543 
544 		*buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset);
545 		buf++;
546 	}
547 
548 	return buf;
549 }
550 
551 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset,
552 				  const struct hclge_comm_stats_str strs[],
553 				  int size, u8 *data)
554 {
555 	char *buff = (char *)data;
556 	u32 i;
557 
558 	if (stringset != ETH_SS_STATS)
559 		return buff;
560 
561 	for (i = 0; i < size; i++) {
562 		if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
563 			continue;
564 
565 		snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc);
566 		buff = buff + ETH_GSTRING_LEN;
567 	}
568 
569 	return (u8 *)buff;
570 }
571 
572 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
573 {
574 	struct hnae3_handle *handle;
575 	int status;
576 
577 	handle = &hdev->vport[0].nic;
578 	if (handle->client) {
579 		status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
580 		if (status) {
581 			dev_err(&hdev->pdev->dev,
582 				"Update TQPS stats fail, status = %d.\n",
583 				status);
584 		}
585 	}
586 
587 	hclge_update_fec_stats(hdev);
588 
589 	status = hclge_mac_update_stats(hdev);
590 	if (status)
591 		dev_err(&hdev->pdev->dev,
592 			"Update MAC stats fail, status = %d.\n", status);
593 }
594 
595 static void hclge_update_stats(struct hnae3_handle *handle)
596 {
597 	struct hclge_vport *vport = hclge_get_vport(handle);
598 	struct hclge_dev *hdev = vport->back;
599 	int status;
600 
601 	if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
602 		return;
603 
604 	status = hclge_mac_update_stats(hdev);
605 	if (status)
606 		dev_err(&hdev->pdev->dev,
607 			"Update MAC stats fail, status = %d.\n",
608 			status);
609 
610 	status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
611 	if (status)
612 		dev_err(&hdev->pdev->dev,
613 			"Update TQPS stats fail, status = %d.\n",
614 			status);
615 
616 	clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
617 }
618 
619 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
620 {
621 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \
622 		HNAE3_SUPPORT_PHY_LOOPBACK | \
623 		HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \
624 		HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \
625 		HNAE3_SUPPORT_EXTERNAL_LOOPBACK)
626 
627 	struct hclge_vport *vport = hclge_get_vport(handle);
628 	struct hclge_dev *hdev = vport->back;
629 	int count = 0;
630 
631 	/* Loopback test support rules:
632 	 * mac: only GE mode support
633 	 * serdes: all mac mode will support include GE/XGE/LGE/CGE
634 	 * phy: only support when phy device exist on board
635 	 */
636 	if (stringset == ETH_SS_TEST) {
637 		/* clear loopback bit flags at first */
638 		handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
639 		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 ||
640 		    hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
641 		    hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
642 		    hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
643 			count += 1;
644 			handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
645 		}
646 
647 		count += 1;
648 		handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
649 		count += 1;
650 		handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
651 		count += 1;
652 		handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK;
653 
654 		if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv &&
655 		     hdev->hw.mac.phydev->drv->set_loopback) ||
656 		    hnae3_dev_phy_imp_supported(hdev)) {
657 			count += 1;
658 			handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK;
659 		}
660 	} else if (stringset == ETH_SS_STATS) {
661 		count = hclge_comm_get_count(hdev, g_mac_stats_string,
662 					     ARRAY_SIZE(g_mac_stats_string)) +
663 			hclge_comm_tqps_get_sset_count(handle);
664 	}
665 
666 	return count;
667 }
668 
669 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset,
670 			      u8 *data)
671 {
672 	struct hclge_vport *vport = hclge_get_vport(handle);
673 	struct hclge_dev *hdev = vport->back;
674 	u8 *p = (char *)data;
675 	int size;
676 
677 	if (stringset == ETH_SS_STATS) {
678 		size = ARRAY_SIZE(g_mac_stats_string);
679 		p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string,
680 					   size, p);
681 		p = hclge_comm_tqps_get_strings(handle, p);
682 	} else if (stringset == ETH_SS_TEST) {
683 		if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) {
684 			memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL],
685 			       ETH_GSTRING_LEN);
686 			p += ETH_GSTRING_LEN;
687 		}
688 		if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
689 			memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP],
690 			       ETH_GSTRING_LEN);
691 			p += ETH_GSTRING_LEN;
692 		}
693 		if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
694 			memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
695 			       ETH_GSTRING_LEN);
696 			p += ETH_GSTRING_LEN;
697 		}
698 		if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
699 			memcpy(p,
700 			       hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
701 			       ETH_GSTRING_LEN);
702 			p += ETH_GSTRING_LEN;
703 		}
704 		if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
705 			memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY],
706 			       ETH_GSTRING_LEN);
707 			p += ETH_GSTRING_LEN;
708 		}
709 	}
710 }
711 
712 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
713 {
714 	struct hclge_vport *vport = hclge_get_vport(handle);
715 	struct hclge_dev *hdev = vport->back;
716 	u64 *p;
717 
718 	p = hclge_comm_get_stats(hdev, g_mac_stats_string,
719 				 ARRAY_SIZE(g_mac_stats_string), data);
720 	p = hclge_comm_tqps_get_stats(handle, p);
721 }
722 
723 static void hclge_get_mac_stat(struct hnae3_handle *handle,
724 			       struct hns3_mac_stats *mac_stats)
725 {
726 	struct hclge_vport *vport = hclge_get_vport(handle);
727 	struct hclge_dev *hdev = vport->back;
728 
729 	hclge_update_stats(handle);
730 
731 	mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num;
732 	mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num;
733 }
734 
735 static int hclge_parse_func_status(struct hclge_dev *hdev,
736 				   struct hclge_func_status_cmd *status)
737 {
738 #define HCLGE_MAC_ID_MASK	0xF
739 
740 	if (!(status->pf_state & HCLGE_PF_STATE_DONE))
741 		return -EINVAL;
742 
743 	/* Set the pf to main pf */
744 	if (status->pf_state & HCLGE_PF_STATE_MAIN)
745 		hdev->flag |= HCLGE_FLAG_MAIN;
746 	else
747 		hdev->flag &= ~HCLGE_FLAG_MAIN;
748 
749 	hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK;
750 	return 0;
751 }
752 
753 static int hclge_query_function_status(struct hclge_dev *hdev)
754 {
755 #define HCLGE_QUERY_MAX_CNT	5
756 
757 	struct hclge_func_status_cmd *req;
758 	struct hclge_desc desc;
759 	int timeout = 0;
760 	int ret;
761 
762 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
763 	req = (struct hclge_func_status_cmd *)desc.data;
764 
765 	do {
766 		ret = hclge_cmd_send(&hdev->hw, &desc, 1);
767 		if (ret) {
768 			dev_err(&hdev->pdev->dev,
769 				"query function status failed %d.\n", ret);
770 			return ret;
771 		}
772 
773 		/* Check pf reset is done */
774 		if (req->pf_state)
775 			break;
776 		usleep_range(1000, 2000);
777 	} while (timeout++ < HCLGE_QUERY_MAX_CNT);
778 
779 	return hclge_parse_func_status(hdev, req);
780 }
781 
782 static int hclge_query_pf_resource(struct hclge_dev *hdev)
783 {
784 	struct hclge_pf_res_cmd *req;
785 	struct hclge_desc desc;
786 	int ret;
787 
788 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
789 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
790 	if (ret) {
791 		dev_err(&hdev->pdev->dev,
792 			"query pf resource failed %d.\n", ret);
793 		return ret;
794 	}
795 
796 	req = (struct hclge_pf_res_cmd *)desc.data;
797 	hdev->num_tqps = le16_to_cpu(req->tqp_num) +
798 			 le16_to_cpu(req->ext_tqp_num);
799 	hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
800 
801 	if (req->tx_buf_size)
802 		hdev->tx_buf_size =
803 			le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
804 	else
805 		hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
806 
807 	hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT);
808 
809 	if (req->dv_buf_size)
810 		hdev->dv_buf_size =
811 			le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
812 	else
813 		hdev->dv_buf_size = HCLGE_DEFAULT_DV;
814 
815 	hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
816 
817 	hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic);
818 	if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
819 		dev_err(&hdev->pdev->dev,
820 			"only %u msi resources available, not enough for pf(min:2).\n",
821 			hdev->num_nic_msi);
822 		return -EINVAL;
823 	}
824 
825 	if (hnae3_dev_roce_supported(hdev)) {
826 		hdev->num_roce_msi =
827 			le16_to_cpu(req->pf_intr_vector_number_roce);
828 
829 		/* PF should have NIC vectors and Roce vectors,
830 		 * NIC vectors are queued before Roce vectors.
831 		 */
832 		hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi;
833 	} else {
834 		hdev->num_msi = hdev->num_nic_msi;
835 	}
836 
837 	return 0;
838 }
839 
840 static int hclge_parse_speed(u8 speed_cmd, u32 *speed)
841 {
842 	switch (speed_cmd) {
843 	case HCLGE_FW_MAC_SPEED_10M:
844 		*speed = HCLGE_MAC_SPEED_10M;
845 		break;
846 	case HCLGE_FW_MAC_SPEED_100M:
847 		*speed = HCLGE_MAC_SPEED_100M;
848 		break;
849 	case HCLGE_FW_MAC_SPEED_1G:
850 		*speed = HCLGE_MAC_SPEED_1G;
851 		break;
852 	case HCLGE_FW_MAC_SPEED_10G:
853 		*speed = HCLGE_MAC_SPEED_10G;
854 		break;
855 	case HCLGE_FW_MAC_SPEED_25G:
856 		*speed = HCLGE_MAC_SPEED_25G;
857 		break;
858 	case HCLGE_FW_MAC_SPEED_40G:
859 		*speed = HCLGE_MAC_SPEED_40G;
860 		break;
861 	case HCLGE_FW_MAC_SPEED_50G:
862 		*speed = HCLGE_MAC_SPEED_50G;
863 		break;
864 	case HCLGE_FW_MAC_SPEED_100G:
865 		*speed = HCLGE_MAC_SPEED_100G;
866 		break;
867 	case HCLGE_FW_MAC_SPEED_200G:
868 		*speed = HCLGE_MAC_SPEED_200G;
869 		break;
870 	default:
871 		return -EINVAL;
872 	}
873 
874 	return 0;
875 }
876 
877 static const struct hclge_speed_bit_map speed_bit_map[] = {
878 	{HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT},
879 	{HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT},
880 	{HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT},
881 	{HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT},
882 	{HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT},
883 	{HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},
884 	{HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS},
885 	{HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS},
886 	{HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},
887 };
888 
889 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit)
890 {
891 	u16 i;
892 
893 	for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) {
894 		if (speed == speed_bit_map[i].speed) {
895 			*speed_bit = speed_bit_map[i].speed_bit;
896 			return 0;
897 		}
898 	}
899 
900 	return -EINVAL;
901 }
902 
903 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed)
904 {
905 	struct hclge_vport *vport = hclge_get_vport(handle);
906 	struct hclge_dev *hdev = vport->back;
907 	u32 speed_ability = hdev->hw.mac.speed_ability;
908 	u32 speed_bit = 0;
909 	int ret;
910 
911 	ret = hclge_get_speed_bit(speed, &speed_bit);
912 	if (ret)
913 		return ret;
914 
915 	if (speed_bit & speed_ability)
916 		return 0;
917 
918 	return -EINVAL;
919 }
920 
921 static void hclge_update_fec_support(struct hclge_mac *mac)
922 {
923 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported);
924 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
925 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported);
926 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
927 
928 	if (mac->fec_ability & BIT(HNAE3_FEC_BASER))
929 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
930 				 mac->supported);
931 	if (mac->fec_ability & BIT(HNAE3_FEC_RS))
932 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
933 				 mac->supported);
934 	if (mac->fec_ability & BIT(HNAE3_FEC_LLRS))
935 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
936 				 mac->supported);
937 	if (mac->fec_ability & BIT(HNAE3_FEC_NONE))
938 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
939 				 mac->supported);
940 }
941 
942 static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[8] = {
943 	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT},
944 	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT},
945 	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT},
946 	{HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT},
947 	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT},
948 	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT},
949 	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT},
950 	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},
951 };
952 
953 static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[6] = {
954 	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT},
955 	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT},
956 	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT},
957 	{HCLGE_SUPPORT_100G_R4_BIT,
958 	 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT},
959 	{HCLGE_SUPPORT_100G_R2_BIT,
960 	 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT},
961 	{HCLGE_SUPPORT_200G_BIT,
962 	 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},
963 };
964 
965 static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[8] = {
966 	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT},
967 	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT},
968 	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT},
969 	{HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT},
970 	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT},
971 	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT},
972 	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT},
973 	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},
974 };
975 
976 static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[9] = {
977 	{HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},
978 	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},
979 	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT},
980 	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT},
981 	{HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT},
982 	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT},
983 	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT},
984 	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT},
985 	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},
986 };
987 
988 static void hclge_convert_setting_sr(u16 speed_ability,
989 				     unsigned long *link_mode)
990 {
991 	int i;
992 
993 	for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) {
994 		if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit)
995 			linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode,
996 					 link_mode);
997 	}
998 }
999 
1000 static void hclge_convert_setting_lr(u16 speed_ability,
1001 				     unsigned long *link_mode)
1002 {
1003 	int i;
1004 
1005 	for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) {
1006 		if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit)
1007 			linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode,
1008 					 link_mode);
1009 	}
1010 }
1011 
1012 static void hclge_convert_setting_cr(u16 speed_ability,
1013 				     unsigned long *link_mode)
1014 {
1015 	int i;
1016 
1017 	for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) {
1018 		if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit)
1019 			linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode,
1020 					 link_mode);
1021 	}
1022 }
1023 
1024 static void hclge_convert_setting_kr(u16 speed_ability,
1025 				     unsigned long *link_mode)
1026 {
1027 	int i;
1028 
1029 	for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) {
1030 		if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit)
1031 			linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode,
1032 					 link_mode);
1033 	}
1034 }
1035 
1036 static void hclge_convert_setting_fec(struct hclge_mac *mac)
1037 {
1038 	/* If firmware has reported fec_ability, don't need to convert by speed */
1039 	if (mac->fec_ability)
1040 		goto out;
1041 
1042 	switch (mac->speed) {
1043 	case HCLGE_MAC_SPEED_10G:
1044 	case HCLGE_MAC_SPEED_40G:
1045 		mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) |
1046 				   BIT(HNAE3_FEC_NONE);
1047 		break;
1048 	case HCLGE_MAC_SPEED_25G:
1049 	case HCLGE_MAC_SPEED_50G:
1050 		mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) |
1051 				   BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE);
1052 		break;
1053 	case HCLGE_MAC_SPEED_100G:
1054 		mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
1055 				   BIT(HNAE3_FEC_NONE);
1056 		break;
1057 	case HCLGE_MAC_SPEED_200G:
1058 		mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
1059 				   BIT(HNAE3_FEC_LLRS);
1060 		break;
1061 	default:
1062 		mac->fec_ability = 0;
1063 		break;
1064 	}
1065 
1066 out:
1067 	hclge_update_fec_support(mac);
1068 }
1069 
1070 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
1071 					u16 speed_ability)
1072 {
1073 	struct hclge_mac *mac = &hdev->hw.mac;
1074 
1075 	if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1076 		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1077 				 mac->supported);
1078 
1079 	hclge_convert_setting_sr(speed_ability, mac->supported);
1080 	hclge_convert_setting_lr(speed_ability, mac->supported);
1081 	hclge_convert_setting_cr(speed_ability, mac->supported);
1082 	if (hnae3_dev_fec_supported(hdev))
1083 		hclge_convert_setting_fec(mac);
1084 
1085 	if (hnae3_dev_pause_supported(hdev))
1086 		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1087 
1088 	linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported);
1089 	linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1090 }
1091 
1092 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
1093 					    u16 speed_ability)
1094 {
1095 	struct hclge_mac *mac = &hdev->hw.mac;
1096 
1097 	hclge_convert_setting_kr(speed_ability, mac->supported);
1098 	if (hnae3_dev_fec_supported(hdev))
1099 		hclge_convert_setting_fec(mac);
1100 
1101 	if (hnae3_dev_pause_supported(hdev))
1102 		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1103 
1104 	linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported);
1105 	linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1106 }
1107 
1108 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev,
1109 					 u16 speed_ability)
1110 {
1111 	unsigned long *supported = hdev->hw.mac.supported;
1112 
1113 	/* default to support all speed for GE port */
1114 	if (!speed_ability)
1115 		speed_ability = HCLGE_SUPPORT_GE;
1116 
1117 	if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1118 		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1119 				 supported);
1120 
1121 	if (speed_ability & HCLGE_SUPPORT_100M_BIT) {
1122 		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1123 				 supported);
1124 		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
1125 				 supported);
1126 	}
1127 
1128 	if (speed_ability & HCLGE_SUPPORT_10M_BIT) {
1129 		linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported);
1130 		linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported);
1131 	}
1132 
1133 	if (hnae3_dev_pause_supported(hdev)) {
1134 		linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1135 		linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
1136 	}
1137 
1138 	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
1139 	linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
1140 }
1141 
1142 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability)
1143 {
1144 	u8 media_type = hdev->hw.mac.media_type;
1145 
1146 	if (media_type == HNAE3_MEDIA_TYPE_FIBER)
1147 		hclge_parse_fiber_link_mode(hdev, speed_ability);
1148 	else if (media_type == HNAE3_MEDIA_TYPE_COPPER)
1149 		hclge_parse_copper_link_mode(hdev, speed_ability);
1150 	else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE)
1151 		hclge_parse_backplane_link_mode(hdev, speed_ability);
1152 }
1153 
1154 static u32 hclge_get_max_speed(u16 speed_ability)
1155 {
1156 	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1157 		return HCLGE_MAC_SPEED_200G;
1158 
1159 	if (speed_ability & HCLGE_SUPPORT_100G_BITS)
1160 		return HCLGE_MAC_SPEED_100G;
1161 
1162 	if (speed_ability & HCLGE_SUPPORT_50G_BITS)
1163 		return HCLGE_MAC_SPEED_50G;
1164 
1165 	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1166 		return HCLGE_MAC_SPEED_40G;
1167 
1168 	if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1169 		return HCLGE_MAC_SPEED_25G;
1170 
1171 	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1172 		return HCLGE_MAC_SPEED_10G;
1173 
1174 	if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1175 		return HCLGE_MAC_SPEED_1G;
1176 
1177 	if (speed_ability & HCLGE_SUPPORT_100M_BIT)
1178 		return HCLGE_MAC_SPEED_100M;
1179 
1180 	if (speed_ability & HCLGE_SUPPORT_10M_BIT)
1181 		return HCLGE_MAC_SPEED_10M;
1182 
1183 	return HCLGE_MAC_SPEED_1G;
1184 }
1185 
1186 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1187 {
1188 #define HCLGE_TX_SPARE_SIZE_UNIT		4096
1189 #define SPEED_ABILITY_EXT_SHIFT			8
1190 
1191 	struct hclge_cfg_param_cmd *req;
1192 	u64 mac_addr_tmp_high;
1193 	u16 speed_ability_ext;
1194 	u64 mac_addr_tmp;
1195 	unsigned int i;
1196 
1197 	req = (struct hclge_cfg_param_cmd *)desc[0].data;
1198 
1199 	/* get the configuration */
1200 	cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1201 				      HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1202 	cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1203 					    HCLGE_CFG_TQP_DESC_N_M,
1204 					    HCLGE_CFG_TQP_DESC_N_S);
1205 
1206 	cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1207 					HCLGE_CFG_PHY_ADDR_M,
1208 					HCLGE_CFG_PHY_ADDR_S);
1209 	cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1210 					  HCLGE_CFG_MEDIA_TP_M,
1211 					  HCLGE_CFG_MEDIA_TP_S);
1212 	cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1213 					  HCLGE_CFG_RX_BUF_LEN_M,
1214 					  HCLGE_CFG_RX_BUF_LEN_S);
1215 	/* get mac_address */
1216 	mac_addr_tmp = __le32_to_cpu(req->param[2]);
1217 	mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1218 					    HCLGE_CFG_MAC_ADDR_H_M,
1219 					    HCLGE_CFG_MAC_ADDR_H_S);
1220 
1221 	mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1222 
1223 	cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1224 					     HCLGE_CFG_DEFAULT_SPEED_M,
1225 					     HCLGE_CFG_DEFAULT_SPEED_S);
1226 	cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1227 					       HCLGE_CFG_RSS_SIZE_M,
1228 					       HCLGE_CFG_RSS_SIZE_S);
1229 
1230 	for (i = 0; i < ETH_ALEN; i++)
1231 		cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1232 
1233 	req = (struct hclge_cfg_param_cmd *)desc[1].data;
1234 	cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1235 
1236 	cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1237 					     HCLGE_CFG_SPEED_ABILITY_M,
1238 					     HCLGE_CFG_SPEED_ABILITY_S);
1239 	speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]),
1240 					    HCLGE_CFG_SPEED_ABILITY_EXT_M,
1241 					    HCLGE_CFG_SPEED_ABILITY_EXT_S);
1242 	cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT;
1243 
1244 	cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]),
1245 					       HCLGE_CFG_VLAN_FLTR_CAP_M,
1246 					       HCLGE_CFG_VLAN_FLTR_CAP_S);
1247 
1248 	cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
1249 					 HCLGE_CFG_UMV_TBL_SPACE_M,
1250 					 HCLGE_CFG_UMV_TBL_SPACE_S);
1251 
1252 	cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]),
1253 					       HCLGE_CFG_PF_RSS_SIZE_M,
1254 					       HCLGE_CFG_PF_RSS_SIZE_S);
1255 
1256 	/* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a
1257 	 * power of 2, instead of reading out directly. This would
1258 	 * be more flexible for future changes and expansions.
1259 	 * When VF max  rss size field is HCLGE_CFG_RSS_SIZE_S,
1260 	 * it does not make sense if PF's field is 0. In this case, PF and VF
1261 	 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S.
1262 	 */
1263 	cfg->pf_rss_size_max = cfg->pf_rss_size_max ?
1264 			       1U << cfg->pf_rss_size_max :
1265 			       cfg->vf_rss_size_max;
1266 
1267 	/* The unit of the tx spare buffer size queried from configuration
1268 	 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is
1269 	 * needed here.
1270 	 */
1271 	cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]),
1272 						 HCLGE_CFG_TX_SPARE_BUF_SIZE_M,
1273 						 HCLGE_CFG_TX_SPARE_BUF_SIZE_S);
1274 	cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT;
1275 }
1276 
1277 /* hclge_get_cfg: query the static parameter from flash
1278  * @hdev: pointer to struct hclge_dev
1279  * @hcfg: the config structure to be getted
1280  */
1281 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1282 {
1283 	struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1284 	struct hclge_cfg_param_cmd *req;
1285 	unsigned int i;
1286 	int ret;
1287 
1288 	for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1289 		u32 offset = 0;
1290 
1291 		req = (struct hclge_cfg_param_cmd *)desc[i].data;
1292 		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1293 					   true);
1294 		hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1295 				HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1296 		/* Len should be united by 4 bytes when send to hardware */
1297 		hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1298 				HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1299 		req->offset = cpu_to_le32(offset);
1300 	}
1301 
1302 	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1303 	if (ret) {
1304 		dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
1305 		return ret;
1306 	}
1307 
1308 	hclge_parse_cfg(hcfg, desc);
1309 
1310 	return 0;
1311 }
1312 
1313 static void hclge_set_default_dev_specs(struct hclge_dev *hdev)
1314 {
1315 #define HCLGE_MAX_NON_TSO_BD_NUM			8U
1316 
1317 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1318 
1319 	ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1320 	ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1321 	ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1322 	ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE;
1323 	ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL;
1324 	ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME;
1325 	ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM;
1326 	ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1327 	ae_dev->dev_specs.tnl_num = 0;
1328 }
1329 
1330 static void hclge_parse_dev_specs(struct hclge_dev *hdev,
1331 				  struct hclge_desc *desc)
1332 {
1333 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1334 	struct hclge_dev_specs_0_cmd *req0;
1335 	struct hclge_dev_specs_1_cmd *req1;
1336 
1337 	req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data;
1338 	req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data;
1339 
1340 	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
1341 	ae_dev->dev_specs.rss_ind_tbl_size =
1342 		le16_to_cpu(req0->rss_ind_tbl_size);
1343 	ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
1344 	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
1345 	ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate);
1346 	ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num);
1347 	ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
1348 	ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
1349 	ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size);
1350 	ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size);
1351 	ae_dev->dev_specs.tnl_num = req1->tnl_num;
1352 }
1353 
1354 static void hclge_check_dev_specs(struct hclge_dev *hdev)
1355 {
1356 	struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
1357 
1358 	if (!dev_specs->max_non_tso_bd_num)
1359 		dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1360 	if (!dev_specs->rss_ind_tbl_size)
1361 		dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1362 	if (!dev_specs->rss_key_size)
1363 		dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1364 	if (!dev_specs->max_tm_rate)
1365 		dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE;
1366 	if (!dev_specs->max_qset_num)
1367 		dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM;
1368 	if (!dev_specs->max_int_gl)
1369 		dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL;
1370 	if (!dev_specs->max_frm_size)
1371 		dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME;
1372 	if (!dev_specs->umv_size)
1373 		dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1374 }
1375 
1376 static int hclge_query_mac_stats_num(struct hclge_dev *hdev)
1377 {
1378 	u32 reg_num = 0;
1379 	int ret;
1380 
1381 	ret = hclge_mac_query_reg_num(hdev, &reg_num);
1382 	if (ret && ret != -EOPNOTSUPP)
1383 		return ret;
1384 
1385 	hdev->ae_dev->dev_specs.mac_stats_num = reg_num;
1386 	return 0;
1387 }
1388 
1389 static int hclge_query_dev_specs(struct hclge_dev *hdev)
1390 {
1391 	struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM];
1392 	int ret;
1393 	int i;
1394 
1395 	ret = hclge_query_mac_stats_num(hdev);
1396 	if (ret)
1397 		return ret;
1398 
1399 	/* set default specifications as devices lower than version V3 do not
1400 	 * support querying specifications from firmware.
1401 	 */
1402 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
1403 		hclge_set_default_dev_specs(hdev);
1404 		return 0;
1405 	}
1406 
1407 	for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1408 		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS,
1409 					   true);
1410 		desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
1411 	}
1412 	hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
1413 
1414 	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM);
1415 	if (ret)
1416 		return ret;
1417 
1418 	hclge_parse_dev_specs(hdev, desc);
1419 	hclge_check_dev_specs(hdev);
1420 
1421 	return 0;
1422 }
1423 
1424 static int hclge_get_cap(struct hclge_dev *hdev)
1425 {
1426 	int ret;
1427 
1428 	ret = hclge_query_function_status(hdev);
1429 	if (ret) {
1430 		dev_err(&hdev->pdev->dev,
1431 			"query function status error %d.\n", ret);
1432 		return ret;
1433 	}
1434 
1435 	/* get pf resource */
1436 	return hclge_query_pf_resource(hdev);
1437 }
1438 
1439 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev)
1440 {
1441 #define HCLGE_MIN_TX_DESC	64
1442 #define HCLGE_MIN_RX_DESC	64
1443 
1444 	if (!is_kdump_kernel())
1445 		return;
1446 
1447 	dev_info(&hdev->pdev->dev,
1448 		 "Running kdump kernel. Using minimal resources\n");
1449 
1450 	/* minimal queue pairs equals to the number of vports */
1451 	hdev->num_tqps = hdev->num_req_vfs + 1;
1452 	hdev->num_tx_desc = HCLGE_MIN_TX_DESC;
1453 	hdev->num_rx_desc = HCLGE_MIN_RX_DESC;
1454 }
1455 
1456 static void hclge_init_tc_config(struct hclge_dev *hdev)
1457 {
1458 	unsigned int i;
1459 
1460 	if (hdev->tc_max > HNAE3_MAX_TC ||
1461 	    hdev->tc_max < 1) {
1462 		dev_warn(&hdev->pdev->dev, "TC num = %u.\n",
1463 			 hdev->tc_max);
1464 		hdev->tc_max = 1;
1465 	}
1466 
1467 	/* Dev does not support DCB */
1468 	if (!hnae3_dev_dcb_supported(hdev)) {
1469 		hdev->tc_max = 1;
1470 		hdev->pfc_max = 0;
1471 	} else {
1472 		hdev->pfc_max = hdev->tc_max;
1473 	}
1474 
1475 	hdev->tm_info.num_tc = 1;
1476 
1477 	/* Currently not support uncontiuous tc */
1478 	for (i = 0; i < hdev->tm_info.num_tc; i++)
1479 		hnae3_set_bit(hdev->hw_tc_map, i, 1);
1480 
1481 	hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1482 }
1483 
1484 static int hclge_configure(struct hclge_dev *hdev)
1485 {
1486 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1487 	struct hclge_cfg cfg;
1488 	int ret;
1489 
1490 	ret = hclge_get_cfg(hdev, &cfg);
1491 	if (ret)
1492 		return ret;
1493 
1494 	hdev->base_tqp_pid = 0;
1495 	hdev->vf_rss_size_max = cfg.vf_rss_size_max;
1496 	hdev->pf_rss_size_max = cfg.pf_rss_size_max;
1497 	hdev->rx_buf_len = cfg.rx_buf_len;
1498 	ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1499 	hdev->hw.mac.media_type = cfg.media_type;
1500 	hdev->hw.mac.phy_addr = cfg.phy_addr;
1501 	hdev->num_tx_desc = cfg.tqp_desc_num;
1502 	hdev->num_rx_desc = cfg.tqp_desc_num;
1503 	hdev->tm_info.num_pg = 1;
1504 	hdev->tc_max = cfg.tc_num;
1505 	hdev->tm_info.hw_pfc_map = 0;
1506 	if (cfg.umv_space)
1507 		hdev->wanted_umv_size = cfg.umv_space;
1508 	else
1509 		hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size;
1510 	hdev->tx_spare_buf_size = cfg.tx_spare_buf_size;
1511 	hdev->gro_en = true;
1512 	if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF)
1513 		set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
1514 
1515 	if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
1516 		hdev->fd_en = true;
1517 		hdev->fd_active_type = HCLGE_FD_RULE_NONE;
1518 	}
1519 
1520 	ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1521 	if (ret) {
1522 		dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n",
1523 			cfg.default_speed, ret);
1524 		return ret;
1525 	}
1526 
1527 	hclge_parse_link_mode(hdev, cfg.speed_ability);
1528 
1529 	hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability);
1530 
1531 	hclge_init_tc_config(hdev);
1532 	hclge_init_kdump_kernel_config(hdev);
1533 
1534 	return ret;
1535 }
1536 
1537 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min,
1538 			    u16 tso_mss_max)
1539 {
1540 	struct hclge_cfg_tso_status_cmd *req;
1541 	struct hclge_desc desc;
1542 
1543 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1544 
1545 	req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1546 	req->tso_mss_min = cpu_to_le16(tso_mss_min);
1547 	req->tso_mss_max = cpu_to_le16(tso_mss_max);
1548 
1549 	return hclge_cmd_send(&hdev->hw, &desc, 1);
1550 }
1551 
1552 static int hclge_config_gro(struct hclge_dev *hdev)
1553 {
1554 	struct hclge_cfg_gro_status_cmd *req;
1555 	struct hclge_desc desc;
1556 	int ret;
1557 
1558 	if (!hnae3_ae_dev_gro_supported(hdev->ae_dev))
1559 		return 0;
1560 
1561 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
1562 	req = (struct hclge_cfg_gro_status_cmd *)desc.data;
1563 
1564 	req->gro_en = hdev->gro_en ? 1 : 0;
1565 
1566 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1567 	if (ret)
1568 		dev_err(&hdev->pdev->dev,
1569 			"GRO hardware config cmd failed, ret = %d\n", ret);
1570 
1571 	return ret;
1572 }
1573 
1574 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1575 {
1576 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1577 	struct hclge_comm_tqp *tqp;
1578 	int i;
1579 
1580 	hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1581 				  sizeof(struct hclge_comm_tqp), GFP_KERNEL);
1582 	if (!hdev->htqp)
1583 		return -ENOMEM;
1584 
1585 	tqp = hdev->htqp;
1586 
1587 	for (i = 0; i < hdev->num_tqps; i++) {
1588 		tqp->dev = &hdev->pdev->dev;
1589 		tqp->index = i;
1590 
1591 		tqp->q.ae_algo = &ae_algo;
1592 		tqp->q.buf_size = hdev->rx_buf_len;
1593 		tqp->q.tx_desc_num = hdev->num_tx_desc;
1594 		tqp->q.rx_desc_num = hdev->num_rx_desc;
1595 
1596 		/* need an extended offset to configure queues >=
1597 		 * HCLGE_TQP_MAX_SIZE_DEV_V2
1598 		 */
1599 		if (i < HCLGE_TQP_MAX_SIZE_DEV_V2)
1600 			tqp->q.io_base = hdev->hw.hw.io_base +
1601 					 HCLGE_TQP_REG_OFFSET +
1602 					 i * HCLGE_TQP_REG_SIZE;
1603 		else
1604 			tqp->q.io_base = hdev->hw.hw.io_base +
1605 					 HCLGE_TQP_REG_OFFSET +
1606 					 HCLGE_TQP_EXT_REG_OFFSET +
1607 					 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) *
1608 					 HCLGE_TQP_REG_SIZE;
1609 
1610 		/* when device supports tx push and has device memory,
1611 		 * the queue can execute push mode or doorbell mode on
1612 		 * device memory.
1613 		 */
1614 		if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
1615 			tqp->q.mem_base = hdev->hw.hw.mem_base +
1616 					  HCLGE_TQP_MEM_OFFSET(hdev, i);
1617 
1618 		tqp++;
1619 	}
1620 
1621 	return 0;
1622 }
1623 
1624 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1625 				  u16 tqp_pid, u16 tqp_vid, bool is_pf)
1626 {
1627 	struct hclge_tqp_map_cmd *req;
1628 	struct hclge_desc desc;
1629 	int ret;
1630 
1631 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1632 
1633 	req = (struct hclge_tqp_map_cmd *)desc.data;
1634 	req->tqp_id = cpu_to_le16(tqp_pid);
1635 	req->tqp_vf = func_id;
1636 	req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B;
1637 	if (!is_pf)
1638 		req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B;
1639 	req->tqp_vid = cpu_to_le16(tqp_vid);
1640 
1641 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1642 	if (ret)
1643 		dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1644 
1645 	return ret;
1646 }
1647 
1648 static int  hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps)
1649 {
1650 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1651 	struct hclge_dev *hdev = vport->back;
1652 	int i, alloced;
1653 
1654 	for (i = 0, alloced = 0; i < hdev->num_tqps &&
1655 	     alloced < num_tqps; i++) {
1656 		if (!hdev->htqp[i].alloced) {
1657 			hdev->htqp[i].q.handle = &vport->nic;
1658 			hdev->htqp[i].q.tqp_index = alloced;
1659 			hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc;
1660 			hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc;
1661 			kinfo->tqp[alloced] = &hdev->htqp[i].q;
1662 			hdev->htqp[i].alloced = true;
1663 			alloced++;
1664 		}
1665 	}
1666 	vport->alloc_tqps = alloced;
1667 	kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max,
1668 				vport->alloc_tqps / hdev->tm_info.num_tc);
1669 
1670 	/* ensure one to one mapping between irq and queue at default */
1671 	kinfo->rss_size = min_t(u16, kinfo->rss_size,
1672 				(hdev->num_nic_msi - 1) / hdev->tm_info.num_tc);
1673 
1674 	return 0;
1675 }
1676 
1677 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps,
1678 			    u16 num_tx_desc, u16 num_rx_desc)
1679 
1680 {
1681 	struct hnae3_handle *nic = &vport->nic;
1682 	struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1683 	struct hclge_dev *hdev = vport->back;
1684 	int ret;
1685 
1686 	kinfo->num_tx_desc = num_tx_desc;
1687 	kinfo->num_rx_desc = num_rx_desc;
1688 
1689 	kinfo->rx_buf_len = hdev->rx_buf_len;
1690 	kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size;
1691 
1692 	kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps,
1693 				  sizeof(struct hnae3_queue *), GFP_KERNEL);
1694 	if (!kinfo->tqp)
1695 		return -ENOMEM;
1696 
1697 	ret = hclge_assign_tqp(vport, num_tqps);
1698 	if (ret)
1699 		dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1700 
1701 	return ret;
1702 }
1703 
1704 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1705 				  struct hclge_vport *vport)
1706 {
1707 	struct hnae3_handle *nic = &vport->nic;
1708 	struct hnae3_knic_private_info *kinfo;
1709 	u16 i;
1710 
1711 	kinfo = &nic->kinfo;
1712 	for (i = 0; i < vport->alloc_tqps; i++) {
1713 		struct hclge_comm_tqp *q =
1714 			container_of(kinfo->tqp[i], struct hclge_comm_tqp, q);
1715 		bool is_pf;
1716 		int ret;
1717 
1718 		is_pf = !(vport->vport_id);
1719 		ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1720 					     i, is_pf);
1721 		if (ret)
1722 			return ret;
1723 	}
1724 
1725 	return 0;
1726 }
1727 
1728 static int hclge_map_tqp(struct hclge_dev *hdev)
1729 {
1730 	struct hclge_vport *vport = hdev->vport;
1731 	u16 i, num_vport;
1732 
1733 	num_vport = hdev->num_req_vfs + 1;
1734 	for (i = 0; i < num_vport; i++) {
1735 		int ret;
1736 
1737 		ret = hclge_map_tqp_to_vport(hdev, vport);
1738 		if (ret)
1739 			return ret;
1740 
1741 		vport++;
1742 	}
1743 
1744 	return 0;
1745 }
1746 
1747 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1748 {
1749 	struct hnae3_handle *nic = &vport->nic;
1750 	struct hclge_dev *hdev = vport->back;
1751 	int ret;
1752 
1753 	nic->pdev = hdev->pdev;
1754 	nic->ae_algo = &ae_algo;
1755 	nic->numa_node_mask = hdev->numa_node_mask;
1756 	nic->kinfo.io_base = hdev->hw.hw.io_base;
1757 
1758 	ret = hclge_knic_setup(vport, num_tqps,
1759 			       hdev->num_tx_desc, hdev->num_rx_desc);
1760 	if (ret)
1761 		dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret);
1762 
1763 	return ret;
1764 }
1765 
1766 static int hclge_alloc_vport(struct hclge_dev *hdev)
1767 {
1768 	struct pci_dev *pdev = hdev->pdev;
1769 	struct hclge_vport *vport;
1770 	u32 tqp_main_vport;
1771 	u32 tqp_per_vport;
1772 	int num_vport, i;
1773 	int ret;
1774 
1775 	/* We need to alloc a vport for main NIC of PF */
1776 	num_vport = hdev->num_req_vfs + 1;
1777 
1778 	if (hdev->num_tqps < num_vport) {
1779 		dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)",
1780 			hdev->num_tqps, num_vport);
1781 		return -EINVAL;
1782 	}
1783 
1784 	/* Alloc the same number of TQPs for every vport */
1785 	tqp_per_vport = hdev->num_tqps / num_vport;
1786 	tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1787 
1788 	vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1789 			     GFP_KERNEL);
1790 	if (!vport)
1791 		return -ENOMEM;
1792 
1793 	hdev->vport = vport;
1794 	hdev->num_alloc_vport = num_vport;
1795 
1796 	if (IS_ENABLED(CONFIG_PCI_IOV))
1797 		hdev->num_alloc_vfs = hdev->num_req_vfs;
1798 
1799 	for (i = 0; i < num_vport; i++) {
1800 		vport->back = hdev;
1801 		vport->vport_id = i;
1802 		vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO;
1803 		vport->mps = HCLGE_MAC_DEFAULT_FRAME;
1804 		vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE;
1805 		vport->port_base_vlan_cfg.tbl_sta = true;
1806 		vport->rxvlan_cfg.rx_vlan_offload_en = true;
1807 		vport->req_vlan_fltr_en = true;
1808 		INIT_LIST_HEAD(&vport->vlan_list);
1809 		INIT_LIST_HEAD(&vport->uc_mac_list);
1810 		INIT_LIST_HEAD(&vport->mc_mac_list);
1811 		spin_lock_init(&vport->mac_list_lock);
1812 
1813 		if (i == 0)
1814 			ret = hclge_vport_setup(vport, tqp_main_vport);
1815 		else
1816 			ret = hclge_vport_setup(vport, tqp_per_vport);
1817 		if (ret) {
1818 			dev_err(&pdev->dev,
1819 				"vport setup failed for vport %d, %d\n",
1820 				i, ret);
1821 			return ret;
1822 		}
1823 
1824 		vport++;
1825 	}
1826 
1827 	return 0;
1828 }
1829 
1830 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1831 				    struct hclge_pkt_buf_alloc *buf_alloc)
1832 {
1833 /* TX buffer size is unit by 128 byte */
1834 #define HCLGE_BUF_SIZE_UNIT_SHIFT	7
1835 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK	BIT(15)
1836 	struct hclge_tx_buff_alloc_cmd *req;
1837 	struct hclge_desc desc;
1838 	int ret;
1839 	u8 i;
1840 
1841 	req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1842 
1843 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1844 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1845 		u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1846 
1847 		req->tx_pkt_buff[i] =
1848 			cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1849 				     HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1850 	}
1851 
1852 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1853 	if (ret)
1854 		dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1855 			ret);
1856 
1857 	return ret;
1858 }
1859 
1860 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1861 				 struct hclge_pkt_buf_alloc *buf_alloc)
1862 {
1863 	int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1864 
1865 	if (ret)
1866 		dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1867 
1868 	return ret;
1869 }
1870 
1871 static u32 hclge_get_tc_num(struct hclge_dev *hdev)
1872 {
1873 	unsigned int i;
1874 	u32 cnt = 0;
1875 
1876 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1877 		if (hdev->hw_tc_map & BIT(i))
1878 			cnt++;
1879 	return cnt;
1880 }
1881 
1882 /* Get the number of pfc enabled TCs, which have private buffer */
1883 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1884 				  struct hclge_pkt_buf_alloc *buf_alloc)
1885 {
1886 	struct hclge_priv_buf *priv;
1887 	unsigned int i;
1888 	int cnt = 0;
1889 
1890 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1891 		priv = &buf_alloc->priv_buf[i];
1892 		if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1893 		    priv->enable)
1894 			cnt++;
1895 	}
1896 
1897 	return cnt;
1898 }
1899 
1900 /* Get the number of pfc disabled TCs, which have private buffer */
1901 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1902 				     struct hclge_pkt_buf_alloc *buf_alloc)
1903 {
1904 	struct hclge_priv_buf *priv;
1905 	unsigned int i;
1906 	int cnt = 0;
1907 
1908 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1909 		priv = &buf_alloc->priv_buf[i];
1910 		if (hdev->hw_tc_map & BIT(i) &&
1911 		    !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1912 		    priv->enable)
1913 			cnt++;
1914 	}
1915 
1916 	return cnt;
1917 }
1918 
1919 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1920 {
1921 	struct hclge_priv_buf *priv;
1922 	u32 rx_priv = 0;
1923 	int i;
1924 
1925 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1926 		priv = &buf_alloc->priv_buf[i];
1927 		if (priv->enable)
1928 			rx_priv += priv->buf_size;
1929 	}
1930 	return rx_priv;
1931 }
1932 
1933 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1934 {
1935 	u32 i, total_tx_size = 0;
1936 
1937 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1938 		total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1939 
1940 	return total_tx_size;
1941 }
1942 
1943 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1944 				struct hclge_pkt_buf_alloc *buf_alloc,
1945 				u32 rx_all)
1946 {
1947 	u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
1948 	u32 tc_num = hclge_get_tc_num(hdev);
1949 	u32 shared_buf, aligned_mps;
1950 	u32 rx_priv;
1951 	int i;
1952 
1953 	aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1954 
1955 	if (hnae3_dev_dcb_supported(hdev))
1956 		shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps +
1957 					hdev->dv_buf_size;
1958 	else
1959 		shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF
1960 					+ hdev->dv_buf_size;
1961 
1962 	shared_buf_tc = tc_num * aligned_mps + aligned_mps;
1963 	shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc),
1964 			     HCLGE_BUF_SIZE_UNIT);
1965 
1966 	rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1967 	if (rx_all < rx_priv + shared_std)
1968 		return false;
1969 
1970 	shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT);
1971 	buf_alloc->s_buf.buf_size = shared_buf;
1972 	if (hnae3_dev_dcb_supported(hdev)) {
1973 		buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
1974 		buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1975 			- roundup(aligned_mps / HCLGE_BUF_DIV_BY,
1976 				  HCLGE_BUF_SIZE_UNIT);
1977 	} else {
1978 		buf_alloc->s_buf.self.high = aligned_mps +
1979 						HCLGE_NON_DCB_ADDITIONAL_BUF;
1980 		buf_alloc->s_buf.self.low = aligned_mps;
1981 	}
1982 
1983 	if (hnae3_dev_dcb_supported(hdev)) {
1984 		hi_thrd = shared_buf - hdev->dv_buf_size;
1985 
1986 		if (tc_num <= NEED_RESERVE_TC_NUM)
1987 			hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
1988 					/ BUF_MAX_PERCENT;
1989 
1990 		if (tc_num)
1991 			hi_thrd = hi_thrd / tc_num;
1992 
1993 		hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps);
1994 		hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT);
1995 		lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY;
1996 	} else {
1997 		hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF;
1998 		lo_thrd = aligned_mps;
1999 	}
2000 
2001 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2002 		buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2003 		buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2004 	}
2005 
2006 	return true;
2007 }
2008 
2009 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
2010 				struct hclge_pkt_buf_alloc *buf_alloc)
2011 {
2012 	u32 i, total_size;
2013 
2014 	total_size = hdev->pkt_buf_size;
2015 
2016 	/* alloc tx buffer for all enabled tc */
2017 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2018 		struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2019 
2020 		if (hdev->hw_tc_map & BIT(i)) {
2021 			if (total_size < hdev->tx_buf_size)
2022 				return -ENOMEM;
2023 
2024 			priv->tx_buf_size = hdev->tx_buf_size;
2025 		} else {
2026 			priv->tx_buf_size = 0;
2027 		}
2028 
2029 		total_size -= priv->tx_buf_size;
2030 	}
2031 
2032 	return 0;
2033 }
2034 
2035 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max,
2036 				  struct hclge_pkt_buf_alloc *buf_alloc)
2037 {
2038 	u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2039 	u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
2040 	unsigned int i;
2041 
2042 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2043 		struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2044 
2045 		priv->enable = 0;
2046 		priv->wl.low = 0;
2047 		priv->wl.high = 0;
2048 		priv->buf_size = 0;
2049 
2050 		if (!(hdev->hw_tc_map & BIT(i)))
2051 			continue;
2052 
2053 		priv->enable = 1;
2054 
2055 		if (hdev->tm_info.hw_pfc_map & BIT(i)) {
2056 			priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT;
2057 			priv->wl.high = roundup(priv->wl.low + aligned_mps,
2058 						HCLGE_BUF_SIZE_UNIT);
2059 		} else {
2060 			priv->wl.low = 0;
2061 			priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) :
2062 					aligned_mps;
2063 		}
2064 
2065 		priv->buf_size = priv->wl.high + hdev->dv_buf_size;
2066 	}
2067 
2068 	return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2069 }
2070 
2071 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev,
2072 					  struct hclge_pkt_buf_alloc *buf_alloc)
2073 {
2074 	u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2075 	int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
2076 	int i;
2077 
2078 	/* let the last to be cleared first */
2079 	for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2080 		struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2081 		unsigned int mask = BIT((unsigned int)i);
2082 
2083 		if (hdev->hw_tc_map & mask &&
2084 		    !(hdev->tm_info.hw_pfc_map & mask)) {
2085 			/* Clear the no pfc TC private buffer */
2086 			priv->wl.low = 0;
2087 			priv->wl.high = 0;
2088 			priv->buf_size = 0;
2089 			priv->enable = 0;
2090 			no_pfc_priv_num--;
2091 		}
2092 
2093 		if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2094 		    no_pfc_priv_num == 0)
2095 			break;
2096 	}
2097 
2098 	return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2099 }
2100 
2101 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev,
2102 					struct hclge_pkt_buf_alloc *buf_alloc)
2103 {
2104 	u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2105 	int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
2106 	int i;
2107 
2108 	/* let the last to be cleared first */
2109 	for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2110 		struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2111 		unsigned int mask = BIT((unsigned int)i);
2112 
2113 		if (hdev->hw_tc_map & mask &&
2114 		    hdev->tm_info.hw_pfc_map & mask) {
2115 			/* Reduce the number of pfc TC with private buffer */
2116 			priv->wl.low = 0;
2117 			priv->enable = 0;
2118 			priv->wl.high = 0;
2119 			priv->buf_size = 0;
2120 			pfc_priv_num--;
2121 		}
2122 
2123 		if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2124 		    pfc_priv_num == 0)
2125 			break;
2126 	}
2127 
2128 	return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2129 }
2130 
2131 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev,
2132 				      struct hclge_pkt_buf_alloc *buf_alloc)
2133 {
2134 #define COMPENSATE_BUFFER	0x3C00
2135 #define COMPENSATE_HALF_MPS_NUM	5
2136 #define PRIV_WL_GAP		0x1800
2137 
2138 	u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2139 	u32 tc_num = hclge_get_tc_num(hdev);
2140 	u32 half_mps = hdev->mps >> 1;
2141 	u32 min_rx_priv;
2142 	unsigned int i;
2143 
2144 	if (tc_num)
2145 		rx_priv = rx_priv / tc_num;
2146 
2147 	if (tc_num <= NEED_RESERVE_TC_NUM)
2148 		rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
2149 
2150 	min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER +
2151 			COMPENSATE_HALF_MPS_NUM * half_mps;
2152 	min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT);
2153 	rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT);
2154 	if (rx_priv < min_rx_priv)
2155 		return false;
2156 
2157 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2158 		struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2159 
2160 		priv->enable = 0;
2161 		priv->wl.low = 0;
2162 		priv->wl.high = 0;
2163 		priv->buf_size = 0;
2164 
2165 		if (!(hdev->hw_tc_map & BIT(i)))
2166 			continue;
2167 
2168 		priv->enable = 1;
2169 		priv->buf_size = rx_priv;
2170 		priv->wl.high = rx_priv - hdev->dv_buf_size;
2171 		priv->wl.low = priv->wl.high - PRIV_WL_GAP;
2172 	}
2173 
2174 	buf_alloc->s_buf.buf_size = 0;
2175 
2176 	return true;
2177 }
2178 
2179 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
2180  * @hdev: pointer to struct hclge_dev
2181  * @buf_alloc: pointer to buffer calculation data
2182  * @return: 0: calculate successful, negative: fail
2183  */
2184 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
2185 				struct hclge_pkt_buf_alloc *buf_alloc)
2186 {
2187 	/* When DCB is not supported, rx private buffer is not allocated. */
2188 	if (!hnae3_dev_dcb_supported(hdev)) {
2189 		u32 rx_all = hdev->pkt_buf_size;
2190 
2191 		rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
2192 		if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
2193 			return -ENOMEM;
2194 
2195 		return 0;
2196 	}
2197 
2198 	if (hclge_only_alloc_priv_buff(hdev, buf_alloc))
2199 		return 0;
2200 
2201 	if (hclge_rx_buf_calc_all(hdev, true, buf_alloc))
2202 		return 0;
2203 
2204 	/* try to decrease the buffer size */
2205 	if (hclge_rx_buf_calc_all(hdev, false, buf_alloc))
2206 		return 0;
2207 
2208 	if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc))
2209 		return 0;
2210 
2211 	if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc))
2212 		return 0;
2213 
2214 	return -ENOMEM;
2215 }
2216 
2217 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
2218 				   struct hclge_pkt_buf_alloc *buf_alloc)
2219 {
2220 	struct hclge_rx_priv_buff_cmd *req;
2221 	struct hclge_desc desc;
2222 	int ret;
2223 	int i;
2224 
2225 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
2226 	req = (struct hclge_rx_priv_buff_cmd *)desc.data;
2227 
2228 	/* Alloc private buffer TCs */
2229 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2230 		struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2231 
2232 		req->buf_num[i] =
2233 			cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
2234 		req->buf_num[i] |=
2235 			cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
2236 	}
2237 
2238 	req->shared_buf =
2239 		cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
2240 			    (1 << HCLGE_TC0_PRI_BUF_EN_B));
2241 
2242 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2243 	if (ret)
2244 		dev_err(&hdev->pdev->dev,
2245 			"rx private buffer alloc cmd failed %d\n", ret);
2246 
2247 	return ret;
2248 }
2249 
2250 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
2251 				   struct hclge_pkt_buf_alloc *buf_alloc)
2252 {
2253 	struct hclge_rx_priv_wl_buf *req;
2254 	struct hclge_priv_buf *priv;
2255 	struct hclge_desc desc[2];
2256 	int i, j;
2257 	int ret;
2258 
2259 	for (i = 0; i < 2; i++) {
2260 		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
2261 					   false);
2262 		req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
2263 
2264 		/* The first descriptor set the NEXT bit to 1 */
2265 		if (i == 0)
2266 			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2267 		else
2268 			desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2269 
2270 		for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2271 			u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
2272 
2273 			priv = &buf_alloc->priv_buf[idx];
2274 			req->tc_wl[j].high =
2275 				cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
2276 			req->tc_wl[j].high |=
2277 				cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2278 			req->tc_wl[j].low =
2279 				cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
2280 			req->tc_wl[j].low |=
2281 				 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2282 		}
2283 	}
2284 
2285 	/* Send 2 descriptor at one time */
2286 	ret = hclge_cmd_send(&hdev->hw, desc, 2);
2287 	if (ret)
2288 		dev_err(&hdev->pdev->dev,
2289 			"rx private waterline config cmd failed %d\n",
2290 			ret);
2291 	return ret;
2292 }
2293 
2294 static int hclge_common_thrd_config(struct hclge_dev *hdev,
2295 				    struct hclge_pkt_buf_alloc *buf_alloc)
2296 {
2297 	struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
2298 	struct hclge_rx_com_thrd *req;
2299 	struct hclge_desc desc[2];
2300 	struct hclge_tc_thrd *tc;
2301 	int i, j;
2302 	int ret;
2303 
2304 	for (i = 0; i < 2; i++) {
2305 		hclge_cmd_setup_basic_desc(&desc[i],
2306 					   HCLGE_OPC_RX_COM_THRD_ALLOC, false);
2307 		req = (struct hclge_rx_com_thrd *)&desc[i].data;
2308 
2309 		/* The first descriptor set the NEXT bit to 1 */
2310 		if (i == 0)
2311 			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2312 		else
2313 			desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2314 
2315 		for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2316 			tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
2317 
2318 			req->com_thrd[j].high =
2319 				cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
2320 			req->com_thrd[j].high |=
2321 				 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2322 			req->com_thrd[j].low =
2323 				cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
2324 			req->com_thrd[j].low |=
2325 				 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2326 		}
2327 	}
2328 
2329 	/* Send 2 descriptors at one time */
2330 	ret = hclge_cmd_send(&hdev->hw, desc, 2);
2331 	if (ret)
2332 		dev_err(&hdev->pdev->dev,
2333 			"common threshold config cmd failed %d\n", ret);
2334 	return ret;
2335 }
2336 
2337 static int hclge_common_wl_config(struct hclge_dev *hdev,
2338 				  struct hclge_pkt_buf_alloc *buf_alloc)
2339 {
2340 	struct hclge_shared_buf *buf = &buf_alloc->s_buf;
2341 	struct hclge_rx_com_wl *req;
2342 	struct hclge_desc desc;
2343 	int ret;
2344 
2345 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
2346 
2347 	req = (struct hclge_rx_com_wl *)desc.data;
2348 	req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
2349 	req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2350 
2351 	req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
2352 	req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2353 
2354 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2355 	if (ret)
2356 		dev_err(&hdev->pdev->dev,
2357 			"common waterline config cmd failed %d\n", ret);
2358 
2359 	return ret;
2360 }
2361 
2362 int hclge_buffer_alloc(struct hclge_dev *hdev)
2363 {
2364 	struct hclge_pkt_buf_alloc *pkt_buf;
2365 	int ret;
2366 
2367 	pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
2368 	if (!pkt_buf)
2369 		return -ENOMEM;
2370 
2371 	ret = hclge_tx_buffer_calc(hdev, pkt_buf);
2372 	if (ret) {
2373 		dev_err(&hdev->pdev->dev,
2374 			"could not calc tx buffer size for all TCs %d\n", ret);
2375 		goto out;
2376 	}
2377 
2378 	ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
2379 	if (ret) {
2380 		dev_err(&hdev->pdev->dev,
2381 			"could not alloc tx buffers %d\n", ret);
2382 		goto out;
2383 	}
2384 
2385 	ret = hclge_rx_buffer_calc(hdev, pkt_buf);
2386 	if (ret) {
2387 		dev_err(&hdev->pdev->dev,
2388 			"could not calc rx priv buffer size for all TCs %d\n",
2389 			ret);
2390 		goto out;
2391 	}
2392 
2393 	ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
2394 	if (ret) {
2395 		dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
2396 			ret);
2397 		goto out;
2398 	}
2399 
2400 	if (hnae3_dev_dcb_supported(hdev)) {
2401 		ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2402 		if (ret) {
2403 			dev_err(&hdev->pdev->dev,
2404 				"could not configure rx private waterline %d\n",
2405 				ret);
2406 			goto out;
2407 		}
2408 
2409 		ret = hclge_common_thrd_config(hdev, pkt_buf);
2410 		if (ret) {
2411 			dev_err(&hdev->pdev->dev,
2412 				"could not configure common threshold %d\n",
2413 				ret);
2414 			goto out;
2415 		}
2416 	}
2417 
2418 	ret = hclge_common_wl_config(hdev, pkt_buf);
2419 	if (ret)
2420 		dev_err(&hdev->pdev->dev,
2421 			"could not configure common waterline %d\n", ret);
2422 
2423 out:
2424 	kfree(pkt_buf);
2425 	return ret;
2426 }
2427 
2428 static int hclge_init_roce_base_info(struct hclge_vport *vport)
2429 {
2430 	struct hnae3_handle *roce = &vport->roce;
2431 	struct hnae3_handle *nic = &vport->nic;
2432 	struct hclge_dev *hdev = vport->back;
2433 
2434 	roce->rinfo.num_vectors = vport->back->num_roce_msi;
2435 
2436 	if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi)
2437 		return -EINVAL;
2438 
2439 	roce->rinfo.base_vector = hdev->num_nic_msi;
2440 
2441 	roce->rinfo.netdev = nic->kinfo.netdev;
2442 	roce->rinfo.roce_io_base = hdev->hw.hw.io_base;
2443 	roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;
2444 
2445 	roce->pdev = nic->pdev;
2446 	roce->ae_algo = nic->ae_algo;
2447 	roce->numa_node_mask = nic->numa_node_mask;
2448 
2449 	return 0;
2450 }
2451 
2452 static int hclge_init_msi(struct hclge_dev *hdev)
2453 {
2454 	struct pci_dev *pdev = hdev->pdev;
2455 	int vectors;
2456 	int i;
2457 
2458 	vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2459 					hdev->num_msi,
2460 					PCI_IRQ_MSI | PCI_IRQ_MSIX);
2461 	if (vectors < 0) {
2462 		dev_err(&pdev->dev,
2463 			"failed(%d) to allocate MSI/MSI-X vectors\n",
2464 			vectors);
2465 		return vectors;
2466 	}
2467 	if (vectors < hdev->num_msi)
2468 		dev_warn(&hdev->pdev->dev,
2469 			 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2470 			 hdev->num_msi, vectors);
2471 
2472 	hdev->num_msi = vectors;
2473 	hdev->num_msi_left = vectors;
2474 
2475 	hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2476 					   sizeof(u16), GFP_KERNEL);
2477 	if (!hdev->vector_status) {
2478 		pci_free_irq_vectors(pdev);
2479 		return -ENOMEM;
2480 	}
2481 
2482 	for (i = 0; i < hdev->num_msi; i++)
2483 		hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2484 
2485 	hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2486 					sizeof(int), GFP_KERNEL);
2487 	if (!hdev->vector_irq) {
2488 		pci_free_irq_vectors(pdev);
2489 		return -ENOMEM;
2490 	}
2491 
2492 	return 0;
2493 }
2494 
2495 static u8 hclge_check_speed_dup(u8 duplex, int speed)
2496 {
2497 	if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
2498 		duplex = HCLGE_MAC_FULL;
2499 
2500 	return duplex;
2501 }
2502 
2503 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = {
2504 	{HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M},
2505 	{HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M},
2506 	{HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G},
2507 	{HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G},
2508 	{HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G},
2509 	{HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G},
2510 	{HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G},
2511 	{HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G},
2512 	{HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G},
2513 };
2514 
2515 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw)
2516 {
2517 	u16 i;
2518 
2519 	for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) {
2520 		if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) {
2521 			*speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw;
2522 			return 0;
2523 		}
2524 	}
2525 
2526 	return -EINVAL;
2527 }
2528 
2529 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
2530 				      u8 duplex, u8 lane_num)
2531 {
2532 	struct hclge_config_mac_speed_dup_cmd *req;
2533 	struct hclge_desc desc;
2534 	u32 speed_fw;
2535 	int ret;
2536 
2537 	req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2538 
2539 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2540 
2541 	if (duplex)
2542 		hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1);
2543 
2544 	ret = hclge_convert_to_fw_speed(speed, &speed_fw);
2545 	if (ret) {
2546 		dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2547 		return ret;
2548 	}
2549 
2550 	hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S,
2551 			speed_fw);
2552 	hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2553 		      1);
2554 	req->lane_num = lane_num;
2555 
2556 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2557 	if (ret) {
2558 		dev_err(&hdev->pdev->dev,
2559 			"mac speed/duplex config cmd failed %d.\n", ret);
2560 		return ret;
2561 	}
2562 
2563 	return 0;
2564 }
2565 
2566 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num)
2567 {
2568 	struct hclge_mac *mac = &hdev->hw.mac;
2569 	int ret;
2570 
2571 	duplex = hclge_check_speed_dup(duplex, speed);
2572 	if (!mac->support_autoneg && mac->speed == speed &&
2573 	    mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0))
2574 		return 0;
2575 
2576 	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num);
2577 	if (ret)
2578 		return ret;
2579 
2580 	hdev->hw.mac.speed = speed;
2581 	hdev->hw.mac.duplex = duplex;
2582 	if (!lane_num)
2583 		hdev->hw.mac.lane_num = lane_num;
2584 
2585 	return 0;
2586 }
2587 
2588 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2589 				     u8 duplex, u8 lane_num)
2590 {
2591 	struct hclge_vport *vport = hclge_get_vport(handle);
2592 	struct hclge_dev *hdev = vport->back;
2593 
2594 	return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num);
2595 }
2596 
2597 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2598 {
2599 	struct hclge_config_auto_neg_cmd *req;
2600 	struct hclge_desc desc;
2601 	u32 flag = 0;
2602 	int ret;
2603 
2604 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2605 
2606 	req = (struct hclge_config_auto_neg_cmd *)desc.data;
2607 	if (enable)
2608 		hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U);
2609 	req->cfg_an_cmd_flag = cpu_to_le32(flag);
2610 
2611 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2612 	if (ret)
2613 		dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2614 			ret);
2615 
2616 	return ret;
2617 }
2618 
2619 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2620 {
2621 	struct hclge_vport *vport = hclge_get_vport(handle);
2622 	struct hclge_dev *hdev = vport->back;
2623 
2624 	if (!hdev->hw.mac.support_autoneg) {
2625 		if (enable) {
2626 			dev_err(&hdev->pdev->dev,
2627 				"autoneg is not supported by current port\n");
2628 			return -EOPNOTSUPP;
2629 		} else {
2630 			return 0;
2631 		}
2632 	}
2633 
2634 	return hclge_set_autoneg_en(hdev, enable);
2635 }
2636 
2637 static int hclge_get_autoneg(struct hnae3_handle *handle)
2638 {
2639 	struct hclge_vport *vport = hclge_get_vport(handle);
2640 	struct hclge_dev *hdev = vport->back;
2641 	struct phy_device *phydev = hdev->hw.mac.phydev;
2642 
2643 	if (phydev)
2644 		return phydev->autoneg;
2645 
2646 	return hdev->hw.mac.autoneg;
2647 }
2648 
2649 static int hclge_restart_autoneg(struct hnae3_handle *handle)
2650 {
2651 	struct hclge_vport *vport = hclge_get_vport(handle);
2652 	struct hclge_dev *hdev = vport->back;
2653 	int ret;
2654 
2655 	dev_dbg(&hdev->pdev->dev, "restart autoneg\n");
2656 
2657 	ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2658 	if (ret)
2659 		return ret;
2660 	return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2661 }
2662 
2663 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt)
2664 {
2665 	struct hclge_vport *vport = hclge_get_vport(handle);
2666 	struct hclge_dev *hdev = vport->back;
2667 
2668 	if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg)
2669 		return hclge_set_autoneg_en(hdev, !halt);
2670 
2671 	return 0;
2672 }
2673 
2674 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev,
2675 					struct hclge_desc *desc, u32 desc_len)
2676 {
2677 	u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2;
2678 	u32 desc_index = 0;
2679 	u32 data_index = 0;
2680 	u32 i;
2681 
2682 	for (i = 0; i < lane_size; i++) {
2683 		if (data_index >= HCLGE_DESC_DATA_LEN) {
2684 			desc_index++;
2685 			data_index = 0;
2686 		}
2687 
2688 		if (desc_index >= desc_len)
2689 			return;
2690 
2691 		hdev->fec_stats.per_lanes[i] +=
2692 			le32_to_cpu(desc[desc_index].data[data_index]);
2693 		data_index++;
2694 	}
2695 }
2696 
2697 static void hclge_parse_fec_stats(struct hclge_dev *hdev,
2698 				  struct hclge_desc *desc, u32 desc_len)
2699 {
2700 	struct hclge_query_fec_stats_cmd *req;
2701 
2702 	req = (struct hclge_query_fec_stats_cmd *)desc[0].data;
2703 
2704 	hdev->fec_stats.base_r_lane_num = req->base_r_lane_num;
2705 	hdev->fec_stats.rs_corr_blocks +=
2706 		le32_to_cpu(req->rs_fec_corr_blocks);
2707 	hdev->fec_stats.rs_uncorr_blocks +=
2708 		le32_to_cpu(req->rs_fec_uncorr_blocks);
2709 	hdev->fec_stats.rs_error_blocks +=
2710 		le32_to_cpu(req->rs_fec_error_blocks);
2711 	hdev->fec_stats.base_r_corr_blocks +=
2712 		le32_to_cpu(req->base_r_fec_corr_blocks);
2713 	hdev->fec_stats.base_r_uncorr_blocks +=
2714 		le32_to_cpu(req->base_r_fec_uncorr_blocks);
2715 
2716 	hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1);
2717 }
2718 
2719 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev)
2720 {
2721 	struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM];
2722 	int ret;
2723 	u32 i;
2724 
2725 	for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) {
2726 		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS,
2727 					   true);
2728 		if (i != (HCLGE_FEC_STATS_CMD_NUM - 1))
2729 			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2730 	}
2731 
2732 	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM);
2733 	if (ret)
2734 		return ret;
2735 
2736 	hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM);
2737 
2738 	return 0;
2739 }
2740 
2741 static void hclge_update_fec_stats(struct hclge_dev *hdev)
2742 {
2743 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2744 	int ret;
2745 
2746 	if (!hnae3_ae_dev_fec_stats_supported(ae_dev) ||
2747 	    test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state))
2748 		return;
2749 
2750 	ret = hclge_update_fec_stats_hw(hdev);
2751 	if (ret)
2752 		dev_err(&hdev->pdev->dev,
2753 			"failed to update fec stats, ret = %d\n", ret);
2754 
2755 	clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state);
2756 }
2757 
2758 static void hclge_get_fec_stats_total(struct hclge_dev *hdev,
2759 				      struct ethtool_fec_stats *fec_stats)
2760 {
2761 	fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks;
2762 	fec_stats->uncorrectable_blocks.total =
2763 		hdev->fec_stats.rs_uncorr_blocks;
2764 }
2765 
2766 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev,
2767 				      struct ethtool_fec_stats *fec_stats)
2768 {
2769 	u32 i;
2770 
2771 	if (hdev->fec_stats.base_r_lane_num == 0 ||
2772 	    hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) {
2773 		dev_err(&hdev->pdev->dev,
2774 			"fec stats lane number(%llu) is invalid\n",
2775 			hdev->fec_stats.base_r_lane_num);
2776 		return;
2777 	}
2778 
2779 	for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) {
2780 		fec_stats->corrected_blocks.lanes[i] =
2781 			hdev->fec_stats.base_r_corr_per_lanes[i];
2782 		fec_stats->uncorrectable_blocks.lanes[i] =
2783 			hdev->fec_stats.base_r_uncorr_per_lanes[i];
2784 	}
2785 }
2786 
2787 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev,
2788 				     struct ethtool_fec_stats *fec_stats)
2789 {
2790 	u32 fec_mode = hdev->hw.mac.fec_mode;
2791 
2792 	switch (fec_mode) {
2793 	case BIT(HNAE3_FEC_RS):
2794 	case BIT(HNAE3_FEC_LLRS):
2795 		hclge_get_fec_stats_total(hdev, fec_stats);
2796 		break;
2797 	case BIT(HNAE3_FEC_BASER):
2798 		hclge_get_fec_stats_lanes(hdev, fec_stats);
2799 		break;
2800 	default:
2801 		dev_err(&hdev->pdev->dev,
2802 			"fec stats is not supported by current fec mode(0x%x)\n",
2803 			fec_mode);
2804 		break;
2805 	}
2806 }
2807 
2808 static void hclge_get_fec_stats(struct hnae3_handle *handle,
2809 				struct ethtool_fec_stats *fec_stats)
2810 {
2811 	struct hclge_vport *vport = hclge_get_vport(handle);
2812 	struct hclge_dev *hdev = vport->back;
2813 	u32 fec_mode = hdev->hw.mac.fec_mode;
2814 
2815 	if (fec_mode == BIT(HNAE3_FEC_NONE) ||
2816 	    fec_mode == BIT(HNAE3_FEC_AUTO) ||
2817 	    fec_mode == BIT(HNAE3_FEC_USER_DEF))
2818 		return;
2819 
2820 	hclge_update_fec_stats(hdev);
2821 
2822 	hclge_comm_get_fec_stats(hdev, fec_stats);
2823 }
2824 
2825 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode)
2826 {
2827 	struct hclge_config_fec_cmd *req;
2828 	struct hclge_desc desc;
2829 	int ret;
2830 
2831 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false);
2832 
2833 	req = (struct hclge_config_fec_cmd *)desc.data;
2834 	if (fec_mode & BIT(HNAE3_FEC_AUTO))
2835 		hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1);
2836 	if (fec_mode & BIT(HNAE3_FEC_RS))
2837 		hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2838 				HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS);
2839 	if (fec_mode & BIT(HNAE3_FEC_LLRS))
2840 		hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2841 				HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS);
2842 	if (fec_mode & BIT(HNAE3_FEC_BASER))
2843 		hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2844 				HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER);
2845 
2846 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2847 	if (ret)
2848 		dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret);
2849 
2850 	return ret;
2851 }
2852 
2853 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode)
2854 {
2855 	struct hclge_vport *vport = hclge_get_vport(handle);
2856 	struct hclge_dev *hdev = vport->back;
2857 	struct hclge_mac *mac = &hdev->hw.mac;
2858 	int ret;
2859 
2860 	if (fec_mode && !(mac->fec_ability & fec_mode)) {
2861 		dev_err(&hdev->pdev->dev, "unsupported fec mode\n");
2862 		return -EINVAL;
2863 	}
2864 
2865 	ret = hclge_set_fec_hw(hdev, fec_mode);
2866 	if (ret)
2867 		return ret;
2868 
2869 	mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF);
2870 	return 0;
2871 }
2872 
2873 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability,
2874 			  u8 *fec_mode)
2875 {
2876 	struct hclge_vport *vport = hclge_get_vport(handle);
2877 	struct hclge_dev *hdev = vport->back;
2878 	struct hclge_mac *mac = &hdev->hw.mac;
2879 
2880 	if (fec_ability)
2881 		*fec_ability = mac->fec_ability;
2882 	if (fec_mode)
2883 		*fec_mode = mac->fec_mode;
2884 }
2885 
2886 static int hclge_mac_init(struct hclge_dev *hdev)
2887 {
2888 	struct hclge_mac *mac = &hdev->hw.mac;
2889 	int ret;
2890 
2891 	hdev->support_sfp_query = true;
2892 	hdev->hw.mac.duplex = HCLGE_MAC_FULL;
2893 	ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
2894 					 hdev->hw.mac.duplex, hdev->hw.mac.lane_num);
2895 	if (ret)
2896 		return ret;
2897 
2898 	if (hdev->hw.mac.support_autoneg) {
2899 		ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg);
2900 		if (ret)
2901 			return ret;
2902 	}
2903 
2904 	mac->link = 0;
2905 
2906 	if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) {
2907 		ret = hclge_set_fec_hw(hdev, mac->user_fec_mode);
2908 		if (ret)
2909 			return ret;
2910 	}
2911 
2912 	ret = hclge_set_mac_mtu(hdev, hdev->mps);
2913 	if (ret) {
2914 		dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret);
2915 		return ret;
2916 	}
2917 
2918 	ret = hclge_set_default_loopback(hdev);
2919 	if (ret)
2920 		return ret;
2921 
2922 	ret = hclge_buffer_alloc(hdev);
2923 	if (ret)
2924 		dev_err(&hdev->pdev->dev,
2925 			"allocate buffer fail, ret=%d\n", ret);
2926 
2927 	return ret;
2928 }
2929 
2930 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2931 {
2932 	if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2933 	    !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) {
2934 		hdev->last_mbx_scheduled = jiffies;
2935 		mod_delayed_work(hclge_wq, &hdev->service_task, 0);
2936 	}
2937 }
2938 
2939 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2940 {
2941 	if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2942 	    test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) &&
2943 	    !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) {
2944 		hdev->last_rst_scheduled = jiffies;
2945 		mod_delayed_work(hclge_wq, &hdev->service_task, 0);
2946 	}
2947 }
2948 
2949 static void hclge_errhand_task_schedule(struct hclge_dev *hdev)
2950 {
2951 	if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2952 	    !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
2953 		mod_delayed_work(hclge_wq, &hdev->service_task, 0);
2954 }
2955 
2956 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time)
2957 {
2958 	if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2959 	    !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
2960 		mod_delayed_work(hclge_wq, &hdev->service_task, delay_time);
2961 }
2962 
2963 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status)
2964 {
2965 	struct hclge_link_status_cmd *req;
2966 	struct hclge_desc desc;
2967 	int ret;
2968 
2969 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2970 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2971 	if (ret) {
2972 		dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2973 			ret);
2974 		return ret;
2975 	}
2976 
2977 	req = (struct hclge_link_status_cmd *)desc.data;
2978 	*link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ?
2979 		HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
2980 
2981 	return 0;
2982 }
2983 
2984 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status)
2985 {
2986 	struct phy_device *phydev = hdev->hw.mac.phydev;
2987 
2988 	*link_status = HCLGE_LINK_STATUS_DOWN;
2989 
2990 	if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2991 		return 0;
2992 
2993 	if (phydev && (phydev->state != PHY_RUNNING || !phydev->link))
2994 		return 0;
2995 
2996 	return hclge_get_mac_link_status(hdev, link_status);
2997 }
2998 
2999 static void hclge_push_link_status(struct hclge_dev *hdev)
3000 {
3001 	struct hclge_vport *vport;
3002 	int ret;
3003 	u16 i;
3004 
3005 	for (i = 0; i < pci_num_vf(hdev->pdev); i++) {
3006 		vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
3007 
3008 		if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) ||
3009 		    vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO)
3010 			continue;
3011 
3012 		ret = hclge_push_vf_link_status(vport);
3013 		if (ret) {
3014 			dev_err(&hdev->pdev->dev,
3015 				"failed to push link status to vf%u, ret = %d\n",
3016 				i, ret);
3017 		}
3018 	}
3019 }
3020 
3021 static void hclge_update_link_status(struct hclge_dev *hdev)
3022 {
3023 	struct hnae3_handle *rhandle = &hdev->vport[0].roce;
3024 	struct hnae3_handle *handle = &hdev->vport[0].nic;
3025 	struct hnae3_client *rclient = hdev->roce_client;
3026 	struct hnae3_client *client = hdev->nic_client;
3027 	int state;
3028 	int ret;
3029 
3030 	if (!client)
3031 		return;
3032 
3033 	if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state))
3034 		return;
3035 
3036 	ret = hclge_get_mac_phy_link(hdev, &state);
3037 	if (ret) {
3038 		clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
3039 		return;
3040 	}
3041 
3042 	if (state != hdev->hw.mac.link) {
3043 		hdev->hw.mac.link = state;
3044 		client->ops->link_status_change(handle, state);
3045 		hclge_config_mac_tnl_int(hdev, state);
3046 		if (rclient && rclient->ops->link_status_change)
3047 			rclient->ops->link_status_change(rhandle, state);
3048 
3049 		hclge_push_link_status(hdev);
3050 	}
3051 
3052 	clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
3053 }
3054 
3055 static void hclge_update_speed_advertising(struct hclge_mac *mac)
3056 {
3057 	u32 speed_ability;
3058 
3059 	if (hclge_get_speed_bit(mac->speed, &speed_ability))
3060 		return;
3061 
3062 	switch (mac->module_type) {
3063 	case HNAE3_MODULE_TYPE_FIBRE_LR:
3064 		hclge_convert_setting_lr(speed_ability, mac->advertising);
3065 		break;
3066 	case HNAE3_MODULE_TYPE_FIBRE_SR:
3067 	case HNAE3_MODULE_TYPE_AOC:
3068 		hclge_convert_setting_sr(speed_ability, mac->advertising);
3069 		break;
3070 	case HNAE3_MODULE_TYPE_CR:
3071 		hclge_convert_setting_cr(speed_ability, mac->advertising);
3072 		break;
3073 	case HNAE3_MODULE_TYPE_KR:
3074 		hclge_convert_setting_kr(speed_ability, mac->advertising);
3075 		break;
3076 	default:
3077 		break;
3078 	}
3079 }
3080 
3081 static void hclge_update_fec_advertising(struct hclge_mac *mac)
3082 {
3083 	if (mac->fec_mode & BIT(HNAE3_FEC_RS))
3084 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
3085 				 mac->advertising);
3086 	else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS))
3087 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
3088 				 mac->advertising);
3089 	else if (mac->fec_mode & BIT(HNAE3_FEC_BASER))
3090 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
3091 				 mac->advertising);
3092 	else
3093 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
3094 				 mac->advertising);
3095 }
3096 
3097 static void hclge_update_pause_advertising(struct hclge_dev *hdev)
3098 {
3099 	struct hclge_mac *mac = &hdev->hw.mac;
3100 	bool rx_en, tx_en;
3101 
3102 	switch (hdev->fc_mode_last_time) {
3103 	case HCLGE_FC_RX_PAUSE:
3104 		rx_en = true;
3105 		tx_en = false;
3106 		break;
3107 	case HCLGE_FC_TX_PAUSE:
3108 		rx_en = false;
3109 		tx_en = true;
3110 		break;
3111 	case HCLGE_FC_FULL:
3112 		rx_en = true;
3113 		tx_en = true;
3114 		break;
3115 	default:
3116 		rx_en = false;
3117 		tx_en = false;
3118 		break;
3119 	}
3120 
3121 	linkmode_set_pause(mac->advertising, tx_en, rx_en);
3122 }
3123 
3124 static void hclge_update_advertising(struct hclge_dev *hdev)
3125 {
3126 	struct hclge_mac *mac = &hdev->hw.mac;
3127 
3128 	linkmode_zero(mac->advertising);
3129 	hclge_update_speed_advertising(mac);
3130 	hclge_update_fec_advertising(mac);
3131 	hclge_update_pause_advertising(hdev);
3132 }
3133 
3134 static void hclge_update_port_capability(struct hclge_dev *hdev,
3135 					 struct hclge_mac *mac)
3136 {
3137 	if (hnae3_dev_fec_supported(hdev))
3138 		hclge_convert_setting_fec(mac);
3139 
3140 	/* firmware can not identify back plane type, the media type
3141 	 * read from configuration can help deal it
3142 	 */
3143 	if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE &&
3144 	    mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN)
3145 		mac->module_type = HNAE3_MODULE_TYPE_KR;
3146 	else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3147 		mac->module_type = HNAE3_MODULE_TYPE_TP;
3148 
3149 	if (mac->support_autoneg) {
3150 		linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported);
3151 		linkmode_copy(mac->advertising, mac->supported);
3152 	} else {
3153 		linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
3154 				   mac->supported);
3155 		hclge_update_advertising(hdev);
3156 	}
3157 }
3158 
3159 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed)
3160 {
3161 	struct hclge_sfp_info_cmd *resp;
3162 	struct hclge_desc desc;
3163 	int ret;
3164 
3165 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3166 	resp = (struct hclge_sfp_info_cmd *)desc.data;
3167 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3168 	if (ret == -EOPNOTSUPP) {
3169 		dev_warn(&hdev->pdev->dev,
3170 			 "IMP do not support get SFP speed %d\n", ret);
3171 		return ret;
3172 	} else if (ret) {
3173 		dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret);
3174 		return ret;
3175 	}
3176 
3177 	*speed = le32_to_cpu(resp->speed);
3178 
3179 	return 0;
3180 }
3181 
3182 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac)
3183 {
3184 	struct hclge_sfp_info_cmd *resp;
3185 	struct hclge_desc desc;
3186 	int ret;
3187 
3188 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3189 	resp = (struct hclge_sfp_info_cmd *)desc.data;
3190 
3191 	resp->query_type = QUERY_ACTIVE_SPEED;
3192 
3193 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3194 	if (ret == -EOPNOTSUPP) {
3195 		dev_warn(&hdev->pdev->dev,
3196 			 "IMP does not support get SFP info %d\n", ret);
3197 		return ret;
3198 	} else if (ret) {
3199 		dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret);
3200 		return ret;
3201 	}
3202 
3203 	/* In some case, mac speed get from IMP may be 0, it shouldn't be
3204 	 * set to mac->speed.
3205 	 */
3206 	if (!le32_to_cpu(resp->speed))
3207 		return 0;
3208 
3209 	mac->speed = le32_to_cpu(resp->speed);
3210 	/* if resp->speed_ability is 0, it means it's an old version
3211 	 * firmware, do not update these params
3212 	 */
3213 	if (resp->speed_ability) {
3214 		mac->module_type = le32_to_cpu(resp->module_type);
3215 		mac->speed_ability = le32_to_cpu(resp->speed_ability);
3216 		mac->autoneg = resp->autoneg;
3217 		mac->support_autoneg = resp->autoneg_ability;
3218 		mac->speed_type = QUERY_ACTIVE_SPEED;
3219 		mac->lane_num = resp->lane_num;
3220 		if (!resp->active_fec)
3221 			mac->fec_mode = 0;
3222 		else
3223 			mac->fec_mode = BIT(resp->active_fec);
3224 		mac->fec_ability = resp->fec_ability;
3225 	} else {
3226 		mac->speed_type = QUERY_SFP_SPEED;
3227 	}
3228 
3229 	return 0;
3230 }
3231 
3232 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle,
3233 					struct ethtool_link_ksettings *cmd)
3234 {
3235 	struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3236 	struct hclge_vport *vport = hclge_get_vport(handle);
3237 	struct hclge_phy_link_ksetting_0_cmd *req0;
3238 	struct hclge_phy_link_ksetting_1_cmd *req1;
3239 	u32 supported, advertising, lp_advertising;
3240 	struct hclge_dev *hdev = vport->back;
3241 	int ret;
3242 
3243 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3244 				   true);
3245 	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3246 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3247 				   true);
3248 
3249 	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3250 	if (ret) {
3251 		dev_err(&hdev->pdev->dev,
3252 			"failed to get phy link ksetting, ret = %d.\n", ret);
3253 		return ret;
3254 	}
3255 
3256 	req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3257 	cmd->base.autoneg = req0->autoneg;
3258 	cmd->base.speed = le32_to_cpu(req0->speed);
3259 	cmd->base.duplex = req0->duplex;
3260 	cmd->base.port = req0->port;
3261 	cmd->base.transceiver = req0->transceiver;
3262 	cmd->base.phy_address = req0->phy_address;
3263 	cmd->base.eth_tp_mdix = req0->eth_tp_mdix;
3264 	cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl;
3265 	supported = le32_to_cpu(req0->supported);
3266 	advertising = le32_to_cpu(req0->advertising);
3267 	lp_advertising = le32_to_cpu(req0->lp_advertising);
3268 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3269 						supported);
3270 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3271 						advertising);
3272 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
3273 						lp_advertising);
3274 
3275 	req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3276 	cmd->base.master_slave_cfg = req1->master_slave_cfg;
3277 	cmd->base.master_slave_state = req1->master_slave_state;
3278 
3279 	return 0;
3280 }
3281 
3282 static int
3283 hclge_set_phy_link_ksettings(struct hnae3_handle *handle,
3284 			     const struct ethtool_link_ksettings *cmd)
3285 {
3286 	struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3287 	struct hclge_vport *vport = hclge_get_vport(handle);
3288 	struct hclge_phy_link_ksetting_0_cmd *req0;
3289 	struct hclge_phy_link_ksetting_1_cmd *req1;
3290 	struct hclge_dev *hdev = vport->back;
3291 	u32 advertising;
3292 	int ret;
3293 
3294 	if (cmd->base.autoneg == AUTONEG_DISABLE &&
3295 	    ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) ||
3296 	     (cmd->base.duplex != DUPLEX_HALF &&
3297 	      cmd->base.duplex != DUPLEX_FULL)))
3298 		return -EINVAL;
3299 
3300 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3301 				   false);
3302 	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3303 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3304 				   false);
3305 
3306 	req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3307 	req0->autoneg = cmd->base.autoneg;
3308 	req0->speed = cpu_to_le32(cmd->base.speed);
3309 	req0->duplex = cmd->base.duplex;
3310 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
3311 						cmd->link_modes.advertising);
3312 	req0->advertising = cpu_to_le32(advertising);
3313 	req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl;
3314 
3315 	req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3316 	req1->master_slave_cfg = cmd->base.master_slave_cfg;
3317 
3318 	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3319 	if (ret) {
3320 		dev_err(&hdev->pdev->dev,
3321 			"failed to set phy link ksettings, ret = %d.\n", ret);
3322 		return ret;
3323 	}
3324 
3325 	hdev->hw.mac.autoneg = cmd->base.autoneg;
3326 	hdev->hw.mac.speed = cmd->base.speed;
3327 	hdev->hw.mac.duplex = cmd->base.duplex;
3328 	linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising);
3329 
3330 	return 0;
3331 }
3332 
3333 static int hclge_update_tp_port_info(struct hclge_dev *hdev)
3334 {
3335 	struct ethtool_link_ksettings cmd;
3336 	int ret;
3337 
3338 	if (!hnae3_dev_phy_imp_supported(hdev))
3339 		return 0;
3340 
3341 	ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd);
3342 	if (ret)
3343 		return ret;
3344 
3345 	hdev->hw.mac.autoneg = cmd.base.autoneg;
3346 	hdev->hw.mac.speed = cmd.base.speed;
3347 	hdev->hw.mac.duplex = cmd.base.duplex;
3348 	linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising);
3349 
3350 	return 0;
3351 }
3352 
3353 static int hclge_tp_port_init(struct hclge_dev *hdev)
3354 {
3355 	struct ethtool_link_ksettings cmd;
3356 
3357 	if (!hnae3_dev_phy_imp_supported(hdev))
3358 		return 0;
3359 
3360 	cmd.base.autoneg = hdev->hw.mac.autoneg;
3361 	cmd.base.speed = hdev->hw.mac.speed;
3362 	cmd.base.duplex = hdev->hw.mac.duplex;
3363 	linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising);
3364 
3365 	return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd);
3366 }
3367 
3368 static int hclge_update_port_info(struct hclge_dev *hdev)
3369 {
3370 	struct hclge_mac *mac = &hdev->hw.mac;
3371 	int speed;
3372 	int ret;
3373 
3374 	/* get the port info from SFP cmd if not copper port */
3375 	if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3376 		return hclge_update_tp_port_info(hdev);
3377 
3378 	/* if IMP does not support get SFP/qSFP info, return directly */
3379 	if (!hdev->support_sfp_query)
3380 		return 0;
3381 
3382 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3383 		speed = mac->speed;
3384 		ret = hclge_get_sfp_info(hdev, mac);
3385 	} else {
3386 		speed = HCLGE_MAC_SPEED_UNKNOWN;
3387 		ret = hclge_get_sfp_speed(hdev, &speed);
3388 	}
3389 
3390 	if (ret == -EOPNOTSUPP) {
3391 		hdev->support_sfp_query = false;
3392 		return ret;
3393 	} else if (ret) {
3394 		return ret;
3395 	}
3396 
3397 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3398 		if (mac->speed_type == QUERY_ACTIVE_SPEED) {
3399 			hclge_update_port_capability(hdev, mac);
3400 			if (mac->speed != speed)
3401 				(void)hclge_tm_port_shaper_cfg(hdev);
3402 			return 0;
3403 		}
3404 		return hclge_cfg_mac_speed_dup(hdev, mac->speed,
3405 					       HCLGE_MAC_FULL, mac->lane_num);
3406 	} else {
3407 		if (speed == HCLGE_MAC_SPEED_UNKNOWN)
3408 			return 0; /* do nothing if no SFP */
3409 
3410 		/* must config full duplex for SFP */
3411 		return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0);
3412 	}
3413 }
3414 
3415 static int hclge_get_status(struct hnae3_handle *handle)
3416 {
3417 	struct hclge_vport *vport = hclge_get_vport(handle);
3418 	struct hclge_dev *hdev = vport->back;
3419 
3420 	hclge_update_link_status(hdev);
3421 
3422 	return hdev->hw.mac.link;
3423 }
3424 
3425 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf)
3426 {
3427 	if (!pci_num_vf(hdev->pdev)) {
3428 		dev_err(&hdev->pdev->dev,
3429 			"SRIOV is disabled, can not get vport(%d) info.\n", vf);
3430 		return NULL;
3431 	}
3432 
3433 	if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) {
3434 		dev_err(&hdev->pdev->dev,
3435 			"vf id(%d) is out of range(0 <= vfid < %d)\n",
3436 			vf, pci_num_vf(hdev->pdev));
3437 		return NULL;
3438 	}
3439 
3440 	/* VF start from 1 in vport */
3441 	vf += HCLGE_VF_VPORT_START_NUM;
3442 	return &hdev->vport[vf];
3443 }
3444 
3445 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf,
3446 			       struct ifla_vf_info *ivf)
3447 {
3448 	struct hclge_vport *vport = hclge_get_vport(handle);
3449 	struct hclge_dev *hdev = vport->back;
3450 
3451 	vport = hclge_get_vf_vport(hdev, vf);
3452 	if (!vport)
3453 		return -EINVAL;
3454 
3455 	ivf->vf = vf;
3456 	ivf->linkstate = vport->vf_info.link_state;
3457 	ivf->spoofchk = vport->vf_info.spoofchk;
3458 	ivf->trusted = vport->vf_info.trusted;
3459 	ivf->min_tx_rate = 0;
3460 	ivf->max_tx_rate = vport->vf_info.max_tx_rate;
3461 	ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag;
3462 	ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto);
3463 	ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos;
3464 	ether_addr_copy(ivf->mac, vport->vf_info.mac);
3465 
3466 	return 0;
3467 }
3468 
3469 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
3470 				   int link_state)
3471 {
3472 	struct hclge_vport *vport = hclge_get_vport(handle);
3473 	struct hclge_dev *hdev = vport->back;
3474 	int link_state_old;
3475 	int ret;
3476 
3477 	vport = hclge_get_vf_vport(hdev, vf);
3478 	if (!vport)
3479 		return -EINVAL;
3480 
3481 	link_state_old = vport->vf_info.link_state;
3482 	vport->vf_info.link_state = link_state;
3483 
3484 	/* return success directly if the VF is unalive, VF will
3485 	 * query link state itself when it starts work.
3486 	 */
3487 	if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
3488 		return 0;
3489 
3490 	ret = hclge_push_vf_link_status(vport);
3491 	if (ret) {
3492 		vport->vf_info.link_state = link_state_old;
3493 		dev_err(&hdev->pdev->dev,
3494 			"failed to push vf%d link status, ret = %d\n", vf, ret);
3495 	}
3496 
3497 	return ret;
3498 }
3499 
3500 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
3501 {
3502 	u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;
3503 
3504 	/* fetch the events from their corresponding regs */
3505 	cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
3506 	msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
3507 	hw_err_src_reg = hclge_read_dev(&hdev->hw,
3508 					HCLGE_RAS_PF_OTHER_INT_STS_REG);
3509 
3510 	/* Assumption: If by any chance reset and mailbox events are reported
3511 	 * together then we will only process reset event in this go and will
3512 	 * defer the processing of the mailbox events. Since, we would have not
3513 	 * cleared RX CMDQ event this time we would receive again another
3514 	 * interrupt from H/W just for the mailbox.
3515 	 *
3516 	 * check for vector0 reset event sources
3517 	 */
3518 	if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
3519 		dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
3520 		set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
3521 		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3522 		*clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
3523 		hdev->rst_stats.imp_rst_cnt++;
3524 		return HCLGE_VECTOR0_EVENT_RST;
3525 	}
3526 
3527 	if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
3528 		dev_info(&hdev->pdev->dev, "global reset interrupt\n");
3529 		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3530 		set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
3531 		*clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
3532 		hdev->rst_stats.global_rst_cnt++;
3533 		return HCLGE_VECTOR0_EVENT_RST;
3534 	}
3535 
3536 	/* check for vector0 msix event and hardware error event source */
3537 	if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK ||
3538 	    hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK)
3539 		return HCLGE_VECTOR0_EVENT_ERR;
3540 
3541 	/* check for vector0 ptp event source */
3542 	if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) {
3543 		*clearval = msix_src_reg;
3544 		return HCLGE_VECTOR0_EVENT_PTP;
3545 	}
3546 
3547 	/* check for vector0 mailbox(=CMDQ RX) event source */
3548 	if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
3549 		cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
3550 		*clearval = cmdq_src_reg;
3551 		return HCLGE_VECTOR0_EVENT_MBX;
3552 	}
3553 
3554 	/* print other vector0 event source */
3555 	dev_info(&hdev->pdev->dev,
3556 		 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n",
3557 		 cmdq_src_reg, hw_err_src_reg, msix_src_reg);
3558 
3559 	return HCLGE_VECTOR0_EVENT_OTHER;
3560 }
3561 
3562 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
3563 				    u32 regclr)
3564 {
3565 #define HCLGE_IMP_RESET_DELAY		5
3566 
3567 	switch (event_type) {
3568 	case HCLGE_VECTOR0_EVENT_PTP:
3569 	case HCLGE_VECTOR0_EVENT_RST:
3570 		if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B))
3571 			mdelay(HCLGE_IMP_RESET_DELAY);
3572 
3573 		hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
3574 		break;
3575 	case HCLGE_VECTOR0_EVENT_MBX:
3576 		hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
3577 		break;
3578 	default:
3579 		break;
3580 	}
3581 }
3582 
3583 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
3584 {
3585 	hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
3586 				BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
3587 				BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
3588 				BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
3589 	hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
3590 }
3591 
3592 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
3593 {
3594 	writel(enable ? 1 : 0, vector->addr);
3595 }
3596 
3597 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
3598 {
3599 	struct hclge_dev *hdev = data;
3600 	unsigned long flags;
3601 	u32 clearval = 0;
3602 	u32 event_cause;
3603 
3604 	hclge_enable_vector(&hdev->misc_vector, false);
3605 	event_cause = hclge_check_event_cause(hdev, &clearval);
3606 
3607 	/* vector 0 interrupt is shared with reset and mailbox source events. */
3608 	switch (event_cause) {
3609 	case HCLGE_VECTOR0_EVENT_ERR:
3610 		hclge_errhand_task_schedule(hdev);
3611 		break;
3612 	case HCLGE_VECTOR0_EVENT_RST:
3613 		hclge_reset_task_schedule(hdev);
3614 		break;
3615 	case HCLGE_VECTOR0_EVENT_PTP:
3616 		spin_lock_irqsave(&hdev->ptp->lock, flags);
3617 		hclge_ptp_clean_tx_hwts(hdev);
3618 		spin_unlock_irqrestore(&hdev->ptp->lock, flags);
3619 		break;
3620 	case HCLGE_VECTOR0_EVENT_MBX:
3621 		/* If we are here then,
3622 		 * 1. Either we are not handling any mbx task and we are not
3623 		 *    scheduled as well
3624 		 *                        OR
3625 		 * 2. We could be handling a mbx task but nothing more is
3626 		 *    scheduled.
3627 		 * In both cases, we should schedule mbx task as there are more
3628 		 * mbx messages reported by this interrupt.
3629 		 */
3630 		hclge_mbx_task_schedule(hdev);
3631 		break;
3632 	default:
3633 		dev_warn(&hdev->pdev->dev,
3634 			 "received unknown or unhandled event of vector0\n");
3635 		break;
3636 	}
3637 
3638 	hclge_clear_event_cause(hdev, event_cause, clearval);
3639 
3640 	/* Enable interrupt if it is not caused by reset event or error event */
3641 	if (event_cause == HCLGE_VECTOR0_EVENT_PTP ||
3642 	    event_cause == HCLGE_VECTOR0_EVENT_MBX ||
3643 	    event_cause == HCLGE_VECTOR0_EVENT_OTHER)
3644 		hclge_enable_vector(&hdev->misc_vector, true);
3645 
3646 	return IRQ_HANDLED;
3647 }
3648 
3649 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
3650 {
3651 	if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
3652 		dev_warn(&hdev->pdev->dev,
3653 			 "vector(vector_id %d) has been freed.\n", vector_id);
3654 		return;
3655 	}
3656 
3657 	hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
3658 	hdev->num_msi_left += 1;
3659 	hdev->num_msi_used -= 1;
3660 }
3661 
3662 static void hclge_get_misc_vector(struct hclge_dev *hdev)
3663 {
3664 	struct hclge_misc_vector *vector = &hdev->misc_vector;
3665 
3666 	vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
3667 
3668 	vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
3669 	hdev->vector_status[0] = 0;
3670 
3671 	hdev->num_msi_left -= 1;
3672 	hdev->num_msi_used += 1;
3673 }
3674 
3675 static int hclge_misc_irq_init(struct hclge_dev *hdev)
3676 {
3677 	int ret;
3678 
3679 	hclge_get_misc_vector(hdev);
3680 
3681 	/* this would be explicitly freed in the end */
3682 	snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
3683 		 HCLGE_NAME, pci_name(hdev->pdev));
3684 	ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
3685 			  0, hdev->misc_vector.name, hdev);
3686 	if (ret) {
3687 		hclge_free_vector(hdev, 0);
3688 		dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
3689 			hdev->misc_vector.vector_irq);
3690 	}
3691 
3692 	return ret;
3693 }
3694 
3695 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
3696 {
3697 	free_irq(hdev->misc_vector.vector_irq, hdev);
3698 	hclge_free_vector(hdev, 0);
3699 }
3700 
3701 int hclge_notify_client(struct hclge_dev *hdev,
3702 			enum hnae3_reset_notify_type type)
3703 {
3704 	struct hnae3_handle *handle = &hdev->vport[0].nic;
3705 	struct hnae3_client *client = hdev->nic_client;
3706 	int ret;
3707 
3708 	if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client)
3709 		return 0;
3710 
3711 	if (!client->ops->reset_notify)
3712 		return -EOPNOTSUPP;
3713 
3714 	ret = client->ops->reset_notify(handle, type);
3715 	if (ret)
3716 		dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
3717 			type, ret);
3718 
3719 	return ret;
3720 }
3721 
3722 static int hclge_notify_roce_client(struct hclge_dev *hdev,
3723 				    enum hnae3_reset_notify_type type)
3724 {
3725 	struct hnae3_handle *handle = &hdev->vport[0].roce;
3726 	struct hnae3_client *client = hdev->roce_client;
3727 	int ret;
3728 
3729 	if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client)
3730 		return 0;
3731 
3732 	if (!client->ops->reset_notify)
3733 		return -EOPNOTSUPP;
3734 
3735 	ret = client->ops->reset_notify(handle, type);
3736 	if (ret)
3737 		dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
3738 			type, ret);
3739 
3740 	return ret;
3741 }
3742 
3743 static int hclge_reset_wait(struct hclge_dev *hdev)
3744 {
3745 #define HCLGE_RESET_WATI_MS	100
3746 #define HCLGE_RESET_WAIT_CNT	350
3747 
3748 	u32 val, reg, reg_bit;
3749 	u32 cnt = 0;
3750 
3751 	switch (hdev->reset_type) {
3752 	case HNAE3_IMP_RESET:
3753 		reg = HCLGE_GLOBAL_RESET_REG;
3754 		reg_bit = HCLGE_IMP_RESET_BIT;
3755 		break;
3756 	case HNAE3_GLOBAL_RESET:
3757 		reg = HCLGE_GLOBAL_RESET_REG;
3758 		reg_bit = HCLGE_GLOBAL_RESET_BIT;
3759 		break;
3760 	case HNAE3_FUNC_RESET:
3761 		reg = HCLGE_FUN_RST_ING;
3762 		reg_bit = HCLGE_FUN_RST_ING_B;
3763 		break;
3764 	default:
3765 		dev_err(&hdev->pdev->dev,
3766 			"Wait for unsupported reset type: %d\n",
3767 			hdev->reset_type);
3768 		return -EINVAL;
3769 	}
3770 
3771 	val = hclge_read_dev(&hdev->hw, reg);
3772 	while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
3773 		msleep(HCLGE_RESET_WATI_MS);
3774 		val = hclge_read_dev(&hdev->hw, reg);
3775 		cnt++;
3776 	}
3777 
3778 	if (cnt >= HCLGE_RESET_WAIT_CNT) {
3779 		dev_warn(&hdev->pdev->dev,
3780 			 "Wait for reset timeout: %d\n", hdev->reset_type);
3781 		return -EBUSY;
3782 	}
3783 
3784 	return 0;
3785 }
3786 
3787 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
3788 {
3789 	struct hclge_vf_rst_cmd *req;
3790 	struct hclge_desc desc;
3791 
3792 	req = (struct hclge_vf_rst_cmd *)desc.data;
3793 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
3794 	req->dest_vfid = func_id;
3795 
3796 	if (reset)
3797 		req->vf_rst = 0x1;
3798 
3799 	return hclge_cmd_send(&hdev->hw, &desc, 1);
3800 }
3801 
3802 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
3803 {
3804 	int i;
3805 
3806 	for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) {
3807 		struct hclge_vport *vport = &hdev->vport[i];
3808 		int ret;
3809 
3810 		/* Send cmd to set/clear VF's FUNC_RST_ING */
3811 		ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
3812 		if (ret) {
3813 			dev_err(&hdev->pdev->dev,
3814 				"set vf(%u) rst failed %d!\n",
3815 				vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3816 				ret);
3817 			return ret;
3818 		}
3819 
3820 		if (!reset ||
3821 		    !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state))
3822 			continue;
3823 
3824 		if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) &&
3825 		    hdev->reset_type == HNAE3_FUNC_RESET) {
3826 			set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET,
3827 				&vport->need_notify);
3828 			continue;
3829 		}
3830 
3831 		/* Inform VF to process the reset.
3832 		 * hclge_inform_reset_assert_to_vf may fail if VF
3833 		 * driver is not loaded.
3834 		 */
3835 		ret = hclge_inform_reset_assert_to_vf(vport);
3836 		if (ret)
3837 			dev_warn(&hdev->pdev->dev,
3838 				 "inform reset to vf(%u) failed %d!\n",
3839 				 vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3840 				 ret);
3841 	}
3842 
3843 	return 0;
3844 }
3845 
3846 static void hclge_mailbox_service_task(struct hclge_dev *hdev)
3847 {
3848 	if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) ||
3849 	    test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) ||
3850 	    test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
3851 		return;
3852 
3853 	if (time_is_before_jiffies(hdev->last_mbx_scheduled +
3854 				   HCLGE_MBX_SCHED_TIMEOUT))
3855 		dev_warn(&hdev->pdev->dev,
3856 			 "mbx service task is scheduled after %ums on cpu%u!\n",
3857 			 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled),
3858 			 smp_processor_id());
3859 
3860 	hclge_mbx_handler(hdev);
3861 
3862 	clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
3863 }
3864 
3865 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev)
3866 {
3867 	struct hclge_pf_rst_sync_cmd *req;
3868 	struct hclge_desc desc;
3869 	int cnt = 0;
3870 	int ret;
3871 
3872 	req = (struct hclge_pf_rst_sync_cmd *)desc.data;
3873 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true);
3874 
3875 	do {
3876 		/* vf need to down netdev by mbx during PF or FLR reset */
3877 		hclge_mailbox_service_task(hdev);
3878 
3879 		ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3880 		/* for compatible with old firmware, wait
3881 		 * 100 ms for VF to stop IO
3882 		 */
3883 		if (ret == -EOPNOTSUPP) {
3884 			msleep(HCLGE_RESET_SYNC_TIME);
3885 			return;
3886 		} else if (ret) {
3887 			dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n",
3888 				 ret);
3889 			return;
3890 		} else if (req->all_vf_ready) {
3891 			return;
3892 		}
3893 		msleep(HCLGE_PF_RESET_SYNC_TIME);
3894 		hclge_comm_cmd_reuse_desc(&desc, true);
3895 	} while (cnt++ < HCLGE_PF_RESET_SYNC_CNT);
3896 
3897 	dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n");
3898 }
3899 
3900 void hclge_report_hw_error(struct hclge_dev *hdev,
3901 			   enum hnae3_hw_error_type type)
3902 {
3903 	struct hnae3_client *client = hdev->nic_client;
3904 
3905 	if (!client || !client->ops->process_hw_error ||
3906 	    !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state))
3907 		return;
3908 
3909 	client->ops->process_hw_error(&hdev->vport[0].nic, type);
3910 }
3911 
3912 static void hclge_handle_imp_error(struct hclge_dev *hdev)
3913 {
3914 	u32 reg_val;
3915 
3916 	reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
3917 	if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) {
3918 		hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR);
3919 		reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B);
3920 		hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
3921 	}
3922 
3923 	if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) {
3924 		hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR);
3925 		reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B);
3926 		hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
3927 	}
3928 }
3929 
3930 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
3931 {
3932 	struct hclge_desc desc;
3933 	struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
3934 	int ret;
3935 
3936 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
3937 	hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
3938 	req->fun_reset_vfid = func_id;
3939 
3940 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3941 	if (ret)
3942 		dev_err(&hdev->pdev->dev,
3943 			"send function reset cmd fail, status =%d\n", ret);
3944 
3945 	return ret;
3946 }
3947 
3948 static void hclge_do_reset(struct hclge_dev *hdev)
3949 {
3950 	struct hnae3_handle *handle = &hdev->vport[0].nic;
3951 	struct pci_dev *pdev = hdev->pdev;
3952 	u32 val;
3953 
3954 	if (hclge_get_hw_reset_stat(handle)) {
3955 		dev_info(&pdev->dev, "hardware reset not finish\n");
3956 		dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n",
3957 			 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING),
3958 			 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG));
3959 		return;
3960 	}
3961 
3962 	switch (hdev->reset_type) {
3963 	case HNAE3_IMP_RESET:
3964 		dev_info(&pdev->dev, "IMP reset requested\n");
3965 		val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
3966 		hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1);
3967 		hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val);
3968 		break;
3969 	case HNAE3_GLOBAL_RESET:
3970 		dev_info(&pdev->dev, "global reset requested\n");
3971 		val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
3972 		hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
3973 		hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
3974 		break;
3975 	case HNAE3_FUNC_RESET:
3976 		dev_info(&pdev->dev, "PF reset requested\n");
3977 		/* schedule again to check later */
3978 		set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
3979 		hclge_reset_task_schedule(hdev);
3980 		break;
3981 	default:
3982 		dev_warn(&pdev->dev,
3983 			 "unsupported reset type: %d\n", hdev->reset_type);
3984 		break;
3985 	}
3986 }
3987 
3988 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
3989 						   unsigned long *addr)
3990 {
3991 	enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
3992 	struct hclge_dev *hdev = ae_dev->priv;
3993 
3994 	/* return the highest priority reset level amongst all */
3995 	if (test_bit(HNAE3_IMP_RESET, addr)) {
3996 		rst_level = HNAE3_IMP_RESET;
3997 		clear_bit(HNAE3_IMP_RESET, addr);
3998 		clear_bit(HNAE3_GLOBAL_RESET, addr);
3999 		clear_bit(HNAE3_FUNC_RESET, addr);
4000 	} else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
4001 		rst_level = HNAE3_GLOBAL_RESET;
4002 		clear_bit(HNAE3_GLOBAL_RESET, addr);
4003 		clear_bit(HNAE3_FUNC_RESET, addr);
4004 	} else if (test_bit(HNAE3_FUNC_RESET, addr)) {
4005 		rst_level = HNAE3_FUNC_RESET;
4006 		clear_bit(HNAE3_FUNC_RESET, addr);
4007 	} else if (test_bit(HNAE3_FLR_RESET, addr)) {
4008 		rst_level = HNAE3_FLR_RESET;
4009 		clear_bit(HNAE3_FLR_RESET, addr);
4010 	}
4011 
4012 	if (hdev->reset_type != HNAE3_NONE_RESET &&
4013 	    rst_level < hdev->reset_type)
4014 		return HNAE3_NONE_RESET;
4015 
4016 	return rst_level;
4017 }
4018 
4019 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
4020 {
4021 	u32 clearval = 0;
4022 
4023 	switch (hdev->reset_type) {
4024 	case HNAE3_IMP_RESET:
4025 		clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
4026 		break;
4027 	case HNAE3_GLOBAL_RESET:
4028 		clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
4029 		break;
4030 	default:
4031 		break;
4032 	}
4033 
4034 	if (!clearval)
4035 		return;
4036 
4037 	/* For revision 0x20, the reset interrupt source
4038 	 * can only be cleared after hardware reset done
4039 	 */
4040 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
4041 		hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG,
4042 				clearval);
4043 
4044 	hclge_enable_vector(&hdev->misc_vector, true);
4045 }
4046 
4047 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable)
4048 {
4049 	u32 reg_val;
4050 
4051 	reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
4052 	if (enable)
4053 		reg_val |= HCLGE_COMM_NIC_SW_RST_RDY;
4054 	else
4055 		reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY;
4056 
4057 	hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
4058 }
4059 
4060 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev)
4061 {
4062 	int ret;
4063 
4064 	ret = hclge_set_all_vf_rst(hdev, true);
4065 	if (ret)
4066 		return ret;
4067 
4068 	hclge_func_reset_sync_vf(hdev);
4069 
4070 	return 0;
4071 }
4072 
4073 static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
4074 {
4075 	u32 reg_val;
4076 	int ret = 0;
4077 
4078 	switch (hdev->reset_type) {
4079 	case HNAE3_FUNC_RESET:
4080 		ret = hclge_func_reset_notify_vf(hdev);
4081 		if (ret)
4082 			return ret;
4083 
4084 		ret = hclge_func_reset_cmd(hdev, 0);
4085 		if (ret) {
4086 			dev_err(&hdev->pdev->dev,
4087 				"asserting function reset fail %d!\n", ret);
4088 			return ret;
4089 		}
4090 
4091 		/* After performaning pf reset, it is not necessary to do the
4092 		 * mailbox handling or send any command to firmware, because
4093 		 * any mailbox handling or command to firmware is only valid
4094 		 * after hclge_comm_cmd_init is called.
4095 		 */
4096 		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
4097 		hdev->rst_stats.pf_rst_cnt++;
4098 		break;
4099 	case HNAE3_FLR_RESET:
4100 		ret = hclge_func_reset_notify_vf(hdev);
4101 		if (ret)
4102 			return ret;
4103 		break;
4104 	case HNAE3_IMP_RESET:
4105 		hclge_handle_imp_error(hdev);
4106 		reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
4107 		hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
4108 				BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
4109 		break;
4110 	default:
4111 		break;
4112 	}
4113 
4114 	/* inform hardware that preparatory work is done */
4115 	msleep(HCLGE_RESET_SYNC_TIME);
4116 	hclge_reset_handshake(hdev, true);
4117 	dev_info(&hdev->pdev->dev, "prepare wait ok\n");
4118 
4119 	return ret;
4120 }
4121 
4122 static void hclge_show_rst_info(struct hclge_dev *hdev)
4123 {
4124 	char *buf;
4125 
4126 	buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL);
4127 	if (!buf)
4128 		return;
4129 
4130 	hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN);
4131 
4132 	dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf);
4133 
4134 	kfree(buf);
4135 }
4136 
4137 static bool hclge_reset_err_handle(struct hclge_dev *hdev)
4138 {
4139 #define MAX_RESET_FAIL_CNT 5
4140 
4141 	if (hdev->reset_pending) {
4142 		dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
4143 			 hdev->reset_pending);
4144 		return true;
4145 	} else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
4146 		   HCLGE_RESET_INT_M) {
4147 		dev_info(&hdev->pdev->dev,
4148 			 "reset failed because new reset interrupt\n");
4149 		hclge_clear_reset_cause(hdev);
4150 		return false;
4151 	} else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) {
4152 		hdev->rst_stats.reset_fail_cnt++;
4153 		set_bit(hdev->reset_type, &hdev->reset_pending);
4154 		dev_info(&hdev->pdev->dev,
4155 			 "re-schedule reset task(%u)\n",
4156 			 hdev->rst_stats.reset_fail_cnt);
4157 		return true;
4158 	}
4159 
4160 	hclge_clear_reset_cause(hdev);
4161 
4162 	/* recover the handshake status when reset fail */
4163 	hclge_reset_handshake(hdev, true);
4164 
4165 	dev_err(&hdev->pdev->dev, "Reset fail!\n");
4166 
4167 	hclge_show_rst_info(hdev);
4168 
4169 	set_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4170 
4171 	return false;
4172 }
4173 
4174 static void hclge_update_reset_level(struct hclge_dev *hdev)
4175 {
4176 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4177 	enum hnae3_reset_type reset_level;
4178 
4179 	/* reset request will not be set during reset, so clear
4180 	 * pending reset request to avoid unnecessary reset
4181 	 * caused by the same reason.
4182 	 */
4183 	hclge_get_reset_level(ae_dev, &hdev->reset_request);
4184 
4185 	/* if default_reset_request has a higher level reset request,
4186 	 * it should be handled as soon as possible. since some errors
4187 	 * need this kind of reset to fix.
4188 	 */
4189 	reset_level = hclge_get_reset_level(ae_dev,
4190 					    &hdev->default_reset_request);
4191 	if (reset_level != HNAE3_NONE_RESET)
4192 		set_bit(reset_level, &hdev->reset_request);
4193 }
4194 
4195 static int hclge_set_rst_done(struct hclge_dev *hdev)
4196 {
4197 	struct hclge_pf_rst_done_cmd *req;
4198 	struct hclge_desc desc;
4199 	int ret;
4200 
4201 	req = (struct hclge_pf_rst_done_cmd *)desc.data;
4202 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false);
4203 	req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT;
4204 
4205 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4206 	/* To be compatible with the old firmware, which does not support
4207 	 * command HCLGE_OPC_PF_RST_DONE, just print a warning and
4208 	 * return success
4209 	 */
4210 	if (ret == -EOPNOTSUPP) {
4211 		dev_warn(&hdev->pdev->dev,
4212 			 "current firmware does not support command(0x%x)!\n",
4213 			 HCLGE_OPC_PF_RST_DONE);
4214 		return 0;
4215 	} else if (ret) {
4216 		dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n",
4217 			ret);
4218 	}
4219 
4220 	return ret;
4221 }
4222 
4223 static int hclge_reset_prepare_up(struct hclge_dev *hdev)
4224 {
4225 	int ret = 0;
4226 
4227 	switch (hdev->reset_type) {
4228 	case HNAE3_FUNC_RESET:
4229 	case HNAE3_FLR_RESET:
4230 		ret = hclge_set_all_vf_rst(hdev, false);
4231 		break;
4232 	case HNAE3_GLOBAL_RESET:
4233 	case HNAE3_IMP_RESET:
4234 		ret = hclge_set_rst_done(hdev);
4235 		break;
4236 	default:
4237 		break;
4238 	}
4239 
4240 	/* clear up the handshake status after re-initialize done */
4241 	hclge_reset_handshake(hdev, false);
4242 
4243 	return ret;
4244 }
4245 
4246 static int hclge_reset_stack(struct hclge_dev *hdev)
4247 {
4248 	int ret;
4249 
4250 	ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
4251 	if (ret)
4252 		return ret;
4253 
4254 	ret = hclge_reset_ae_dev(hdev->ae_dev);
4255 	if (ret)
4256 		return ret;
4257 
4258 	return hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
4259 }
4260 
4261 static int hclge_reset_prepare(struct hclge_dev *hdev)
4262 {
4263 	int ret;
4264 
4265 	hdev->rst_stats.reset_cnt++;
4266 	/* perform reset of the stack & ae device for a client */
4267 	ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
4268 	if (ret)
4269 		return ret;
4270 
4271 	rtnl_lock();
4272 	ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
4273 	rtnl_unlock();
4274 	if (ret)
4275 		return ret;
4276 
4277 	return hclge_reset_prepare_wait(hdev);
4278 }
4279 
4280 static int hclge_reset_rebuild(struct hclge_dev *hdev)
4281 {
4282 	int ret;
4283 
4284 	hdev->rst_stats.hw_reset_done_cnt++;
4285 
4286 	ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
4287 	if (ret)
4288 		return ret;
4289 
4290 	rtnl_lock();
4291 	ret = hclge_reset_stack(hdev);
4292 	rtnl_unlock();
4293 	if (ret)
4294 		return ret;
4295 
4296 	hclge_clear_reset_cause(hdev);
4297 
4298 	ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
4299 	/* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1
4300 	 * times
4301 	 */
4302 	if (ret &&
4303 	    hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1)
4304 		return ret;
4305 
4306 	ret = hclge_reset_prepare_up(hdev);
4307 	if (ret)
4308 		return ret;
4309 
4310 	rtnl_lock();
4311 	ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
4312 	rtnl_unlock();
4313 	if (ret)
4314 		return ret;
4315 
4316 	ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
4317 	if (ret)
4318 		return ret;
4319 
4320 	hdev->last_reset_time = jiffies;
4321 	hdev->rst_stats.reset_fail_cnt = 0;
4322 	hdev->rst_stats.reset_done_cnt++;
4323 	clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4324 
4325 	hclge_update_reset_level(hdev);
4326 
4327 	return 0;
4328 }
4329 
4330 static void hclge_reset(struct hclge_dev *hdev)
4331 {
4332 	if (hclge_reset_prepare(hdev))
4333 		goto err_reset;
4334 
4335 	if (hclge_reset_wait(hdev))
4336 		goto err_reset;
4337 
4338 	if (hclge_reset_rebuild(hdev))
4339 		goto err_reset;
4340 
4341 	return;
4342 
4343 err_reset:
4344 	if (hclge_reset_err_handle(hdev))
4345 		hclge_reset_task_schedule(hdev);
4346 }
4347 
4348 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
4349 {
4350 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
4351 	struct hclge_dev *hdev = ae_dev->priv;
4352 
4353 	/* We might end up getting called broadly because of 2 below cases:
4354 	 * 1. Recoverable error was conveyed through APEI and only way to bring
4355 	 *    normalcy is to reset.
4356 	 * 2. A new reset request from the stack due to timeout
4357 	 *
4358 	 * check if this is a new reset request and we are not here just because
4359 	 * last reset attempt did not succeed and watchdog hit us again. We will
4360 	 * know this if last reset request did not occur very recently (watchdog
4361 	 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
4362 	 * In case of new request we reset the "reset level" to PF reset.
4363 	 * And if it is a repeat reset request of the most recent one then we
4364 	 * want to make sure we throttle the reset request. Therefore, we will
4365 	 * not allow it again before 3*HZ times.
4366 	 */
4367 
4368 	if (time_before(jiffies, (hdev->last_reset_time +
4369 				  HCLGE_RESET_INTERVAL))) {
4370 		mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
4371 		return;
4372 	}
4373 
4374 	if (hdev->default_reset_request) {
4375 		hdev->reset_level =
4376 			hclge_get_reset_level(ae_dev,
4377 					      &hdev->default_reset_request);
4378 	} else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) {
4379 		hdev->reset_level = HNAE3_FUNC_RESET;
4380 	}
4381 
4382 	dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n",
4383 		 hdev->reset_level);
4384 
4385 	/* request reset & schedule reset task */
4386 	set_bit(hdev->reset_level, &hdev->reset_request);
4387 	hclge_reset_task_schedule(hdev);
4388 
4389 	if (hdev->reset_level < HNAE3_GLOBAL_RESET)
4390 		hdev->reset_level++;
4391 }
4392 
4393 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
4394 					enum hnae3_reset_type rst_type)
4395 {
4396 	struct hclge_dev *hdev = ae_dev->priv;
4397 
4398 	set_bit(rst_type, &hdev->default_reset_request);
4399 }
4400 
4401 static void hclge_reset_timer(struct timer_list *t)
4402 {
4403 	struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
4404 
4405 	/* if default_reset_request has no value, it means that this reset
4406 	 * request has already be handled, so just return here
4407 	 */
4408 	if (!hdev->default_reset_request)
4409 		return;
4410 
4411 	dev_info(&hdev->pdev->dev,
4412 		 "triggering reset in reset timer\n");
4413 	hclge_reset_event(hdev->pdev, NULL);
4414 }
4415 
4416 static void hclge_reset_subtask(struct hclge_dev *hdev)
4417 {
4418 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4419 
4420 	/* check if there is any ongoing reset in the hardware. This status can
4421 	 * be checked from reset_pending. If there is then, we need to wait for
4422 	 * hardware to complete reset.
4423 	 *    a. If we are able to figure out in reasonable time that hardware
4424 	 *       has fully resetted then, we can proceed with driver, client
4425 	 *       reset.
4426 	 *    b. else, we can come back later to check this status so re-sched
4427 	 *       now.
4428 	 */
4429 	hdev->last_reset_time = jiffies;
4430 	hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending);
4431 	if (hdev->reset_type != HNAE3_NONE_RESET)
4432 		hclge_reset(hdev);
4433 
4434 	/* check if we got any *new* reset requests to be honored */
4435 	hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request);
4436 	if (hdev->reset_type != HNAE3_NONE_RESET)
4437 		hclge_do_reset(hdev);
4438 
4439 	hdev->reset_type = HNAE3_NONE_RESET;
4440 }
4441 
4442 static void hclge_handle_err_reset_request(struct hclge_dev *hdev)
4443 {
4444 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4445 	enum hnae3_reset_type reset_type;
4446 
4447 	if (ae_dev->hw_err_reset_req) {
4448 		reset_type = hclge_get_reset_level(ae_dev,
4449 						   &ae_dev->hw_err_reset_req);
4450 		hclge_set_def_reset_request(ae_dev, reset_type);
4451 	}
4452 
4453 	if (hdev->default_reset_request && ae_dev->ops->reset_event)
4454 		ae_dev->ops->reset_event(hdev->pdev, NULL);
4455 
4456 	/* enable interrupt after error handling complete */
4457 	hclge_enable_vector(&hdev->misc_vector, true);
4458 }
4459 
4460 static void hclge_handle_err_recovery(struct hclge_dev *hdev)
4461 {
4462 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4463 
4464 	ae_dev->hw_err_reset_req = 0;
4465 
4466 	if (hclge_find_error_source(hdev)) {
4467 		hclge_handle_error_info_log(ae_dev);
4468 		hclge_handle_mac_tnl(hdev);
4469 		hclge_handle_vf_queue_err_ras(hdev);
4470 	}
4471 
4472 	hclge_handle_err_reset_request(hdev);
4473 }
4474 
4475 static void hclge_misc_err_recovery(struct hclge_dev *hdev)
4476 {
4477 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4478 	struct device *dev = &hdev->pdev->dev;
4479 	u32 msix_sts_reg;
4480 
4481 	msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
4482 	if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
4483 		if (hclge_handle_hw_msix_error
4484 				(hdev, &hdev->default_reset_request))
4485 			dev_info(dev, "received msix interrupt 0x%x\n",
4486 				 msix_sts_reg);
4487 	}
4488 
4489 	hclge_handle_hw_ras_error(ae_dev);
4490 
4491 	hclge_handle_err_reset_request(hdev);
4492 }
4493 
4494 static void hclge_errhand_service_task(struct hclge_dev *hdev)
4495 {
4496 	if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
4497 		return;
4498 
4499 	if (hnae3_dev_ras_imp_supported(hdev))
4500 		hclge_handle_err_recovery(hdev);
4501 	else
4502 		hclge_misc_err_recovery(hdev);
4503 }
4504 
4505 static void hclge_reset_service_task(struct hclge_dev *hdev)
4506 {
4507 	if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
4508 		return;
4509 
4510 	if (time_is_before_jiffies(hdev->last_rst_scheduled +
4511 				   HCLGE_RESET_SCHED_TIMEOUT))
4512 		dev_warn(&hdev->pdev->dev,
4513 			 "reset service task is scheduled after %ums on cpu%u!\n",
4514 			 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled),
4515 			 smp_processor_id());
4516 
4517 	down(&hdev->reset_sem);
4518 	set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4519 
4520 	hclge_reset_subtask(hdev);
4521 
4522 	clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4523 	up(&hdev->reset_sem);
4524 }
4525 
4526 static void hclge_update_vport_alive(struct hclge_dev *hdev)
4527 {
4528 #define HCLGE_ALIVE_SECONDS_NORMAL		8
4529 
4530 	unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ;
4531 	int i;
4532 
4533 	/* start from vport 1 for PF is always alive */
4534 	for (i = 1; i < hdev->num_alloc_vport; i++) {
4535 		struct hclge_vport *vport = &hdev->vport[i];
4536 
4537 		if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) ||
4538 		    !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
4539 			continue;
4540 		if (time_after(jiffies, vport->last_active_jiffies +
4541 			       alive_time)) {
4542 			clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
4543 			dev_warn(&hdev->pdev->dev,
4544 				 "VF %u heartbeat timeout\n",
4545 				 i - HCLGE_VF_VPORT_START_NUM);
4546 		}
4547 	}
4548 }
4549 
4550 static void hclge_periodic_service_task(struct hclge_dev *hdev)
4551 {
4552 	unsigned long delta = round_jiffies_relative(HZ);
4553 
4554 	if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
4555 		return;
4556 
4557 	/* Always handle the link updating to make sure link state is
4558 	 * updated when it is triggered by mbx.
4559 	 */
4560 	hclge_update_link_status(hdev);
4561 	hclge_sync_mac_table(hdev);
4562 	hclge_sync_promisc_mode(hdev);
4563 	hclge_sync_fd_table(hdev);
4564 
4565 	if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
4566 		delta = jiffies - hdev->last_serv_processed;
4567 
4568 		if (delta < round_jiffies_relative(HZ)) {
4569 			delta = round_jiffies_relative(HZ) - delta;
4570 			goto out;
4571 		}
4572 	}
4573 
4574 	hdev->serv_processed_cnt++;
4575 	hclge_update_vport_alive(hdev);
4576 
4577 	if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) {
4578 		hdev->last_serv_processed = jiffies;
4579 		goto out;
4580 	}
4581 
4582 	if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL))
4583 		hclge_update_stats_for_all(hdev);
4584 
4585 	hclge_update_port_info(hdev);
4586 	hclge_sync_vlan_filter(hdev);
4587 
4588 	if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL))
4589 		hclge_rfs_filter_expire(hdev);
4590 
4591 	hdev->last_serv_processed = jiffies;
4592 
4593 out:
4594 	hclge_task_schedule(hdev, delta);
4595 }
4596 
4597 static void hclge_ptp_service_task(struct hclge_dev *hdev)
4598 {
4599 	unsigned long flags;
4600 
4601 	if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) ||
4602 	    !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) ||
4603 	    !time_is_before_jiffies(hdev->ptp->tx_start + HZ))
4604 		return;
4605 
4606 	/* to prevent concurrence with the irq handler */
4607 	spin_lock_irqsave(&hdev->ptp->lock, flags);
4608 
4609 	/* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq
4610 	 * handler may handle it just before spin_lock_irqsave().
4611 	 */
4612 	if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state))
4613 		hclge_ptp_clean_tx_hwts(hdev);
4614 
4615 	spin_unlock_irqrestore(&hdev->ptp->lock, flags);
4616 }
4617 
4618 static void hclge_service_task(struct work_struct *work)
4619 {
4620 	struct hclge_dev *hdev =
4621 		container_of(work, struct hclge_dev, service_task.work);
4622 
4623 	hclge_errhand_service_task(hdev);
4624 	hclge_reset_service_task(hdev);
4625 	hclge_ptp_service_task(hdev);
4626 	hclge_mailbox_service_task(hdev);
4627 	hclge_periodic_service_task(hdev);
4628 
4629 	/* Handle error recovery, reset and mbx again in case periodical task
4630 	 * delays the handling by calling hclge_task_schedule() in
4631 	 * hclge_periodic_service_task().
4632 	 */
4633 	hclge_errhand_service_task(hdev);
4634 	hclge_reset_service_task(hdev);
4635 	hclge_mailbox_service_task(hdev);
4636 }
4637 
4638 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
4639 {
4640 	/* VF handle has no client */
4641 	if (!handle->client)
4642 		return container_of(handle, struct hclge_vport, nic);
4643 	else if (handle->client->type == HNAE3_CLIENT_ROCE)
4644 		return container_of(handle, struct hclge_vport, roce);
4645 	else
4646 		return container_of(handle, struct hclge_vport, nic);
4647 }
4648 
4649 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx,
4650 				  struct hnae3_vector_info *vector_info)
4651 {
4652 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2	64
4653 
4654 	vector_info->vector = pci_irq_vector(hdev->pdev, idx);
4655 
4656 	/* need an extend offset to config vector >= 64 */
4657 	if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2)
4658 		vector_info->io_addr = hdev->hw.hw.io_base +
4659 				HCLGE_VECTOR_REG_BASE +
4660 				(idx - 1) * HCLGE_VECTOR_REG_OFFSET;
4661 	else
4662 		vector_info->io_addr = hdev->hw.hw.io_base +
4663 				HCLGE_VECTOR_EXT_REG_BASE +
4664 				(idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4665 				HCLGE_VECTOR_REG_OFFSET_H +
4666 				(idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4667 				HCLGE_VECTOR_REG_OFFSET;
4668 
4669 	hdev->vector_status[idx] = hdev->vport[0].vport_id;
4670 	hdev->vector_irq[idx] = vector_info->vector;
4671 }
4672 
4673 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
4674 			    struct hnae3_vector_info *vector_info)
4675 {
4676 	struct hclge_vport *vport = hclge_get_vport(handle);
4677 	struct hnae3_vector_info *vector = vector_info;
4678 	struct hclge_dev *hdev = vport->back;
4679 	int alloc = 0;
4680 	u16 i = 0;
4681 	u16 j;
4682 
4683 	vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num);
4684 	vector_num = min(hdev->num_msi_left, vector_num);
4685 
4686 	for (j = 0; j < vector_num; j++) {
4687 		while (++i < hdev->num_nic_msi) {
4688 			if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
4689 				hclge_get_vector_info(hdev, i, vector);
4690 				vector++;
4691 				alloc++;
4692 
4693 				break;
4694 			}
4695 		}
4696 	}
4697 	hdev->num_msi_left -= alloc;
4698 	hdev->num_msi_used += alloc;
4699 
4700 	return alloc;
4701 }
4702 
4703 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
4704 {
4705 	int i;
4706 
4707 	for (i = 0; i < hdev->num_msi; i++)
4708 		if (vector == hdev->vector_irq[i])
4709 			return i;
4710 
4711 	return -EINVAL;
4712 }
4713 
4714 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
4715 {
4716 	struct hclge_vport *vport = hclge_get_vport(handle);
4717 	struct hclge_dev *hdev = vport->back;
4718 	int vector_id;
4719 
4720 	vector_id = hclge_get_vector_index(hdev, vector);
4721 	if (vector_id < 0) {
4722 		dev_err(&hdev->pdev->dev,
4723 			"Get vector index fail. vector = %d\n", vector);
4724 		return vector_id;
4725 	}
4726 
4727 	hclge_free_vector(hdev, vector_id);
4728 
4729 	return 0;
4730 }
4731 
4732 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
4733 			 u8 *key, u8 *hfunc)
4734 {
4735 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4736 	struct hclge_vport *vport = hclge_get_vport(handle);
4737 	struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg;
4738 
4739 	hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc);
4740 
4741 	hclge_comm_get_rss_indir_tbl(rss_cfg, indir,
4742 				     ae_dev->dev_specs.rss_ind_tbl_size);
4743 
4744 	return 0;
4745 }
4746 
4747 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
4748 			 const  u8 *key, const  u8 hfunc)
4749 {
4750 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4751 	struct hclge_vport *vport = hclge_get_vport(handle);
4752 	struct hclge_dev *hdev = vport->back;
4753 	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
4754 	int ret, i;
4755 
4756 	ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc);
4757 	if (ret) {
4758 		dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc);
4759 		return ret;
4760 	}
4761 
4762 	/* Update the shadow RSS table with user specified qids */
4763 	for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
4764 		rss_cfg->rss_indirection_tbl[i] = indir[i];
4765 
4766 	/* Update the hardware */
4767 	return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw,
4768 					      rss_cfg->rss_indirection_tbl);
4769 }
4770 
4771 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
4772 			       struct ethtool_rxnfc *nfc)
4773 {
4774 	struct hclge_vport *vport = hclge_get_vport(handle);
4775 	struct hclge_dev *hdev = vport->back;
4776 	int ret;
4777 
4778 	ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw,
4779 				       &hdev->rss_cfg, nfc);
4780 	if (ret) {
4781 		dev_err(&hdev->pdev->dev,
4782 			"failed to set rss tuple, ret = %d.\n", ret);
4783 		return ret;
4784 	}
4785 
4786 	return 0;
4787 }
4788 
4789 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
4790 			       struct ethtool_rxnfc *nfc)
4791 {
4792 	struct hclge_vport *vport = hclge_get_vport(handle);
4793 	u8 tuple_sets;
4794 	int ret;
4795 
4796 	nfc->data = 0;
4797 
4798 	ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type,
4799 				       &tuple_sets);
4800 	if (ret || !tuple_sets)
4801 		return ret;
4802 
4803 	nfc->data = hclge_comm_convert_rss_tuple(tuple_sets);
4804 
4805 	return 0;
4806 }
4807 
4808 static int hclge_get_tc_size(struct hnae3_handle *handle)
4809 {
4810 	struct hclge_vport *vport = hclge_get_vport(handle);
4811 	struct hclge_dev *hdev = vport->back;
4812 
4813 	return hdev->pf_rss_size_max;
4814 }
4815 
4816 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev)
4817 {
4818 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
4819 	struct hclge_vport *vport = hdev->vport;
4820 	u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
4821 	u16 tc_valid[HCLGE_MAX_TC_NUM] = {0};
4822 	u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
4823 	struct hnae3_tc_info *tc_info;
4824 	u16 roundup_size;
4825 	u16 rss_size;
4826 	int i;
4827 
4828 	tc_info = &vport->nic.kinfo.tc_info;
4829 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
4830 		rss_size = tc_info->tqp_count[i];
4831 		tc_valid[i] = 0;
4832 
4833 		if (!(hdev->hw_tc_map & BIT(i)))
4834 			continue;
4835 
4836 		/* tc_size set to hardware is the log2 of roundup power of two
4837 		 * of rss_size, the acutal queue size is limited by indirection
4838 		 * table.
4839 		 */
4840 		if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size ||
4841 		    rss_size == 0) {
4842 			dev_err(&hdev->pdev->dev,
4843 				"Configure rss tc size failed, invalid TC_SIZE = %u\n",
4844 				rss_size);
4845 			return -EINVAL;
4846 		}
4847 
4848 		roundup_size = roundup_pow_of_two(rss_size);
4849 		roundup_size = ilog2(roundup_size);
4850 
4851 		tc_valid[i] = 1;
4852 		tc_size[i] = roundup_size;
4853 		tc_offset[i] = tc_info->tqp_offset[i];
4854 	}
4855 
4856 	return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
4857 					  tc_size);
4858 }
4859 
4860 int hclge_rss_init_hw(struct hclge_dev *hdev)
4861 {
4862 	u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl;
4863 	u8 *key = hdev->rss_cfg.rss_hash_key;
4864 	u8 hfunc = hdev->rss_cfg.rss_algo;
4865 	int ret;
4866 
4867 	ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,
4868 					     rss_indir);
4869 	if (ret)
4870 		return ret;
4871 
4872 	ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key);
4873 	if (ret)
4874 		return ret;
4875 
4876 	ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg);
4877 	if (ret)
4878 		return ret;
4879 
4880 	return hclge_init_rss_tc_mode(hdev);
4881 }
4882 
4883 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
4884 				int vector_id, bool en,
4885 				struct hnae3_ring_chain_node *ring_chain)
4886 {
4887 	struct hclge_dev *hdev = vport->back;
4888 	struct hnae3_ring_chain_node *node;
4889 	struct hclge_desc desc;
4890 	struct hclge_ctrl_vector_chain_cmd *req =
4891 		(struct hclge_ctrl_vector_chain_cmd *)desc.data;
4892 	enum hclge_comm_cmd_status status;
4893 	enum hclge_opcode_type op;
4894 	u16 tqp_type_and_id;
4895 	int i;
4896 
4897 	op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
4898 	hclge_cmd_setup_basic_desc(&desc, op, false);
4899 	req->int_vector_id_l = hnae3_get_field(vector_id,
4900 					       HCLGE_VECTOR_ID_L_M,
4901 					       HCLGE_VECTOR_ID_L_S);
4902 	req->int_vector_id_h = hnae3_get_field(vector_id,
4903 					       HCLGE_VECTOR_ID_H_M,
4904 					       HCLGE_VECTOR_ID_H_S);
4905 
4906 	i = 0;
4907 	for (node = ring_chain; node; node = node->next) {
4908 		tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
4909 		hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
4910 				HCLGE_INT_TYPE_S,
4911 				hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
4912 		hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
4913 				HCLGE_TQP_ID_S, node->tqp_index);
4914 		hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
4915 				HCLGE_INT_GL_IDX_S,
4916 				hnae3_get_field(node->int_gl_idx,
4917 						HNAE3_RING_GL_IDX_M,
4918 						HNAE3_RING_GL_IDX_S));
4919 		req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
4920 		if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
4921 			req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
4922 			req->vfid = vport->vport_id;
4923 
4924 			status = hclge_cmd_send(&hdev->hw, &desc, 1);
4925 			if (status) {
4926 				dev_err(&hdev->pdev->dev,
4927 					"Map TQP fail, status is %d.\n",
4928 					status);
4929 				return -EIO;
4930 			}
4931 			i = 0;
4932 
4933 			hclge_cmd_setup_basic_desc(&desc,
4934 						   op,
4935 						   false);
4936 			req->int_vector_id_l =
4937 				hnae3_get_field(vector_id,
4938 						HCLGE_VECTOR_ID_L_M,
4939 						HCLGE_VECTOR_ID_L_S);
4940 			req->int_vector_id_h =
4941 				hnae3_get_field(vector_id,
4942 						HCLGE_VECTOR_ID_H_M,
4943 						HCLGE_VECTOR_ID_H_S);
4944 		}
4945 	}
4946 
4947 	if (i > 0) {
4948 		req->int_cause_num = i;
4949 		req->vfid = vport->vport_id;
4950 		status = hclge_cmd_send(&hdev->hw, &desc, 1);
4951 		if (status) {
4952 			dev_err(&hdev->pdev->dev,
4953 				"Map TQP fail, status is %d.\n", status);
4954 			return -EIO;
4955 		}
4956 	}
4957 
4958 	return 0;
4959 }
4960 
4961 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector,
4962 				    struct hnae3_ring_chain_node *ring_chain)
4963 {
4964 	struct hclge_vport *vport = hclge_get_vport(handle);
4965 	struct hclge_dev *hdev = vport->back;
4966 	int vector_id;
4967 
4968 	vector_id = hclge_get_vector_index(hdev, vector);
4969 	if (vector_id < 0) {
4970 		dev_err(&hdev->pdev->dev,
4971 			"failed to get vector index. vector=%d\n", vector);
4972 		return vector_id;
4973 	}
4974 
4975 	return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
4976 }
4977 
4978 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector,
4979 				       struct hnae3_ring_chain_node *ring_chain)
4980 {
4981 	struct hclge_vport *vport = hclge_get_vport(handle);
4982 	struct hclge_dev *hdev = vport->back;
4983 	int vector_id, ret;
4984 
4985 	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
4986 		return 0;
4987 
4988 	vector_id = hclge_get_vector_index(hdev, vector);
4989 	if (vector_id < 0) {
4990 		dev_err(&handle->pdev->dev,
4991 			"Get vector index fail. ret =%d\n", vector_id);
4992 		return vector_id;
4993 	}
4994 
4995 	ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
4996 	if (ret)
4997 		dev_err(&handle->pdev->dev,
4998 			"Unmap ring from vector fail. vectorid=%d, ret =%d\n",
4999 			vector_id, ret);
5000 
5001 	return ret;
5002 }
5003 
5004 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id,
5005 				      bool en_uc, bool en_mc, bool en_bc)
5006 {
5007 	struct hclge_vport *vport = &hdev->vport[vf_id];
5008 	struct hnae3_handle *handle = &vport->nic;
5009 	struct hclge_promisc_cfg_cmd *req;
5010 	struct hclge_desc desc;
5011 	bool uc_tx_en = en_uc;
5012 	u8 promisc_cfg = 0;
5013 	int ret;
5014 
5015 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
5016 
5017 	req = (struct hclge_promisc_cfg_cmd *)desc.data;
5018 	req->vf_id = vf_id;
5019 
5020 	if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags))
5021 		uc_tx_en = false;
5022 
5023 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0);
5024 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0);
5025 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0);
5026 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0);
5027 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0);
5028 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0);
5029 	req->extend_promisc = promisc_cfg;
5030 
5031 	/* to be compatible with DEVICE_VERSION_V1/2 */
5032 	promisc_cfg = 0;
5033 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0);
5034 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0);
5035 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0);
5036 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1);
5037 	hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1);
5038 	req->promisc = promisc_cfg;
5039 
5040 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5041 	if (ret)
5042 		dev_err(&hdev->pdev->dev,
5043 			"failed to set vport %u promisc mode, ret = %d.\n",
5044 			vf_id, ret);
5045 
5046 	return ret;
5047 }
5048 
5049 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
5050 				 bool en_mc_pmc, bool en_bc_pmc)
5051 {
5052 	return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id,
5053 					  en_uc_pmc, en_mc_pmc, en_bc_pmc);
5054 }
5055 
5056 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
5057 				  bool en_mc_pmc)
5058 {
5059 	struct hclge_vport *vport = hclge_get_vport(handle);
5060 	struct hclge_dev *hdev = vport->back;
5061 	bool en_bc_pmc = true;
5062 
5063 	/* For device whose version below V2, if broadcast promisc enabled,
5064 	 * vlan filter is always bypassed. So broadcast promisc should be
5065 	 * disabled until user enable promisc mode
5066 	 */
5067 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
5068 		en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false;
5069 
5070 	return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc,
5071 					    en_bc_pmc);
5072 }
5073 
5074 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle)
5075 {
5076 	struct hclge_vport *vport = hclge_get_vport(handle);
5077 
5078 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
5079 }
5080 
5081 static void hclge_sync_fd_state(struct hclge_dev *hdev)
5082 {
5083 	if (hlist_empty(&hdev->fd_rule_list))
5084 		hdev->fd_active_type = HCLGE_FD_RULE_NONE;
5085 }
5086 
5087 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location)
5088 {
5089 	if (!test_bit(location, hdev->fd_bmap)) {
5090 		set_bit(location, hdev->fd_bmap);
5091 		hdev->hclge_fd_rule_num++;
5092 	}
5093 }
5094 
5095 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location)
5096 {
5097 	if (test_bit(location, hdev->fd_bmap)) {
5098 		clear_bit(location, hdev->fd_bmap);
5099 		hdev->hclge_fd_rule_num--;
5100 	}
5101 }
5102 
5103 static void hclge_fd_free_node(struct hclge_dev *hdev,
5104 			       struct hclge_fd_rule *rule)
5105 {
5106 	hlist_del(&rule->rule_node);
5107 	kfree(rule);
5108 	hclge_sync_fd_state(hdev);
5109 }
5110 
5111 static void hclge_update_fd_rule_node(struct hclge_dev *hdev,
5112 				      struct hclge_fd_rule *old_rule,
5113 				      struct hclge_fd_rule *new_rule,
5114 				      enum HCLGE_FD_NODE_STATE state)
5115 {
5116 	switch (state) {
5117 	case HCLGE_FD_TO_ADD:
5118 	case HCLGE_FD_ACTIVE:
5119 		/* 1) if the new state is TO_ADD, just replace the old rule
5120 		 * with the same location, no matter its state, because the
5121 		 * new rule will be configured to the hardware.
5122 		 * 2) if the new state is ACTIVE, it means the new rule
5123 		 * has been configured to the hardware, so just replace
5124 		 * the old rule node with the same location.
5125 		 * 3) for it doesn't add a new node to the list, so it's
5126 		 * unnecessary to update the rule number and fd_bmap.
5127 		 */
5128 		new_rule->rule_node.next = old_rule->rule_node.next;
5129 		new_rule->rule_node.pprev = old_rule->rule_node.pprev;
5130 		memcpy(old_rule, new_rule, sizeof(*old_rule));
5131 		kfree(new_rule);
5132 		break;
5133 	case HCLGE_FD_DELETED:
5134 		hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5135 		hclge_fd_free_node(hdev, old_rule);
5136 		break;
5137 	case HCLGE_FD_TO_DEL:
5138 		/* if new request is TO_DEL, and old rule is existent
5139 		 * 1) the state of old rule is TO_DEL, we need do nothing,
5140 		 * because we delete rule by location, other rule content
5141 		 * is unncessary.
5142 		 * 2) the state of old rule is ACTIVE, we need to change its
5143 		 * state to TO_DEL, so the rule will be deleted when periodic
5144 		 * task being scheduled.
5145 		 * 3) the state of old rule is TO_ADD, it means the rule hasn't
5146 		 * been added to hardware, so we just delete the rule node from
5147 		 * fd_rule_list directly.
5148 		 */
5149 		if (old_rule->state == HCLGE_FD_TO_ADD) {
5150 			hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5151 			hclge_fd_free_node(hdev, old_rule);
5152 			return;
5153 		}
5154 		old_rule->state = HCLGE_FD_TO_DEL;
5155 		break;
5156 	}
5157 }
5158 
5159 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist,
5160 						u16 location,
5161 						struct hclge_fd_rule **parent)
5162 {
5163 	struct hclge_fd_rule *rule;
5164 	struct hlist_node *node;
5165 
5166 	hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
5167 		if (rule->location == location)
5168 			return rule;
5169 		else if (rule->location > location)
5170 			return NULL;
5171 		/* record the parent node, use to keep the nodes in fd_rule_list
5172 		 * in ascend order.
5173 		 */
5174 		*parent = rule;
5175 	}
5176 
5177 	return NULL;
5178 }
5179 
5180 /* insert fd rule node in ascend order according to rule->location */
5181 static void hclge_fd_insert_rule_node(struct hlist_head *hlist,
5182 				      struct hclge_fd_rule *rule,
5183 				      struct hclge_fd_rule *parent)
5184 {
5185 	INIT_HLIST_NODE(&rule->rule_node);
5186 
5187 	if (parent)
5188 		hlist_add_behind(&rule->rule_node, &parent->rule_node);
5189 	else
5190 		hlist_add_head(&rule->rule_node, hlist);
5191 }
5192 
5193 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev,
5194 				     struct hclge_fd_user_def_cfg *cfg)
5195 {
5196 	struct hclge_fd_user_def_cfg_cmd *req;
5197 	struct hclge_desc desc;
5198 	u16 data = 0;
5199 	int ret;
5200 
5201 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false);
5202 
5203 	req = (struct hclge_fd_user_def_cfg_cmd *)desc.data;
5204 
5205 	hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0);
5206 	hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5207 			HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset);
5208 	req->ol2_cfg = cpu_to_le16(data);
5209 
5210 	data = 0;
5211 	hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0);
5212 	hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5213 			HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset);
5214 	req->ol3_cfg = cpu_to_le16(data);
5215 
5216 	data = 0;
5217 	hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0);
5218 	hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5219 			HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset);
5220 	req->ol4_cfg = cpu_to_le16(data);
5221 
5222 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5223 	if (ret)
5224 		dev_err(&hdev->pdev->dev,
5225 			"failed to set fd user def data, ret= %d\n", ret);
5226 	return ret;
5227 }
5228 
5229 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked)
5230 {
5231 	int ret;
5232 
5233 	if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state))
5234 		return;
5235 
5236 	if (!locked)
5237 		spin_lock_bh(&hdev->fd_rule_lock);
5238 
5239 	ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg);
5240 	if (ret)
5241 		set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5242 
5243 	if (!locked)
5244 		spin_unlock_bh(&hdev->fd_rule_lock);
5245 }
5246 
5247 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev,
5248 					  struct hclge_fd_rule *rule)
5249 {
5250 	struct hlist_head *hlist = &hdev->fd_rule_list;
5251 	struct hclge_fd_rule *fd_rule, *parent = NULL;
5252 	struct hclge_fd_user_def_info *info, *old_info;
5253 	struct hclge_fd_user_def_cfg *cfg;
5254 
5255 	if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5256 	    rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5257 		return 0;
5258 
5259 	/* for valid layer is start from 1, so need minus 1 to get the cfg */
5260 	cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5261 	info = &rule->ep.user_def;
5262 
5263 	if (!cfg->ref_cnt || cfg->offset == info->offset)
5264 		return 0;
5265 
5266 	if (cfg->ref_cnt > 1)
5267 		goto error;
5268 
5269 	fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent);
5270 	if (fd_rule) {
5271 		old_info = &fd_rule->ep.user_def;
5272 		if (info->layer == old_info->layer)
5273 			return 0;
5274 	}
5275 
5276 error:
5277 	dev_err(&hdev->pdev->dev,
5278 		"No available offset for layer%d fd rule, each layer only support one user def offset.\n",
5279 		info->layer + 1);
5280 	return -ENOSPC;
5281 }
5282 
5283 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev,
5284 					 struct hclge_fd_rule *rule)
5285 {
5286 	struct hclge_fd_user_def_cfg *cfg;
5287 
5288 	if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5289 	    rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5290 		return;
5291 
5292 	cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5293 	if (!cfg->ref_cnt) {
5294 		cfg->offset = rule->ep.user_def.offset;
5295 		set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5296 	}
5297 	cfg->ref_cnt++;
5298 }
5299 
5300 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev,
5301 					 struct hclge_fd_rule *rule)
5302 {
5303 	struct hclge_fd_user_def_cfg *cfg;
5304 
5305 	if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5306 	    rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5307 		return;
5308 
5309 	cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5310 	if (!cfg->ref_cnt)
5311 		return;
5312 
5313 	cfg->ref_cnt--;
5314 	if (!cfg->ref_cnt) {
5315 		cfg->offset = 0;
5316 		set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5317 	}
5318 }
5319 
5320 static void hclge_update_fd_list(struct hclge_dev *hdev,
5321 				 enum HCLGE_FD_NODE_STATE state, u16 location,
5322 				 struct hclge_fd_rule *new_rule)
5323 {
5324 	struct hlist_head *hlist = &hdev->fd_rule_list;
5325 	struct hclge_fd_rule *fd_rule, *parent = NULL;
5326 
5327 	fd_rule = hclge_find_fd_rule(hlist, location, &parent);
5328 	if (fd_rule) {
5329 		hclge_fd_dec_user_def_refcnt(hdev, fd_rule);
5330 		if (state == HCLGE_FD_ACTIVE)
5331 			hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5332 		hclge_sync_fd_user_def_cfg(hdev, true);
5333 
5334 		hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state);
5335 		return;
5336 	}
5337 
5338 	/* it's unlikely to fail here, because we have checked the rule
5339 	 * exist before.
5340 	 */
5341 	if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) {
5342 		dev_warn(&hdev->pdev->dev,
5343 			 "failed to delete fd rule %u, it's inexistent\n",
5344 			 location);
5345 		return;
5346 	}
5347 
5348 	hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5349 	hclge_sync_fd_user_def_cfg(hdev, true);
5350 
5351 	hclge_fd_insert_rule_node(hlist, new_rule, parent);
5352 	hclge_fd_inc_rule_cnt(hdev, new_rule->location);
5353 
5354 	if (state == HCLGE_FD_TO_ADD) {
5355 		set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
5356 		hclge_task_schedule(hdev, 0);
5357 	}
5358 }
5359 
5360 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
5361 {
5362 	struct hclge_get_fd_mode_cmd *req;
5363 	struct hclge_desc desc;
5364 	int ret;
5365 
5366 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
5367 
5368 	req = (struct hclge_get_fd_mode_cmd *)desc.data;
5369 
5370 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5371 	if (ret) {
5372 		dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
5373 		return ret;
5374 	}
5375 
5376 	*fd_mode = req->mode;
5377 
5378 	return ret;
5379 }
5380 
5381 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
5382 				   u32 *stage1_entry_num,
5383 				   u32 *stage2_entry_num,
5384 				   u16 *stage1_counter_num,
5385 				   u16 *stage2_counter_num)
5386 {
5387 	struct hclge_get_fd_allocation_cmd *req;
5388 	struct hclge_desc desc;
5389 	int ret;
5390 
5391 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
5392 
5393 	req = (struct hclge_get_fd_allocation_cmd *)desc.data;
5394 
5395 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5396 	if (ret) {
5397 		dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
5398 			ret);
5399 		return ret;
5400 	}
5401 
5402 	*stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
5403 	*stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
5404 	*stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
5405 	*stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
5406 
5407 	return ret;
5408 }
5409 
5410 static int hclge_set_fd_key_config(struct hclge_dev *hdev,
5411 				   enum HCLGE_FD_STAGE stage_num)
5412 {
5413 	struct hclge_set_fd_key_config_cmd *req;
5414 	struct hclge_fd_key_cfg *stage;
5415 	struct hclge_desc desc;
5416 	int ret;
5417 
5418 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
5419 
5420 	req = (struct hclge_set_fd_key_config_cmd *)desc.data;
5421 	stage = &hdev->fd_cfg.key_cfg[stage_num];
5422 	req->stage = stage_num;
5423 	req->key_select = stage->key_sel;
5424 	req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
5425 	req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
5426 	req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
5427 	req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
5428 	req->tuple_mask = cpu_to_le32(~stage->tuple_active);
5429 	req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
5430 
5431 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5432 	if (ret)
5433 		dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
5434 
5435 	return ret;
5436 }
5437 
5438 static void hclge_fd_disable_user_def(struct hclge_dev *hdev)
5439 {
5440 	struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg;
5441 
5442 	spin_lock_bh(&hdev->fd_rule_lock);
5443 	memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg));
5444 	spin_unlock_bh(&hdev->fd_rule_lock);
5445 
5446 	hclge_fd_set_user_def_cmd(hdev, cfg);
5447 }
5448 
5449 static int hclge_init_fd_config(struct hclge_dev *hdev)
5450 {
5451 #define LOW_2_WORDS		0x03
5452 	struct hclge_fd_key_cfg *key_cfg;
5453 	int ret;
5454 
5455 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
5456 		return 0;
5457 
5458 	ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
5459 	if (ret)
5460 		return ret;
5461 
5462 	switch (hdev->fd_cfg.fd_mode) {
5463 	case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
5464 		hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
5465 		break;
5466 	case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
5467 		hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
5468 		break;
5469 	default:
5470 		dev_err(&hdev->pdev->dev,
5471 			"Unsupported flow director mode %u\n",
5472 			hdev->fd_cfg.fd_mode);
5473 		return -EOPNOTSUPP;
5474 	}
5475 
5476 	key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
5477 	key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE;
5478 	key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
5479 	key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
5480 	key_cfg->outer_sipv6_word_en = 0;
5481 	key_cfg->outer_dipv6_word_en = 0;
5482 
5483 	key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
5484 				BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
5485 				BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
5486 				BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5487 
5488 	/* If use max 400bit key, we can support tuples for ether type */
5489 	if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
5490 		key_cfg->tuple_active |=
5491 				BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
5492 		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5493 			key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
5494 	}
5495 
5496 	/* roce_type is used to filter roce frames
5497 	 * dst_vport is used to specify the rule
5498 	 */
5499 	key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
5500 
5501 	ret = hclge_get_fd_allocation(hdev,
5502 				      &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
5503 				      &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
5504 				      &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
5505 				      &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
5506 	if (ret)
5507 		return ret;
5508 
5509 	return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
5510 }
5511 
5512 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
5513 				int loc, u8 *key, bool is_add)
5514 {
5515 	struct hclge_fd_tcam_config_1_cmd *req1;
5516 	struct hclge_fd_tcam_config_2_cmd *req2;
5517 	struct hclge_fd_tcam_config_3_cmd *req3;
5518 	struct hclge_desc desc[3];
5519 	int ret;
5520 
5521 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
5522 	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5523 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
5524 	desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5525 	hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
5526 
5527 	req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
5528 	req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
5529 	req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
5530 
5531 	req1->stage = stage;
5532 	req1->xy_sel = sel_x ? 1 : 0;
5533 	hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
5534 	req1->index = cpu_to_le32(loc);
5535 	req1->entry_vld = sel_x ? is_add : 0;
5536 
5537 	if (key) {
5538 		memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
5539 		memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
5540 		       sizeof(req2->tcam_data));
5541 		memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
5542 		       sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
5543 	}
5544 
5545 	ret = hclge_cmd_send(&hdev->hw, desc, 3);
5546 	if (ret)
5547 		dev_err(&hdev->pdev->dev,
5548 			"config tcam key fail, ret=%d\n",
5549 			ret);
5550 
5551 	return ret;
5552 }
5553 
5554 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
5555 			      struct hclge_fd_ad_data *action)
5556 {
5557 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
5558 	struct hclge_fd_ad_config_cmd *req;
5559 	struct hclge_desc desc;
5560 	u64 ad_data = 0;
5561 	int ret;
5562 
5563 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
5564 
5565 	req = (struct hclge_fd_ad_config_cmd *)desc.data;
5566 	req->index = cpu_to_le32(loc);
5567 	req->stage = stage;
5568 
5569 	hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
5570 		      action->write_rule_id_to_bd);
5571 	hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
5572 			action->rule_id);
5573 	if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) {
5574 		hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B,
5575 			      action->override_tc);
5576 		hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M,
5577 				HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size);
5578 	}
5579 	ad_data <<= 32;
5580 	hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
5581 	hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
5582 		      action->forward_to_direct_queue);
5583 	hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
5584 			action->queue_id);
5585 	hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
5586 	hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
5587 			HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
5588 	hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
5589 	hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
5590 			action->counter_id);
5591 
5592 	req->ad_data = cpu_to_le64(ad_data);
5593 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5594 	if (ret)
5595 		dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
5596 
5597 	return ret;
5598 }
5599 
5600 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
5601 				   struct hclge_fd_rule *rule)
5602 {
5603 	int offset, moffset, ip_offset;
5604 	enum HCLGE_FD_KEY_OPT key_opt;
5605 	u16 tmp_x_s, tmp_y_s;
5606 	u32 tmp_x_l, tmp_y_l;
5607 	u8 *p = (u8 *)rule;
5608 	int i;
5609 
5610 	if (rule->unused_tuple & BIT(tuple_bit))
5611 		return true;
5612 
5613 	key_opt = tuple_key_info[tuple_bit].key_opt;
5614 	offset = tuple_key_info[tuple_bit].offset;
5615 	moffset = tuple_key_info[tuple_bit].moffset;
5616 
5617 	switch (key_opt) {
5618 	case KEY_OPT_U8:
5619 		calc_x(*key_x, p[offset], p[moffset]);
5620 		calc_y(*key_y, p[offset], p[moffset]);
5621 
5622 		return true;
5623 	case KEY_OPT_LE16:
5624 		calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5625 		calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5626 		*(__le16 *)key_x = cpu_to_le16(tmp_x_s);
5627 		*(__le16 *)key_y = cpu_to_le16(tmp_y_s);
5628 
5629 		return true;
5630 	case KEY_OPT_LE32:
5631 		calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5632 		calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5633 		*(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5634 		*(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5635 
5636 		return true;
5637 	case KEY_OPT_MAC:
5638 		for (i = 0; i < ETH_ALEN; i++) {
5639 			calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i],
5640 			       p[moffset + i]);
5641 			calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i],
5642 			       p[moffset + i]);
5643 		}
5644 
5645 		return true;
5646 	case KEY_OPT_IP:
5647 		ip_offset = IPV4_INDEX * sizeof(u32);
5648 		calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]),
5649 		       *(u32 *)(&p[moffset + ip_offset]));
5650 		calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]),
5651 		       *(u32 *)(&p[moffset + ip_offset]));
5652 		*(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5653 		*(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5654 
5655 		return true;
5656 	default:
5657 		return false;
5658 	}
5659 }
5660 
5661 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
5662 				 u8 vf_id, u8 network_port_id)
5663 {
5664 	u32 port_number = 0;
5665 
5666 	if (port_type == HOST_PORT) {
5667 		hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
5668 				pf_id);
5669 		hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
5670 				vf_id);
5671 		hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
5672 	} else {
5673 		hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
5674 				HCLGE_NETWORK_PORT_ID_S, network_port_id);
5675 		hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
5676 	}
5677 
5678 	return port_number;
5679 }
5680 
5681 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
5682 				       __le32 *key_x, __le32 *key_y,
5683 				       struct hclge_fd_rule *rule)
5684 {
5685 	u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
5686 	u8 cur_pos = 0, tuple_size, shift_bits;
5687 	unsigned int i;
5688 
5689 	for (i = 0; i < MAX_META_DATA; i++) {
5690 		tuple_size = meta_data_key_info[i].key_length;
5691 		tuple_bit = key_cfg->meta_data_active & BIT(i);
5692 
5693 		switch (tuple_bit) {
5694 		case BIT(ROCE_TYPE):
5695 			hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
5696 			cur_pos += tuple_size;
5697 			break;
5698 		case BIT(DST_VPORT):
5699 			port_number = hclge_get_port_number(HOST_PORT, 0,
5700 							    rule->vf_id, 0);
5701 			hnae3_set_field(meta_data,
5702 					GENMASK(cur_pos + tuple_size, cur_pos),
5703 					cur_pos, port_number);
5704 			cur_pos += tuple_size;
5705 			break;
5706 		default:
5707 			break;
5708 		}
5709 	}
5710 
5711 	calc_x(tmp_x, meta_data, 0xFFFFFFFF);
5712 	calc_y(tmp_y, meta_data, 0xFFFFFFFF);
5713 	shift_bits = sizeof(meta_data) * 8 - cur_pos;
5714 
5715 	*key_x = cpu_to_le32(tmp_x << shift_bits);
5716 	*key_y = cpu_to_le32(tmp_y << shift_bits);
5717 }
5718 
5719 /* A complete key is combined with meta data key and tuple key.
5720  * Meta data key is stored at the MSB region, and tuple key is stored at
5721  * the LSB region, unused bits will be filled 0.
5722  */
5723 static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
5724 			    struct hclge_fd_rule *rule)
5725 {
5726 	struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
5727 	u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
5728 	u8 *cur_key_x, *cur_key_y;
5729 	u8 meta_data_region;
5730 	u8 tuple_size;
5731 	int ret;
5732 	u32 i;
5733 
5734 	memset(key_x, 0, sizeof(key_x));
5735 	memset(key_y, 0, sizeof(key_y));
5736 	cur_key_x = key_x;
5737 	cur_key_y = key_y;
5738 
5739 	for (i = 0; i < MAX_TUPLE; i++) {
5740 		bool tuple_valid;
5741 
5742 		tuple_size = tuple_key_info[i].key_length / 8;
5743 		if (!(key_cfg->tuple_active & BIT(i)))
5744 			continue;
5745 
5746 		tuple_valid = hclge_fd_convert_tuple(i, cur_key_x,
5747 						     cur_key_y, rule);
5748 		if (tuple_valid) {
5749 			cur_key_x += tuple_size;
5750 			cur_key_y += tuple_size;
5751 		}
5752 	}
5753 
5754 	meta_data_region = hdev->fd_cfg.max_key_length / 8 -
5755 			MAX_META_DATA_LENGTH / 8;
5756 
5757 	hclge_fd_convert_meta_data(key_cfg,
5758 				   (__le32 *)(key_x + meta_data_region),
5759 				   (__le32 *)(key_y + meta_data_region),
5760 				   rule);
5761 
5762 	ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
5763 				   true);
5764 	if (ret) {
5765 		dev_err(&hdev->pdev->dev,
5766 			"fd key_y config fail, loc=%u, ret=%d\n",
5767 			rule->queue_id, ret);
5768 		return ret;
5769 	}
5770 
5771 	ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
5772 				   true);
5773 	if (ret)
5774 		dev_err(&hdev->pdev->dev,
5775 			"fd key_x config fail, loc=%u, ret=%d\n",
5776 			rule->queue_id, ret);
5777 	return ret;
5778 }
5779 
5780 static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
5781 			       struct hclge_fd_rule *rule)
5782 {
5783 	struct hclge_vport *vport = hdev->vport;
5784 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5785 	struct hclge_fd_ad_data ad_data;
5786 
5787 	memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data));
5788 	ad_data.ad_id = rule->location;
5789 
5790 	if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
5791 		ad_data.drop_packet = true;
5792 	} else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) {
5793 		ad_data.override_tc = true;
5794 		ad_data.queue_id =
5795 			kinfo->tc_info.tqp_offset[rule->cls_flower.tc];
5796 		ad_data.tc_size =
5797 			ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]);
5798 	} else {
5799 		ad_data.forward_to_direct_queue = true;
5800 		ad_data.queue_id = rule->queue_id;
5801 	}
5802 
5803 	if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) {
5804 		ad_data.use_counter = true;
5805 		ad_data.counter_id = rule->vf_id %
5806 				     hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1];
5807 	} else {
5808 		ad_data.use_counter = false;
5809 		ad_data.counter_id = 0;
5810 	}
5811 
5812 	ad_data.use_next_stage = false;
5813 	ad_data.next_input_key = 0;
5814 
5815 	ad_data.write_rule_id_to_bd = true;
5816 	ad_data.rule_id = rule->location;
5817 
5818 	return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
5819 }
5820 
5821 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec,
5822 				       u32 *unused_tuple)
5823 {
5824 	if (!spec || !unused_tuple)
5825 		return -EINVAL;
5826 
5827 	*unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5828 
5829 	if (!spec->ip4src)
5830 		*unused_tuple |= BIT(INNER_SRC_IP);
5831 
5832 	if (!spec->ip4dst)
5833 		*unused_tuple |= BIT(INNER_DST_IP);
5834 
5835 	if (!spec->psrc)
5836 		*unused_tuple |= BIT(INNER_SRC_PORT);
5837 
5838 	if (!spec->pdst)
5839 		*unused_tuple |= BIT(INNER_DST_PORT);
5840 
5841 	if (!spec->tos)
5842 		*unused_tuple |= BIT(INNER_IP_TOS);
5843 
5844 	return 0;
5845 }
5846 
5847 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec,
5848 				    u32 *unused_tuple)
5849 {
5850 	if (!spec || !unused_tuple)
5851 		return -EINVAL;
5852 
5853 	*unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
5854 		BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5855 
5856 	if (!spec->ip4src)
5857 		*unused_tuple |= BIT(INNER_SRC_IP);
5858 
5859 	if (!spec->ip4dst)
5860 		*unused_tuple |= BIT(INNER_DST_IP);
5861 
5862 	if (!spec->tos)
5863 		*unused_tuple |= BIT(INNER_IP_TOS);
5864 
5865 	if (!spec->proto)
5866 		*unused_tuple |= BIT(INNER_IP_PROTO);
5867 
5868 	if (spec->l4_4_bytes)
5869 		return -EOPNOTSUPP;
5870 
5871 	if (spec->ip_ver != ETH_RX_NFC_IP4)
5872 		return -EOPNOTSUPP;
5873 
5874 	return 0;
5875 }
5876 
5877 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec,
5878 				       u32 *unused_tuple)
5879 {
5880 	if (!spec || !unused_tuple)
5881 		return -EINVAL;
5882 
5883 	*unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5884 
5885 	/* check whether src/dst ip address used */
5886 	if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
5887 		*unused_tuple |= BIT(INNER_SRC_IP);
5888 
5889 	if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
5890 		*unused_tuple |= BIT(INNER_DST_IP);
5891 
5892 	if (!spec->psrc)
5893 		*unused_tuple |= BIT(INNER_SRC_PORT);
5894 
5895 	if (!spec->pdst)
5896 		*unused_tuple |= BIT(INNER_DST_PORT);
5897 
5898 	if (!spec->tclass)
5899 		*unused_tuple |= BIT(INNER_IP_TOS);
5900 
5901 	return 0;
5902 }
5903 
5904 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec,
5905 				    u32 *unused_tuple)
5906 {
5907 	if (!spec || !unused_tuple)
5908 		return -EINVAL;
5909 
5910 	*unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
5911 			BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5912 
5913 	/* check whether src/dst ip address used */
5914 	if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
5915 		*unused_tuple |= BIT(INNER_SRC_IP);
5916 
5917 	if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
5918 		*unused_tuple |= BIT(INNER_DST_IP);
5919 
5920 	if (!spec->l4_proto)
5921 		*unused_tuple |= BIT(INNER_IP_PROTO);
5922 
5923 	if (!spec->tclass)
5924 		*unused_tuple |= BIT(INNER_IP_TOS);
5925 
5926 	if (spec->l4_4_bytes)
5927 		return -EOPNOTSUPP;
5928 
5929 	return 0;
5930 }
5931 
5932 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple)
5933 {
5934 	if (!spec || !unused_tuple)
5935 		return -EINVAL;
5936 
5937 	*unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
5938 		BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
5939 		BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
5940 
5941 	if (is_zero_ether_addr(spec->h_source))
5942 		*unused_tuple |= BIT(INNER_SRC_MAC);
5943 
5944 	if (is_zero_ether_addr(spec->h_dest))
5945 		*unused_tuple |= BIT(INNER_DST_MAC);
5946 
5947 	if (!spec->h_proto)
5948 		*unused_tuple |= BIT(INNER_ETH_TYPE);
5949 
5950 	return 0;
5951 }
5952 
5953 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev,
5954 				    struct ethtool_rx_flow_spec *fs,
5955 				    u32 *unused_tuple)
5956 {
5957 	if (fs->flow_type & FLOW_EXT) {
5958 		if (fs->h_ext.vlan_etype) {
5959 			dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n");
5960 			return -EOPNOTSUPP;
5961 		}
5962 
5963 		if (!fs->h_ext.vlan_tci)
5964 			*unused_tuple |= BIT(INNER_VLAN_TAG_FST);
5965 
5966 		if (fs->m_ext.vlan_tci &&
5967 		    be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) {
5968 			dev_err(&hdev->pdev->dev,
5969 				"failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n",
5970 				ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1);
5971 			return -EINVAL;
5972 		}
5973 	} else {
5974 		*unused_tuple |= BIT(INNER_VLAN_TAG_FST);
5975 	}
5976 
5977 	if (fs->flow_type & FLOW_MAC_EXT) {
5978 		if (hdev->fd_cfg.fd_mode !=
5979 		    HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
5980 			dev_err(&hdev->pdev->dev,
5981 				"FLOW_MAC_EXT is not supported in current fd mode!\n");
5982 			return -EOPNOTSUPP;
5983 		}
5984 
5985 		if (is_zero_ether_addr(fs->h_ext.h_dest))
5986 			*unused_tuple |= BIT(INNER_DST_MAC);
5987 		else
5988 			*unused_tuple &= ~BIT(INNER_DST_MAC);
5989 	}
5990 
5991 	return 0;
5992 }
5993 
5994 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple,
5995 				       struct hclge_fd_user_def_info *info)
5996 {
5997 	switch (flow_type) {
5998 	case ETHER_FLOW:
5999 		info->layer = HCLGE_FD_USER_DEF_L2;
6000 		*unused_tuple &= ~BIT(INNER_L2_RSV);
6001 		break;
6002 	case IP_USER_FLOW:
6003 	case IPV6_USER_FLOW:
6004 		info->layer = HCLGE_FD_USER_DEF_L3;
6005 		*unused_tuple &= ~BIT(INNER_L3_RSV);
6006 		break;
6007 	case TCP_V4_FLOW:
6008 	case UDP_V4_FLOW:
6009 	case TCP_V6_FLOW:
6010 	case UDP_V6_FLOW:
6011 		info->layer = HCLGE_FD_USER_DEF_L4;
6012 		*unused_tuple &= ~BIT(INNER_L4_RSV);
6013 		break;
6014 	default:
6015 		return -EOPNOTSUPP;
6016 	}
6017 
6018 	return 0;
6019 }
6020 
6021 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs)
6022 {
6023 	return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0;
6024 }
6025 
6026 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev,
6027 					 struct ethtool_rx_flow_spec *fs,
6028 					 u32 *unused_tuple,
6029 					 struct hclge_fd_user_def_info *info)
6030 {
6031 	u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active;
6032 	u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6033 	u16 data, offset, data_mask, offset_mask;
6034 	int ret;
6035 
6036 	info->layer = HCLGE_FD_USER_DEF_NONE;
6037 	*unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
6038 
6039 	if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs))
6040 		return 0;
6041 
6042 	/* user-def data from ethtool is 64 bit value, the bit0~15 is used
6043 	 * for data, and bit32~47 is used for offset.
6044 	 */
6045 	data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
6046 	data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
6047 	offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
6048 	offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
6049 
6050 	if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) {
6051 		dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
6052 		return -EOPNOTSUPP;
6053 	}
6054 
6055 	if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) {
6056 		dev_err(&hdev->pdev->dev,
6057 			"user-def offset[%u] should be no more than %u\n",
6058 			offset, HCLGE_FD_MAX_USER_DEF_OFFSET);
6059 		return -EINVAL;
6060 	}
6061 
6062 	if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) {
6063 		dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n");
6064 		return -EINVAL;
6065 	}
6066 
6067 	ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info);
6068 	if (ret) {
6069 		dev_err(&hdev->pdev->dev,
6070 			"unsupported flow type for user-def bytes, ret = %d\n",
6071 			ret);
6072 		return ret;
6073 	}
6074 
6075 	info->data = data;
6076 	info->data_mask = data_mask;
6077 	info->offset = offset;
6078 
6079 	return 0;
6080 }
6081 
6082 static int hclge_fd_check_spec(struct hclge_dev *hdev,
6083 			       struct ethtool_rx_flow_spec *fs,
6084 			       u32 *unused_tuple,
6085 			       struct hclge_fd_user_def_info *info)
6086 {
6087 	u32 flow_type;
6088 	int ret;
6089 
6090 	if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
6091 		dev_err(&hdev->pdev->dev,
6092 			"failed to config fd rules, invalid rule location: %u, max is %u\n.",
6093 			fs->location,
6094 			hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1);
6095 		return -EINVAL;
6096 	}
6097 
6098 	ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info);
6099 	if (ret)
6100 		return ret;
6101 
6102 	flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6103 	switch (flow_type) {
6104 	case SCTP_V4_FLOW:
6105 	case TCP_V4_FLOW:
6106 	case UDP_V4_FLOW:
6107 		ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec,
6108 						  unused_tuple);
6109 		break;
6110 	case IP_USER_FLOW:
6111 		ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec,
6112 					       unused_tuple);
6113 		break;
6114 	case SCTP_V6_FLOW:
6115 	case TCP_V6_FLOW:
6116 	case UDP_V6_FLOW:
6117 		ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec,
6118 						  unused_tuple);
6119 		break;
6120 	case IPV6_USER_FLOW:
6121 		ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec,
6122 					       unused_tuple);
6123 		break;
6124 	case ETHER_FLOW:
6125 		if (hdev->fd_cfg.fd_mode !=
6126 			HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
6127 			dev_err(&hdev->pdev->dev,
6128 				"ETHER_FLOW is not supported in current fd mode!\n");
6129 			return -EOPNOTSUPP;
6130 		}
6131 
6132 		ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec,
6133 						 unused_tuple);
6134 		break;
6135 	default:
6136 		dev_err(&hdev->pdev->dev,
6137 			"unsupported protocol type, protocol type = %#x\n",
6138 			flow_type);
6139 		return -EOPNOTSUPP;
6140 	}
6141 
6142 	if (ret) {
6143 		dev_err(&hdev->pdev->dev,
6144 			"failed to check flow union tuple, ret = %d\n",
6145 			ret);
6146 		return ret;
6147 	}
6148 
6149 	return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple);
6150 }
6151 
6152 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs,
6153 				      struct hclge_fd_rule *rule, u8 ip_proto)
6154 {
6155 	rule->tuples.src_ip[IPV4_INDEX] =
6156 			be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
6157 	rule->tuples_mask.src_ip[IPV4_INDEX] =
6158 			be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
6159 
6160 	rule->tuples.dst_ip[IPV4_INDEX] =
6161 			be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
6162 	rule->tuples_mask.dst_ip[IPV4_INDEX] =
6163 			be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
6164 
6165 	rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
6166 	rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
6167 
6168 	rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
6169 	rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
6170 
6171 	rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
6172 	rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
6173 
6174 	rule->tuples.ether_proto = ETH_P_IP;
6175 	rule->tuples_mask.ether_proto = 0xFFFF;
6176 
6177 	rule->tuples.ip_proto = ip_proto;
6178 	rule->tuples_mask.ip_proto = 0xFF;
6179 }
6180 
6181 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs,
6182 				   struct hclge_fd_rule *rule)
6183 {
6184 	rule->tuples.src_ip[IPV4_INDEX] =
6185 			be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
6186 	rule->tuples_mask.src_ip[IPV4_INDEX] =
6187 			be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
6188 
6189 	rule->tuples.dst_ip[IPV4_INDEX] =
6190 			be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
6191 	rule->tuples_mask.dst_ip[IPV4_INDEX] =
6192 			be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
6193 
6194 	rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
6195 	rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
6196 
6197 	rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
6198 	rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
6199 
6200 	rule->tuples.ether_proto = ETH_P_IP;
6201 	rule->tuples_mask.ether_proto = 0xFFFF;
6202 }
6203 
6204 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs,
6205 				      struct hclge_fd_rule *rule, u8 ip_proto)
6206 {
6207 	be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src,
6208 			  IPV6_SIZE);
6209 	be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src,
6210 			  IPV6_SIZE);
6211 
6212 	be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst,
6213 			  IPV6_SIZE);
6214 	be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst,
6215 			  IPV6_SIZE);
6216 
6217 	rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
6218 	rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
6219 
6220 	rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
6221 	rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
6222 
6223 	rule->tuples.ether_proto = ETH_P_IPV6;
6224 	rule->tuples_mask.ether_proto = 0xFFFF;
6225 
6226 	rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6227 	rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6228 
6229 	rule->tuples.ip_proto = ip_proto;
6230 	rule->tuples_mask.ip_proto = 0xFF;
6231 }
6232 
6233 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs,
6234 				   struct hclge_fd_rule *rule)
6235 {
6236 	be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src,
6237 			  IPV6_SIZE);
6238 	be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src,
6239 			  IPV6_SIZE);
6240 
6241 	be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst,
6242 			  IPV6_SIZE);
6243 	be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst,
6244 			  IPV6_SIZE);
6245 
6246 	rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
6247 	rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
6248 
6249 	rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6250 	rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6251 
6252 	rule->tuples.ether_proto = ETH_P_IPV6;
6253 	rule->tuples_mask.ether_proto = 0xFFFF;
6254 }
6255 
6256 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs,
6257 				     struct hclge_fd_rule *rule)
6258 {
6259 	ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source);
6260 	ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source);
6261 
6262 	ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest);
6263 	ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest);
6264 
6265 	rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto);
6266 	rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto);
6267 }
6268 
6269 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info,
6270 					struct hclge_fd_rule *rule)
6271 {
6272 	switch (info->layer) {
6273 	case HCLGE_FD_USER_DEF_L2:
6274 		rule->tuples.l2_user_def = info->data;
6275 		rule->tuples_mask.l2_user_def = info->data_mask;
6276 		break;
6277 	case HCLGE_FD_USER_DEF_L3:
6278 		rule->tuples.l3_user_def = info->data;
6279 		rule->tuples_mask.l3_user_def = info->data_mask;
6280 		break;
6281 	case HCLGE_FD_USER_DEF_L4:
6282 		rule->tuples.l4_user_def = (u32)info->data << 16;
6283 		rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16;
6284 		break;
6285 	default:
6286 		break;
6287 	}
6288 
6289 	rule->ep.user_def = *info;
6290 }
6291 
6292 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs,
6293 			      struct hclge_fd_rule *rule,
6294 			      struct hclge_fd_user_def_info *info)
6295 {
6296 	u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6297 
6298 	switch (flow_type) {
6299 	case SCTP_V4_FLOW:
6300 		hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP);
6301 		break;
6302 	case TCP_V4_FLOW:
6303 		hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP);
6304 		break;
6305 	case UDP_V4_FLOW:
6306 		hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP);
6307 		break;
6308 	case IP_USER_FLOW:
6309 		hclge_fd_get_ip4_tuple(fs, rule);
6310 		break;
6311 	case SCTP_V6_FLOW:
6312 		hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP);
6313 		break;
6314 	case TCP_V6_FLOW:
6315 		hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP);
6316 		break;
6317 	case UDP_V6_FLOW:
6318 		hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP);
6319 		break;
6320 	case IPV6_USER_FLOW:
6321 		hclge_fd_get_ip6_tuple(fs, rule);
6322 		break;
6323 	case ETHER_FLOW:
6324 		hclge_fd_get_ether_tuple(fs, rule);
6325 		break;
6326 	default:
6327 		return -EOPNOTSUPP;
6328 	}
6329 
6330 	if (fs->flow_type & FLOW_EXT) {
6331 		rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
6332 		rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
6333 		hclge_fd_get_user_def_tuple(info, rule);
6334 	}
6335 
6336 	if (fs->flow_type & FLOW_MAC_EXT) {
6337 		ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
6338 		ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
6339 	}
6340 
6341 	return 0;
6342 }
6343 
6344 static int hclge_fd_config_rule(struct hclge_dev *hdev,
6345 				struct hclge_fd_rule *rule)
6346 {
6347 	int ret;
6348 
6349 	ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
6350 	if (ret)
6351 		return ret;
6352 
6353 	return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
6354 }
6355 
6356 static int hclge_add_fd_entry_common(struct hclge_dev *hdev,
6357 				     struct hclge_fd_rule *rule)
6358 {
6359 	int ret;
6360 
6361 	spin_lock_bh(&hdev->fd_rule_lock);
6362 
6363 	if (hdev->fd_active_type != rule->rule_type &&
6364 	    (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6365 	     hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) {
6366 		dev_err(&hdev->pdev->dev,
6367 			"mode conflict(new type %d, active type %d), please delete existent rules first\n",
6368 			rule->rule_type, hdev->fd_active_type);
6369 		spin_unlock_bh(&hdev->fd_rule_lock);
6370 		return -EINVAL;
6371 	}
6372 
6373 	ret = hclge_fd_check_user_def_refcnt(hdev, rule);
6374 	if (ret)
6375 		goto out;
6376 
6377 	ret = hclge_clear_arfs_rules(hdev);
6378 	if (ret)
6379 		goto out;
6380 
6381 	ret = hclge_fd_config_rule(hdev, rule);
6382 	if (ret)
6383 		goto out;
6384 
6385 	rule->state = HCLGE_FD_ACTIVE;
6386 	hdev->fd_active_type = rule->rule_type;
6387 	hclge_update_fd_list(hdev, rule->state, rule->location, rule);
6388 
6389 out:
6390 	spin_unlock_bh(&hdev->fd_rule_lock);
6391 	return ret;
6392 }
6393 
6394 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle)
6395 {
6396 	struct hclge_vport *vport = hclge_get_vport(handle);
6397 	struct hclge_dev *hdev = vport->back;
6398 
6399 	return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE;
6400 }
6401 
6402 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie,
6403 				      u16 *vport_id, u8 *action, u16 *queue_id)
6404 {
6405 	struct hclge_vport *vport = hdev->vport;
6406 
6407 	if (ring_cookie == RX_CLS_FLOW_DISC) {
6408 		*action = HCLGE_FD_ACTION_DROP_PACKET;
6409 	} else {
6410 		u32 ring = ethtool_get_flow_spec_ring(ring_cookie);
6411 		u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie);
6412 		u16 tqps;
6413 
6414 		/* To keep consistent with user's configuration, minus 1 when
6415 		 * printing 'vf', because vf id from ethtool is added 1 for vf.
6416 		 */
6417 		if (vf > hdev->num_req_vfs) {
6418 			dev_err(&hdev->pdev->dev,
6419 				"Error: vf id (%u) should be less than %u\n",
6420 				vf - 1U, hdev->num_req_vfs);
6421 			return -EINVAL;
6422 		}
6423 
6424 		*vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
6425 		tqps = hdev->vport[vf].nic.kinfo.num_tqps;
6426 
6427 		if (ring >= tqps) {
6428 			dev_err(&hdev->pdev->dev,
6429 				"Error: queue id (%u) > max tqp num (%u)\n",
6430 				ring, tqps - 1U);
6431 			return -EINVAL;
6432 		}
6433 
6434 		*action = HCLGE_FD_ACTION_SELECT_QUEUE;
6435 		*queue_id = ring;
6436 	}
6437 
6438 	return 0;
6439 }
6440 
6441 static int hclge_add_fd_entry(struct hnae3_handle *handle,
6442 			      struct ethtool_rxnfc *cmd)
6443 {
6444 	struct hclge_vport *vport = hclge_get_vport(handle);
6445 	struct hclge_dev *hdev = vport->back;
6446 	struct hclge_fd_user_def_info info;
6447 	u16 dst_vport_id = 0, q_index = 0;
6448 	struct ethtool_rx_flow_spec *fs;
6449 	struct hclge_fd_rule *rule;
6450 	u32 unused = 0;
6451 	u8 action;
6452 	int ret;
6453 
6454 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
6455 		dev_err(&hdev->pdev->dev,
6456 			"flow table director is not supported\n");
6457 		return -EOPNOTSUPP;
6458 	}
6459 
6460 	if (!hdev->fd_en) {
6461 		dev_err(&hdev->pdev->dev,
6462 			"please enable flow director first\n");
6463 		return -EOPNOTSUPP;
6464 	}
6465 
6466 	fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6467 
6468 	ret = hclge_fd_check_spec(hdev, fs, &unused, &info);
6469 	if (ret)
6470 		return ret;
6471 
6472 	ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id,
6473 					 &action, &q_index);
6474 	if (ret)
6475 		return ret;
6476 
6477 	rule = kzalloc(sizeof(*rule), GFP_KERNEL);
6478 	if (!rule)
6479 		return -ENOMEM;
6480 
6481 	ret = hclge_fd_get_tuple(fs, rule, &info);
6482 	if (ret) {
6483 		kfree(rule);
6484 		return ret;
6485 	}
6486 
6487 	rule->flow_type = fs->flow_type;
6488 	rule->location = fs->location;
6489 	rule->unused_tuple = unused;
6490 	rule->vf_id = dst_vport_id;
6491 	rule->queue_id = q_index;
6492 	rule->action = action;
6493 	rule->rule_type = HCLGE_FD_EP_ACTIVE;
6494 
6495 	ret = hclge_add_fd_entry_common(hdev, rule);
6496 	if (ret)
6497 		kfree(rule);
6498 
6499 	return ret;
6500 }
6501 
6502 static int hclge_del_fd_entry(struct hnae3_handle *handle,
6503 			      struct ethtool_rxnfc *cmd)
6504 {
6505 	struct hclge_vport *vport = hclge_get_vport(handle);
6506 	struct hclge_dev *hdev = vport->back;
6507 	struct ethtool_rx_flow_spec *fs;
6508 	int ret;
6509 
6510 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6511 		return -EOPNOTSUPP;
6512 
6513 	fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6514 
6515 	if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6516 		return -EINVAL;
6517 
6518 	spin_lock_bh(&hdev->fd_rule_lock);
6519 	if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6520 	    !test_bit(fs->location, hdev->fd_bmap)) {
6521 		dev_err(&hdev->pdev->dev,
6522 			"Delete fail, rule %u is inexistent\n", fs->location);
6523 		spin_unlock_bh(&hdev->fd_rule_lock);
6524 		return -ENOENT;
6525 	}
6526 
6527 	ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location,
6528 				   NULL, false);
6529 	if (ret)
6530 		goto out;
6531 
6532 	hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL);
6533 
6534 out:
6535 	spin_unlock_bh(&hdev->fd_rule_lock);
6536 	return ret;
6537 }
6538 
6539 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev,
6540 					 bool clear_list)
6541 {
6542 	struct hclge_fd_rule *rule;
6543 	struct hlist_node *node;
6544 	u16 location;
6545 
6546 	spin_lock_bh(&hdev->fd_rule_lock);
6547 
6548 	for_each_set_bit(location, hdev->fd_bmap,
6549 			 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6550 		hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location,
6551 				     NULL, false);
6552 
6553 	if (clear_list) {
6554 		hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
6555 					  rule_node) {
6556 			hlist_del(&rule->rule_node);
6557 			kfree(rule);
6558 		}
6559 		hdev->fd_active_type = HCLGE_FD_RULE_NONE;
6560 		hdev->hclge_fd_rule_num = 0;
6561 		bitmap_zero(hdev->fd_bmap,
6562 			    hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
6563 	}
6564 
6565 	spin_unlock_bh(&hdev->fd_rule_lock);
6566 }
6567 
6568 static void hclge_del_all_fd_entries(struct hclge_dev *hdev)
6569 {
6570 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6571 		return;
6572 
6573 	hclge_clear_fd_rules_in_list(hdev, true);
6574 	hclge_fd_disable_user_def(hdev);
6575 }
6576 
6577 static int hclge_restore_fd_entries(struct hnae3_handle *handle)
6578 {
6579 	struct hclge_vport *vport = hclge_get_vport(handle);
6580 	struct hclge_dev *hdev = vport->back;
6581 	struct hclge_fd_rule *rule;
6582 	struct hlist_node *node;
6583 
6584 	/* Return ok here, because reset error handling will check this
6585 	 * return value. If error is returned here, the reset process will
6586 	 * fail.
6587 	 */
6588 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6589 		return 0;
6590 
6591 	/* if fd is disabled, should not restore it when reset */
6592 	if (!hdev->fd_en)
6593 		return 0;
6594 
6595 	spin_lock_bh(&hdev->fd_rule_lock);
6596 	hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6597 		if (rule->state == HCLGE_FD_ACTIVE)
6598 			rule->state = HCLGE_FD_TO_ADD;
6599 	}
6600 	spin_unlock_bh(&hdev->fd_rule_lock);
6601 	set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
6602 
6603 	return 0;
6604 }
6605 
6606 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
6607 				 struct ethtool_rxnfc *cmd)
6608 {
6609 	struct hclge_vport *vport = hclge_get_vport(handle);
6610 	struct hclge_dev *hdev = vport->back;
6611 
6612 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle))
6613 		return -EOPNOTSUPP;
6614 
6615 	cmd->rule_cnt = hdev->hclge_fd_rule_num;
6616 	cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
6617 
6618 	return 0;
6619 }
6620 
6621 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule,
6622 				     struct ethtool_tcpip4_spec *spec,
6623 				     struct ethtool_tcpip4_spec *spec_mask)
6624 {
6625 	spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6626 	spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6627 			0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6628 
6629 	spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6630 	spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6631 			0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6632 
6633 	spec->psrc = cpu_to_be16(rule->tuples.src_port);
6634 	spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6635 			0 : cpu_to_be16(rule->tuples_mask.src_port);
6636 
6637 	spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6638 	spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6639 			0 : cpu_to_be16(rule->tuples_mask.dst_port);
6640 
6641 	spec->tos = rule->tuples.ip_tos;
6642 	spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6643 			0 : rule->tuples_mask.ip_tos;
6644 }
6645 
6646 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule,
6647 				  struct ethtool_usrip4_spec *spec,
6648 				  struct ethtool_usrip4_spec *spec_mask)
6649 {
6650 	spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6651 	spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6652 			0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6653 
6654 	spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6655 	spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6656 			0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6657 
6658 	spec->tos = rule->tuples.ip_tos;
6659 	spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6660 			0 : rule->tuples_mask.ip_tos;
6661 
6662 	spec->proto = rule->tuples.ip_proto;
6663 	spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6664 			0 : rule->tuples_mask.ip_proto;
6665 
6666 	spec->ip_ver = ETH_RX_NFC_IP4;
6667 }
6668 
6669 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule,
6670 				     struct ethtool_tcpip6_spec *spec,
6671 				     struct ethtool_tcpip6_spec *spec_mask)
6672 {
6673 	cpu_to_be32_array(spec->ip6src,
6674 			  rule->tuples.src_ip, IPV6_SIZE);
6675 	cpu_to_be32_array(spec->ip6dst,
6676 			  rule->tuples.dst_ip, IPV6_SIZE);
6677 	if (rule->unused_tuple & BIT(INNER_SRC_IP))
6678 		memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6679 	else
6680 		cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip,
6681 				  IPV6_SIZE);
6682 
6683 	if (rule->unused_tuple & BIT(INNER_DST_IP))
6684 		memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6685 	else
6686 		cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip,
6687 				  IPV6_SIZE);
6688 
6689 	spec->tclass = rule->tuples.ip_tos;
6690 	spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6691 			0 : rule->tuples_mask.ip_tos;
6692 
6693 	spec->psrc = cpu_to_be16(rule->tuples.src_port);
6694 	spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6695 			0 : cpu_to_be16(rule->tuples_mask.src_port);
6696 
6697 	spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6698 	spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6699 			0 : cpu_to_be16(rule->tuples_mask.dst_port);
6700 }
6701 
6702 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule,
6703 				  struct ethtool_usrip6_spec *spec,
6704 				  struct ethtool_usrip6_spec *spec_mask)
6705 {
6706 	cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE);
6707 	cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE);
6708 	if (rule->unused_tuple & BIT(INNER_SRC_IP))
6709 		memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6710 	else
6711 		cpu_to_be32_array(spec_mask->ip6src,
6712 				  rule->tuples_mask.src_ip, IPV6_SIZE);
6713 
6714 	if (rule->unused_tuple & BIT(INNER_DST_IP))
6715 		memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6716 	else
6717 		cpu_to_be32_array(spec_mask->ip6dst,
6718 				  rule->tuples_mask.dst_ip, IPV6_SIZE);
6719 
6720 	spec->tclass = rule->tuples.ip_tos;
6721 	spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6722 			0 : rule->tuples_mask.ip_tos;
6723 
6724 	spec->l4_proto = rule->tuples.ip_proto;
6725 	spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6726 			0 : rule->tuples_mask.ip_proto;
6727 }
6728 
6729 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule,
6730 				    struct ethhdr *spec,
6731 				    struct ethhdr *spec_mask)
6732 {
6733 	ether_addr_copy(spec->h_source, rule->tuples.src_mac);
6734 	ether_addr_copy(spec->h_dest, rule->tuples.dst_mac);
6735 
6736 	if (rule->unused_tuple & BIT(INNER_SRC_MAC))
6737 		eth_zero_addr(spec_mask->h_source);
6738 	else
6739 		ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac);
6740 
6741 	if (rule->unused_tuple & BIT(INNER_DST_MAC))
6742 		eth_zero_addr(spec_mask->h_dest);
6743 	else
6744 		ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac);
6745 
6746 	spec->h_proto = cpu_to_be16(rule->tuples.ether_proto);
6747 	spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
6748 			0 : cpu_to_be16(rule->tuples_mask.ether_proto);
6749 }
6750 
6751 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs,
6752 				       struct hclge_fd_rule *rule)
6753 {
6754 	if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) ==
6755 	    HCLGE_FD_TUPLE_USER_DEF_TUPLES) {
6756 		fs->h_ext.data[0] = 0;
6757 		fs->h_ext.data[1] = 0;
6758 		fs->m_ext.data[0] = 0;
6759 		fs->m_ext.data[1] = 0;
6760 	} else {
6761 		fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset);
6762 		fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data);
6763 		fs->m_ext.data[0] =
6764 				cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK);
6765 		fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask);
6766 	}
6767 }
6768 
6769 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs,
6770 				  struct hclge_fd_rule *rule)
6771 {
6772 	if (fs->flow_type & FLOW_EXT) {
6773 		fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
6774 		fs->m_ext.vlan_tci =
6775 				rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
6776 				0 : cpu_to_be16(rule->tuples_mask.vlan_tag1);
6777 
6778 		hclge_fd_get_user_def_info(fs, rule);
6779 	}
6780 
6781 	if (fs->flow_type & FLOW_MAC_EXT) {
6782 		ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
6783 		if (rule->unused_tuple & BIT(INNER_DST_MAC))
6784 			eth_zero_addr(fs->m_u.ether_spec.h_dest);
6785 		else
6786 			ether_addr_copy(fs->m_u.ether_spec.h_dest,
6787 					rule->tuples_mask.dst_mac);
6788 	}
6789 }
6790 
6791 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev,
6792 					       u16 location)
6793 {
6794 	struct hclge_fd_rule *rule = NULL;
6795 	struct hlist_node *node2;
6796 
6797 	hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
6798 		if (rule->location == location)
6799 			return rule;
6800 		else if (rule->location > location)
6801 			return NULL;
6802 	}
6803 
6804 	return NULL;
6805 }
6806 
6807 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs,
6808 				     struct hclge_fd_rule *rule)
6809 {
6810 	if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
6811 		fs->ring_cookie = RX_CLS_FLOW_DISC;
6812 	} else {
6813 		u64 vf_id;
6814 
6815 		fs->ring_cookie = rule->queue_id;
6816 		vf_id = rule->vf_id;
6817 		vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
6818 		fs->ring_cookie |= vf_id;
6819 	}
6820 }
6821 
6822 static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
6823 				  struct ethtool_rxnfc *cmd)
6824 {
6825 	struct hclge_vport *vport = hclge_get_vport(handle);
6826 	struct hclge_fd_rule *rule = NULL;
6827 	struct hclge_dev *hdev = vport->back;
6828 	struct ethtool_rx_flow_spec *fs;
6829 
6830 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6831 		return -EOPNOTSUPP;
6832 
6833 	fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6834 
6835 	spin_lock_bh(&hdev->fd_rule_lock);
6836 
6837 	rule = hclge_get_fd_rule(hdev, fs->location);
6838 	if (!rule) {
6839 		spin_unlock_bh(&hdev->fd_rule_lock);
6840 		return -ENOENT;
6841 	}
6842 
6843 	fs->flow_type = rule->flow_type;
6844 	switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
6845 	case SCTP_V4_FLOW:
6846 	case TCP_V4_FLOW:
6847 	case UDP_V4_FLOW:
6848 		hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec,
6849 					 &fs->m_u.tcp_ip4_spec);
6850 		break;
6851 	case IP_USER_FLOW:
6852 		hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec,
6853 				      &fs->m_u.usr_ip4_spec);
6854 		break;
6855 	case SCTP_V6_FLOW:
6856 	case TCP_V6_FLOW:
6857 	case UDP_V6_FLOW:
6858 		hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec,
6859 					 &fs->m_u.tcp_ip6_spec);
6860 		break;
6861 	case IPV6_USER_FLOW:
6862 		hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec,
6863 				      &fs->m_u.usr_ip6_spec);
6864 		break;
6865 	/* The flow type of fd rule has been checked before adding in to rule
6866 	 * list. As other flow types have been handled, it must be ETHER_FLOW
6867 	 * for the default case
6868 	 */
6869 	default:
6870 		hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec,
6871 					&fs->m_u.ether_spec);
6872 		break;
6873 	}
6874 
6875 	hclge_fd_get_ext_info(fs, rule);
6876 
6877 	hclge_fd_get_ring_cookie(fs, rule);
6878 
6879 	spin_unlock_bh(&hdev->fd_rule_lock);
6880 
6881 	return 0;
6882 }
6883 
6884 static int hclge_get_all_rules(struct hnae3_handle *handle,
6885 			       struct ethtool_rxnfc *cmd, u32 *rule_locs)
6886 {
6887 	struct hclge_vport *vport = hclge_get_vport(handle);
6888 	struct hclge_dev *hdev = vport->back;
6889 	struct hclge_fd_rule *rule;
6890 	struct hlist_node *node2;
6891 	int cnt = 0;
6892 
6893 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6894 		return -EOPNOTSUPP;
6895 
6896 	cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
6897 
6898 	spin_lock_bh(&hdev->fd_rule_lock);
6899 	hlist_for_each_entry_safe(rule, node2,
6900 				  &hdev->fd_rule_list, rule_node) {
6901 		if (cnt == cmd->rule_cnt) {
6902 			spin_unlock_bh(&hdev->fd_rule_lock);
6903 			return -EMSGSIZE;
6904 		}
6905 
6906 		if (rule->state == HCLGE_FD_TO_DEL)
6907 			continue;
6908 
6909 		rule_locs[cnt] = rule->location;
6910 		cnt++;
6911 	}
6912 
6913 	spin_unlock_bh(&hdev->fd_rule_lock);
6914 
6915 	cmd->rule_cnt = cnt;
6916 
6917 	return 0;
6918 }
6919 
6920 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys,
6921 				     struct hclge_fd_rule_tuples *tuples)
6922 {
6923 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32
6924 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32
6925 
6926 	tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto);
6927 	tuples->ip_proto = fkeys->basic.ip_proto;
6928 	tuples->dst_port = be16_to_cpu(fkeys->ports.dst);
6929 
6930 	if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
6931 		tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src);
6932 		tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst);
6933 	} else {
6934 		int i;
6935 
6936 		for (i = 0; i < IPV6_SIZE; i++) {
6937 			tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]);
6938 			tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]);
6939 		}
6940 	}
6941 }
6942 
6943 /* traverse all rules, check whether an existed rule has the same tuples */
6944 static struct hclge_fd_rule *
6945 hclge_fd_search_flow_keys(struct hclge_dev *hdev,
6946 			  const struct hclge_fd_rule_tuples *tuples)
6947 {
6948 	struct hclge_fd_rule *rule = NULL;
6949 	struct hlist_node *node;
6950 
6951 	hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6952 		if (!memcmp(tuples, &rule->tuples, sizeof(*tuples)))
6953 			return rule;
6954 	}
6955 
6956 	return NULL;
6957 }
6958 
6959 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples,
6960 				     struct hclge_fd_rule *rule)
6961 {
6962 	rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
6963 			     BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) |
6964 			     BIT(INNER_SRC_PORT);
6965 	rule->action = 0;
6966 	rule->vf_id = 0;
6967 	rule->rule_type = HCLGE_FD_ARFS_ACTIVE;
6968 	rule->state = HCLGE_FD_TO_ADD;
6969 	if (tuples->ether_proto == ETH_P_IP) {
6970 		if (tuples->ip_proto == IPPROTO_TCP)
6971 			rule->flow_type = TCP_V4_FLOW;
6972 		else
6973 			rule->flow_type = UDP_V4_FLOW;
6974 	} else {
6975 		if (tuples->ip_proto == IPPROTO_TCP)
6976 			rule->flow_type = TCP_V6_FLOW;
6977 		else
6978 			rule->flow_type = UDP_V6_FLOW;
6979 	}
6980 	memcpy(&rule->tuples, tuples, sizeof(rule->tuples));
6981 	memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask));
6982 }
6983 
6984 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id,
6985 				      u16 flow_id, struct flow_keys *fkeys)
6986 {
6987 	struct hclge_vport *vport = hclge_get_vport(handle);
6988 	struct hclge_fd_rule_tuples new_tuples = {};
6989 	struct hclge_dev *hdev = vport->back;
6990 	struct hclge_fd_rule *rule;
6991 	u16 bit_id;
6992 
6993 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6994 		return -EOPNOTSUPP;
6995 
6996 	/* when there is already fd rule existed add by user,
6997 	 * arfs should not work
6998 	 */
6999 	spin_lock_bh(&hdev->fd_rule_lock);
7000 	if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE &&
7001 	    hdev->fd_active_type != HCLGE_FD_RULE_NONE) {
7002 		spin_unlock_bh(&hdev->fd_rule_lock);
7003 		return -EOPNOTSUPP;
7004 	}
7005 
7006 	hclge_fd_get_flow_tuples(fkeys, &new_tuples);
7007 
7008 	/* check is there flow director filter existed for this flow,
7009 	 * if not, create a new filter for it;
7010 	 * if filter exist with different queue id, modify the filter;
7011 	 * if filter exist with same queue id, do nothing
7012 	 */
7013 	rule = hclge_fd_search_flow_keys(hdev, &new_tuples);
7014 	if (!rule) {
7015 		bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM);
7016 		if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
7017 			spin_unlock_bh(&hdev->fd_rule_lock);
7018 			return -ENOSPC;
7019 		}
7020 
7021 		rule = kzalloc(sizeof(*rule), GFP_ATOMIC);
7022 		if (!rule) {
7023 			spin_unlock_bh(&hdev->fd_rule_lock);
7024 			return -ENOMEM;
7025 		}
7026 
7027 		rule->location = bit_id;
7028 		rule->arfs.flow_id = flow_id;
7029 		rule->queue_id = queue_id;
7030 		hclge_fd_build_arfs_rule(&new_tuples, rule);
7031 		hclge_update_fd_list(hdev, rule->state, rule->location, rule);
7032 		hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE;
7033 	} else if (rule->queue_id != queue_id) {
7034 		rule->queue_id = queue_id;
7035 		rule->state = HCLGE_FD_TO_ADD;
7036 		set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7037 		hclge_task_schedule(hdev, 0);
7038 	}
7039 	spin_unlock_bh(&hdev->fd_rule_lock);
7040 	return rule->location;
7041 }
7042 
7043 static void hclge_rfs_filter_expire(struct hclge_dev *hdev)
7044 {
7045 #ifdef CONFIG_RFS_ACCEL
7046 	struct hnae3_handle *handle = &hdev->vport[0].nic;
7047 	struct hclge_fd_rule *rule;
7048 	struct hlist_node *node;
7049 
7050 	spin_lock_bh(&hdev->fd_rule_lock);
7051 	if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) {
7052 		spin_unlock_bh(&hdev->fd_rule_lock);
7053 		return;
7054 	}
7055 	hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7056 		if (rule->state != HCLGE_FD_ACTIVE)
7057 			continue;
7058 		if (rps_may_expire_flow(handle->netdev, rule->queue_id,
7059 					rule->arfs.flow_id, rule->location)) {
7060 			rule->state = HCLGE_FD_TO_DEL;
7061 			set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7062 		}
7063 	}
7064 	spin_unlock_bh(&hdev->fd_rule_lock);
7065 #endif
7066 }
7067 
7068 /* make sure being called after lock up with fd_rule_lock */
7069 static int hclge_clear_arfs_rules(struct hclge_dev *hdev)
7070 {
7071 #ifdef CONFIG_RFS_ACCEL
7072 	struct hclge_fd_rule *rule;
7073 	struct hlist_node *node;
7074 	int ret;
7075 
7076 	if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE)
7077 		return 0;
7078 
7079 	hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7080 		switch (rule->state) {
7081 		case HCLGE_FD_TO_DEL:
7082 		case HCLGE_FD_ACTIVE:
7083 			ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
7084 						   rule->location, NULL, false);
7085 			if (ret)
7086 				return ret;
7087 			fallthrough;
7088 		case HCLGE_FD_TO_ADD:
7089 			hclge_fd_dec_rule_cnt(hdev, rule->location);
7090 			hlist_del(&rule->rule_node);
7091 			kfree(rule);
7092 			break;
7093 		default:
7094 			break;
7095 		}
7096 	}
7097 	hclge_sync_fd_state(hdev);
7098 
7099 #endif
7100 	return 0;
7101 }
7102 
7103 static void hclge_get_cls_key_basic(const struct flow_rule *flow,
7104 				    struct hclge_fd_rule *rule)
7105 {
7106 	if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) {
7107 		struct flow_match_basic match;
7108 		u16 ethtype_key, ethtype_mask;
7109 
7110 		flow_rule_match_basic(flow, &match);
7111 		ethtype_key = ntohs(match.key->n_proto);
7112 		ethtype_mask = ntohs(match.mask->n_proto);
7113 
7114 		if (ethtype_key == ETH_P_ALL) {
7115 			ethtype_key = 0;
7116 			ethtype_mask = 0;
7117 		}
7118 		rule->tuples.ether_proto = ethtype_key;
7119 		rule->tuples_mask.ether_proto = ethtype_mask;
7120 		rule->tuples.ip_proto = match.key->ip_proto;
7121 		rule->tuples_mask.ip_proto = match.mask->ip_proto;
7122 	} else {
7123 		rule->unused_tuple |= BIT(INNER_IP_PROTO);
7124 		rule->unused_tuple |= BIT(INNER_ETH_TYPE);
7125 	}
7126 }
7127 
7128 static void hclge_get_cls_key_mac(const struct flow_rule *flow,
7129 				  struct hclge_fd_rule *rule)
7130 {
7131 	if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
7132 		struct flow_match_eth_addrs match;
7133 
7134 		flow_rule_match_eth_addrs(flow, &match);
7135 		ether_addr_copy(rule->tuples.dst_mac, match.key->dst);
7136 		ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst);
7137 		ether_addr_copy(rule->tuples.src_mac, match.key->src);
7138 		ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src);
7139 	} else {
7140 		rule->unused_tuple |= BIT(INNER_DST_MAC);
7141 		rule->unused_tuple |= BIT(INNER_SRC_MAC);
7142 	}
7143 }
7144 
7145 static void hclge_get_cls_key_vlan(const struct flow_rule *flow,
7146 				   struct hclge_fd_rule *rule)
7147 {
7148 	if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) {
7149 		struct flow_match_vlan match;
7150 
7151 		flow_rule_match_vlan(flow, &match);
7152 		rule->tuples.vlan_tag1 = match.key->vlan_id |
7153 				(match.key->vlan_priority << VLAN_PRIO_SHIFT);
7154 		rule->tuples_mask.vlan_tag1 = match.mask->vlan_id |
7155 				(match.mask->vlan_priority << VLAN_PRIO_SHIFT);
7156 	} else {
7157 		rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST);
7158 	}
7159 }
7160 
7161 static void hclge_get_cls_key_ip(const struct flow_rule *flow,
7162 				 struct hclge_fd_rule *rule)
7163 {
7164 	u16 addr_type = 0;
7165 
7166 	if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) {
7167 		struct flow_match_control match;
7168 
7169 		flow_rule_match_control(flow, &match);
7170 		addr_type = match.key->addr_type;
7171 	}
7172 
7173 	if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
7174 		struct flow_match_ipv4_addrs match;
7175 
7176 		flow_rule_match_ipv4_addrs(flow, &match);
7177 		rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src);
7178 		rule->tuples_mask.src_ip[IPV4_INDEX] =
7179 						be32_to_cpu(match.mask->src);
7180 		rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst);
7181 		rule->tuples_mask.dst_ip[IPV4_INDEX] =
7182 						be32_to_cpu(match.mask->dst);
7183 	} else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
7184 		struct flow_match_ipv6_addrs match;
7185 
7186 		flow_rule_match_ipv6_addrs(flow, &match);
7187 		be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32,
7188 				  IPV6_SIZE);
7189 		be32_to_cpu_array(rule->tuples_mask.src_ip,
7190 				  match.mask->src.s6_addr32, IPV6_SIZE);
7191 		be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32,
7192 				  IPV6_SIZE);
7193 		be32_to_cpu_array(rule->tuples_mask.dst_ip,
7194 				  match.mask->dst.s6_addr32, IPV6_SIZE);
7195 	} else {
7196 		rule->unused_tuple |= BIT(INNER_SRC_IP);
7197 		rule->unused_tuple |= BIT(INNER_DST_IP);
7198 	}
7199 }
7200 
7201 static void hclge_get_cls_key_port(const struct flow_rule *flow,
7202 				   struct hclge_fd_rule *rule)
7203 {
7204 	if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) {
7205 		struct flow_match_ports match;
7206 
7207 		flow_rule_match_ports(flow, &match);
7208 
7209 		rule->tuples.src_port = be16_to_cpu(match.key->src);
7210 		rule->tuples_mask.src_port = be16_to_cpu(match.mask->src);
7211 		rule->tuples.dst_port = be16_to_cpu(match.key->dst);
7212 		rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst);
7213 	} else {
7214 		rule->unused_tuple |= BIT(INNER_SRC_PORT);
7215 		rule->unused_tuple |= BIT(INNER_DST_PORT);
7216 	}
7217 }
7218 
7219 static int hclge_parse_cls_flower(struct hclge_dev *hdev,
7220 				  struct flow_cls_offload *cls_flower,
7221 				  struct hclge_fd_rule *rule)
7222 {
7223 	struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower);
7224 	struct flow_dissector *dissector = flow->match.dissector;
7225 
7226 	if (dissector->used_keys &
7227 	    ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
7228 	      BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
7229 	      BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
7230 	      BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
7231 	      BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
7232 	      BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
7233 	      BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) {
7234 		dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n",
7235 			dissector->used_keys);
7236 		return -EOPNOTSUPP;
7237 	}
7238 
7239 	hclge_get_cls_key_basic(flow, rule);
7240 	hclge_get_cls_key_mac(flow, rule);
7241 	hclge_get_cls_key_vlan(flow, rule);
7242 	hclge_get_cls_key_ip(flow, rule);
7243 	hclge_get_cls_key_port(flow, rule);
7244 
7245 	return 0;
7246 }
7247 
7248 static int hclge_check_cls_flower(struct hclge_dev *hdev,
7249 				  struct flow_cls_offload *cls_flower, int tc)
7250 {
7251 	u32 prio = cls_flower->common.prio;
7252 
7253 	if (tc < 0 || tc > hdev->tc_max) {
7254 		dev_err(&hdev->pdev->dev, "invalid traffic class\n");
7255 		return -EINVAL;
7256 	}
7257 
7258 	if (prio == 0 ||
7259 	    prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
7260 		dev_err(&hdev->pdev->dev,
7261 			"prio %u should be in range[1, %u]\n",
7262 			prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
7263 		return -EINVAL;
7264 	}
7265 
7266 	if (test_bit(prio - 1, hdev->fd_bmap)) {
7267 		dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio);
7268 		return -EINVAL;
7269 	}
7270 	return 0;
7271 }
7272 
7273 static int hclge_add_cls_flower(struct hnae3_handle *handle,
7274 				struct flow_cls_offload *cls_flower,
7275 				int tc)
7276 {
7277 	struct hclge_vport *vport = hclge_get_vport(handle);
7278 	struct hclge_dev *hdev = vport->back;
7279 	struct hclge_fd_rule *rule;
7280 	int ret;
7281 
7282 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
7283 		dev_err(&hdev->pdev->dev,
7284 			"cls flower is not supported\n");
7285 		return -EOPNOTSUPP;
7286 	}
7287 
7288 	ret = hclge_check_cls_flower(hdev, cls_flower, tc);
7289 	if (ret) {
7290 		dev_err(&hdev->pdev->dev,
7291 			"failed to check cls flower params, ret = %d\n", ret);
7292 		return ret;
7293 	}
7294 
7295 	rule = kzalloc(sizeof(*rule), GFP_KERNEL);
7296 	if (!rule)
7297 		return -ENOMEM;
7298 
7299 	ret = hclge_parse_cls_flower(hdev, cls_flower, rule);
7300 	if (ret) {
7301 		kfree(rule);
7302 		return ret;
7303 	}
7304 
7305 	rule->action = HCLGE_FD_ACTION_SELECT_TC;
7306 	rule->cls_flower.tc = tc;
7307 	rule->location = cls_flower->common.prio - 1;
7308 	rule->vf_id = 0;
7309 	rule->cls_flower.cookie = cls_flower->cookie;
7310 	rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE;
7311 
7312 	ret = hclge_add_fd_entry_common(hdev, rule);
7313 	if (ret)
7314 		kfree(rule);
7315 
7316 	return ret;
7317 }
7318 
7319 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev,
7320 						   unsigned long cookie)
7321 {
7322 	struct hclge_fd_rule *rule;
7323 	struct hlist_node *node;
7324 
7325 	hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7326 		if (rule->cls_flower.cookie == cookie)
7327 			return rule;
7328 	}
7329 
7330 	return NULL;
7331 }
7332 
7333 static int hclge_del_cls_flower(struct hnae3_handle *handle,
7334 				struct flow_cls_offload *cls_flower)
7335 {
7336 	struct hclge_vport *vport = hclge_get_vport(handle);
7337 	struct hclge_dev *hdev = vport->back;
7338 	struct hclge_fd_rule *rule;
7339 	int ret;
7340 
7341 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7342 		return -EOPNOTSUPP;
7343 
7344 	spin_lock_bh(&hdev->fd_rule_lock);
7345 
7346 	rule = hclge_find_cls_flower(hdev, cls_flower->cookie);
7347 	if (!rule) {
7348 		spin_unlock_bh(&hdev->fd_rule_lock);
7349 		return -EINVAL;
7350 	}
7351 
7352 	ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location,
7353 				   NULL, false);
7354 	if (ret) {
7355 		/* if tcam config fail, set rule state to TO_DEL,
7356 		 * so the rule will be deleted when periodic
7357 		 * task being scheduled.
7358 		 */
7359 		hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL);
7360 		set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7361 		spin_unlock_bh(&hdev->fd_rule_lock);
7362 		return ret;
7363 	}
7364 
7365 	hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL);
7366 	spin_unlock_bh(&hdev->fd_rule_lock);
7367 
7368 	return 0;
7369 }
7370 
7371 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist)
7372 {
7373 	struct hclge_fd_rule *rule;
7374 	struct hlist_node *node;
7375 	int ret = 0;
7376 
7377 	if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state))
7378 		return;
7379 
7380 	spin_lock_bh(&hdev->fd_rule_lock);
7381 
7382 	hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
7383 		switch (rule->state) {
7384 		case HCLGE_FD_TO_ADD:
7385 			ret = hclge_fd_config_rule(hdev, rule);
7386 			if (ret)
7387 				goto out;
7388 			rule->state = HCLGE_FD_ACTIVE;
7389 			break;
7390 		case HCLGE_FD_TO_DEL:
7391 			ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
7392 						   rule->location, NULL, false);
7393 			if (ret)
7394 				goto out;
7395 			hclge_fd_dec_rule_cnt(hdev, rule->location);
7396 			hclge_fd_free_node(hdev, rule);
7397 			break;
7398 		default:
7399 			break;
7400 		}
7401 	}
7402 
7403 out:
7404 	if (ret)
7405 		set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7406 
7407 	spin_unlock_bh(&hdev->fd_rule_lock);
7408 }
7409 
7410 static void hclge_sync_fd_table(struct hclge_dev *hdev)
7411 {
7412 	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7413 		return;
7414 
7415 	if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) {
7416 		bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE;
7417 
7418 		hclge_clear_fd_rules_in_list(hdev, clear_list);
7419 	}
7420 
7421 	hclge_sync_fd_user_def_cfg(hdev, false);
7422 
7423 	hclge_sync_fd_list(hdev, &hdev->fd_rule_list);
7424 }
7425 
7426 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
7427 {
7428 	struct hclge_vport *vport = hclge_get_vport(handle);
7429 	struct hclge_dev *hdev = vport->back;
7430 
7431 	return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
7432 	       hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
7433 }
7434 
7435 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle)
7436 {
7437 	struct hclge_vport *vport = hclge_get_vport(handle);
7438 	struct hclge_dev *hdev = vport->back;
7439 
7440 	return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
7441 }
7442 
7443 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
7444 {
7445 	struct hclge_vport *vport = hclge_get_vport(handle);
7446 	struct hclge_dev *hdev = vport->back;
7447 
7448 	return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
7449 }
7450 
7451 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
7452 {
7453 	struct hclge_vport *vport = hclge_get_vport(handle);
7454 	struct hclge_dev *hdev = vport->back;
7455 
7456 	return hdev->rst_stats.hw_reset_done_cnt;
7457 }
7458 
7459 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
7460 {
7461 	struct hclge_vport *vport = hclge_get_vport(handle);
7462 	struct hclge_dev *hdev = vport->back;
7463 
7464 	hdev->fd_en = enable;
7465 
7466 	if (!enable)
7467 		set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state);
7468 	else
7469 		hclge_restore_fd_entries(handle);
7470 
7471 	hclge_task_schedule(hdev, 0);
7472 }
7473 
7474 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
7475 {
7476 #define HCLGE_LINK_STATUS_WAIT_CNT  3
7477 
7478 	struct hclge_desc desc;
7479 	struct hclge_config_mac_mode_cmd *req =
7480 		(struct hclge_config_mac_mode_cmd *)desc.data;
7481 	u32 loop_en = 0;
7482 	int ret;
7483 
7484 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
7485 
7486 	if (enable) {
7487 		hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U);
7488 		hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U);
7489 		hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U);
7490 		hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U);
7491 		hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U);
7492 		hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U);
7493 		hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U);
7494 		hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U);
7495 		hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U);
7496 		hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U);
7497 	}
7498 
7499 	req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7500 
7501 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7502 	if (ret) {
7503 		dev_err(&hdev->pdev->dev,
7504 			"mac enable fail, ret =%d.\n", ret);
7505 		return;
7506 	}
7507 
7508 	if (!enable)
7509 		hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN,
7510 					   HCLGE_LINK_STATUS_WAIT_CNT);
7511 }
7512 
7513 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid,
7514 				     u8 switch_param, u8 param_mask)
7515 {
7516 	struct hclge_mac_vlan_switch_cmd *req;
7517 	struct hclge_desc desc;
7518 	u32 func_id;
7519 	int ret;
7520 
7521 	func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0);
7522 	req = (struct hclge_mac_vlan_switch_cmd *)desc.data;
7523 
7524 	/* read current config parameter */
7525 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM,
7526 				   true);
7527 	req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL;
7528 	req->func_id = cpu_to_le32(func_id);
7529 
7530 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7531 	if (ret) {
7532 		dev_err(&hdev->pdev->dev,
7533 			"read mac vlan switch parameter fail, ret = %d\n", ret);
7534 		return ret;
7535 	}
7536 
7537 	/* modify and write new config parameter */
7538 	hclge_comm_cmd_reuse_desc(&desc, false);
7539 	req->switch_param = (req->switch_param & param_mask) | switch_param;
7540 	req->param_mask = param_mask;
7541 
7542 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7543 	if (ret)
7544 		dev_err(&hdev->pdev->dev,
7545 			"set mac vlan switch parameter fail, ret = %d\n", ret);
7546 	return ret;
7547 }
7548 
7549 static void hclge_phy_link_status_wait(struct hclge_dev *hdev,
7550 				       int link_ret)
7551 {
7552 #define HCLGE_PHY_LINK_STATUS_NUM  200
7553 
7554 	struct phy_device *phydev = hdev->hw.mac.phydev;
7555 	int i = 0;
7556 	int ret;
7557 
7558 	do {
7559 		ret = phy_read_status(phydev);
7560 		if (ret) {
7561 			dev_err(&hdev->pdev->dev,
7562 				"phy update link status fail, ret = %d\n", ret);
7563 			return;
7564 		}
7565 
7566 		if (phydev->link == link_ret)
7567 			break;
7568 
7569 		msleep(HCLGE_LINK_STATUS_MS);
7570 	} while (++i < HCLGE_PHY_LINK_STATUS_NUM);
7571 }
7572 
7573 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret,
7574 				      int wait_cnt)
7575 {
7576 	int link_status;
7577 	int i = 0;
7578 	int ret;
7579 
7580 	do {
7581 		ret = hclge_get_mac_link_status(hdev, &link_status);
7582 		if (ret)
7583 			return ret;
7584 		if (link_status == link_ret)
7585 			return 0;
7586 
7587 		msleep(HCLGE_LINK_STATUS_MS);
7588 	} while (++i < wait_cnt);
7589 	return -EBUSY;
7590 }
7591 
7592 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en,
7593 					  bool is_phy)
7594 {
7595 #define HCLGE_MAC_LINK_STATUS_NUM  100
7596 
7597 	int link_ret;
7598 
7599 	link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
7600 
7601 	if (is_phy)
7602 		hclge_phy_link_status_wait(hdev, link_ret);
7603 
7604 	return hclge_mac_link_status_wait(hdev, link_ret,
7605 					  HCLGE_MAC_LINK_STATUS_NUM);
7606 }
7607 
7608 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
7609 {
7610 	struct hclge_config_mac_mode_cmd *req;
7611 	struct hclge_desc desc;
7612 	u32 loop_en;
7613 	int ret;
7614 
7615 	req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
7616 	/* 1 Read out the MAC mode config at first */
7617 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
7618 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7619 	if (ret) {
7620 		dev_err(&hdev->pdev->dev,
7621 			"mac loopback get fail, ret =%d.\n", ret);
7622 		return ret;
7623 	}
7624 
7625 	/* 2 Then setup the loopback flag */
7626 	loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
7627 	hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
7628 
7629 	req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7630 
7631 	/* 3 Config mac work mode with loopback flag
7632 	 * and its original configure parameters
7633 	 */
7634 	hclge_comm_cmd_reuse_desc(&desc, false);
7635 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7636 	if (ret)
7637 		dev_err(&hdev->pdev->dev,
7638 			"mac loopback set fail, ret =%d.\n", ret);
7639 	return ret;
7640 }
7641 
7642 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en,
7643 					      enum hnae3_loop loop_mode)
7644 {
7645 	struct hclge_common_lb_cmd *req;
7646 	struct hclge_desc desc;
7647 	u8 loop_mode_b;
7648 	int ret;
7649 
7650 	req = (struct hclge_common_lb_cmd *)desc.data;
7651 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false);
7652 
7653 	switch (loop_mode) {
7654 	case HNAE3_LOOP_SERIAL_SERDES:
7655 		loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
7656 		break;
7657 	case HNAE3_LOOP_PARALLEL_SERDES:
7658 		loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
7659 		break;
7660 	case HNAE3_LOOP_PHY:
7661 		loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B;
7662 		break;
7663 	default:
7664 		dev_err(&hdev->pdev->dev,
7665 			"unsupported loopback mode %d\n", loop_mode);
7666 		return -ENOTSUPP;
7667 	}
7668 
7669 	req->mask = loop_mode_b;
7670 	if (en)
7671 		req->enable = loop_mode_b;
7672 
7673 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7674 	if (ret)
7675 		dev_err(&hdev->pdev->dev,
7676 			"failed to send loopback cmd, loop_mode = %d, ret = %d\n",
7677 			loop_mode, ret);
7678 
7679 	return ret;
7680 }
7681 
7682 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev)
7683 {
7684 #define HCLGE_COMMON_LB_RETRY_MS	10
7685 #define HCLGE_COMMON_LB_RETRY_NUM	100
7686 
7687 	struct hclge_common_lb_cmd *req;
7688 	struct hclge_desc desc;
7689 	u32 i = 0;
7690 	int ret;
7691 
7692 	req = (struct hclge_common_lb_cmd *)desc.data;
7693 
7694 	do {
7695 		msleep(HCLGE_COMMON_LB_RETRY_MS);
7696 		hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK,
7697 					   true);
7698 		ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7699 		if (ret) {
7700 			dev_err(&hdev->pdev->dev,
7701 				"failed to get loopback done status, ret = %d\n",
7702 				ret);
7703 			return ret;
7704 		}
7705 	} while (++i < HCLGE_COMMON_LB_RETRY_NUM &&
7706 		 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B));
7707 
7708 	if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) {
7709 		dev_err(&hdev->pdev->dev, "wait loopback timeout\n");
7710 		return -EBUSY;
7711 	} else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) {
7712 		dev_err(&hdev->pdev->dev, "failed to do loopback test\n");
7713 		return -EIO;
7714 	}
7715 
7716 	return 0;
7717 }
7718 
7719 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en,
7720 				     enum hnae3_loop loop_mode)
7721 {
7722 	int ret;
7723 
7724 	ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode);
7725 	if (ret)
7726 		return ret;
7727 
7728 	return hclge_cfg_common_loopback_wait(hdev);
7729 }
7730 
7731 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en,
7732 				     enum hnae3_loop loop_mode)
7733 {
7734 	int ret;
7735 
7736 	ret = hclge_cfg_common_loopback(hdev, en, loop_mode);
7737 	if (ret)
7738 		return ret;
7739 
7740 	hclge_cfg_mac_mode(hdev, en);
7741 
7742 	ret = hclge_mac_phy_link_status_wait(hdev, en, false);
7743 	if (ret)
7744 		dev_err(&hdev->pdev->dev,
7745 			"serdes loopback config mac mode timeout\n");
7746 
7747 	return ret;
7748 }
7749 
7750 static int hclge_enable_phy_loopback(struct hclge_dev *hdev,
7751 				     struct phy_device *phydev)
7752 {
7753 	int ret;
7754 
7755 	if (!phydev->suspended) {
7756 		ret = phy_suspend(phydev);
7757 		if (ret)
7758 			return ret;
7759 	}
7760 
7761 	ret = phy_resume(phydev);
7762 	if (ret)
7763 		return ret;
7764 
7765 	return phy_loopback(phydev, true);
7766 }
7767 
7768 static int hclge_disable_phy_loopback(struct hclge_dev *hdev,
7769 				      struct phy_device *phydev)
7770 {
7771 	int ret;
7772 
7773 	ret = phy_loopback(phydev, false);
7774 	if (ret)
7775 		return ret;
7776 
7777 	return phy_suspend(phydev);
7778 }
7779 
7780 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en)
7781 {
7782 	struct phy_device *phydev = hdev->hw.mac.phydev;
7783 	int ret;
7784 
7785 	if (!phydev) {
7786 		if (hnae3_dev_phy_imp_supported(hdev))
7787 			return hclge_set_common_loopback(hdev, en,
7788 							 HNAE3_LOOP_PHY);
7789 		return -ENOTSUPP;
7790 	}
7791 
7792 	if (en)
7793 		ret = hclge_enable_phy_loopback(hdev, phydev);
7794 	else
7795 		ret = hclge_disable_phy_loopback(hdev, phydev);
7796 	if (ret) {
7797 		dev_err(&hdev->pdev->dev,
7798 			"set phy loopback fail, ret = %d\n", ret);
7799 		return ret;
7800 	}
7801 
7802 	hclge_cfg_mac_mode(hdev, en);
7803 
7804 	ret = hclge_mac_phy_link_status_wait(hdev, en, true);
7805 	if (ret)
7806 		dev_err(&hdev->pdev->dev,
7807 			"phy loopback config mac mode timeout\n");
7808 
7809 	return ret;
7810 }
7811 
7812 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id,
7813 				     u16 stream_id, bool enable)
7814 {
7815 	struct hclge_desc desc;
7816 	struct hclge_cfg_com_tqp_queue_cmd *req =
7817 		(struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
7818 
7819 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
7820 	req->tqp_id = cpu_to_le16(tqp_id);
7821 	req->stream_id = cpu_to_le16(stream_id);
7822 	if (enable)
7823 		req->enable |= 1U << HCLGE_TQP_ENABLE_B;
7824 
7825 	return hclge_cmd_send(&hdev->hw, &desc, 1);
7826 }
7827 
7828 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable)
7829 {
7830 	struct hclge_vport *vport = hclge_get_vport(handle);
7831 	struct hclge_dev *hdev = vport->back;
7832 	int ret;
7833 	u16 i;
7834 
7835 	for (i = 0; i < handle->kinfo.num_tqps; i++) {
7836 		ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable);
7837 		if (ret)
7838 			return ret;
7839 	}
7840 	return 0;
7841 }
7842 
7843 static int hclge_set_loopback(struct hnae3_handle *handle,
7844 			      enum hnae3_loop loop_mode, bool en)
7845 {
7846 	struct hclge_vport *vport = hclge_get_vport(handle);
7847 	struct hclge_dev *hdev = vport->back;
7848 	int ret = 0;
7849 
7850 	/* Loopback can be enabled in three places: SSU, MAC, and serdes. By
7851 	 * default, SSU loopback is enabled, so if the SMAC and the DMAC are
7852 	 * the same, the packets are looped back in the SSU. If SSU loopback
7853 	 * is disabled, packets can reach MAC even if SMAC is the same as DMAC.
7854 	 */
7855 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
7856 		u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B);
7857 
7858 		ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param,
7859 						HCLGE_SWITCH_ALW_LPBK_MASK);
7860 		if (ret)
7861 			return ret;
7862 	}
7863 
7864 	switch (loop_mode) {
7865 	case HNAE3_LOOP_APP:
7866 		ret = hclge_set_app_loopback(hdev, en);
7867 		break;
7868 	case HNAE3_LOOP_SERIAL_SERDES:
7869 	case HNAE3_LOOP_PARALLEL_SERDES:
7870 		ret = hclge_set_common_loopback(hdev, en, loop_mode);
7871 		break;
7872 	case HNAE3_LOOP_PHY:
7873 		ret = hclge_set_phy_loopback(hdev, en);
7874 		break;
7875 	case HNAE3_LOOP_EXTERNAL:
7876 		break;
7877 	default:
7878 		ret = -ENOTSUPP;
7879 		dev_err(&hdev->pdev->dev,
7880 			"loop_mode %d is not supported\n", loop_mode);
7881 		break;
7882 	}
7883 
7884 	if (ret)
7885 		return ret;
7886 
7887 	ret = hclge_tqp_enable(handle, en);
7888 	if (ret)
7889 		dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n",
7890 			en ? "enable" : "disable", ret);
7891 
7892 	return ret;
7893 }
7894 
7895 static int hclge_set_default_loopback(struct hclge_dev *hdev)
7896 {
7897 	int ret;
7898 
7899 	ret = hclge_set_app_loopback(hdev, false);
7900 	if (ret)
7901 		return ret;
7902 
7903 	ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES);
7904 	if (ret)
7905 		return ret;
7906 
7907 	return hclge_cfg_common_loopback(hdev, false,
7908 					 HNAE3_LOOP_PARALLEL_SERDES);
7909 }
7910 
7911 static void hclge_flush_link_update(struct hclge_dev *hdev)
7912 {
7913 #define HCLGE_FLUSH_LINK_TIMEOUT	100000
7914 
7915 	unsigned long last = hdev->serv_processed_cnt;
7916 	int i = 0;
7917 
7918 	while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) &&
7919 	       i++ < HCLGE_FLUSH_LINK_TIMEOUT &&
7920 	       last == hdev->serv_processed_cnt)
7921 		usleep_range(1, 1);
7922 }
7923 
7924 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable)
7925 {
7926 	struct hclge_vport *vport = hclge_get_vport(handle);
7927 	struct hclge_dev *hdev = vport->back;
7928 
7929 	if (enable) {
7930 		hclge_task_schedule(hdev, 0);
7931 	} else {
7932 		/* Set the DOWN flag here to disable link updating */
7933 		set_bit(HCLGE_STATE_DOWN, &hdev->state);
7934 
7935 		/* flush memory to make sure DOWN is seen by service task */
7936 		smp_mb__before_atomic();
7937 		hclge_flush_link_update(hdev);
7938 	}
7939 }
7940 
7941 static int hclge_ae_start(struct hnae3_handle *handle)
7942 {
7943 	struct hclge_vport *vport = hclge_get_vport(handle);
7944 	struct hclge_dev *hdev = vport->back;
7945 
7946 	/* mac enable */
7947 	hclge_cfg_mac_mode(hdev, true);
7948 	clear_bit(HCLGE_STATE_DOWN, &hdev->state);
7949 	hdev->hw.mac.link = 0;
7950 
7951 	/* reset tqp stats */
7952 	hclge_comm_reset_tqp_stats(handle);
7953 
7954 	hclge_mac_start_phy(hdev);
7955 
7956 	return 0;
7957 }
7958 
7959 static void hclge_ae_stop(struct hnae3_handle *handle)
7960 {
7961 	struct hclge_vport *vport = hclge_get_vport(handle);
7962 	struct hclge_dev *hdev = vport->back;
7963 
7964 	set_bit(HCLGE_STATE_DOWN, &hdev->state);
7965 	spin_lock_bh(&hdev->fd_rule_lock);
7966 	hclge_clear_arfs_rules(hdev);
7967 	spin_unlock_bh(&hdev->fd_rule_lock);
7968 
7969 	/* If it is not PF reset or FLR, the firmware will disable the MAC,
7970 	 * so it only need to stop phy here.
7971 	 */
7972 	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
7973 		hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE,
7974 				       HCLGE_PFC_DISABLE);
7975 		if (hdev->reset_type != HNAE3_FUNC_RESET &&
7976 		    hdev->reset_type != HNAE3_FLR_RESET) {
7977 			hclge_mac_stop_phy(hdev);
7978 			hclge_update_link_status(hdev);
7979 			return;
7980 		}
7981 	}
7982 
7983 	hclge_reset_tqp(handle);
7984 
7985 	hclge_config_mac_tnl_int(hdev, false);
7986 
7987 	/* Mac disable */
7988 	hclge_cfg_mac_mode(hdev, false);
7989 
7990 	hclge_mac_stop_phy(hdev);
7991 
7992 	/* reset tqp stats */
7993 	hclge_comm_reset_tqp_stats(handle);
7994 	hclge_update_link_status(hdev);
7995 }
7996 
7997 int hclge_vport_start(struct hclge_vport *vport)
7998 {
7999 	struct hclge_dev *hdev = vport->back;
8000 
8001 	set_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
8002 	set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
8003 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
8004 	vport->last_active_jiffies = jiffies;
8005 	vport->need_notify = 0;
8006 
8007 	if (test_bit(vport->vport_id, hdev->vport_config_block)) {
8008 		if (vport->vport_id) {
8009 			hclge_restore_mac_table_common(vport);
8010 			hclge_restore_vport_vlan_table(vport);
8011 		} else {
8012 			hclge_restore_hw_table(hdev);
8013 		}
8014 	}
8015 
8016 	clear_bit(vport->vport_id, hdev->vport_config_block);
8017 
8018 	return 0;
8019 }
8020 
8021 void hclge_vport_stop(struct hclge_vport *vport)
8022 {
8023 	clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
8024 	clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
8025 	vport->need_notify = 0;
8026 }
8027 
8028 static int hclge_client_start(struct hnae3_handle *handle)
8029 {
8030 	struct hclge_vport *vport = hclge_get_vport(handle);
8031 
8032 	return hclge_vport_start(vport);
8033 }
8034 
8035 static void hclge_client_stop(struct hnae3_handle *handle)
8036 {
8037 	struct hclge_vport *vport = hclge_get_vport(handle);
8038 
8039 	hclge_vport_stop(vport);
8040 }
8041 
8042 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
8043 					 u16 cmdq_resp, u8  resp_code,
8044 					 enum hclge_mac_vlan_tbl_opcode op)
8045 {
8046 	struct hclge_dev *hdev = vport->back;
8047 
8048 	if (cmdq_resp) {
8049 		dev_err(&hdev->pdev->dev,
8050 			"cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n",
8051 			cmdq_resp);
8052 		return -EIO;
8053 	}
8054 
8055 	if (op == HCLGE_MAC_VLAN_ADD) {
8056 		if (!resp_code || resp_code == 1)
8057 			return 0;
8058 		else if (resp_code == HCLGE_ADD_UC_OVERFLOW ||
8059 			 resp_code == HCLGE_ADD_MC_OVERFLOW)
8060 			return -ENOSPC;
8061 
8062 		dev_err(&hdev->pdev->dev,
8063 			"add mac addr failed for undefined, code=%u.\n",
8064 			resp_code);
8065 		return -EIO;
8066 	} else if (op == HCLGE_MAC_VLAN_REMOVE) {
8067 		if (!resp_code) {
8068 			return 0;
8069 		} else if (resp_code == 1) {
8070 			dev_dbg(&hdev->pdev->dev,
8071 				"remove mac addr failed for miss.\n");
8072 			return -ENOENT;
8073 		}
8074 
8075 		dev_err(&hdev->pdev->dev,
8076 			"remove mac addr failed for undefined, code=%u.\n",
8077 			resp_code);
8078 		return -EIO;
8079 	} else if (op == HCLGE_MAC_VLAN_LKUP) {
8080 		if (!resp_code) {
8081 			return 0;
8082 		} else if (resp_code == 1) {
8083 			dev_dbg(&hdev->pdev->dev,
8084 				"lookup mac addr failed for miss.\n");
8085 			return -ENOENT;
8086 		}
8087 
8088 		dev_err(&hdev->pdev->dev,
8089 			"lookup mac addr failed for undefined, code=%u.\n",
8090 			resp_code);
8091 		return -EIO;
8092 	}
8093 
8094 	dev_err(&hdev->pdev->dev,
8095 		"unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op);
8096 
8097 	return -EINVAL;
8098 }
8099 
8100 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
8101 {
8102 #define HCLGE_VF_NUM_IN_FIRST_DESC 192
8103 
8104 	unsigned int word_num;
8105 	unsigned int bit_num;
8106 
8107 	if (vfid > 255 || vfid < 0)
8108 		return -EIO;
8109 
8110 	if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) {
8111 		word_num = vfid / 32;
8112 		bit_num  = vfid % 32;
8113 		if (clr)
8114 			desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
8115 		else
8116 			desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
8117 	} else {
8118 		word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32;
8119 		bit_num  = vfid % 32;
8120 		if (clr)
8121 			desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
8122 		else
8123 			desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
8124 	}
8125 
8126 	return 0;
8127 }
8128 
8129 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
8130 {
8131 #define HCLGE_DESC_NUMBER 3
8132 #define HCLGE_FUNC_NUMBER_PER_DESC 6
8133 	int i, j;
8134 
8135 	for (i = 1; i < HCLGE_DESC_NUMBER; i++)
8136 		for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
8137 			if (desc[i].data[j])
8138 				return false;
8139 
8140 	return true;
8141 }
8142 
8143 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
8144 				   const u8 *addr, bool is_mc)
8145 {
8146 	const unsigned char *mac_addr = addr;
8147 	u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
8148 		       (mac_addr[0]) | (mac_addr[1] << 8);
8149 	u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
8150 
8151 	hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
8152 	if (is_mc) {
8153 		hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
8154 		hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
8155 	}
8156 
8157 	new_req->mac_addr_hi32 = cpu_to_le32(high_val);
8158 	new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
8159 }
8160 
8161 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
8162 				     struct hclge_mac_vlan_tbl_entry_cmd *req)
8163 {
8164 	struct hclge_dev *hdev = vport->back;
8165 	struct hclge_desc desc;
8166 	u8 resp_code;
8167 	u16 retval;
8168 	int ret;
8169 
8170 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
8171 
8172 	memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8173 
8174 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8175 	if (ret) {
8176 		dev_err(&hdev->pdev->dev,
8177 			"del mac addr failed for cmd_send, ret =%d.\n",
8178 			ret);
8179 		return ret;
8180 	}
8181 	resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8182 	retval = le16_to_cpu(desc.retval);
8183 
8184 	return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8185 					     HCLGE_MAC_VLAN_REMOVE);
8186 }
8187 
8188 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
8189 				     struct hclge_mac_vlan_tbl_entry_cmd *req,
8190 				     struct hclge_desc *desc,
8191 				     bool is_mc)
8192 {
8193 	struct hclge_dev *hdev = vport->back;
8194 	u8 resp_code;
8195 	u16 retval;
8196 	int ret;
8197 
8198 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
8199 	if (is_mc) {
8200 		desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8201 		memcpy(desc[0].data,
8202 		       req,
8203 		       sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8204 		hclge_cmd_setup_basic_desc(&desc[1],
8205 					   HCLGE_OPC_MAC_VLAN_ADD,
8206 					   true);
8207 		desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8208 		hclge_cmd_setup_basic_desc(&desc[2],
8209 					   HCLGE_OPC_MAC_VLAN_ADD,
8210 					   true);
8211 		ret = hclge_cmd_send(&hdev->hw, desc, 3);
8212 	} else {
8213 		memcpy(desc[0].data,
8214 		       req,
8215 		       sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8216 		ret = hclge_cmd_send(&hdev->hw, desc, 1);
8217 	}
8218 	if (ret) {
8219 		dev_err(&hdev->pdev->dev,
8220 			"lookup mac addr failed for cmd_send, ret =%d.\n",
8221 			ret);
8222 		return ret;
8223 	}
8224 	resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
8225 	retval = le16_to_cpu(desc[0].retval);
8226 
8227 	return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8228 					     HCLGE_MAC_VLAN_LKUP);
8229 }
8230 
8231 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
8232 				  struct hclge_mac_vlan_tbl_entry_cmd *req,
8233 				  struct hclge_desc *mc_desc)
8234 {
8235 	struct hclge_dev *hdev = vport->back;
8236 	int cfg_status;
8237 	u8 resp_code;
8238 	u16 retval;
8239 	int ret;
8240 
8241 	if (!mc_desc) {
8242 		struct hclge_desc desc;
8243 
8244 		hclge_cmd_setup_basic_desc(&desc,
8245 					   HCLGE_OPC_MAC_VLAN_ADD,
8246 					   false);
8247 		memcpy(desc.data, req,
8248 		       sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8249 		ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8250 		resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8251 		retval = le16_to_cpu(desc.retval);
8252 
8253 		cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8254 							   resp_code,
8255 							   HCLGE_MAC_VLAN_ADD);
8256 	} else {
8257 		hclge_comm_cmd_reuse_desc(&mc_desc[0], false);
8258 		mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8259 		hclge_comm_cmd_reuse_desc(&mc_desc[1], false);
8260 		mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8261 		hclge_comm_cmd_reuse_desc(&mc_desc[2], false);
8262 		mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT);
8263 		memcpy(mc_desc[0].data, req,
8264 		       sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8265 		ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
8266 		resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
8267 		retval = le16_to_cpu(mc_desc[0].retval);
8268 
8269 		cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8270 							   resp_code,
8271 							   HCLGE_MAC_VLAN_ADD);
8272 	}
8273 
8274 	if (ret) {
8275 		dev_err(&hdev->pdev->dev,
8276 			"add mac addr failed for cmd_send, ret =%d.\n",
8277 			ret);
8278 		return ret;
8279 	}
8280 
8281 	return cfg_status;
8282 }
8283 
8284 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
8285 			       u16 *allocated_size)
8286 {
8287 	struct hclge_umv_spc_alc_cmd *req;
8288 	struct hclge_desc desc;
8289 	int ret;
8290 
8291 	req = (struct hclge_umv_spc_alc_cmd *)desc.data;
8292 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
8293 
8294 	req->space_size = cpu_to_le32(space_size);
8295 
8296 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8297 	if (ret) {
8298 		dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n",
8299 			ret);
8300 		return ret;
8301 	}
8302 
8303 	*allocated_size = le32_to_cpu(desc.data[1]);
8304 
8305 	return 0;
8306 }
8307 
8308 static int hclge_init_umv_space(struct hclge_dev *hdev)
8309 {
8310 	u16 allocated_size = 0;
8311 	int ret;
8312 
8313 	ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size);
8314 	if (ret)
8315 		return ret;
8316 
8317 	if (allocated_size < hdev->wanted_umv_size)
8318 		dev_warn(&hdev->pdev->dev,
8319 			 "failed to alloc umv space, want %u, get %u\n",
8320 			 hdev->wanted_umv_size, allocated_size);
8321 
8322 	hdev->max_umv_size = allocated_size;
8323 	hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1);
8324 	hdev->share_umv_size = hdev->priv_umv_size +
8325 			hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8326 
8327 	if (hdev->ae_dev->dev_specs.mc_mac_size)
8328 		set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps);
8329 
8330 	return 0;
8331 }
8332 
8333 static void hclge_reset_umv_space(struct hclge_dev *hdev)
8334 {
8335 	struct hclge_vport *vport;
8336 	int i;
8337 
8338 	for (i = 0; i < hdev->num_alloc_vport; i++) {
8339 		vport = &hdev->vport[i];
8340 		vport->used_umv_num = 0;
8341 	}
8342 
8343 	mutex_lock(&hdev->vport_lock);
8344 	hdev->share_umv_size = hdev->priv_umv_size +
8345 			hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8346 	mutex_unlock(&hdev->vport_lock);
8347 
8348 	hdev->used_mc_mac_num = 0;
8349 }
8350 
8351 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock)
8352 {
8353 	struct hclge_dev *hdev = vport->back;
8354 	bool is_full;
8355 
8356 	if (need_lock)
8357 		mutex_lock(&hdev->vport_lock);
8358 
8359 	is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
8360 		   hdev->share_umv_size == 0);
8361 
8362 	if (need_lock)
8363 		mutex_unlock(&hdev->vport_lock);
8364 
8365 	return is_full;
8366 }
8367 
8368 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
8369 {
8370 	struct hclge_dev *hdev = vport->back;
8371 
8372 	if (is_free) {
8373 		if (vport->used_umv_num > hdev->priv_umv_size)
8374 			hdev->share_umv_size++;
8375 
8376 		if (vport->used_umv_num > 0)
8377 			vport->used_umv_num--;
8378 	} else {
8379 		if (vport->used_umv_num >= hdev->priv_umv_size &&
8380 		    hdev->share_umv_size > 0)
8381 			hdev->share_umv_size--;
8382 		vport->used_umv_num++;
8383 	}
8384 }
8385 
8386 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list,
8387 						  const u8 *mac_addr)
8388 {
8389 	struct hclge_mac_node *mac_node, *tmp;
8390 
8391 	list_for_each_entry_safe(mac_node, tmp, list, node)
8392 		if (ether_addr_equal(mac_addr, mac_node->mac_addr))
8393 			return mac_node;
8394 
8395 	return NULL;
8396 }
8397 
8398 static void hclge_update_mac_node(struct hclge_mac_node *mac_node,
8399 				  enum HCLGE_MAC_NODE_STATE state)
8400 {
8401 	switch (state) {
8402 	/* from set_rx_mode or tmp_add_list */
8403 	case HCLGE_MAC_TO_ADD:
8404 		if (mac_node->state == HCLGE_MAC_TO_DEL)
8405 			mac_node->state = HCLGE_MAC_ACTIVE;
8406 		break;
8407 	/* only from set_rx_mode */
8408 	case HCLGE_MAC_TO_DEL:
8409 		if (mac_node->state == HCLGE_MAC_TO_ADD) {
8410 			list_del(&mac_node->node);
8411 			kfree(mac_node);
8412 		} else {
8413 			mac_node->state = HCLGE_MAC_TO_DEL;
8414 		}
8415 		break;
8416 	/* only from tmp_add_list, the mac_node->state won't be
8417 	 * ACTIVE.
8418 	 */
8419 	case HCLGE_MAC_ACTIVE:
8420 		if (mac_node->state == HCLGE_MAC_TO_ADD)
8421 			mac_node->state = HCLGE_MAC_ACTIVE;
8422 
8423 		break;
8424 	}
8425 }
8426 
8427 int hclge_update_mac_list(struct hclge_vport *vport,
8428 			  enum HCLGE_MAC_NODE_STATE state,
8429 			  enum HCLGE_MAC_ADDR_TYPE mac_type,
8430 			  const unsigned char *addr)
8431 {
8432 	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8433 	struct hclge_dev *hdev = vport->back;
8434 	struct hclge_mac_node *mac_node;
8435 	struct list_head *list;
8436 
8437 	list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8438 		&vport->uc_mac_list : &vport->mc_mac_list;
8439 
8440 	spin_lock_bh(&vport->mac_list_lock);
8441 
8442 	/* if the mac addr is already in the mac list, no need to add a new
8443 	 * one into it, just check the mac addr state, convert it to a new
8444 	 * state, or just remove it, or do nothing.
8445 	 */
8446 	mac_node = hclge_find_mac_node(list, addr);
8447 	if (mac_node) {
8448 		hclge_update_mac_node(mac_node, state);
8449 		spin_unlock_bh(&vport->mac_list_lock);
8450 		set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8451 		return 0;
8452 	}
8453 
8454 	/* if this address is never added, unnecessary to delete */
8455 	if (state == HCLGE_MAC_TO_DEL) {
8456 		spin_unlock_bh(&vport->mac_list_lock);
8457 		hnae3_format_mac_addr(format_mac_addr, addr);
8458 		dev_err(&hdev->pdev->dev,
8459 			"failed to delete address %s from mac list\n",
8460 			format_mac_addr);
8461 		return -ENOENT;
8462 	}
8463 
8464 	mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
8465 	if (!mac_node) {
8466 		spin_unlock_bh(&vport->mac_list_lock);
8467 		return -ENOMEM;
8468 	}
8469 
8470 	set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8471 
8472 	mac_node->state = state;
8473 	ether_addr_copy(mac_node->mac_addr, addr);
8474 	list_add_tail(&mac_node->node, list);
8475 
8476 	spin_unlock_bh(&vport->mac_list_lock);
8477 
8478 	return 0;
8479 }
8480 
8481 static int hclge_add_uc_addr(struct hnae3_handle *handle,
8482 			     const unsigned char *addr)
8483 {
8484 	struct hclge_vport *vport = hclge_get_vport(handle);
8485 
8486 	return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC,
8487 				     addr);
8488 }
8489 
8490 int hclge_add_uc_addr_common(struct hclge_vport *vport,
8491 			     const unsigned char *addr)
8492 {
8493 	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8494 	struct hclge_dev *hdev = vport->back;
8495 	struct hclge_mac_vlan_tbl_entry_cmd req;
8496 	struct hclge_desc desc;
8497 	u16 egress_port = 0;
8498 	int ret;
8499 
8500 	/* mac addr check */
8501 	if (is_zero_ether_addr(addr) ||
8502 	    is_broadcast_ether_addr(addr) ||
8503 	    is_multicast_ether_addr(addr)) {
8504 		hnae3_format_mac_addr(format_mac_addr, addr);
8505 		dev_err(&hdev->pdev->dev,
8506 			"Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n",
8507 			 format_mac_addr, is_zero_ether_addr(addr),
8508 			 is_broadcast_ether_addr(addr),
8509 			 is_multicast_ether_addr(addr));
8510 		return -EINVAL;
8511 	}
8512 
8513 	memset(&req, 0, sizeof(req));
8514 
8515 	hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
8516 			HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
8517 
8518 	req.egress_port = cpu_to_le16(egress_port);
8519 
8520 	hclge_prepare_mac_addr(&req, addr, false);
8521 
8522 	/* Lookup the mac address in the mac_vlan table, and add
8523 	 * it if the entry is inexistent. Repeated unicast entry
8524 	 * is not allowed in the mac vlan table.
8525 	 */
8526 	ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
8527 	if (ret == -ENOENT) {
8528 		mutex_lock(&hdev->vport_lock);
8529 		if (!hclge_is_umv_space_full(vport, false)) {
8530 			ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
8531 			if (!ret)
8532 				hclge_update_umv_space(vport, false);
8533 			mutex_unlock(&hdev->vport_lock);
8534 			return ret;
8535 		}
8536 		mutex_unlock(&hdev->vport_lock);
8537 
8538 		if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE))
8539 			dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
8540 				hdev->priv_umv_size);
8541 
8542 		return -ENOSPC;
8543 	}
8544 
8545 	/* check if we just hit the duplicate */
8546 	if (!ret)
8547 		return -EEXIST;
8548 
8549 	return ret;
8550 }
8551 
8552 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
8553 			    const unsigned char *addr)
8554 {
8555 	struct hclge_vport *vport = hclge_get_vport(handle);
8556 
8557 	return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC,
8558 				     addr);
8559 }
8560 
8561 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
8562 			    const unsigned char *addr)
8563 {
8564 	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8565 	struct hclge_dev *hdev = vport->back;
8566 	struct hclge_mac_vlan_tbl_entry_cmd req;
8567 	int ret;
8568 
8569 	/* mac addr check */
8570 	if (is_zero_ether_addr(addr) ||
8571 	    is_broadcast_ether_addr(addr) ||
8572 	    is_multicast_ether_addr(addr)) {
8573 		hnae3_format_mac_addr(format_mac_addr, addr);
8574 		dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n",
8575 			format_mac_addr);
8576 		return -EINVAL;
8577 	}
8578 
8579 	memset(&req, 0, sizeof(req));
8580 	hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
8581 	hclge_prepare_mac_addr(&req, addr, false);
8582 	ret = hclge_remove_mac_vlan_tbl(vport, &req);
8583 	if (!ret || ret == -ENOENT) {
8584 		mutex_lock(&hdev->vport_lock);
8585 		hclge_update_umv_space(vport, true);
8586 		mutex_unlock(&hdev->vport_lock);
8587 		return 0;
8588 	}
8589 
8590 	return ret;
8591 }
8592 
8593 static int hclge_add_mc_addr(struct hnae3_handle *handle,
8594 			     const unsigned char *addr)
8595 {
8596 	struct hclge_vport *vport = hclge_get_vport(handle);
8597 
8598 	return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC,
8599 				     addr);
8600 }
8601 
8602 int hclge_add_mc_addr_common(struct hclge_vport *vport,
8603 			     const unsigned char *addr)
8604 {
8605 	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8606 	struct hclge_dev *hdev = vport->back;
8607 	struct hclge_mac_vlan_tbl_entry_cmd req;
8608 	struct hclge_desc desc[3];
8609 	bool is_new_addr = false;
8610 	int status;
8611 
8612 	/* mac addr check */
8613 	if (!is_multicast_ether_addr(addr)) {
8614 		hnae3_format_mac_addr(format_mac_addr, addr);
8615 		dev_err(&hdev->pdev->dev,
8616 			"Add mc mac err! invalid mac:%s.\n",
8617 			 format_mac_addr);
8618 		return -EINVAL;
8619 	}
8620 	memset(&req, 0, sizeof(req));
8621 	hclge_prepare_mac_addr(&req, addr, true);
8622 	status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8623 	if (status) {
8624 		if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) &&
8625 		    hdev->used_mc_mac_num >=
8626 		    hdev->ae_dev->dev_specs.mc_mac_size)
8627 			goto err_no_space;
8628 
8629 		is_new_addr = true;
8630 
8631 		/* This mac addr do not exist, add new entry for it */
8632 		memset(desc[0].data, 0, sizeof(desc[0].data));
8633 		memset(desc[1].data, 0, sizeof(desc[0].data));
8634 		memset(desc[2].data, 0, sizeof(desc[0].data));
8635 	}
8636 	status = hclge_update_desc_vfid(desc, vport->vport_id, false);
8637 	if (status)
8638 		return status;
8639 	status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8640 	if (status == -ENOSPC)
8641 		goto err_no_space;
8642 	else if (!status && is_new_addr)
8643 		hdev->used_mc_mac_num++;
8644 
8645 	return status;
8646 
8647 err_no_space:
8648 	/* if already overflow, not to print each time */
8649 	if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) {
8650 		vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8651 		dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
8652 	}
8653 
8654 	return -ENOSPC;
8655 }
8656 
8657 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
8658 			    const unsigned char *addr)
8659 {
8660 	struct hclge_vport *vport = hclge_get_vport(handle);
8661 
8662 	return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC,
8663 				     addr);
8664 }
8665 
8666 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
8667 			    const unsigned char *addr)
8668 {
8669 	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8670 	struct hclge_dev *hdev = vport->back;
8671 	struct hclge_mac_vlan_tbl_entry_cmd req;
8672 	enum hclge_comm_cmd_status status;
8673 	struct hclge_desc desc[3];
8674 
8675 	/* mac addr check */
8676 	if (!is_multicast_ether_addr(addr)) {
8677 		hnae3_format_mac_addr(format_mac_addr, addr);
8678 		dev_dbg(&hdev->pdev->dev,
8679 			"Remove mc mac err! invalid mac:%s.\n",
8680 			 format_mac_addr);
8681 		return -EINVAL;
8682 	}
8683 
8684 	memset(&req, 0, sizeof(req));
8685 	hclge_prepare_mac_addr(&req, addr, true);
8686 	status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8687 	if (!status) {
8688 		/* This mac addr exist, remove this handle's VFID for it */
8689 		status = hclge_update_desc_vfid(desc, vport->vport_id, true);
8690 		if (status)
8691 			return status;
8692 
8693 		if (hclge_is_all_function_id_zero(desc)) {
8694 			/* All the vfid is zero, so need to delete this entry */
8695 			status = hclge_remove_mac_vlan_tbl(vport, &req);
8696 			if (!status)
8697 				hdev->used_mc_mac_num--;
8698 		} else {
8699 			/* Not all the vfid is zero, update the vfid */
8700 			status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8701 		}
8702 	} else if (status == -ENOENT) {
8703 		status = 0;
8704 	}
8705 
8706 	return status;
8707 }
8708 
8709 static void hclge_sync_vport_mac_list(struct hclge_vport *vport,
8710 				      struct list_head *list,
8711 				      enum HCLGE_MAC_ADDR_TYPE mac_type)
8712 {
8713 	int (*sync)(struct hclge_vport *vport, const unsigned char *addr);
8714 	struct hclge_mac_node *mac_node, *tmp;
8715 	int ret;
8716 
8717 	if (mac_type == HCLGE_MAC_ADDR_UC)
8718 		sync = hclge_add_uc_addr_common;
8719 	else
8720 		sync = hclge_add_mc_addr_common;
8721 
8722 	list_for_each_entry_safe(mac_node, tmp, list, node) {
8723 		ret = sync(vport, mac_node->mac_addr);
8724 		if (!ret) {
8725 			mac_node->state = HCLGE_MAC_ACTIVE;
8726 		} else {
8727 			set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8728 				&vport->state);
8729 
8730 			/* If one unicast mac address is existing in hardware,
8731 			 * we need to try whether other unicast mac addresses
8732 			 * are new addresses that can be added.
8733 			 * Multicast mac address can be reusable, even though
8734 			 * there is no space to add new multicast mac address,
8735 			 * we should check whether other mac addresses are
8736 			 * existing in hardware for reuse.
8737 			 */
8738 			if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) ||
8739 			    (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC))
8740 				break;
8741 		}
8742 	}
8743 }
8744 
8745 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport,
8746 					struct list_head *list,
8747 					enum HCLGE_MAC_ADDR_TYPE mac_type)
8748 {
8749 	int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
8750 	struct hclge_mac_node *mac_node, *tmp;
8751 	int ret;
8752 
8753 	if (mac_type == HCLGE_MAC_ADDR_UC)
8754 		unsync = hclge_rm_uc_addr_common;
8755 	else
8756 		unsync = hclge_rm_mc_addr_common;
8757 
8758 	list_for_each_entry_safe(mac_node, tmp, list, node) {
8759 		ret = unsync(vport, mac_node->mac_addr);
8760 		if (!ret || ret == -ENOENT) {
8761 			list_del(&mac_node->node);
8762 			kfree(mac_node);
8763 		} else {
8764 			set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8765 				&vport->state);
8766 			break;
8767 		}
8768 	}
8769 }
8770 
8771 static bool hclge_sync_from_add_list(struct list_head *add_list,
8772 				     struct list_head *mac_list)
8773 {
8774 	struct hclge_mac_node *mac_node, *tmp, *new_node;
8775 	bool all_added = true;
8776 
8777 	list_for_each_entry_safe(mac_node, tmp, add_list, node) {
8778 		if (mac_node->state == HCLGE_MAC_TO_ADD)
8779 			all_added = false;
8780 
8781 		/* if the mac address from tmp_add_list is not in the
8782 		 * uc/mc_mac_list, it means have received a TO_DEL request
8783 		 * during the time window of adding the mac address into mac
8784 		 * table. if mac_node state is ACTIVE, then change it to TO_DEL,
8785 		 * then it will be removed at next time. else it must be TO_ADD,
8786 		 * this address hasn't been added into mac table,
8787 		 * so just remove the mac node.
8788 		 */
8789 		new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8790 		if (new_node) {
8791 			hclge_update_mac_node(new_node, mac_node->state);
8792 			list_del(&mac_node->node);
8793 			kfree(mac_node);
8794 		} else if (mac_node->state == HCLGE_MAC_ACTIVE) {
8795 			mac_node->state = HCLGE_MAC_TO_DEL;
8796 			list_move_tail(&mac_node->node, mac_list);
8797 		} else {
8798 			list_del(&mac_node->node);
8799 			kfree(mac_node);
8800 		}
8801 	}
8802 
8803 	return all_added;
8804 }
8805 
8806 static void hclge_sync_from_del_list(struct list_head *del_list,
8807 				     struct list_head *mac_list)
8808 {
8809 	struct hclge_mac_node *mac_node, *tmp, *new_node;
8810 
8811 	list_for_each_entry_safe(mac_node, tmp, del_list, node) {
8812 		new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8813 		if (new_node) {
8814 			/* If the mac addr exists in the mac list, it means
8815 			 * received a new TO_ADD request during the time window
8816 			 * of configuring the mac address. For the mac node
8817 			 * state is TO_ADD, and the address is already in the
8818 			 * in the hardware(due to delete fail), so we just need
8819 			 * to change the mac node state to ACTIVE.
8820 			 */
8821 			new_node->state = HCLGE_MAC_ACTIVE;
8822 			list_del(&mac_node->node);
8823 			kfree(mac_node);
8824 		} else {
8825 			list_move_tail(&mac_node->node, mac_list);
8826 		}
8827 	}
8828 }
8829 
8830 static void hclge_update_overflow_flags(struct hclge_vport *vport,
8831 					enum HCLGE_MAC_ADDR_TYPE mac_type,
8832 					bool is_all_added)
8833 {
8834 	if (mac_type == HCLGE_MAC_ADDR_UC) {
8835 		if (is_all_added)
8836 			vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE;
8837 		else if (hclge_is_umv_space_full(vport, true))
8838 			vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE;
8839 	} else {
8840 		if (is_all_added)
8841 			vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE;
8842 		else
8843 			vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8844 	}
8845 }
8846 
8847 static void hclge_sync_vport_mac_table(struct hclge_vport *vport,
8848 				       enum HCLGE_MAC_ADDR_TYPE mac_type)
8849 {
8850 	struct hclge_mac_node *mac_node, *tmp, *new_node;
8851 	struct list_head tmp_add_list, tmp_del_list;
8852 	struct list_head *list;
8853 	bool all_added;
8854 
8855 	INIT_LIST_HEAD(&tmp_add_list);
8856 	INIT_LIST_HEAD(&tmp_del_list);
8857 
8858 	/* move the mac addr to the tmp_add_list and tmp_del_list, then
8859 	 * we can add/delete these mac addr outside the spin lock
8860 	 */
8861 	list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8862 		&vport->uc_mac_list : &vport->mc_mac_list;
8863 
8864 	spin_lock_bh(&vport->mac_list_lock);
8865 
8866 	list_for_each_entry_safe(mac_node, tmp, list, node) {
8867 		switch (mac_node->state) {
8868 		case HCLGE_MAC_TO_DEL:
8869 			list_move_tail(&mac_node->node, &tmp_del_list);
8870 			break;
8871 		case HCLGE_MAC_TO_ADD:
8872 			new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
8873 			if (!new_node)
8874 				goto stop_traverse;
8875 			ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
8876 			new_node->state = mac_node->state;
8877 			list_add_tail(&new_node->node, &tmp_add_list);
8878 			break;
8879 		default:
8880 			break;
8881 		}
8882 	}
8883 
8884 stop_traverse:
8885 	spin_unlock_bh(&vport->mac_list_lock);
8886 
8887 	/* delete first, in order to get max mac table space for adding */
8888 	hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
8889 	hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type);
8890 
8891 	/* if some mac addresses were added/deleted fail, move back to the
8892 	 * mac_list, and retry at next time.
8893 	 */
8894 	spin_lock_bh(&vport->mac_list_lock);
8895 
8896 	hclge_sync_from_del_list(&tmp_del_list, list);
8897 	all_added = hclge_sync_from_add_list(&tmp_add_list, list);
8898 
8899 	spin_unlock_bh(&vport->mac_list_lock);
8900 
8901 	hclge_update_overflow_flags(vport, mac_type, all_added);
8902 }
8903 
8904 static bool hclge_need_sync_mac_table(struct hclge_vport *vport)
8905 {
8906 	struct hclge_dev *hdev = vport->back;
8907 
8908 	if (test_bit(vport->vport_id, hdev->vport_config_block))
8909 		return false;
8910 
8911 	if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state))
8912 		return true;
8913 
8914 	return false;
8915 }
8916 
8917 static void hclge_sync_mac_table(struct hclge_dev *hdev)
8918 {
8919 	int i;
8920 
8921 	for (i = 0; i < hdev->num_alloc_vport; i++) {
8922 		struct hclge_vport *vport = &hdev->vport[i];
8923 
8924 		if (!hclge_need_sync_mac_table(vport))
8925 			continue;
8926 
8927 		hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC);
8928 		hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC);
8929 	}
8930 }
8931 
8932 static void hclge_build_del_list(struct list_head *list,
8933 				 bool is_del_list,
8934 				 struct list_head *tmp_del_list)
8935 {
8936 	struct hclge_mac_node *mac_cfg, *tmp;
8937 
8938 	list_for_each_entry_safe(mac_cfg, tmp, list, node) {
8939 		switch (mac_cfg->state) {
8940 		case HCLGE_MAC_TO_DEL:
8941 		case HCLGE_MAC_ACTIVE:
8942 			list_move_tail(&mac_cfg->node, tmp_del_list);
8943 			break;
8944 		case HCLGE_MAC_TO_ADD:
8945 			if (is_del_list) {
8946 				list_del(&mac_cfg->node);
8947 				kfree(mac_cfg);
8948 			}
8949 			break;
8950 		}
8951 	}
8952 }
8953 
8954 static void hclge_unsync_del_list(struct hclge_vport *vport,
8955 				  int (*unsync)(struct hclge_vport *vport,
8956 						const unsigned char *addr),
8957 				  bool is_del_list,
8958 				  struct list_head *tmp_del_list)
8959 {
8960 	struct hclge_mac_node *mac_cfg, *tmp;
8961 	int ret;
8962 
8963 	list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) {
8964 		ret = unsync(vport, mac_cfg->mac_addr);
8965 		if (!ret || ret == -ENOENT) {
8966 			/* clear all mac addr from hardware, but remain these
8967 			 * mac addr in the mac list, and restore them after
8968 			 * vf reset finished.
8969 			 */
8970 			if (!is_del_list &&
8971 			    mac_cfg->state == HCLGE_MAC_ACTIVE) {
8972 				mac_cfg->state = HCLGE_MAC_TO_ADD;
8973 			} else {
8974 				list_del(&mac_cfg->node);
8975 				kfree(mac_cfg);
8976 			}
8977 		} else if (is_del_list) {
8978 			mac_cfg->state = HCLGE_MAC_TO_DEL;
8979 		}
8980 	}
8981 }
8982 
8983 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
8984 				  enum HCLGE_MAC_ADDR_TYPE mac_type)
8985 {
8986 	int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
8987 	struct hclge_dev *hdev = vport->back;
8988 	struct list_head tmp_del_list, *list;
8989 
8990 	if (mac_type == HCLGE_MAC_ADDR_UC) {
8991 		list = &vport->uc_mac_list;
8992 		unsync = hclge_rm_uc_addr_common;
8993 	} else {
8994 		list = &vport->mc_mac_list;
8995 		unsync = hclge_rm_mc_addr_common;
8996 	}
8997 
8998 	INIT_LIST_HEAD(&tmp_del_list);
8999 
9000 	if (!is_del_list)
9001 		set_bit(vport->vport_id, hdev->vport_config_block);
9002 
9003 	spin_lock_bh(&vport->mac_list_lock);
9004 
9005 	hclge_build_del_list(list, is_del_list, &tmp_del_list);
9006 
9007 	spin_unlock_bh(&vport->mac_list_lock);
9008 
9009 	hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list);
9010 
9011 	spin_lock_bh(&vport->mac_list_lock);
9012 
9013 	hclge_sync_from_del_list(&tmp_del_list, list);
9014 
9015 	spin_unlock_bh(&vport->mac_list_lock);
9016 }
9017 
9018 /* remove all mac address when uninitailize */
9019 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport,
9020 					enum HCLGE_MAC_ADDR_TYPE mac_type)
9021 {
9022 	struct hclge_mac_node *mac_node, *tmp;
9023 	struct hclge_dev *hdev = vport->back;
9024 	struct list_head tmp_del_list, *list;
9025 
9026 	INIT_LIST_HEAD(&tmp_del_list);
9027 
9028 	list = (mac_type == HCLGE_MAC_ADDR_UC) ?
9029 		&vport->uc_mac_list : &vport->mc_mac_list;
9030 
9031 	spin_lock_bh(&vport->mac_list_lock);
9032 
9033 	list_for_each_entry_safe(mac_node, tmp, list, node) {
9034 		switch (mac_node->state) {
9035 		case HCLGE_MAC_TO_DEL:
9036 		case HCLGE_MAC_ACTIVE:
9037 			list_move_tail(&mac_node->node, &tmp_del_list);
9038 			break;
9039 		case HCLGE_MAC_TO_ADD:
9040 			list_del(&mac_node->node);
9041 			kfree(mac_node);
9042 			break;
9043 		}
9044 	}
9045 
9046 	spin_unlock_bh(&vport->mac_list_lock);
9047 
9048 	hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
9049 
9050 	if (!list_empty(&tmp_del_list))
9051 		dev_warn(&hdev->pdev->dev,
9052 			 "uninit %s mac list for vport %u not completely.\n",
9053 			 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc",
9054 			 vport->vport_id);
9055 
9056 	list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) {
9057 		list_del(&mac_node->node);
9058 		kfree(mac_node);
9059 	}
9060 }
9061 
9062 static void hclge_uninit_mac_table(struct hclge_dev *hdev)
9063 {
9064 	struct hclge_vport *vport;
9065 	int i;
9066 
9067 	for (i = 0; i < hdev->num_alloc_vport; i++) {
9068 		vport = &hdev->vport[i];
9069 		hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC);
9070 		hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC);
9071 	}
9072 }
9073 
9074 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
9075 					      u16 cmdq_resp, u8 resp_code)
9076 {
9077 #define HCLGE_ETHERTYPE_SUCCESS_ADD		0
9078 #define HCLGE_ETHERTYPE_ALREADY_ADD		1
9079 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW	2
9080 #define HCLGE_ETHERTYPE_KEY_CONFLICT		3
9081 
9082 	int return_status;
9083 
9084 	if (cmdq_resp) {
9085 		dev_err(&hdev->pdev->dev,
9086 			"cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
9087 			cmdq_resp);
9088 		return -EIO;
9089 	}
9090 
9091 	switch (resp_code) {
9092 	case HCLGE_ETHERTYPE_SUCCESS_ADD:
9093 	case HCLGE_ETHERTYPE_ALREADY_ADD:
9094 		return_status = 0;
9095 		break;
9096 	case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
9097 		dev_err(&hdev->pdev->dev,
9098 			"add mac ethertype failed for manager table overflow.\n");
9099 		return_status = -EIO;
9100 		break;
9101 	case HCLGE_ETHERTYPE_KEY_CONFLICT:
9102 		dev_err(&hdev->pdev->dev,
9103 			"add mac ethertype failed for key conflict.\n");
9104 		return_status = -EIO;
9105 		break;
9106 	default:
9107 		dev_err(&hdev->pdev->dev,
9108 			"add mac ethertype failed for undefined, code=%u.\n",
9109 			resp_code);
9110 		return_status = -EIO;
9111 	}
9112 
9113 	return return_status;
9114 }
9115 
9116 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf,
9117 			    u8 *mac_addr)
9118 {
9119 	struct hclge_vport *vport = hclge_get_vport(handle);
9120 	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
9121 	struct hclge_dev *hdev = vport->back;
9122 
9123 	vport = hclge_get_vf_vport(hdev, vf);
9124 	if (!vport)
9125 		return -EINVAL;
9126 
9127 	hnae3_format_mac_addr(format_mac_addr, mac_addr);
9128 	if (ether_addr_equal(mac_addr, vport->vf_info.mac)) {
9129 		dev_info(&hdev->pdev->dev,
9130 			 "Specified MAC(=%s) is same as before, no change committed!\n",
9131 			 format_mac_addr);
9132 		return 0;
9133 	}
9134 
9135 	ether_addr_copy(vport->vf_info.mac, mac_addr);
9136 
9137 	/* there is a timewindow for PF to know VF unalive, it may
9138 	 * cause send mailbox fail, but it doesn't matter, VF will
9139 	 * query it when reinit.
9140 	 */
9141 	if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) {
9142 		dev_info(&hdev->pdev->dev,
9143 			 "MAC of VF %d has been set to %s, and it will be reinitialized!\n",
9144 			 vf, format_mac_addr);
9145 		(void)hclge_inform_reset_assert_to_vf(vport);
9146 		return 0;
9147 	}
9148 
9149 	dev_info(&hdev->pdev->dev,
9150 		 "MAC of VF %d has been set to %s, will be active after VF reset\n",
9151 		 vf, format_mac_addr);
9152 	return 0;
9153 }
9154 
9155 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
9156 			     const struct hclge_mac_mgr_tbl_entry_cmd *req)
9157 {
9158 	struct hclge_desc desc;
9159 	u8 resp_code;
9160 	u16 retval;
9161 	int ret;
9162 
9163 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
9164 	memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
9165 
9166 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9167 	if (ret) {
9168 		dev_err(&hdev->pdev->dev,
9169 			"add mac ethertype failed for cmd_send, ret =%d.\n",
9170 			ret);
9171 		return ret;
9172 	}
9173 
9174 	resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
9175 	retval = le16_to_cpu(desc.retval);
9176 
9177 	return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
9178 }
9179 
9180 static int init_mgr_tbl(struct hclge_dev *hdev)
9181 {
9182 	int ret;
9183 	int i;
9184 
9185 	for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
9186 		ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
9187 		if (ret) {
9188 			dev_err(&hdev->pdev->dev,
9189 				"add mac ethertype failed, ret =%d.\n",
9190 				ret);
9191 			return ret;
9192 		}
9193 	}
9194 
9195 	return 0;
9196 }
9197 
9198 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
9199 {
9200 	struct hclge_vport *vport = hclge_get_vport(handle);
9201 	struct hclge_dev *hdev = vport->back;
9202 
9203 	ether_addr_copy(p, hdev->hw.mac.mac_addr);
9204 }
9205 
9206 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
9207 				       const u8 *old_addr, const u8 *new_addr)
9208 {
9209 	struct list_head *list = &vport->uc_mac_list;
9210 	struct hclge_mac_node *old_node, *new_node;
9211 
9212 	new_node = hclge_find_mac_node(list, new_addr);
9213 	if (!new_node) {
9214 		new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
9215 		if (!new_node)
9216 			return -ENOMEM;
9217 
9218 		new_node->state = HCLGE_MAC_TO_ADD;
9219 		ether_addr_copy(new_node->mac_addr, new_addr);
9220 		list_add(&new_node->node, list);
9221 	} else {
9222 		if (new_node->state == HCLGE_MAC_TO_DEL)
9223 			new_node->state = HCLGE_MAC_ACTIVE;
9224 
9225 		/* make sure the new addr is in the list head, avoid dev
9226 		 * addr may be not re-added into mac table for the umv space
9227 		 * limitation after global/imp reset which will clear mac
9228 		 * table by hardware.
9229 		 */
9230 		list_move(&new_node->node, list);
9231 	}
9232 
9233 	if (old_addr && !ether_addr_equal(old_addr, new_addr)) {
9234 		old_node = hclge_find_mac_node(list, old_addr);
9235 		if (old_node) {
9236 			if (old_node->state == HCLGE_MAC_TO_ADD) {
9237 				list_del(&old_node->node);
9238 				kfree(old_node);
9239 			} else {
9240 				old_node->state = HCLGE_MAC_TO_DEL;
9241 			}
9242 		}
9243 	}
9244 
9245 	set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
9246 
9247 	return 0;
9248 }
9249 
9250 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p,
9251 			      bool is_first)
9252 {
9253 	const unsigned char *new_addr = (const unsigned char *)p;
9254 	struct hclge_vport *vport = hclge_get_vport(handle);
9255 	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
9256 	struct hclge_dev *hdev = vport->back;
9257 	unsigned char *old_addr = NULL;
9258 	int ret;
9259 
9260 	/* mac addr check */
9261 	if (is_zero_ether_addr(new_addr) ||
9262 	    is_broadcast_ether_addr(new_addr) ||
9263 	    is_multicast_ether_addr(new_addr)) {
9264 		hnae3_format_mac_addr(format_mac_addr, new_addr);
9265 		dev_err(&hdev->pdev->dev,
9266 			"change uc mac err! invalid mac: %s.\n",
9267 			 format_mac_addr);
9268 		return -EINVAL;
9269 	}
9270 
9271 	ret = hclge_pause_addr_cfg(hdev, new_addr);
9272 	if (ret) {
9273 		dev_err(&hdev->pdev->dev,
9274 			"failed to configure mac pause address, ret = %d\n",
9275 			ret);
9276 		return ret;
9277 	}
9278 
9279 	if (!is_first)
9280 		old_addr = hdev->hw.mac.mac_addr;
9281 
9282 	spin_lock_bh(&vport->mac_list_lock);
9283 	ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr);
9284 	if (ret) {
9285 		hnae3_format_mac_addr(format_mac_addr, new_addr);
9286 		dev_err(&hdev->pdev->dev,
9287 			"failed to change the mac addr:%s, ret = %d\n",
9288 			format_mac_addr, ret);
9289 		spin_unlock_bh(&vport->mac_list_lock);
9290 
9291 		if (!is_first)
9292 			hclge_pause_addr_cfg(hdev, old_addr);
9293 
9294 		return ret;
9295 	}
9296 	/* we must update dev addr with spin lock protect, preventing dev addr
9297 	 * being removed by set_rx_mode path.
9298 	 */
9299 	ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
9300 	spin_unlock_bh(&vport->mac_list_lock);
9301 
9302 	hclge_task_schedule(hdev, 0);
9303 
9304 	return 0;
9305 }
9306 
9307 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd)
9308 {
9309 	struct mii_ioctl_data *data = if_mii(ifr);
9310 
9311 	if (!hnae3_dev_phy_imp_supported(hdev))
9312 		return -EOPNOTSUPP;
9313 
9314 	switch (cmd) {
9315 	case SIOCGMIIPHY:
9316 		data->phy_id = hdev->hw.mac.phy_addr;
9317 		/* this command reads phy id and register at the same time */
9318 		fallthrough;
9319 	case SIOCGMIIREG:
9320 		data->val_out = hclge_read_phy_reg(hdev, data->reg_num);
9321 		return 0;
9322 
9323 	case SIOCSMIIREG:
9324 		return hclge_write_phy_reg(hdev, data->reg_num, data->val_in);
9325 	default:
9326 		return -EOPNOTSUPP;
9327 	}
9328 }
9329 
9330 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
9331 			  int cmd)
9332 {
9333 	struct hclge_vport *vport = hclge_get_vport(handle);
9334 	struct hclge_dev *hdev = vport->back;
9335 
9336 	switch (cmd) {
9337 	case SIOCGHWTSTAMP:
9338 		return hclge_ptp_get_cfg(hdev, ifr);
9339 	case SIOCSHWTSTAMP:
9340 		return hclge_ptp_set_cfg(hdev, ifr);
9341 	default:
9342 		if (!hdev->hw.mac.phydev)
9343 			return hclge_mii_ioctl(hdev, ifr, cmd);
9344 	}
9345 
9346 	return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
9347 }
9348 
9349 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id,
9350 					     bool bypass_en)
9351 {
9352 	struct hclge_port_vlan_filter_bypass_cmd *req;
9353 	struct hclge_desc desc;
9354 	int ret;
9355 
9356 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false);
9357 	req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data;
9358 	req->vf_id = vf_id;
9359 	hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B,
9360 		      bypass_en ? 1 : 0);
9361 
9362 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9363 	if (ret)
9364 		dev_err(&hdev->pdev->dev,
9365 			"failed to set vport%u port vlan filter bypass state, ret = %d.\n",
9366 			vf_id, ret);
9367 
9368 	return ret;
9369 }
9370 
9371 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
9372 				      u8 fe_type, bool filter_en, u8 vf_id)
9373 {
9374 	struct hclge_vlan_filter_ctrl_cmd *req;
9375 	struct hclge_desc desc;
9376 	int ret;
9377 
9378 	/* read current vlan filter parameter */
9379 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true);
9380 	req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
9381 	req->vlan_type = vlan_type;
9382 	req->vf_id = vf_id;
9383 
9384 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9385 	if (ret) {
9386 		dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n",
9387 			vf_id, ret);
9388 		return ret;
9389 	}
9390 
9391 	/* modify and write new config parameter */
9392 	hclge_comm_cmd_reuse_desc(&desc, false);
9393 	req->vlan_fe = filter_en ?
9394 			(req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type);
9395 
9396 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9397 	if (ret)
9398 		dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n",
9399 			vf_id, ret);
9400 
9401 	return ret;
9402 }
9403 
9404 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable)
9405 {
9406 	struct hclge_dev *hdev = vport->back;
9407 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
9408 	int ret;
9409 
9410 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
9411 		return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9412 						  HCLGE_FILTER_FE_EGRESS_V1_B,
9413 						  enable, vport->vport_id);
9414 
9415 	ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9416 					 HCLGE_FILTER_FE_EGRESS, enable,
9417 					 vport->vport_id);
9418 	if (ret)
9419 		return ret;
9420 
9421 	if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) {
9422 		ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id,
9423 							!enable);
9424 	} else if (!vport->vport_id) {
9425 		if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
9426 			enable = false;
9427 
9428 		ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
9429 						 HCLGE_FILTER_FE_INGRESS,
9430 						 enable, 0);
9431 	}
9432 
9433 	return ret;
9434 }
9435 
9436 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport)
9437 {
9438 	struct hnae3_handle *handle = &vport->nic;
9439 	struct hclge_vport_vlan_cfg *vlan, *tmp;
9440 	struct hclge_dev *hdev = vport->back;
9441 
9442 	if (vport->vport_id) {
9443 		if (vport->port_base_vlan_cfg.state !=
9444 			HNAE3_PORT_BASE_VLAN_DISABLE)
9445 			return true;
9446 
9447 		if (vport->vf_info.trusted && vport->vf_info.request_uc_en)
9448 			return false;
9449 	} else if (handle->netdev_flags & HNAE3_USER_UPE) {
9450 		return false;
9451 	}
9452 
9453 	if (!vport->req_vlan_fltr_en)
9454 		return false;
9455 
9456 	/* compatible with former device, always enable vlan filter */
9457 	if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
9458 		return true;
9459 
9460 	list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node)
9461 		if (vlan->vlan_id != 0)
9462 			return true;
9463 
9464 	return false;
9465 }
9466 
9467 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en)
9468 {
9469 	struct hclge_dev *hdev = vport->back;
9470 	bool need_en;
9471 	int ret;
9472 
9473 	mutex_lock(&hdev->vport_lock);
9474 
9475 	vport->req_vlan_fltr_en = request_en;
9476 
9477 	need_en = hclge_need_enable_vport_vlan_filter(vport);
9478 	if (need_en == vport->cur_vlan_fltr_en) {
9479 		mutex_unlock(&hdev->vport_lock);
9480 		return 0;
9481 	}
9482 
9483 	ret = hclge_set_vport_vlan_filter(vport, need_en);
9484 	if (ret) {
9485 		mutex_unlock(&hdev->vport_lock);
9486 		return ret;
9487 	}
9488 
9489 	vport->cur_vlan_fltr_en = need_en;
9490 
9491 	mutex_unlock(&hdev->vport_lock);
9492 
9493 	return 0;
9494 }
9495 
9496 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
9497 {
9498 	struct hclge_vport *vport = hclge_get_vport(handle);
9499 
9500 	return hclge_enable_vport_vlan_filter(vport, enable);
9501 }
9502 
9503 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid,
9504 					bool is_kill, u16 vlan,
9505 					struct hclge_desc *desc)
9506 {
9507 	struct hclge_vlan_filter_vf_cfg_cmd *req0;
9508 	struct hclge_vlan_filter_vf_cfg_cmd *req1;
9509 	u8 vf_byte_val;
9510 	u8 vf_byte_off;
9511 	int ret;
9512 
9513 	hclge_cmd_setup_basic_desc(&desc[0],
9514 				   HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9515 	hclge_cmd_setup_basic_desc(&desc[1],
9516 				   HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9517 
9518 	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
9519 
9520 	vf_byte_off = vfid / 8;
9521 	vf_byte_val = 1 << (vfid % 8);
9522 
9523 	req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9524 	req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
9525 
9526 	req0->vlan_id  = cpu_to_le16(vlan);
9527 	req0->vlan_cfg = is_kill;
9528 
9529 	if (vf_byte_off < HCLGE_MAX_VF_BYTES)
9530 		req0->vf_bitmap[vf_byte_off] = vf_byte_val;
9531 	else
9532 		req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
9533 
9534 	ret = hclge_cmd_send(&hdev->hw, desc, 2);
9535 	if (ret) {
9536 		dev_err(&hdev->pdev->dev,
9537 			"Send vf vlan command fail, ret =%d.\n",
9538 			ret);
9539 		return ret;
9540 	}
9541 
9542 	return 0;
9543 }
9544 
9545 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid,
9546 					  bool is_kill, struct hclge_desc *desc)
9547 {
9548 	struct hclge_vlan_filter_vf_cfg_cmd *req;
9549 
9550 	req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9551 
9552 	if (!is_kill) {
9553 #define HCLGE_VF_VLAN_NO_ENTRY	2
9554 		if (!req->resp_code || req->resp_code == 1)
9555 			return 0;
9556 
9557 		if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
9558 			set_bit(vfid, hdev->vf_vlan_full);
9559 			dev_warn(&hdev->pdev->dev,
9560 				 "vf vlan table is full, vf vlan filter is disabled\n");
9561 			return 0;
9562 		}
9563 
9564 		dev_err(&hdev->pdev->dev,
9565 			"Add vf vlan filter fail, ret =%u.\n",
9566 			req->resp_code);
9567 	} else {
9568 #define HCLGE_VF_VLAN_DEL_NO_FOUND	1
9569 		if (!req->resp_code)
9570 			return 0;
9571 
9572 		/* vf vlan filter is disabled when vf vlan table is full,
9573 		 * then new vlan id will not be added into vf vlan table.
9574 		 * Just return 0 without warning, avoid massive verbose
9575 		 * print logs when unload.
9576 		 */
9577 		if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND)
9578 			return 0;
9579 
9580 		dev_err(&hdev->pdev->dev,
9581 			"Kill vf vlan filter fail, ret =%u.\n",
9582 			req->resp_code);
9583 	}
9584 
9585 	return -EIO;
9586 }
9587 
9588 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
9589 				    bool is_kill, u16 vlan)
9590 {
9591 	struct hclge_vport *vport = &hdev->vport[vfid];
9592 	struct hclge_desc desc[2];
9593 	int ret;
9594 
9595 	/* if vf vlan table is full, firmware will close vf vlan filter, it
9596 	 * is unable and unnecessary to add new vlan id to vf vlan filter.
9597 	 * If spoof check is enable, and vf vlan is full, it shouldn't add
9598 	 * new vlan, because tx packets with these vlan id will be dropped.
9599 	 */
9600 	if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) {
9601 		if (vport->vf_info.spoofchk && vlan) {
9602 			dev_err(&hdev->pdev->dev,
9603 				"Can't add vlan due to spoof check is on and vf vlan table is full\n");
9604 			return -EPERM;
9605 		}
9606 		return 0;
9607 	}
9608 
9609 	ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc);
9610 	if (ret)
9611 		return ret;
9612 
9613 	return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc);
9614 }
9615 
9616 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
9617 				      u16 vlan_id, bool is_kill)
9618 {
9619 	struct hclge_vlan_filter_pf_cfg_cmd *req;
9620 	struct hclge_desc desc;
9621 	u8 vlan_offset_byte_val;
9622 	u8 vlan_offset_byte;
9623 	u8 vlan_offset_160;
9624 	int ret;
9625 
9626 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
9627 
9628 	vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP;
9629 	vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) /
9630 			   HCLGE_VLAN_BYTE_SIZE;
9631 	vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE);
9632 
9633 	req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
9634 	req->vlan_offset = vlan_offset_160;
9635 	req->vlan_cfg = is_kill;
9636 	req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
9637 
9638 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9639 	if (ret)
9640 		dev_err(&hdev->pdev->dev,
9641 			"port vlan command, send fail, ret =%d.\n", ret);
9642 	return ret;
9643 }
9644 
9645 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id,
9646 					u16 vlan_id, bool is_kill)
9647 {
9648 	/* vlan 0 may be added twice when 8021q module is enabled */
9649 	if (!is_kill && !vlan_id &&
9650 	    test_bit(vport_id, hdev->vlan_table[vlan_id]))
9651 		return false;
9652 
9653 	if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
9654 		dev_warn(&hdev->pdev->dev,
9655 			 "Add port vlan failed, vport %u is already in vlan %u\n",
9656 			 vport_id, vlan_id);
9657 		return false;
9658 	}
9659 
9660 	if (is_kill &&
9661 	    !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
9662 		dev_warn(&hdev->pdev->dev,
9663 			 "Delete port vlan failed, vport %u is not in vlan %u\n",
9664 			 vport_id, vlan_id);
9665 		return false;
9666 	}
9667 
9668 	return true;
9669 }
9670 
9671 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
9672 				    u16 vport_id, u16 vlan_id,
9673 				    bool is_kill)
9674 {
9675 	u16 vport_idx, vport_num = 0;
9676 	int ret;
9677 
9678 	if (is_kill && !vlan_id)
9679 		return 0;
9680 
9681 	if (vlan_id >= VLAN_N_VID)
9682 		return -EINVAL;
9683 
9684 	ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id);
9685 	if (ret) {
9686 		dev_err(&hdev->pdev->dev,
9687 			"Set %u vport vlan filter config fail, ret =%d.\n",
9688 			vport_id, ret);
9689 		return ret;
9690 	}
9691 
9692 	if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill))
9693 		return 0;
9694 
9695 	for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
9696 		vport_num++;
9697 
9698 	if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
9699 		ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
9700 						 is_kill);
9701 
9702 	return ret;
9703 }
9704 
9705 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
9706 {
9707 	struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
9708 	struct hclge_vport_vtag_tx_cfg_cmd *req;
9709 	struct hclge_dev *hdev = vport->back;
9710 	struct hclge_desc desc;
9711 	u16 bmap_index;
9712 	int status;
9713 
9714 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
9715 
9716 	req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
9717 	req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
9718 	req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
9719 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
9720 		      vcfg->accept_tag1 ? 1 : 0);
9721 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
9722 		      vcfg->accept_untag1 ? 1 : 0);
9723 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
9724 		      vcfg->accept_tag2 ? 1 : 0);
9725 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
9726 		      vcfg->accept_untag2 ? 1 : 0);
9727 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
9728 		      vcfg->insert_tag1_en ? 1 : 0);
9729 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
9730 		      vcfg->insert_tag2_en ? 1 : 0);
9731 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B,
9732 		      vcfg->tag_shift_mode_en ? 1 : 0);
9733 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
9734 
9735 	req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9736 	bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9737 			HCLGE_VF_NUM_PER_BYTE;
9738 	req->vf_bitmap[bmap_index] =
9739 		1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9740 
9741 	status = hclge_cmd_send(&hdev->hw, &desc, 1);
9742 	if (status)
9743 		dev_err(&hdev->pdev->dev,
9744 			"Send port txvlan cfg command fail, ret =%d\n",
9745 			status);
9746 
9747 	return status;
9748 }
9749 
9750 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
9751 {
9752 	struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
9753 	struct hclge_vport_vtag_rx_cfg_cmd *req;
9754 	struct hclge_dev *hdev = vport->back;
9755 	struct hclge_desc desc;
9756 	u16 bmap_index;
9757 	int status;
9758 
9759 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
9760 
9761 	req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
9762 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
9763 		      vcfg->strip_tag1_en ? 1 : 0);
9764 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
9765 		      vcfg->strip_tag2_en ? 1 : 0);
9766 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
9767 		      vcfg->vlan1_vlan_prionly ? 1 : 0);
9768 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
9769 		      vcfg->vlan2_vlan_prionly ? 1 : 0);
9770 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B,
9771 		      vcfg->strip_tag1_discard_en ? 1 : 0);
9772 	hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B,
9773 		      vcfg->strip_tag2_discard_en ? 1 : 0);
9774 
9775 	req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9776 	bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9777 			HCLGE_VF_NUM_PER_BYTE;
9778 	req->vf_bitmap[bmap_index] =
9779 		1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9780 
9781 	status = hclge_cmd_send(&hdev->hw, &desc, 1);
9782 	if (status)
9783 		dev_err(&hdev->pdev->dev,
9784 			"Send port rxvlan cfg command fail, ret =%d\n",
9785 			status);
9786 
9787 	return status;
9788 }
9789 
9790 static int hclge_vlan_offload_cfg(struct hclge_vport *vport,
9791 				  u16 port_base_vlan_state,
9792 				  u16 vlan_tag, u8 qos)
9793 {
9794 	int ret;
9795 
9796 	if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9797 		vport->txvlan_cfg.accept_tag1 = true;
9798 		vport->txvlan_cfg.insert_tag1_en = false;
9799 		vport->txvlan_cfg.default_tag1 = 0;
9800 	} else {
9801 		struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev);
9802 
9803 		vport->txvlan_cfg.accept_tag1 =
9804 			ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3;
9805 		vport->txvlan_cfg.insert_tag1_en = true;
9806 		vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) |
9807 						 vlan_tag;
9808 	}
9809 
9810 	vport->txvlan_cfg.accept_untag1 = true;
9811 
9812 	/* accept_tag2 and accept_untag2 are not supported on
9813 	 * pdev revision(0x20), new revision support them,
9814 	 * this two fields can not be configured by user.
9815 	 */
9816 	vport->txvlan_cfg.accept_tag2 = true;
9817 	vport->txvlan_cfg.accept_untag2 = true;
9818 	vport->txvlan_cfg.insert_tag2_en = false;
9819 	vport->txvlan_cfg.default_tag2 = 0;
9820 	vport->txvlan_cfg.tag_shift_mode_en = true;
9821 
9822 	if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9823 		vport->rxvlan_cfg.strip_tag1_en = false;
9824 		vport->rxvlan_cfg.strip_tag2_en =
9825 				vport->rxvlan_cfg.rx_vlan_offload_en;
9826 		vport->rxvlan_cfg.strip_tag2_discard_en = false;
9827 	} else {
9828 		vport->rxvlan_cfg.strip_tag1_en =
9829 				vport->rxvlan_cfg.rx_vlan_offload_en;
9830 		vport->rxvlan_cfg.strip_tag2_en = true;
9831 		vport->rxvlan_cfg.strip_tag2_discard_en = true;
9832 	}
9833 
9834 	vport->rxvlan_cfg.strip_tag1_discard_en = false;
9835 	vport->rxvlan_cfg.vlan1_vlan_prionly = false;
9836 	vport->rxvlan_cfg.vlan2_vlan_prionly = false;
9837 
9838 	ret = hclge_set_vlan_tx_offload_cfg(vport);
9839 	if (ret)
9840 		return ret;
9841 
9842 	return hclge_set_vlan_rx_offload_cfg(vport);
9843 }
9844 
9845 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
9846 {
9847 	struct hclge_rx_vlan_type_cfg_cmd *rx_req;
9848 	struct hclge_tx_vlan_type_cfg_cmd *tx_req;
9849 	struct hclge_desc desc;
9850 	int status;
9851 
9852 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
9853 	rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
9854 	rx_req->ot_fst_vlan_type =
9855 		cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
9856 	rx_req->ot_sec_vlan_type =
9857 		cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
9858 	rx_req->in_fst_vlan_type =
9859 		cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
9860 	rx_req->in_sec_vlan_type =
9861 		cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
9862 
9863 	status = hclge_cmd_send(&hdev->hw, &desc, 1);
9864 	if (status) {
9865 		dev_err(&hdev->pdev->dev,
9866 			"Send rxvlan protocol type command fail, ret =%d\n",
9867 			status);
9868 		return status;
9869 	}
9870 
9871 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
9872 
9873 	tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
9874 	tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
9875 	tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
9876 
9877 	status = hclge_cmd_send(&hdev->hw, &desc, 1);
9878 	if (status)
9879 		dev_err(&hdev->pdev->dev,
9880 			"Send txvlan protocol type command fail, ret =%d\n",
9881 			status);
9882 
9883 	return status;
9884 }
9885 
9886 static int hclge_init_vlan_filter(struct hclge_dev *hdev)
9887 {
9888 	struct hclge_vport *vport;
9889 	int ret;
9890 	int i;
9891 
9892 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
9893 		return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9894 						  HCLGE_FILTER_FE_EGRESS_V1_B,
9895 						  true, 0);
9896 
9897 	/* for revision 0x21, vf vlan filter is per function */
9898 	for (i = 0; i < hdev->num_alloc_vport; i++) {
9899 		vport = &hdev->vport[i];
9900 		ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9901 						 HCLGE_FILTER_FE_EGRESS, true,
9902 						 vport->vport_id);
9903 		if (ret)
9904 			return ret;
9905 		vport->cur_vlan_fltr_en = true;
9906 	}
9907 
9908 	return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
9909 					  HCLGE_FILTER_FE_INGRESS, true, 0);
9910 }
9911 
9912 static int hclge_init_vlan_type(struct hclge_dev *hdev)
9913 {
9914 	hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q;
9915 	hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q;
9916 	hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q;
9917 	hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q;
9918 	hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q;
9919 	hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q;
9920 
9921 	return hclge_set_vlan_protocol_type(hdev);
9922 }
9923 
9924 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev)
9925 {
9926 	struct hclge_port_base_vlan_config *cfg;
9927 	struct hclge_vport *vport;
9928 	int ret;
9929 	int i;
9930 
9931 	for (i = 0; i < hdev->num_alloc_vport; i++) {
9932 		vport = &hdev->vport[i];
9933 		cfg = &vport->port_base_vlan_cfg;
9934 
9935 		ret = hclge_vlan_offload_cfg(vport, cfg->state,
9936 					     cfg->vlan_info.vlan_tag,
9937 					     cfg->vlan_info.qos);
9938 		if (ret)
9939 			return ret;
9940 	}
9941 	return 0;
9942 }
9943 
9944 static int hclge_init_vlan_config(struct hclge_dev *hdev)
9945 {
9946 	struct hnae3_handle *handle = &hdev->vport[0].nic;
9947 	int ret;
9948 
9949 	ret = hclge_init_vlan_filter(hdev);
9950 	if (ret)
9951 		return ret;
9952 
9953 	ret = hclge_init_vlan_type(hdev);
9954 	if (ret)
9955 		return ret;
9956 
9957 	ret = hclge_init_vport_vlan_offload(hdev);
9958 	if (ret)
9959 		return ret;
9960 
9961 	return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
9962 }
9963 
9964 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
9965 				       bool writen_to_tbl)
9966 {
9967 	struct hclge_vport_vlan_cfg *vlan, *tmp;
9968 	struct hclge_dev *hdev = vport->back;
9969 
9970 	mutex_lock(&hdev->vport_lock);
9971 
9972 	list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
9973 		if (vlan->vlan_id == vlan_id) {
9974 			mutex_unlock(&hdev->vport_lock);
9975 			return;
9976 		}
9977 	}
9978 
9979 	vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
9980 	if (!vlan) {
9981 		mutex_unlock(&hdev->vport_lock);
9982 		return;
9983 	}
9984 
9985 	vlan->hd_tbl_status = writen_to_tbl;
9986 	vlan->vlan_id = vlan_id;
9987 
9988 	list_add_tail(&vlan->node, &vport->vlan_list);
9989 	mutex_unlock(&hdev->vport_lock);
9990 }
9991 
9992 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport)
9993 {
9994 	struct hclge_vport_vlan_cfg *vlan, *tmp;
9995 	struct hclge_dev *hdev = vport->back;
9996 	int ret;
9997 
9998 	mutex_lock(&hdev->vport_lock);
9999 
10000 	list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10001 		if (!vlan->hd_tbl_status) {
10002 			ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10003 						       vport->vport_id,
10004 						       vlan->vlan_id, false);
10005 			if (ret) {
10006 				dev_err(&hdev->pdev->dev,
10007 					"restore vport vlan list failed, ret=%d\n",
10008 					ret);
10009 
10010 				mutex_unlock(&hdev->vport_lock);
10011 				return ret;
10012 			}
10013 		}
10014 		vlan->hd_tbl_status = true;
10015 	}
10016 
10017 	mutex_unlock(&hdev->vport_lock);
10018 
10019 	return 0;
10020 }
10021 
10022 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
10023 				      bool is_write_tbl)
10024 {
10025 	struct hclge_vport_vlan_cfg *vlan, *tmp;
10026 	struct hclge_dev *hdev = vport->back;
10027 
10028 	mutex_lock(&hdev->vport_lock);
10029 
10030 	list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10031 		if (vlan->vlan_id == vlan_id) {
10032 			if (is_write_tbl && vlan->hd_tbl_status)
10033 				hclge_set_vlan_filter_hw(hdev,
10034 							 htons(ETH_P_8021Q),
10035 							 vport->vport_id,
10036 							 vlan_id,
10037 							 true);
10038 
10039 			list_del(&vlan->node);
10040 			kfree(vlan);
10041 			break;
10042 		}
10043 	}
10044 
10045 	mutex_unlock(&hdev->vport_lock);
10046 }
10047 
10048 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list)
10049 {
10050 	struct hclge_vport_vlan_cfg *vlan, *tmp;
10051 	struct hclge_dev *hdev = vport->back;
10052 
10053 	mutex_lock(&hdev->vport_lock);
10054 
10055 	list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10056 		if (vlan->hd_tbl_status)
10057 			hclge_set_vlan_filter_hw(hdev,
10058 						 htons(ETH_P_8021Q),
10059 						 vport->vport_id,
10060 						 vlan->vlan_id,
10061 						 true);
10062 
10063 		vlan->hd_tbl_status = false;
10064 		if (is_del_list) {
10065 			list_del(&vlan->node);
10066 			kfree(vlan);
10067 		}
10068 	}
10069 	clear_bit(vport->vport_id, hdev->vf_vlan_full);
10070 	mutex_unlock(&hdev->vport_lock);
10071 }
10072 
10073 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev)
10074 {
10075 	struct hclge_vport_vlan_cfg *vlan, *tmp;
10076 	struct hclge_vport *vport;
10077 	int i;
10078 
10079 	mutex_lock(&hdev->vport_lock);
10080 
10081 	for (i = 0; i < hdev->num_alloc_vport; i++) {
10082 		vport = &hdev->vport[i];
10083 		list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10084 			list_del(&vlan->node);
10085 			kfree(vlan);
10086 		}
10087 	}
10088 
10089 	mutex_unlock(&hdev->vport_lock);
10090 }
10091 
10092 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev)
10093 {
10094 	struct hclge_vlan_info *vlan_info;
10095 	struct hclge_vport *vport;
10096 	u16 vlan_proto;
10097 	u16 vlan_id;
10098 	u16 state;
10099 	int vf_id;
10100 	int ret;
10101 
10102 	/* PF should restore all vfs port base vlan */
10103 	for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) {
10104 		vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM];
10105 		vlan_info = vport->port_base_vlan_cfg.tbl_sta ?
10106 			    &vport->port_base_vlan_cfg.vlan_info :
10107 			    &vport->port_base_vlan_cfg.old_vlan_info;
10108 
10109 		vlan_id = vlan_info->vlan_tag;
10110 		vlan_proto = vlan_info->vlan_proto;
10111 		state = vport->port_base_vlan_cfg.state;
10112 
10113 		if (state != HNAE3_PORT_BASE_VLAN_DISABLE) {
10114 			clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]);
10115 			ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto),
10116 						       vport->vport_id,
10117 						       vlan_id, false);
10118 			vport->port_base_vlan_cfg.tbl_sta = ret == 0;
10119 		}
10120 	}
10121 }
10122 
10123 void hclge_restore_vport_vlan_table(struct hclge_vport *vport)
10124 {
10125 	struct hclge_vport_vlan_cfg *vlan, *tmp;
10126 	struct hclge_dev *hdev = vport->back;
10127 	int ret;
10128 
10129 	mutex_lock(&hdev->vport_lock);
10130 
10131 	if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10132 		list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10133 			ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10134 						       vport->vport_id,
10135 						       vlan->vlan_id, false);
10136 			if (ret)
10137 				break;
10138 			vlan->hd_tbl_status = true;
10139 		}
10140 	}
10141 
10142 	mutex_unlock(&hdev->vport_lock);
10143 }
10144 
10145 /* For global reset and imp reset, hardware will clear the mac table,
10146  * so we change the mac address state from ACTIVE to TO_ADD, then they
10147  * can be restored in the service task after reset complete. Furtherly,
10148  * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to
10149  * be restored after reset, so just remove these mac nodes from mac_list.
10150  */
10151 static void hclge_mac_node_convert_for_reset(struct list_head *list)
10152 {
10153 	struct hclge_mac_node *mac_node, *tmp;
10154 
10155 	list_for_each_entry_safe(mac_node, tmp, list, node) {
10156 		if (mac_node->state == HCLGE_MAC_ACTIVE) {
10157 			mac_node->state = HCLGE_MAC_TO_ADD;
10158 		} else if (mac_node->state == HCLGE_MAC_TO_DEL) {
10159 			list_del(&mac_node->node);
10160 			kfree(mac_node);
10161 		}
10162 	}
10163 }
10164 
10165 void hclge_restore_mac_table_common(struct hclge_vport *vport)
10166 {
10167 	spin_lock_bh(&vport->mac_list_lock);
10168 
10169 	hclge_mac_node_convert_for_reset(&vport->uc_mac_list);
10170 	hclge_mac_node_convert_for_reset(&vport->mc_mac_list);
10171 	set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
10172 
10173 	spin_unlock_bh(&vport->mac_list_lock);
10174 }
10175 
10176 static void hclge_restore_hw_table(struct hclge_dev *hdev)
10177 {
10178 	struct hclge_vport *vport = &hdev->vport[0];
10179 	struct hnae3_handle *handle = &vport->nic;
10180 
10181 	hclge_restore_mac_table_common(vport);
10182 	hclge_restore_vport_port_base_vlan_config(hdev);
10183 	hclge_restore_vport_vlan_table(vport);
10184 	set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
10185 	hclge_restore_fd_entries(handle);
10186 }
10187 
10188 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
10189 {
10190 	struct hclge_vport *vport = hclge_get_vport(handle);
10191 
10192 	if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10193 		vport->rxvlan_cfg.strip_tag1_en = false;
10194 		vport->rxvlan_cfg.strip_tag2_en = enable;
10195 		vport->rxvlan_cfg.strip_tag2_discard_en = false;
10196 	} else {
10197 		vport->rxvlan_cfg.strip_tag1_en = enable;
10198 		vport->rxvlan_cfg.strip_tag2_en = true;
10199 		vport->rxvlan_cfg.strip_tag2_discard_en = true;
10200 	}
10201 
10202 	vport->rxvlan_cfg.strip_tag1_discard_en = false;
10203 	vport->rxvlan_cfg.vlan1_vlan_prionly = false;
10204 	vport->rxvlan_cfg.vlan2_vlan_prionly = false;
10205 	vport->rxvlan_cfg.rx_vlan_offload_en = enable;
10206 
10207 	return hclge_set_vlan_rx_offload_cfg(vport);
10208 }
10209 
10210 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport)
10211 {
10212 	struct hclge_dev *hdev = vport->back;
10213 
10214 	if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
10215 		set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state);
10216 }
10217 
10218 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport,
10219 					    u16 port_base_vlan_state,
10220 					    struct hclge_vlan_info *new_info,
10221 					    struct hclge_vlan_info *old_info)
10222 {
10223 	struct hclge_dev *hdev = vport->back;
10224 	int ret;
10225 
10226 	if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) {
10227 		hclge_rm_vport_all_vlan_table(vport, false);
10228 		/* force clear VLAN 0 */
10229 		ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0);
10230 		if (ret)
10231 			return ret;
10232 		return hclge_set_vlan_filter_hw(hdev,
10233 						 htons(new_info->vlan_proto),
10234 						 vport->vport_id,
10235 						 new_info->vlan_tag,
10236 						 false);
10237 	}
10238 
10239 	vport->port_base_vlan_cfg.tbl_sta = false;
10240 
10241 	/* force add VLAN 0 */
10242 	ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0);
10243 	if (ret)
10244 		return ret;
10245 
10246 	ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto),
10247 				       vport->vport_id, old_info->vlan_tag,
10248 				       true);
10249 	if (ret)
10250 		return ret;
10251 
10252 	return hclge_add_vport_all_vlan_table(vport);
10253 }
10254 
10255 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg,
10256 					  const struct hclge_vlan_info *old_cfg)
10257 {
10258 	if (new_cfg->vlan_tag != old_cfg->vlan_tag)
10259 		return true;
10260 
10261 	if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0))
10262 		return true;
10263 
10264 	return false;
10265 }
10266 
10267 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport,
10268 					   struct hclge_vlan_info *new_info,
10269 					   struct hclge_vlan_info *old_info)
10270 {
10271 	struct hclge_dev *hdev = vport->back;
10272 	int ret;
10273 
10274 	/* add new VLAN tag */
10275 	ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto),
10276 				       vport->vport_id, new_info->vlan_tag,
10277 				       false);
10278 	if (ret)
10279 		return ret;
10280 
10281 	vport->port_base_vlan_cfg.tbl_sta = false;
10282 	/* remove old VLAN tag */
10283 	if (old_info->vlan_tag == 0)
10284 		ret = hclge_set_vf_vlan_common(hdev, vport->vport_id,
10285 					       true, 0);
10286 	else
10287 		ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10288 					       vport->vport_id,
10289 					       old_info->vlan_tag, true);
10290 	if (ret)
10291 		dev_err(&hdev->pdev->dev,
10292 			"failed to clear vport%u port base vlan %u, ret = %d.\n",
10293 			vport->vport_id, old_info->vlan_tag, ret);
10294 
10295 	return ret;
10296 }
10297 
10298 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
10299 				    struct hclge_vlan_info *vlan_info)
10300 {
10301 	struct hnae3_handle *nic = &vport->nic;
10302 	struct hclge_vlan_info *old_vlan_info;
10303 	int ret;
10304 
10305 	old_vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10306 
10307 	ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag,
10308 				     vlan_info->qos);
10309 	if (ret)
10310 		return ret;
10311 
10312 	if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info))
10313 		goto out;
10314 
10315 	if (state == HNAE3_PORT_BASE_VLAN_MODIFY)
10316 		ret = hclge_modify_port_base_vlan_tag(vport, vlan_info,
10317 						      old_vlan_info);
10318 	else
10319 		ret = hclge_update_vlan_filter_entries(vport, state, vlan_info,
10320 						       old_vlan_info);
10321 	if (ret)
10322 		return ret;
10323 
10324 out:
10325 	vport->port_base_vlan_cfg.state = state;
10326 	if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
10327 		nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE;
10328 	else
10329 		nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
10330 
10331 	vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info;
10332 	vport->port_base_vlan_cfg.vlan_info = *vlan_info;
10333 	vport->port_base_vlan_cfg.tbl_sta = true;
10334 	hclge_set_vport_vlan_fltr_change(vport);
10335 
10336 	return 0;
10337 }
10338 
10339 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport,
10340 					  enum hnae3_port_base_vlan_state state,
10341 					  u16 vlan, u8 qos)
10342 {
10343 	if (state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10344 		if (!vlan && !qos)
10345 			return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10346 
10347 		return HNAE3_PORT_BASE_VLAN_ENABLE;
10348 	}
10349 
10350 	if (!vlan && !qos)
10351 		return HNAE3_PORT_BASE_VLAN_DISABLE;
10352 
10353 	if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan &&
10354 	    vport->port_base_vlan_cfg.vlan_info.qos == qos)
10355 		return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10356 
10357 	return HNAE3_PORT_BASE_VLAN_MODIFY;
10358 }
10359 
10360 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
10361 				    u16 vlan, u8 qos, __be16 proto)
10362 {
10363 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
10364 	struct hclge_vport *vport = hclge_get_vport(handle);
10365 	struct hclge_dev *hdev = vport->back;
10366 	struct hclge_vlan_info vlan_info;
10367 	u16 state;
10368 	int ret;
10369 
10370 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
10371 		return -EOPNOTSUPP;
10372 
10373 	vport = hclge_get_vf_vport(hdev, vfid);
10374 	if (!vport)
10375 		return -EINVAL;
10376 
10377 	/* qos is a 3 bits value, so can not be bigger than 7 */
10378 	if (vlan > VLAN_N_VID - 1 || qos > 7)
10379 		return -EINVAL;
10380 	if (proto != htons(ETH_P_8021Q))
10381 		return -EPROTONOSUPPORT;
10382 
10383 	state = hclge_get_port_base_vlan_state(vport,
10384 					       vport->port_base_vlan_cfg.state,
10385 					       vlan, qos);
10386 	if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE)
10387 		return 0;
10388 
10389 	vlan_info.vlan_tag = vlan;
10390 	vlan_info.qos = qos;
10391 	vlan_info.vlan_proto = ntohs(proto);
10392 
10393 	ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info);
10394 	if (ret) {
10395 		dev_err(&hdev->pdev->dev,
10396 			"failed to update port base vlan for vf %d, ret = %d\n",
10397 			vfid, ret);
10398 		return ret;
10399 	}
10400 
10401 	/* there is a timewindow for PF to know VF unalive, it may
10402 	 * cause send mailbox fail, but it doesn't matter, VF will
10403 	 * query it when reinit.
10404 	 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based
10405 	 * VLAN state.
10406 	 */
10407 	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
10408 		if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
10409 			(void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
10410 								vport->vport_id,
10411 								state,
10412 								&vlan_info);
10413 		else
10414 			set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,
10415 				&vport->need_notify);
10416 	}
10417 	return 0;
10418 }
10419 
10420 static void hclge_clear_vf_vlan(struct hclge_dev *hdev)
10421 {
10422 	struct hclge_vlan_info *vlan_info;
10423 	struct hclge_vport *vport;
10424 	int ret;
10425 	int vf;
10426 
10427 	/* clear port base vlan for all vf */
10428 	for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
10429 		vport = &hdev->vport[vf];
10430 		vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10431 
10432 		ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10433 					       vport->vport_id,
10434 					       vlan_info->vlan_tag, true);
10435 		if (ret)
10436 			dev_err(&hdev->pdev->dev,
10437 				"failed to clear vf vlan for vf%d, ret = %d\n",
10438 				vf - HCLGE_VF_VPORT_START_NUM, ret);
10439 	}
10440 }
10441 
10442 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
10443 			  u16 vlan_id, bool is_kill)
10444 {
10445 	struct hclge_vport *vport = hclge_get_vport(handle);
10446 	struct hclge_dev *hdev = vport->back;
10447 	bool writen_to_tbl = false;
10448 	int ret = 0;
10449 
10450 	/* When device is resetting or reset failed, firmware is unable to
10451 	 * handle mailbox. Just record the vlan id, and remove it after
10452 	 * reset finished.
10453 	 */
10454 	if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
10455 	     test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) {
10456 		set_bit(vlan_id, vport->vlan_del_fail_bmap);
10457 		return -EBUSY;
10458 	}
10459 
10460 	/* when port base vlan enabled, we use port base vlan as the vlan
10461 	 * filter entry. In this case, we don't update vlan filter table
10462 	 * when user add new vlan or remove exist vlan, just update the vport
10463 	 * vlan list. The vlan id in vlan list will be writen in vlan filter
10464 	 * table until port base vlan disabled
10465 	 */
10466 	if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10467 		ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id,
10468 					       vlan_id, is_kill);
10469 		writen_to_tbl = true;
10470 	}
10471 
10472 	if (!ret) {
10473 		if (!is_kill)
10474 			hclge_add_vport_vlan_table(vport, vlan_id,
10475 						   writen_to_tbl);
10476 		else if (is_kill && vlan_id != 0)
10477 			hclge_rm_vport_vlan_table(vport, vlan_id, false);
10478 	} else if (is_kill) {
10479 		/* when remove hw vlan filter failed, record the vlan id,
10480 		 * and try to remove it from hw later, to be consistence
10481 		 * with stack
10482 		 */
10483 		set_bit(vlan_id, vport->vlan_del_fail_bmap);
10484 	}
10485 
10486 	hclge_set_vport_vlan_fltr_change(vport);
10487 
10488 	return ret;
10489 }
10490 
10491 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev)
10492 {
10493 	struct hclge_vport *vport;
10494 	int ret;
10495 	u16 i;
10496 
10497 	for (i = 0; i < hdev->num_alloc_vport; i++) {
10498 		vport = &hdev->vport[i];
10499 		if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10500 					&vport->state))
10501 			continue;
10502 
10503 		ret = hclge_enable_vport_vlan_filter(vport,
10504 						     vport->req_vlan_fltr_en);
10505 		if (ret) {
10506 			dev_err(&hdev->pdev->dev,
10507 				"failed to sync vlan filter state for vport%u, ret = %d\n",
10508 				vport->vport_id, ret);
10509 			set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10510 				&vport->state);
10511 			return;
10512 		}
10513 	}
10514 }
10515 
10516 static void hclge_sync_vlan_filter(struct hclge_dev *hdev)
10517 {
10518 #define HCLGE_MAX_SYNC_COUNT	60
10519 
10520 	int i, ret, sync_cnt = 0;
10521 	u16 vlan_id;
10522 
10523 	/* start from vport 1 for PF is always alive */
10524 	for (i = 0; i < hdev->num_alloc_vport; i++) {
10525 		struct hclge_vport *vport = &hdev->vport[i];
10526 
10527 		vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10528 					 VLAN_N_VID);
10529 		while (vlan_id != VLAN_N_VID) {
10530 			ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10531 						       vport->vport_id, vlan_id,
10532 						       true);
10533 			if (ret && ret != -EINVAL)
10534 				return;
10535 
10536 			clear_bit(vlan_id, vport->vlan_del_fail_bmap);
10537 			hclge_rm_vport_vlan_table(vport, vlan_id, false);
10538 			hclge_set_vport_vlan_fltr_change(vport);
10539 
10540 			sync_cnt++;
10541 			if (sync_cnt >= HCLGE_MAX_SYNC_COUNT)
10542 				return;
10543 
10544 			vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10545 						 VLAN_N_VID);
10546 		}
10547 	}
10548 
10549 	hclge_sync_vlan_fltr_state(hdev);
10550 }
10551 
10552 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps)
10553 {
10554 	struct hclge_config_max_frm_size_cmd *req;
10555 	struct hclge_desc desc;
10556 
10557 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
10558 
10559 	req = (struct hclge_config_max_frm_size_cmd *)desc.data;
10560 	req->max_frm_size = cpu_to_le16(new_mps);
10561 	req->min_frm_size = HCLGE_MAC_MIN_FRAME;
10562 
10563 	return hclge_cmd_send(&hdev->hw, &desc, 1);
10564 }
10565 
10566 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
10567 {
10568 	struct hclge_vport *vport = hclge_get_vport(handle);
10569 
10570 	return hclge_set_vport_mtu(vport, new_mtu);
10571 }
10572 
10573 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu)
10574 {
10575 	struct hclge_dev *hdev = vport->back;
10576 	int i, max_frm_size, ret;
10577 
10578 	/* HW supprt 2 layer vlan */
10579 	max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
10580 	if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
10581 	    max_frm_size > hdev->ae_dev->dev_specs.max_frm_size)
10582 		return -EINVAL;
10583 
10584 	max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
10585 	mutex_lock(&hdev->vport_lock);
10586 	/* VF's mps must fit within hdev->mps */
10587 	if (vport->vport_id && max_frm_size > hdev->mps) {
10588 		mutex_unlock(&hdev->vport_lock);
10589 		return -EINVAL;
10590 	} else if (vport->vport_id) {
10591 		vport->mps = max_frm_size;
10592 		mutex_unlock(&hdev->vport_lock);
10593 		return 0;
10594 	}
10595 
10596 	/* PF's mps must be greater then VF's mps */
10597 	for (i = 1; i < hdev->num_alloc_vport; i++)
10598 		if (max_frm_size < hdev->vport[i].mps) {
10599 			dev_err(&hdev->pdev->dev,
10600 				"failed to set pf mtu for less than vport %d, mps = %u.\n",
10601 				i, hdev->vport[i].mps);
10602 			mutex_unlock(&hdev->vport_lock);
10603 			return -EINVAL;
10604 		}
10605 
10606 	hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
10607 
10608 	ret = hclge_set_mac_mtu(hdev, max_frm_size);
10609 	if (ret) {
10610 		dev_err(&hdev->pdev->dev,
10611 			"Change mtu fail, ret =%d\n", ret);
10612 		goto out;
10613 	}
10614 
10615 	hdev->mps = max_frm_size;
10616 	vport->mps = max_frm_size;
10617 
10618 	ret = hclge_buffer_alloc(hdev);
10619 	if (ret)
10620 		dev_err(&hdev->pdev->dev,
10621 			"Allocate buffer fail, ret =%d\n", ret);
10622 
10623 out:
10624 	hclge_notify_client(hdev, HNAE3_UP_CLIENT);
10625 	mutex_unlock(&hdev->vport_lock);
10626 	return ret;
10627 }
10628 
10629 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id,
10630 				    bool enable)
10631 {
10632 	struct hclge_reset_tqp_queue_cmd *req;
10633 	struct hclge_desc desc;
10634 	int ret;
10635 
10636 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
10637 
10638 	req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10639 	req->tqp_id = cpu_to_le16(queue_id);
10640 	if (enable)
10641 		hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U);
10642 
10643 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10644 	if (ret) {
10645 		dev_err(&hdev->pdev->dev,
10646 			"Send tqp reset cmd error, status =%d\n", ret);
10647 		return ret;
10648 	}
10649 
10650 	return 0;
10651 }
10652 
10653 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id,
10654 				  u8 *reset_status)
10655 {
10656 	struct hclge_reset_tqp_queue_cmd *req;
10657 	struct hclge_desc desc;
10658 	int ret;
10659 
10660 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
10661 
10662 	req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10663 	req->tqp_id = cpu_to_le16(queue_id);
10664 
10665 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10666 	if (ret) {
10667 		dev_err(&hdev->pdev->dev,
10668 			"Get reset status error, status =%d\n", ret);
10669 		return ret;
10670 	}
10671 
10672 	*reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
10673 
10674 	return 0;
10675 }
10676 
10677 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id)
10678 {
10679 	struct hclge_comm_tqp *tqp;
10680 	struct hnae3_queue *queue;
10681 
10682 	queue = handle->kinfo.tqp[queue_id];
10683 	tqp = container_of(queue, struct hclge_comm_tqp, q);
10684 
10685 	return tqp->index;
10686 }
10687 
10688 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle)
10689 {
10690 	struct hclge_vport *vport = hclge_get_vport(handle);
10691 	struct hclge_dev *hdev = vport->back;
10692 	u16 reset_try_times = 0;
10693 	u8 reset_status;
10694 	u16 queue_gid;
10695 	int ret;
10696 	u16 i;
10697 
10698 	for (i = 0; i < handle->kinfo.num_tqps; i++) {
10699 		queue_gid = hclge_covert_handle_qid_global(handle, i);
10700 		ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true);
10701 		if (ret) {
10702 			dev_err(&hdev->pdev->dev,
10703 				"failed to send reset tqp cmd, ret = %d\n",
10704 				ret);
10705 			return ret;
10706 		}
10707 
10708 		while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
10709 			ret = hclge_get_reset_status(hdev, queue_gid,
10710 						     &reset_status);
10711 			if (ret)
10712 				return ret;
10713 
10714 			if (reset_status)
10715 				break;
10716 
10717 			/* Wait for tqp hw reset */
10718 			usleep_range(1000, 1200);
10719 		}
10720 
10721 		if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
10722 			dev_err(&hdev->pdev->dev,
10723 				"wait for tqp hw reset timeout\n");
10724 			return -ETIME;
10725 		}
10726 
10727 		ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false);
10728 		if (ret) {
10729 			dev_err(&hdev->pdev->dev,
10730 				"failed to deassert soft reset, ret = %d\n",
10731 				ret);
10732 			return ret;
10733 		}
10734 		reset_try_times = 0;
10735 	}
10736 	return 0;
10737 }
10738 
10739 static int hclge_reset_rcb(struct hnae3_handle *handle)
10740 {
10741 #define HCLGE_RESET_RCB_NOT_SUPPORT	0U
10742 #define HCLGE_RESET_RCB_SUCCESS		1U
10743 
10744 	struct hclge_vport *vport = hclge_get_vport(handle);
10745 	struct hclge_dev *hdev = vport->back;
10746 	struct hclge_reset_cmd *req;
10747 	struct hclge_desc desc;
10748 	u8 return_status;
10749 	u16 queue_gid;
10750 	int ret;
10751 
10752 	queue_gid = hclge_covert_handle_qid_global(handle, 0);
10753 
10754 	req = (struct hclge_reset_cmd *)desc.data;
10755 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
10756 	hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1);
10757 	req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid);
10758 	req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps);
10759 
10760 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10761 	if (ret) {
10762 		dev_err(&hdev->pdev->dev,
10763 			"failed to send rcb reset cmd, ret = %d\n", ret);
10764 		return ret;
10765 	}
10766 
10767 	return_status = req->fun_reset_rcb_return_status;
10768 	if (return_status == HCLGE_RESET_RCB_SUCCESS)
10769 		return 0;
10770 
10771 	if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) {
10772 		dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n",
10773 			return_status);
10774 		return -EIO;
10775 	}
10776 
10777 	/* if reset rcb cmd is unsupported, we need to send reset tqp cmd
10778 	 * again to reset all tqps
10779 	 */
10780 	return hclge_reset_tqp_cmd(handle);
10781 }
10782 
10783 int hclge_reset_tqp(struct hnae3_handle *handle)
10784 {
10785 	struct hclge_vport *vport = hclge_get_vport(handle);
10786 	struct hclge_dev *hdev = vport->back;
10787 	int ret;
10788 
10789 	/* only need to disable PF's tqp */
10790 	if (!vport->vport_id) {
10791 		ret = hclge_tqp_enable(handle, false);
10792 		if (ret) {
10793 			dev_err(&hdev->pdev->dev,
10794 				"failed to disable tqp, ret = %d\n", ret);
10795 			return ret;
10796 		}
10797 	}
10798 
10799 	return hclge_reset_rcb(handle);
10800 }
10801 
10802 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
10803 {
10804 	struct hclge_vport *vport = hclge_get_vport(handle);
10805 	struct hclge_dev *hdev = vport->back;
10806 
10807 	return hdev->fw_version;
10808 }
10809 
10810 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10811 {
10812 	struct phy_device *phydev = hdev->hw.mac.phydev;
10813 
10814 	if (!phydev)
10815 		return;
10816 
10817 	phy_set_asym_pause(phydev, rx_en, tx_en);
10818 }
10819 
10820 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10821 {
10822 	int ret;
10823 
10824 	if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
10825 		return 0;
10826 
10827 	ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
10828 	if (ret)
10829 		dev_err(&hdev->pdev->dev,
10830 			"configure pauseparam error, ret = %d.\n", ret);
10831 
10832 	return ret;
10833 }
10834 
10835 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
10836 {
10837 	struct phy_device *phydev = hdev->hw.mac.phydev;
10838 	u16 remote_advertising = 0;
10839 	u16 local_advertising;
10840 	u32 rx_pause, tx_pause;
10841 	u8 flowctl;
10842 
10843 	if (!phydev->link)
10844 		return 0;
10845 
10846 	if (!phydev->autoneg)
10847 		return hclge_mac_pause_setup_hw(hdev);
10848 
10849 	local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising);
10850 
10851 	if (phydev->pause)
10852 		remote_advertising = LPA_PAUSE_CAP;
10853 
10854 	if (phydev->asym_pause)
10855 		remote_advertising |= LPA_PAUSE_ASYM;
10856 
10857 	flowctl = mii_resolve_flowctrl_fdx(local_advertising,
10858 					   remote_advertising);
10859 	tx_pause = flowctl & FLOW_CTRL_TX;
10860 	rx_pause = flowctl & FLOW_CTRL_RX;
10861 
10862 	if (phydev->duplex == HCLGE_MAC_HALF) {
10863 		tx_pause = 0;
10864 		rx_pause = 0;
10865 	}
10866 
10867 	return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
10868 }
10869 
10870 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
10871 				 u32 *rx_en, u32 *tx_en)
10872 {
10873 	struct hclge_vport *vport = hclge_get_vport(handle);
10874 	struct hclge_dev *hdev = vport->back;
10875 	u8 media_type = hdev->hw.mac.media_type;
10876 
10877 	*auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ?
10878 		    hclge_get_autoneg(handle) : 0;
10879 
10880 	if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
10881 		*rx_en = 0;
10882 		*tx_en = 0;
10883 		return;
10884 	}
10885 
10886 	if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
10887 		*rx_en = 1;
10888 		*tx_en = 0;
10889 	} else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
10890 		*tx_en = 1;
10891 		*rx_en = 0;
10892 	} else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
10893 		*rx_en = 1;
10894 		*tx_en = 1;
10895 	} else {
10896 		*rx_en = 0;
10897 		*tx_en = 0;
10898 	}
10899 }
10900 
10901 static void hclge_record_user_pauseparam(struct hclge_dev *hdev,
10902 					 u32 rx_en, u32 tx_en)
10903 {
10904 	if (rx_en && tx_en)
10905 		hdev->fc_mode_last_time = HCLGE_FC_FULL;
10906 	else if (rx_en && !tx_en)
10907 		hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
10908 	else if (!rx_en && tx_en)
10909 		hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
10910 	else
10911 		hdev->fc_mode_last_time = HCLGE_FC_NONE;
10912 
10913 	hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
10914 }
10915 
10916 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
10917 				u32 rx_en, u32 tx_en)
10918 {
10919 	struct hclge_vport *vport = hclge_get_vport(handle);
10920 	struct hclge_dev *hdev = vport->back;
10921 	struct phy_device *phydev = hdev->hw.mac.phydev;
10922 	u32 fc_autoneg;
10923 
10924 	if (phydev || hnae3_dev_phy_imp_supported(hdev)) {
10925 		fc_autoneg = hclge_get_autoneg(handle);
10926 		if (auto_neg != fc_autoneg) {
10927 			dev_info(&hdev->pdev->dev,
10928 				 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
10929 			return -EOPNOTSUPP;
10930 		}
10931 	}
10932 
10933 	if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
10934 		dev_info(&hdev->pdev->dev,
10935 			 "Priority flow control enabled. Cannot set link flow control.\n");
10936 		return -EOPNOTSUPP;
10937 	}
10938 
10939 	hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
10940 
10941 	hclge_record_user_pauseparam(hdev, rx_en, tx_en);
10942 
10943 	if (!auto_neg || hnae3_dev_phy_imp_supported(hdev))
10944 		return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
10945 
10946 	if (phydev)
10947 		return phy_start_aneg(phydev);
10948 
10949 	return -EOPNOTSUPP;
10950 }
10951 
10952 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
10953 					  u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num)
10954 {
10955 	struct hclge_vport *vport = hclge_get_vport(handle);
10956 	struct hclge_dev *hdev = vport->back;
10957 
10958 	if (speed)
10959 		*speed = hdev->hw.mac.speed;
10960 	if (duplex)
10961 		*duplex = hdev->hw.mac.duplex;
10962 	if (auto_neg)
10963 		*auto_neg = hdev->hw.mac.autoneg;
10964 	if (lane_num)
10965 		*lane_num = hdev->hw.mac.lane_num;
10966 }
10967 
10968 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
10969 				 u8 *module_type)
10970 {
10971 	struct hclge_vport *vport = hclge_get_vport(handle);
10972 	struct hclge_dev *hdev = vport->back;
10973 
10974 	/* When nic is down, the service task is not running, doesn't update
10975 	 * the port information per second. Query the port information before
10976 	 * return the media type, ensure getting the correct media information.
10977 	 */
10978 	hclge_update_port_info(hdev);
10979 
10980 	if (media_type)
10981 		*media_type = hdev->hw.mac.media_type;
10982 
10983 	if (module_type)
10984 		*module_type = hdev->hw.mac.module_type;
10985 }
10986 
10987 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
10988 				u8 *tp_mdix_ctrl, u8 *tp_mdix)
10989 {
10990 	struct hclge_vport *vport = hclge_get_vport(handle);
10991 	struct hclge_dev *hdev = vport->back;
10992 	struct phy_device *phydev = hdev->hw.mac.phydev;
10993 	int mdix_ctrl, mdix, is_resolved;
10994 	unsigned int retval;
10995 
10996 	if (!phydev) {
10997 		*tp_mdix_ctrl = ETH_TP_MDI_INVALID;
10998 		*tp_mdix = ETH_TP_MDI_INVALID;
10999 		return;
11000 	}
11001 
11002 	phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
11003 
11004 	retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
11005 	mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
11006 				    HCLGE_PHY_MDIX_CTRL_S);
11007 
11008 	retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
11009 	mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
11010 	is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
11011 
11012 	phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
11013 
11014 	switch (mdix_ctrl) {
11015 	case 0x0:
11016 		*tp_mdix_ctrl = ETH_TP_MDI;
11017 		break;
11018 	case 0x1:
11019 		*tp_mdix_ctrl = ETH_TP_MDI_X;
11020 		break;
11021 	case 0x3:
11022 		*tp_mdix_ctrl = ETH_TP_MDI_AUTO;
11023 		break;
11024 	default:
11025 		*tp_mdix_ctrl = ETH_TP_MDI_INVALID;
11026 		break;
11027 	}
11028 
11029 	if (!is_resolved)
11030 		*tp_mdix = ETH_TP_MDI_INVALID;
11031 	else if (mdix)
11032 		*tp_mdix = ETH_TP_MDI_X;
11033 	else
11034 		*tp_mdix = ETH_TP_MDI;
11035 }
11036 
11037 static void hclge_info_show(struct hclge_dev *hdev)
11038 {
11039 	struct hnae3_handle *handle = &hdev->vport->nic;
11040 	struct device *dev = &hdev->pdev->dev;
11041 
11042 	dev_info(dev, "PF info begin:\n");
11043 
11044 	dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
11045 	dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
11046 	dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
11047 	dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
11048 	dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs);
11049 	dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
11050 	dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size);
11051 	dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size);
11052 	dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size);
11053 	dev_info(dev, "This is %s PF\n",
11054 		 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main");
11055 	dev_info(dev, "DCB %s\n",
11056 		 handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable");
11057 	dev_info(dev, "MQPRIO %s\n",
11058 		 handle->kinfo.tc_info.mqprio_active ? "enable" : "disable");
11059 	dev_info(dev, "Default tx spare buffer size: %u\n",
11060 		 hdev->tx_spare_buf_size);
11061 
11062 	dev_info(dev, "PF info end.\n");
11063 }
11064 
11065 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
11066 					  struct hclge_vport *vport)
11067 {
11068 	struct hnae3_client *client = vport->nic.client;
11069 	struct hclge_dev *hdev = ae_dev->priv;
11070 	int rst_cnt = hdev->rst_stats.reset_cnt;
11071 	int ret;
11072 
11073 	ret = client->ops->init_instance(&vport->nic);
11074 	if (ret)
11075 		return ret;
11076 
11077 	set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11078 	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
11079 	    rst_cnt != hdev->rst_stats.reset_cnt) {
11080 		ret = -EBUSY;
11081 		goto init_nic_err;
11082 	}
11083 
11084 	/* Enable nic hw error interrupts */
11085 	ret = hclge_config_nic_hw_error(hdev, true);
11086 	if (ret) {
11087 		dev_err(&ae_dev->pdev->dev,
11088 			"fail(%d) to enable hw error interrupts\n", ret);
11089 		goto init_nic_err;
11090 	}
11091 
11092 	hnae3_set_client_init_flag(client, ae_dev, 1);
11093 
11094 	if (netif_msg_drv(&hdev->vport->nic))
11095 		hclge_info_show(hdev);
11096 
11097 	return ret;
11098 
11099 init_nic_err:
11100 	clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11101 	while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11102 		msleep(HCLGE_WAIT_RESET_DONE);
11103 
11104 	client->ops->uninit_instance(&vport->nic, 0);
11105 
11106 	return ret;
11107 }
11108 
11109 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
11110 					   struct hclge_vport *vport)
11111 {
11112 	struct hclge_dev *hdev = ae_dev->priv;
11113 	struct hnae3_client *client;
11114 	int rst_cnt;
11115 	int ret;
11116 
11117 	if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
11118 	    !hdev->nic_client)
11119 		return 0;
11120 
11121 	client = hdev->roce_client;
11122 	ret = hclge_init_roce_base_info(vport);
11123 	if (ret)
11124 		return ret;
11125 
11126 	rst_cnt = hdev->rst_stats.reset_cnt;
11127 	ret = client->ops->init_instance(&vport->roce);
11128 	if (ret)
11129 		return ret;
11130 
11131 	set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11132 	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
11133 	    rst_cnt != hdev->rst_stats.reset_cnt) {
11134 		ret = -EBUSY;
11135 		goto init_roce_err;
11136 	}
11137 
11138 	/* Enable roce ras interrupts */
11139 	ret = hclge_config_rocee_ras_interrupt(hdev, true);
11140 	if (ret) {
11141 		dev_err(&ae_dev->pdev->dev,
11142 			"fail(%d) to enable roce ras interrupts\n", ret);
11143 		goto init_roce_err;
11144 	}
11145 
11146 	hnae3_set_client_init_flag(client, ae_dev, 1);
11147 
11148 	return 0;
11149 
11150 init_roce_err:
11151 	clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11152 	while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11153 		msleep(HCLGE_WAIT_RESET_DONE);
11154 
11155 	hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
11156 
11157 	return ret;
11158 }
11159 
11160 static int hclge_init_client_instance(struct hnae3_client *client,
11161 				      struct hnae3_ae_dev *ae_dev)
11162 {
11163 	struct hclge_dev *hdev = ae_dev->priv;
11164 	struct hclge_vport *vport = &hdev->vport[0];
11165 	int ret;
11166 
11167 	switch (client->type) {
11168 	case HNAE3_CLIENT_KNIC:
11169 		hdev->nic_client = client;
11170 		vport->nic.client = client;
11171 		ret = hclge_init_nic_client_instance(ae_dev, vport);
11172 		if (ret)
11173 			goto clear_nic;
11174 
11175 		ret = hclge_init_roce_client_instance(ae_dev, vport);
11176 		if (ret)
11177 			goto clear_roce;
11178 
11179 		break;
11180 	case HNAE3_CLIENT_ROCE:
11181 		if (hnae3_dev_roce_supported(hdev)) {
11182 			hdev->roce_client = client;
11183 			vport->roce.client = client;
11184 		}
11185 
11186 		ret = hclge_init_roce_client_instance(ae_dev, vport);
11187 		if (ret)
11188 			goto clear_roce;
11189 
11190 		break;
11191 	default:
11192 		return -EINVAL;
11193 	}
11194 
11195 	return 0;
11196 
11197 clear_nic:
11198 	hdev->nic_client = NULL;
11199 	vport->nic.client = NULL;
11200 	return ret;
11201 clear_roce:
11202 	hdev->roce_client = NULL;
11203 	vport->roce.client = NULL;
11204 	return ret;
11205 }
11206 
11207 static void hclge_uninit_client_instance(struct hnae3_client *client,
11208 					 struct hnae3_ae_dev *ae_dev)
11209 {
11210 	struct hclge_dev *hdev = ae_dev->priv;
11211 	struct hclge_vport *vport = &hdev->vport[0];
11212 
11213 	if (hdev->roce_client) {
11214 		clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11215 		while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11216 			msleep(HCLGE_WAIT_RESET_DONE);
11217 
11218 		hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
11219 		hdev->roce_client = NULL;
11220 		vport->roce.client = NULL;
11221 	}
11222 	if (client->type == HNAE3_CLIENT_ROCE)
11223 		return;
11224 	if (hdev->nic_client && client->ops->uninit_instance) {
11225 		clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11226 		while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11227 			msleep(HCLGE_WAIT_RESET_DONE);
11228 
11229 		client->ops->uninit_instance(&vport->nic, 0);
11230 		hdev->nic_client = NULL;
11231 		vport->nic.client = NULL;
11232 	}
11233 }
11234 
11235 static int hclge_dev_mem_map(struct hclge_dev *hdev)
11236 {
11237 	struct pci_dev *pdev = hdev->pdev;
11238 	struct hclge_hw *hw = &hdev->hw;
11239 
11240 	/* for device does not have device memory, return directly */
11241 	if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR)))
11242 		return 0;
11243 
11244 	hw->hw.mem_base =
11245 		devm_ioremap_wc(&pdev->dev,
11246 				pci_resource_start(pdev, HCLGE_MEM_BAR),
11247 				pci_resource_len(pdev, HCLGE_MEM_BAR));
11248 	if (!hw->hw.mem_base) {
11249 		dev_err(&pdev->dev, "failed to map device memory\n");
11250 		return -EFAULT;
11251 	}
11252 
11253 	return 0;
11254 }
11255 
11256 static int hclge_pci_init(struct hclge_dev *hdev)
11257 {
11258 	struct pci_dev *pdev = hdev->pdev;
11259 	struct hclge_hw *hw;
11260 	int ret;
11261 
11262 	ret = pci_enable_device(pdev);
11263 	if (ret) {
11264 		dev_err(&pdev->dev, "failed to enable PCI device\n");
11265 		return ret;
11266 	}
11267 
11268 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
11269 	if (ret) {
11270 		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
11271 		if (ret) {
11272 			dev_err(&pdev->dev,
11273 				"can't set consistent PCI DMA");
11274 			goto err_disable_device;
11275 		}
11276 		dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
11277 	}
11278 
11279 	ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
11280 	if (ret) {
11281 		dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
11282 		goto err_disable_device;
11283 	}
11284 
11285 	pci_set_master(pdev);
11286 	hw = &hdev->hw;
11287 	hw->hw.io_base = pcim_iomap(pdev, 2, 0);
11288 	if (!hw->hw.io_base) {
11289 		dev_err(&pdev->dev, "Can't map configuration register space\n");
11290 		ret = -ENOMEM;
11291 		goto err_release_regions;
11292 	}
11293 
11294 	ret = hclge_dev_mem_map(hdev);
11295 	if (ret)
11296 		goto err_unmap_io_base;
11297 
11298 	hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
11299 
11300 	return 0;
11301 
11302 err_unmap_io_base:
11303 	pcim_iounmap(pdev, hdev->hw.hw.io_base);
11304 err_release_regions:
11305 	pci_release_regions(pdev);
11306 err_disable_device:
11307 	pci_disable_device(pdev);
11308 
11309 	return ret;
11310 }
11311 
11312 static void hclge_pci_uninit(struct hclge_dev *hdev)
11313 {
11314 	struct pci_dev *pdev = hdev->pdev;
11315 
11316 	if (hdev->hw.hw.mem_base)
11317 		devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);
11318 
11319 	pcim_iounmap(pdev, hdev->hw.hw.io_base);
11320 	pci_free_irq_vectors(pdev);
11321 	pci_release_mem_regions(pdev);
11322 	pci_disable_device(pdev);
11323 }
11324 
11325 static void hclge_state_init(struct hclge_dev *hdev)
11326 {
11327 	set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
11328 	set_bit(HCLGE_STATE_DOWN, &hdev->state);
11329 	clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
11330 	clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11331 	clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
11332 	clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
11333 	clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
11334 }
11335 
11336 static void hclge_state_uninit(struct hclge_dev *hdev)
11337 {
11338 	set_bit(HCLGE_STATE_DOWN, &hdev->state);
11339 	set_bit(HCLGE_STATE_REMOVING, &hdev->state);
11340 
11341 	if (hdev->reset_timer.function)
11342 		del_timer_sync(&hdev->reset_timer);
11343 	if (hdev->service_task.work.func)
11344 		cancel_delayed_work_sync(&hdev->service_task);
11345 }
11346 
11347 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
11348 					enum hnae3_reset_type rst_type)
11349 {
11350 #define HCLGE_RESET_RETRY_WAIT_MS	500
11351 #define HCLGE_RESET_RETRY_CNT	5
11352 
11353 	struct hclge_dev *hdev = ae_dev->priv;
11354 	int retry_cnt = 0;
11355 	int ret;
11356 
11357 	while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) {
11358 		down(&hdev->reset_sem);
11359 		set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11360 		hdev->reset_type = rst_type;
11361 		ret = hclge_reset_prepare(hdev);
11362 		if (!ret && !hdev->reset_pending)
11363 			break;
11364 
11365 		dev_err(&hdev->pdev->dev,
11366 			"failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n",
11367 			ret, hdev->reset_pending, retry_cnt);
11368 		clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11369 		up(&hdev->reset_sem);
11370 		msleep(HCLGE_RESET_RETRY_WAIT_MS);
11371 	}
11372 
11373 	/* disable misc vector before reset done */
11374 	hclge_enable_vector(&hdev->misc_vector, false);
11375 	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
11376 
11377 	if (hdev->reset_type == HNAE3_FLR_RESET)
11378 		hdev->rst_stats.flr_rst_cnt++;
11379 }
11380 
11381 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev)
11382 {
11383 	struct hclge_dev *hdev = ae_dev->priv;
11384 	int ret;
11385 
11386 	hclge_enable_vector(&hdev->misc_vector, true);
11387 
11388 	ret = hclge_reset_rebuild(hdev);
11389 	if (ret)
11390 		dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret);
11391 
11392 	hdev->reset_type = HNAE3_NONE_RESET;
11393 	clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11394 	up(&hdev->reset_sem);
11395 }
11396 
11397 static void hclge_clear_resetting_state(struct hclge_dev *hdev)
11398 {
11399 	u16 i;
11400 
11401 	for (i = 0; i < hdev->num_alloc_vport; i++) {
11402 		struct hclge_vport *vport = &hdev->vport[i];
11403 		int ret;
11404 
11405 		 /* Send cmd to clear vport's FUNC_RST_ING */
11406 		ret = hclge_set_vf_rst(hdev, vport->vport_id, false);
11407 		if (ret)
11408 			dev_warn(&hdev->pdev->dev,
11409 				 "clear vport(%u) rst failed %d!\n",
11410 				 vport->vport_id, ret);
11411 	}
11412 }
11413 
11414 static int hclge_clear_hw_resource(struct hclge_dev *hdev)
11415 {
11416 	struct hclge_desc desc;
11417 	int ret;
11418 
11419 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false);
11420 
11421 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11422 	/* This new command is only supported by new firmware, it will
11423 	 * fail with older firmware. Error value -EOPNOSUPP can only be
11424 	 * returned by older firmware running this command, to keep code
11425 	 * backward compatible we will override this value and return
11426 	 * success.
11427 	 */
11428 	if (ret && ret != -EOPNOTSUPP) {
11429 		dev_err(&hdev->pdev->dev,
11430 			"failed to clear hw resource, ret = %d\n", ret);
11431 		return ret;
11432 	}
11433 	return 0;
11434 }
11435 
11436 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev)
11437 {
11438 	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11439 		hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1);
11440 }
11441 
11442 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev)
11443 {
11444 	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11445 		hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0);
11446 }
11447 
11448 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle)
11449 {
11450 	struct hclge_vport *vport = hclge_get_vport(handle);
11451 
11452 	return &vport->back->hw.mac.wol;
11453 }
11454 
11455 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev,
11456 					u32 *wol_supported)
11457 {
11458 	struct hclge_query_wol_supported_cmd *wol_supported_cmd;
11459 	struct hclge_desc desc;
11460 	int ret;
11461 
11462 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE,
11463 				   true);
11464 	wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data;
11465 
11466 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11467 	if (ret) {
11468 		dev_err(&hdev->pdev->dev,
11469 			"failed to query wol supported, ret = %d\n", ret);
11470 		return ret;
11471 	}
11472 
11473 	*wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode);
11474 
11475 	return 0;
11476 }
11477 
11478 static int hclge_set_wol_cfg(struct hclge_dev *hdev,
11479 			     struct hclge_wol_info *wol_info)
11480 {
11481 	struct hclge_wol_cfg_cmd *wol_cfg_cmd;
11482 	struct hclge_desc desc;
11483 	int ret;
11484 
11485 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false);
11486 	wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data;
11487 	wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode);
11488 	wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size;
11489 	memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX);
11490 
11491 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11492 	if (ret)
11493 		dev_err(&hdev->pdev->dev,
11494 			"failed to set wol config, ret = %d\n", ret);
11495 
11496 	return ret;
11497 }
11498 
11499 static int hclge_update_wol(struct hclge_dev *hdev)
11500 {
11501 	struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
11502 
11503 	if (!hnae3_ae_dev_wol_supported(hdev->ae_dev))
11504 		return 0;
11505 
11506 	return hclge_set_wol_cfg(hdev, wol_info);
11507 }
11508 
11509 static int hclge_init_wol(struct hclge_dev *hdev)
11510 {
11511 	struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
11512 	int ret;
11513 
11514 	if (!hnae3_ae_dev_wol_supported(hdev->ae_dev))
11515 		return 0;
11516 
11517 	memset(wol_info, 0, sizeof(struct hclge_wol_info));
11518 	ret = hclge_get_wol_supported_mode(hdev,
11519 					   &wol_info->wol_support_mode);
11520 	if (ret) {
11521 		wol_info->wol_support_mode = 0;
11522 		return ret;
11523 	}
11524 
11525 	return hclge_update_wol(hdev);
11526 }
11527 
11528 static void hclge_get_wol(struct hnae3_handle *handle,
11529 			  struct ethtool_wolinfo *wol)
11530 {
11531 	struct hclge_wol_info *wol_info = hclge_get_wol_info(handle);
11532 
11533 	wol->supported = wol_info->wol_support_mode;
11534 	wol->wolopts = wol_info->wol_current_mode;
11535 	if (wol_info->wol_current_mode & WAKE_MAGICSECURE)
11536 		memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX);
11537 }
11538 
11539 static int hclge_set_wol(struct hnae3_handle *handle,
11540 			 struct ethtool_wolinfo *wol)
11541 {
11542 	struct hclge_wol_info *wol_info = hclge_get_wol_info(handle);
11543 	struct hclge_vport *vport = hclge_get_vport(handle);
11544 	u32 wol_mode;
11545 	int ret;
11546 
11547 	wol_mode = wol->wolopts;
11548 	if (wol_mode & ~wol_info->wol_support_mode)
11549 		return -EINVAL;
11550 
11551 	wol_info->wol_current_mode = wol_mode;
11552 	if (wol_mode & WAKE_MAGICSECURE) {
11553 		memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX);
11554 		wol_info->wol_sopass_size = SOPASS_MAX;
11555 	} else {
11556 		wol_info->wol_sopass_size = 0;
11557 	}
11558 
11559 	ret = hclge_set_wol_cfg(vport->back, wol_info);
11560 	if (ret)
11561 		wol_info->wol_current_mode = 0;
11562 
11563 	return ret;
11564 }
11565 
11566 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
11567 {
11568 	struct pci_dev *pdev = ae_dev->pdev;
11569 	struct hclge_dev *hdev;
11570 	int ret;
11571 
11572 	hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
11573 	if (!hdev)
11574 		return -ENOMEM;
11575 
11576 	hdev->pdev = pdev;
11577 	hdev->ae_dev = ae_dev;
11578 	hdev->reset_type = HNAE3_NONE_RESET;
11579 	hdev->reset_level = HNAE3_FUNC_RESET;
11580 	ae_dev->priv = hdev;
11581 
11582 	/* HW supprt 2 layer vlan */
11583 	hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
11584 
11585 	mutex_init(&hdev->vport_lock);
11586 	spin_lock_init(&hdev->fd_rule_lock);
11587 	sema_init(&hdev->reset_sem, 1);
11588 
11589 	ret = hclge_pci_init(hdev);
11590 	if (ret)
11591 		goto out;
11592 
11593 	ret = hclge_devlink_init(hdev);
11594 	if (ret)
11595 		goto err_pci_uninit;
11596 
11597 	/* Firmware command queue initialize */
11598 	ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
11599 	if (ret)
11600 		goto err_devlink_uninit;
11601 
11602 	/* Firmware command initialize */
11603 	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
11604 				  true, hdev->reset_pending);
11605 	if (ret)
11606 		goto err_cmd_uninit;
11607 
11608 	ret  = hclge_clear_hw_resource(hdev);
11609 	if (ret)
11610 		goto err_cmd_uninit;
11611 
11612 	ret = hclge_get_cap(hdev);
11613 	if (ret)
11614 		goto err_cmd_uninit;
11615 
11616 	ret = hclge_query_dev_specs(hdev);
11617 	if (ret) {
11618 		dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n",
11619 			ret);
11620 		goto err_cmd_uninit;
11621 	}
11622 
11623 	ret = hclge_configure(hdev);
11624 	if (ret) {
11625 		dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
11626 		goto err_cmd_uninit;
11627 	}
11628 
11629 	ret = hclge_init_msi(hdev);
11630 	if (ret) {
11631 		dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
11632 		goto err_cmd_uninit;
11633 	}
11634 
11635 	ret = hclge_misc_irq_init(hdev);
11636 	if (ret)
11637 		goto err_msi_uninit;
11638 
11639 	ret = hclge_alloc_tqps(hdev);
11640 	if (ret) {
11641 		dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
11642 		goto err_msi_irq_uninit;
11643 	}
11644 
11645 	ret = hclge_alloc_vport(hdev);
11646 	if (ret)
11647 		goto err_msi_irq_uninit;
11648 
11649 	ret = hclge_map_tqp(hdev);
11650 	if (ret)
11651 		goto err_msi_irq_uninit;
11652 
11653 	if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
11654 		if (hnae3_dev_phy_imp_supported(hdev))
11655 			ret = hclge_update_tp_port_info(hdev);
11656 		else
11657 			ret = hclge_mac_mdio_config(hdev);
11658 
11659 		if (ret)
11660 			goto err_msi_irq_uninit;
11661 	}
11662 
11663 	ret = hclge_init_umv_space(hdev);
11664 	if (ret)
11665 		goto err_mdiobus_unreg;
11666 
11667 	ret = hclge_mac_init(hdev);
11668 	if (ret) {
11669 		dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
11670 		goto err_mdiobus_unreg;
11671 	}
11672 
11673 	ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
11674 	if (ret) {
11675 		dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
11676 		goto err_mdiobus_unreg;
11677 	}
11678 
11679 	ret = hclge_config_gro(hdev);
11680 	if (ret)
11681 		goto err_mdiobus_unreg;
11682 
11683 	ret = hclge_init_vlan_config(hdev);
11684 	if (ret) {
11685 		dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
11686 		goto err_mdiobus_unreg;
11687 	}
11688 
11689 	ret = hclge_tm_schd_init(hdev);
11690 	if (ret) {
11691 		dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
11692 		goto err_mdiobus_unreg;
11693 	}
11694 
11695 	ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev,
11696 				      &hdev->rss_cfg);
11697 	if (ret) {
11698 		dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
11699 		goto err_mdiobus_unreg;
11700 	}
11701 
11702 	ret = hclge_rss_init_hw(hdev);
11703 	if (ret) {
11704 		dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
11705 		goto err_mdiobus_unreg;
11706 	}
11707 
11708 	ret = init_mgr_tbl(hdev);
11709 	if (ret) {
11710 		dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
11711 		goto err_mdiobus_unreg;
11712 	}
11713 
11714 	ret = hclge_init_fd_config(hdev);
11715 	if (ret) {
11716 		dev_err(&pdev->dev,
11717 			"fd table init fail, ret=%d\n", ret);
11718 		goto err_mdiobus_unreg;
11719 	}
11720 
11721 	ret = hclge_ptp_init(hdev);
11722 	if (ret)
11723 		goto err_mdiobus_unreg;
11724 
11725 	ret = hclge_update_port_info(hdev);
11726 	if (ret)
11727 		goto err_mdiobus_unreg;
11728 
11729 	INIT_KFIFO(hdev->mac_tnl_log);
11730 
11731 	hclge_dcb_ops_set(hdev);
11732 
11733 	timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
11734 	INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task);
11735 
11736 	hclge_clear_all_event_cause(hdev);
11737 	hclge_clear_resetting_state(hdev);
11738 
11739 	/* Log and clear the hw errors those already occurred */
11740 	if (hnae3_dev_ras_imp_supported(hdev))
11741 		hclge_handle_occurred_error(hdev);
11742 	else
11743 		hclge_handle_all_hns_hw_errors(ae_dev);
11744 
11745 	/* request delayed reset for the error recovery because an immediate
11746 	 * global reset on a PF affecting pending initialization of other PFs
11747 	 */
11748 	if (ae_dev->hw_err_reset_req) {
11749 		enum hnae3_reset_type reset_level;
11750 
11751 		reset_level = hclge_get_reset_level(ae_dev,
11752 						    &ae_dev->hw_err_reset_req);
11753 		hclge_set_def_reset_request(ae_dev, reset_level);
11754 		mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
11755 	}
11756 
11757 	hclge_init_rxd_adv_layout(hdev);
11758 
11759 	/* Enable MISC vector(vector0) */
11760 	hclge_enable_vector(&hdev->misc_vector, true);
11761 
11762 	ret = hclge_init_wol(hdev);
11763 	if (ret)
11764 		dev_warn(&pdev->dev,
11765 			 "failed to wake on lan init, ret = %d\n", ret);
11766 
11767 	hclge_state_init(hdev);
11768 	hdev->last_reset_time = jiffies;
11769 
11770 	dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n",
11771 		 HCLGE_DRIVER_NAME);
11772 
11773 	hclge_task_schedule(hdev, round_jiffies_relative(HZ));
11774 
11775 	return 0;
11776 
11777 err_mdiobus_unreg:
11778 	if (hdev->hw.mac.phydev)
11779 		mdiobus_unregister(hdev->hw.mac.mdio_bus);
11780 err_msi_irq_uninit:
11781 	hclge_misc_irq_uninit(hdev);
11782 err_msi_uninit:
11783 	pci_free_irq_vectors(pdev);
11784 err_cmd_uninit:
11785 	hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
11786 err_devlink_uninit:
11787 	hclge_devlink_uninit(hdev);
11788 err_pci_uninit:
11789 	pcim_iounmap(pdev, hdev->hw.hw.io_base);
11790 	pci_release_regions(pdev);
11791 	pci_disable_device(pdev);
11792 out:
11793 	mutex_destroy(&hdev->vport_lock);
11794 	return ret;
11795 }
11796 
11797 static void hclge_stats_clear(struct hclge_dev *hdev)
11798 {
11799 	memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats));
11800 	memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats));
11801 }
11802 
11803 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11804 {
11805 	return hclge_config_switch_param(hdev, vf, enable,
11806 					 HCLGE_SWITCH_ANTI_SPOOF_MASK);
11807 }
11808 
11809 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11810 {
11811 	return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
11812 					  HCLGE_FILTER_FE_NIC_INGRESS_B,
11813 					  enable, vf);
11814 }
11815 
11816 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable)
11817 {
11818 	int ret;
11819 
11820 	ret = hclge_set_mac_spoofchk(hdev, vf, enable);
11821 	if (ret) {
11822 		dev_err(&hdev->pdev->dev,
11823 			"Set vf %d mac spoof check %s failed, ret=%d\n",
11824 			vf, enable ? "on" : "off", ret);
11825 		return ret;
11826 	}
11827 
11828 	ret = hclge_set_vlan_spoofchk(hdev, vf, enable);
11829 	if (ret)
11830 		dev_err(&hdev->pdev->dev,
11831 			"Set vf %d vlan spoof check %s failed, ret=%d\n",
11832 			vf, enable ? "on" : "off", ret);
11833 
11834 	return ret;
11835 }
11836 
11837 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf,
11838 				 bool enable)
11839 {
11840 	struct hclge_vport *vport = hclge_get_vport(handle);
11841 	struct hclge_dev *hdev = vport->back;
11842 	u32 new_spoofchk = enable ? 1 : 0;
11843 	int ret;
11844 
11845 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
11846 		return -EOPNOTSUPP;
11847 
11848 	vport = hclge_get_vf_vport(hdev, vf);
11849 	if (!vport)
11850 		return -EINVAL;
11851 
11852 	if (vport->vf_info.spoofchk == new_spoofchk)
11853 		return 0;
11854 
11855 	if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full))
11856 		dev_warn(&hdev->pdev->dev,
11857 			 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n",
11858 			 vf);
11859 	else if (enable && hclge_is_umv_space_full(vport, true))
11860 		dev_warn(&hdev->pdev->dev,
11861 			 "vf %d mac table is full, enable spoof check may cause its packet send fail\n",
11862 			 vf);
11863 
11864 	ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable);
11865 	if (ret)
11866 		return ret;
11867 
11868 	vport->vf_info.spoofchk = new_spoofchk;
11869 	return 0;
11870 }
11871 
11872 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev)
11873 {
11874 	struct hclge_vport *vport = hdev->vport;
11875 	int ret;
11876 	int i;
11877 
11878 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
11879 		return 0;
11880 
11881 	/* resume the vf spoof check state after reset */
11882 	for (i = 0; i < hdev->num_alloc_vport; i++) {
11883 		ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id,
11884 					       vport->vf_info.spoofchk);
11885 		if (ret)
11886 			return ret;
11887 
11888 		vport++;
11889 	}
11890 
11891 	return 0;
11892 }
11893 
11894 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable)
11895 {
11896 	struct hclge_vport *vport = hclge_get_vport(handle);
11897 	struct hclge_dev *hdev = vport->back;
11898 	u32 new_trusted = enable ? 1 : 0;
11899 
11900 	vport = hclge_get_vf_vport(hdev, vf);
11901 	if (!vport)
11902 		return -EINVAL;
11903 
11904 	if (vport->vf_info.trusted == new_trusted)
11905 		return 0;
11906 
11907 	vport->vf_info.trusted = new_trusted;
11908 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
11909 	hclge_task_schedule(hdev, 0);
11910 
11911 	return 0;
11912 }
11913 
11914 static void hclge_reset_vf_rate(struct hclge_dev *hdev)
11915 {
11916 	int ret;
11917 	int vf;
11918 
11919 	/* reset vf rate to default value */
11920 	for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
11921 		struct hclge_vport *vport = &hdev->vport[vf];
11922 
11923 		vport->vf_info.max_tx_rate = 0;
11924 		ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate);
11925 		if (ret)
11926 			dev_err(&hdev->pdev->dev,
11927 				"vf%d failed to reset to default, ret=%d\n",
11928 				vf - HCLGE_VF_VPORT_START_NUM, ret);
11929 	}
11930 }
11931 
11932 static int hclge_vf_rate_param_check(struct hclge_dev *hdev,
11933 				     int min_tx_rate, int max_tx_rate)
11934 {
11935 	if (min_tx_rate != 0 ||
11936 	    max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) {
11937 		dev_err(&hdev->pdev->dev,
11938 			"min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n",
11939 			min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed);
11940 		return -EINVAL;
11941 	}
11942 
11943 	return 0;
11944 }
11945 
11946 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf,
11947 			     int min_tx_rate, int max_tx_rate, bool force)
11948 {
11949 	struct hclge_vport *vport = hclge_get_vport(handle);
11950 	struct hclge_dev *hdev = vport->back;
11951 	int ret;
11952 
11953 	ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate);
11954 	if (ret)
11955 		return ret;
11956 
11957 	vport = hclge_get_vf_vport(hdev, vf);
11958 	if (!vport)
11959 		return -EINVAL;
11960 
11961 	if (!force && max_tx_rate == vport->vf_info.max_tx_rate)
11962 		return 0;
11963 
11964 	ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate);
11965 	if (ret)
11966 		return ret;
11967 
11968 	vport->vf_info.max_tx_rate = max_tx_rate;
11969 
11970 	return 0;
11971 }
11972 
11973 static int hclge_resume_vf_rate(struct hclge_dev *hdev)
11974 {
11975 	struct hnae3_handle *handle = &hdev->vport->nic;
11976 	struct hclge_vport *vport;
11977 	int ret;
11978 	int vf;
11979 
11980 	/* resume the vf max_tx_rate after reset */
11981 	for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) {
11982 		vport = hclge_get_vf_vport(hdev, vf);
11983 		if (!vport)
11984 			return -EINVAL;
11985 
11986 		/* zero means max rate, after reset, firmware already set it to
11987 		 * max rate, so just continue.
11988 		 */
11989 		if (!vport->vf_info.max_tx_rate)
11990 			continue;
11991 
11992 		ret = hclge_set_vf_rate(handle, vf, 0,
11993 					vport->vf_info.max_tx_rate, true);
11994 		if (ret) {
11995 			dev_err(&hdev->pdev->dev,
11996 				"vf%d failed to resume tx_rate:%u, ret=%d\n",
11997 				vf, vport->vf_info.max_tx_rate, ret);
11998 			return ret;
11999 		}
12000 	}
12001 
12002 	return 0;
12003 }
12004 
12005 static void hclge_reset_vport_state(struct hclge_dev *hdev)
12006 {
12007 	struct hclge_vport *vport = hdev->vport;
12008 	int i;
12009 
12010 	for (i = 0; i < hdev->num_alloc_vport; i++) {
12011 		clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
12012 		vport++;
12013 	}
12014 }
12015 
12016 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
12017 {
12018 	struct hclge_dev *hdev = ae_dev->priv;
12019 	struct pci_dev *pdev = ae_dev->pdev;
12020 	int ret;
12021 
12022 	set_bit(HCLGE_STATE_DOWN, &hdev->state);
12023 
12024 	hclge_stats_clear(hdev);
12025 	/* NOTE: pf reset needn't to clear or restore pf and vf table entry.
12026 	 * so here should not clean table in memory.
12027 	 */
12028 	if (hdev->reset_type == HNAE3_IMP_RESET ||
12029 	    hdev->reset_type == HNAE3_GLOBAL_RESET) {
12030 		memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
12031 		memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full));
12032 		bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport);
12033 		hclge_reset_umv_space(hdev);
12034 	}
12035 
12036 	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
12037 				  true, hdev->reset_pending);
12038 	if (ret) {
12039 		dev_err(&pdev->dev, "Cmd queue init failed\n");
12040 		return ret;
12041 	}
12042 
12043 	ret = hclge_map_tqp(hdev);
12044 	if (ret) {
12045 		dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
12046 		return ret;
12047 	}
12048 
12049 	ret = hclge_mac_init(hdev);
12050 	if (ret) {
12051 		dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
12052 		return ret;
12053 	}
12054 
12055 	ret = hclge_tp_port_init(hdev);
12056 	if (ret) {
12057 		dev_err(&pdev->dev, "failed to init tp port, ret = %d\n",
12058 			ret);
12059 		return ret;
12060 	}
12061 
12062 	ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
12063 	if (ret) {
12064 		dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
12065 		return ret;
12066 	}
12067 
12068 	ret = hclge_config_gro(hdev);
12069 	if (ret)
12070 		return ret;
12071 
12072 	ret = hclge_init_vlan_config(hdev);
12073 	if (ret) {
12074 		dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
12075 		return ret;
12076 	}
12077 
12078 	ret = hclge_tm_init_hw(hdev, true);
12079 	if (ret) {
12080 		dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
12081 		return ret;
12082 	}
12083 
12084 	ret = hclge_rss_init_hw(hdev);
12085 	if (ret) {
12086 		dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
12087 		return ret;
12088 	}
12089 
12090 	ret = init_mgr_tbl(hdev);
12091 	if (ret) {
12092 		dev_err(&pdev->dev,
12093 			"failed to reinit manager table, ret = %d\n", ret);
12094 		return ret;
12095 	}
12096 
12097 	ret = hclge_init_fd_config(hdev);
12098 	if (ret) {
12099 		dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret);
12100 		return ret;
12101 	}
12102 
12103 	ret = hclge_ptp_init(hdev);
12104 	if (ret)
12105 		return ret;
12106 
12107 	/* Log and clear the hw errors those already occurred */
12108 	if (hnae3_dev_ras_imp_supported(hdev))
12109 		hclge_handle_occurred_error(hdev);
12110 	else
12111 		hclge_handle_all_hns_hw_errors(ae_dev);
12112 
12113 	/* Re-enable the hw error interrupts because
12114 	 * the interrupts get disabled on global reset.
12115 	 */
12116 	ret = hclge_config_nic_hw_error(hdev, true);
12117 	if (ret) {
12118 		dev_err(&pdev->dev,
12119 			"fail(%d) to re-enable NIC hw error interrupts\n",
12120 			ret);
12121 		return ret;
12122 	}
12123 
12124 	if (hdev->roce_client) {
12125 		ret = hclge_config_rocee_ras_interrupt(hdev, true);
12126 		if (ret) {
12127 			dev_err(&pdev->dev,
12128 				"fail(%d) to re-enable roce ras interrupts\n",
12129 				ret);
12130 			return ret;
12131 		}
12132 	}
12133 
12134 	hclge_reset_vport_state(hdev);
12135 	ret = hclge_reset_vport_spoofchk(hdev);
12136 	if (ret)
12137 		return ret;
12138 
12139 	ret = hclge_resume_vf_rate(hdev);
12140 	if (ret)
12141 		return ret;
12142 
12143 	hclge_init_rxd_adv_layout(hdev);
12144 
12145 	ret = hclge_update_wol(hdev);
12146 	if (ret)
12147 		dev_warn(&pdev->dev,
12148 			 "failed to update wol config, ret = %d\n", ret);
12149 
12150 	dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
12151 		 HCLGE_DRIVER_NAME);
12152 
12153 	return 0;
12154 }
12155 
12156 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
12157 {
12158 	struct hclge_dev *hdev = ae_dev->priv;
12159 	struct hclge_mac *mac = &hdev->hw.mac;
12160 
12161 	hclge_reset_vf_rate(hdev);
12162 	hclge_clear_vf_vlan(hdev);
12163 	hclge_state_uninit(hdev);
12164 	hclge_ptp_uninit(hdev);
12165 	hclge_uninit_rxd_adv_layout(hdev);
12166 	hclge_uninit_mac_table(hdev);
12167 	hclge_del_all_fd_entries(hdev);
12168 
12169 	if (mac->phydev)
12170 		mdiobus_unregister(mac->mdio_bus);
12171 
12172 	/* Disable MISC vector(vector0) */
12173 	hclge_enable_vector(&hdev->misc_vector, false);
12174 	synchronize_irq(hdev->misc_vector.vector_irq);
12175 
12176 	/* Disable all hw interrupts */
12177 	hclge_config_mac_tnl_int(hdev, false);
12178 	hclge_config_nic_hw_error(hdev, false);
12179 	hclge_config_rocee_ras_interrupt(hdev, false);
12180 
12181 	hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
12182 	hclge_misc_irq_uninit(hdev);
12183 	hclge_devlink_uninit(hdev);
12184 	hclge_pci_uninit(hdev);
12185 	hclge_uninit_vport_vlan_table(hdev);
12186 	mutex_destroy(&hdev->vport_lock);
12187 	ae_dev->priv = NULL;
12188 }
12189 
12190 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
12191 {
12192 	struct hclge_vport *vport = hclge_get_vport(handle);
12193 	struct hclge_dev *hdev = vport->back;
12194 
12195 	return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps);
12196 }
12197 
12198 static void hclge_get_channels(struct hnae3_handle *handle,
12199 			       struct ethtool_channels *ch)
12200 {
12201 	ch->max_combined = hclge_get_max_channels(handle);
12202 	ch->other_count = 1;
12203 	ch->max_other = 1;
12204 	ch->combined_count = handle->kinfo.rss_size;
12205 }
12206 
12207 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
12208 					u16 *alloc_tqps, u16 *max_rss_size)
12209 {
12210 	struct hclge_vport *vport = hclge_get_vport(handle);
12211 	struct hclge_dev *hdev = vport->back;
12212 
12213 	*alloc_tqps = vport->alloc_tqps;
12214 	*max_rss_size = hdev->pf_rss_size_max;
12215 }
12216 
12217 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle)
12218 {
12219 	struct hclge_vport *vport = hclge_get_vport(handle);
12220 	u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
12221 	struct hclge_dev *hdev = vport->back;
12222 	u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
12223 	u16 tc_valid[HCLGE_MAX_TC_NUM];
12224 	u16 roundup_size;
12225 	unsigned int i;
12226 
12227 	roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size);
12228 	roundup_size = ilog2(roundup_size);
12229 	/* Set the RSS TC mode according to the new RSS size */
12230 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
12231 		tc_valid[i] = 0;
12232 
12233 		if (!(hdev->hw_tc_map & BIT(i)))
12234 			continue;
12235 
12236 		tc_valid[i] = 1;
12237 		tc_size[i] = roundup_size;
12238 		tc_offset[i] = vport->nic.kinfo.rss_size * i;
12239 	}
12240 
12241 	return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
12242 					  tc_size);
12243 }
12244 
12245 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
12246 			      bool rxfh_configured)
12247 {
12248 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
12249 	struct hclge_vport *vport = hclge_get_vport(handle);
12250 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
12251 	struct hclge_dev *hdev = vport->back;
12252 	u16 cur_rss_size = kinfo->rss_size;
12253 	u16 cur_tqps = kinfo->num_tqps;
12254 	u32 *rss_indir;
12255 	unsigned int i;
12256 	int ret;
12257 
12258 	kinfo->req_rss_size = new_tqps_num;
12259 
12260 	ret = hclge_tm_vport_map_update(hdev);
12261 	if (ret) {
12262 		dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret);
12263 		return ret;
12264 	}
12265 
12266 	ret = hclge_set_rss_tc_mode_cfg(handle);
12267 	if (ret)
12268 		return ret;
12269 
12270 	/* RSS indirection table has been configured by user */
12271 	if (rxfh_configured)
12272 		goto out;
12273 
12274 	/* Reinitializes the rss indirect table according to the new RSS size */
12275 	rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32),
12276 			    GFP_KERNEL);
12277 	if (!rss_indir)
12278 		return -ENOMEM;
12279 
12280 	for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
12281 		rss_indir[i] = i % kinfo->rss_size;
12282 
12283 	ret = hclge_set_rss(handle, rss_indir, NULL, 0);
12284 	if (ret)
12285 		dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
12286 			ret);
12287 
12288 	kfree(rss_indir);
12289 
12290 out:
12291 	if (!ret)
12292 		dev_info(&hdev->pdev->dev,
12293 			 "Channels changed, rss_size from %u to %u, tqps from %u to %u",
12294 			 cur_rss_size, kinfo->rss_size,
12295 			 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
12296 
12297 	return ret;
12298 }
12299 
12300 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
12301 {
12302 	struct hclge_set_led_state_cmd *req;
12303 	struct hclge_desc desc;
12304 	int ret;
12305 
12306 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
12307 
12308 	req = (struct hclge_set_led_state_cmd *)desc.data;
12309 	hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
12310 			HCLGE_LED_LOCATE_STATE_S, locate_led_status);
12311 
12312 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12313 	if (ret)
12314 		dev_err(&hdev->pdev->dev,
12315 			"Send set led state cmd error, ret =%d\n", ret);
12316 
12317 	return ret;
12318 }
12319 
12320 enum hclge_led_status {
12321 	HCLGE_LED_OFF,
12322 	HCLGE_LED_ON,
12323 	HCLGE_LED_NO_CHANGE = 0xFF,
12324 };
12325 
12326 static int hclge_set_led_id(struct hnae3_handle *handle,
12327 			    enum ethtool_phys_id_state status)
12328 {
12329 	struct hclge_vport *vport = hclge_get_vport(handle);
12330 	struct hclge_dev *hdev = vport->back;
12331 
12332 	switch (status) {
12333 	case ETHTOOL_ID_ACTIVE:
12334 		return hclge_set_led_status(hdev, HCLGE_LED_ON);
12335 	case ETHTOOL_ID_INACTIVE:
12336 		return hclge_set_led_status(hdev, HCLGE_LED_OFF);
12337 	default:
12338 		return -EINVAL;
12339 	}
12340 }
12341 
12342 static void hclge_get_link_mode(struct hnae3_handle *handle,
12343 				unsigned long *supported,
12344 				unsigned long *advertising)
12345 {
12346 	unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
12347 	struct hclge_vport *vport = hclge_get_vport(handle);
12348 	struct hclge_dev *hdev = vport->back;
12349 	unsigned int idx = 0;
12350 
12351 	for (; idx < size; idx++) {
12352 		supported[idx] = hdev->hw.mac.supported[idx];
12353 		advertising[idx] = hdev->hw.mac.advertising[idx];
12354 	}
12355 }
12356 
12357 static int hclge_gro_en(struct hnae3_handle *handle, bool enable)
12358 {
12359 	struct hclge_vport *vport = hclge_get_vport(handle);
12360 	struct hclge_dev *hdev = vport->back;
12361 	bool gro_en_old = hdev->gro_en;
12362 	int ret;
12363 
12364 	hdev->gro_en = enable;
12365 	ret = hclge_config_gro(hdev);
12366 	if (ret)
12367 		hdev->gro_en = gro_en_old;
12368 
12369 	return ret;
12370 }
12371 
12372 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport)
12373 {
12374 	struct hnae3_handle *handle = &vport->nic;
12375 	struct hclge_dev *hdev = vport->back;
12376 	bool uc_en = false;
12377 	bool mc_en = false;
12378 	u8 tmp_flags;
12379 	bool bc_en;
12380 	int ret;
12381 
12382 	if (vport->last_promisc_flags != vport->overflow_promisc_flags) {
12383 		set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
12384 		vport->last_promisc_flags = vport->overflow_promisc_flags;
12385 	}
12386 
12387 	if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12388 				&vport->state))
12389 		return 0;
12390 
12391 	/* for PF */
12392 	if (!vport->vport_id) {
12393 		tmp_flags = handle->netdev_flags | vport->last_promisc_flags;
12394 		ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE,
12395 					     tmp_flags & HNAE3_MPE);
12396 		if (!ret)
12397 			set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
12398 				&vport->state);
12399 		else
12400 			set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12401 				&vport->state);
12402 		return ret;
12403 	}
12404 
12405 	/* for VF */
12406 	if (vport->vf_info.trusted) {
12407 		uc_en = vport->vf_info.request_uc_en > 0 ||
12408 			vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE;
12409 		mc_en = vport->vf_info.request_mc_en > 0 ||
12410 			vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE;
12411 	}
12412 	bc_en = vport->vf_info.request_bc_en > 0;
12413 
12414 	ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en,
12415 					 mc_en, bc_en);
12416 	if (ret) {
12417 		set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
12418 		return ret;
12419 	}
12420 	hclge_set_vport_vlan_fltr_change(vport);
12421 
12422 	return 0;
12423 }
12424 
12425 static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
12426 {
12427 	struct hclge_vport *vport;
12428 	int ret;
12429 	u16 i;
12430 
12431 	for (i = 0; i < hdev->num_alloc_vport; i++) {
12432 		vport = &hdev->vport[i];
12433 
12434 		ret = hclge_sync_vport_promisc_mode(vport);
12435 		if (ret)
12436 			return;
12437 	}
12438 }
12439 
12440 static bool hclge_module_existed(struct hclge_dev *hdev)
12441 {
12442 	struct hclge_desc desc;
12443 	u32 existed;
12444 	int ret;
12445 
12446 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true);
12447 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12448 	if (ret) {
12449 		dev_err(&hdev->pdev->dev,
12450 			"failed to get SFP exist state, ret = %d\n", ret);
12451 		return false;
12452 	}
12453 
12454 	existed = le32_to_cpu(desc.data[0]);
12455 
12456 	return existed != 0;
12457 }
12458 
12459 /* need 6 bds(total 140 bytes) in one reading
12460  * return the number of bytes actually read, 0 means read failed.
12461  */
12462 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset,
12463 				     u32 len, u8 *data)
12464 {
12465 	struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM];
12466 	struct hclge_sfp_info_bd0_cmd *sfp_info_bd0;
12467 	u16 read_len;
12468 	u16 copy_len;
12469 	int ret;
12470 	int i;
12471 
12472 	/* setup all 6 bds to read module eeprom info. */
12473 	for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12474 		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM,
12475 					   true);
12476 
12477 		/* bd0~bd4 need next flag */
12478 		if (i < HCLGE_SFP_INFO_CMD_NUM - 1)
12479 			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
12480 	}
12481 
12482 	/* setup bd0, this bd contains offset and read length. */
12483 	sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data;
12484 	sfp_info_bd0->offset = cpu_to_le16((u16)offset);
12485 	read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN);
12486 	sfp_info_bd0->read_len = cpu_to_le16(read_len);
12487 
12488 	ret = hclge_cmd_send(&hdev->hw, desc, i);
12489 	if (ret) {
12490 		dev_err(&hdev->pdev->dev,
12491 			"failed to get SFP eeprom info, ret = %d\n", ret);
12492 		return 0;
12493 	}
12494 
12495 	/* copy sfp info from bd0 to out buffer. */
12496 	copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN);
12497 	memcpy(data, sfp_info_bd0->data, copy_len);
12498 	read_len = copy_len;
12499 
12500 	/* copy sfp info from bd1~bd5 to out buffer if needed. */
12501 	for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12502 		if (read_len >= len)
12503 			return read_len;
12504 
12505 		copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN);
12506 		memcpy(data + read_len, desc[i].data, copy_len);
12507 		read_len += copy_len;
12508 	}
12509 
12510 	return read_len;
12511 }
12512 
12513 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset,
12514 				   u32 len, u8 *data)
12515 {
12516 	struct hclge_vport *vport = hclge_get_vport(handle);
12517 	struct hclge_dev *hdev = vport->back;
12518 	u32 read_len = 0;
12519 	u16 data_len;
12520 
12521 	if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
12522 		return -EOPNOTSUPP;
12523 
12524 	if (!hclge_module_existed(hdev))
12525 		return -ENXIO;
12526 
12527 	while (read_len < len) {
12528 		data_len = hclge_get_sfp_eeprom_info(hdev,
12529 						     offset + read_len,
12530 						     len - read_len,
12531 						     data + read_len);
12532 		if (!data_len)
12533 			return -EIO;
12534 
12535 		read_len += data_len;
12536 	}
12537 
12538 	return 0;
12539 }
12540 
12541 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle,
12542 					 u32 *status_code)
12543 {
12544 	struct hclge_vport *vport = hclge_get_vport(handle);
12545 	struct hclge_dev *hdev = vport->back;
12546 	struct hclge_desc desc;
12547 	int ret;
12548 
12549 	if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2)
12550 		return -EOPNOTSUPP;
12551 
12552 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true);
12553 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12554 	if (ret) {
12555 		dev_err(&hdev->pdev->dev,
12556 			"failed to query link diagnosis info, ret = %d\n", ret);
12557 		return ret;
12558 	}
12559 
12560 	*status_code = le32_to_cpu(desc.data[0]);
12561 	return 0;
12562 }
12563 
12564 /* After disable sriov, VF still has some config and info need clean,
12565  * which configed by PF.
12566  */
12567 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid)
12568 {
12569 	struct hclge_dev *hdev = vport->back;
12570 	struct hclge_vlan_info vlan_info;
12571 	int ret;
12572 
12573 	clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
12574 	clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
12575 	vport->need_notify = 0;
12576 	vport->mps = 0;
12577 
12578 	/* after disable sriov, clean VF rate configured by PF */
12579 	ret = hclge_tm_qs_shaper_cfg(vport, 0);
12580 	if (ret)
12581 		dev_err(&hdev->pdev->dev,
12582 			"failed to clean vf%d rate config, ret = %d\n",
12583 			vfid, ret);
12584 
12585 	vlan_info.vlan_tag = 0;
12586 	vlan_info.qos = 0;
12587 	vlan_info.vlan_proto = ETH_P_8021Q;
12588 	ret = hclge_update_port_base_vlan_cfg(vport,
12589 					      HNAE3_PORT_BASE_VLAN_DISABLE,
12590 					      &vlan_info);
12591 	if (ret)
12592 		dev_err(&hdev->pdev->dev,
12593 			"failed to clean vf%d port base vlan, ret = %d\n",
12594 			vfid, ret);
12595 
12596 	ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false);
12597 	if (ret)
12598 		dev_err(&hdev->pdev->dev,
12599 			"failed to clean vf%d spoof config, ret = %d\n",
12600 			vfid, ret);
12601 
12602 	memset(&vport->vf_info, 0, sizeof(vport->vf_info));
12603 }
12604 
12605 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs)
12606 {
12607 	struct hclge_dev *hdev = ae_dev->priv;
12608 	struct hclge_vport *vport;
12609 	int i;
12610 
12611 	for (i = 0; i < num_vfs; i++) {
12612 		vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
12613 
12614 		hclge_clear_vport_vf_info(vport, i);
12615 	}
12616 }
12617 
12618 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode,
12619 			       u8 *priority)
12620 {
12621 	struct hclge_vport *vport = hclge_get_vport(h);
12622 
12623 	if (dscp >= HNAE3_MAX_DSCP)
12624 		return -EINVAL;
12625 
12626 	if (tc_mode)
12627 		*tc_mode = vport->nic.kinfo.tc_map_mode;
12628 	if (priority)
12629 		*priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 :
12630 			    vport->nic.kinfo.dscp_prio[dscp];
12631 
12632 	return 0;
12633 }
12634 
12635 static const struct hnae3_ae_ops hclge_ops = {
12636 	.init_ae_dev = hclge_init_ae_dev,
12637 	.uninit_ae_dev = hclge_uninit_ae_dev,
12638 	.reset_prepare = hclge_reset_prepare_general,
12639 	.reset_done = hclge_reset_done,
12640 	.init_client_instance = hclge_init_client_instance,
12641 	.uninit_client_instance = hclge_uninit_client_instance,
12642 	.map_ring_to_vector = hclge_map_ring_to_vector,
12643 	.unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
12644 	.get_vector = hclge_get_vector,
12645 	.put_vector = hclge_put_vector,
12646 	.set_promisc_mode = hclge_set_promisc_mode,
12647 	.request_update_promisc_mode = hclge_request_update_promisc_mode,
12648 	.set_loopback = hclge_set_loopback,
12649 	.start = hclge_ae_start,
12650 	.stop = hclge_ae_stop,
12651 	.client_start = hclge_client_start,
12652 	.client_stop = hclge_client_stop,
12653 	.get_status = hclge_get_status,
12654 	.get_ksettings_an_result = hclge_get_ksettings_an_result,
12655 	.cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
12656 	.get_media_type = hclge_get_media_type,
12657 	.check_port_speed = hclge_check_port_speed,
12658 	.get_fec_stats = hclge_get_fec_stats,
12659 	.get_fec = hclge_get_fec,
12660 	.set_fec = hclge_set_fec,
12661 	.get_rss_key_size = hclge_comm_get_rss_key_size,
12662 	.get_rss = hclge_get_rss,
12663 	.set_rss = hclge_set_rss,
12664 	.set_rss_tuple = hclge_set_rss_tuple,
12665 	.get_rss_tuple = hclge_get_rss_tuple,
12666 	.get_tc_size = hclge_get_tc_size,
12667 	.get_mac_addr = hclge_get_mac_addr,
12668 	.set_mac_addr = hclge_set_mac_addr,
12669 	.do_ioctl = hclge_do_ioctl,
12670 	.add_uc_addr = hclge_add_uc_addr,
12671 	.rm_uc_addr = hclge_rm_uc_addr,
12672 	.add_mc_addr = hclge_add_mc_addr,
12673 	.rm_mc_addr = hclge_rm_mc_addr,
12674 	.set_autoneg = hclge_set_autoneg,
12675 	.get_autoneg = hclge_get_autoneg,
12676 	.restart_autoneg = hclge_restart_autoneg,
12677 	.halt_autoneg = hclge_halt_autoneg,
12678 	.get_pauseparam = hclge_get_pauseparam,
12679 	.set_pauseparam = hclge_set_pauseparam,
12680 	.set_mtu = hclge_set_mtu,
12681 	.reset_queue = hclge_reset_tqp,
12682 	.get_stats = hclge_get_stats,
12683 	.get_mac_stats = hclge_get_mac_stat,
12684 	.update_stats = hclge_update_stats,
12685 	.get_strings = hclge_get_strings,
12686 	.get_sset_count = hclge_get_sset_count,
12687 	.get_fw_version = hclge_get_fw_version,
12688 	.get_mdix_mode = hclge_get_mdix_mode,
12689 	.enable_vlan_filter = hclge_enable_vlan_filter,
12690 	.set_vlan_filter = hclge_set_vlan_filter,
12691 	.set_vf_vlan_filter = hclge_set_vf_vlan_filter,
12692 	.enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
12693 	.reset_event = hclge_reset_event,
12694 	.get_reset_level = hclge_get_reset_level,
12695 	.set_default_reset_request = hclge_set_def_reset_request,
12696 	.get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
12697 	.set_channels = hclge_set_channels,
12698 	.get_channels = hclge_get_channels,
12699 	.get_regs_len = hclge_get_regs_len,
12700 	.get_regs = hclge_get_regs,
12701 	.set_led_id = hclge_set_led_id,
12702 	.get_link_mode = hclge_get_link_mode,
12703 	.add_fd_entry = hclge_add_fd_entry,
12704 	.del_fd_entry = hclge_del_fd_entry,
12705 	.get_fd_rule_cnt = hclge_get_fd_rule_cnt,
12706 	.get_fd_rule_info = hclge_get_fd_rule_info,
12707 	.get_fd_all_rules = hclge_get_all_rules,
12708 	.enable_fd = hclge_enable_fd,
12709 	.add_arfs_entry = hclge_add_fd_entry_by_arfs,
12710 	.dbg_read_cmd = hclge_dbg_read_cmd,
12711 	.handle_hw_ras_error = hclge_handle_hw_ras_error,
12712 	.get_hw_reset_stat = hclge_get_hw_reset_stat,
12713 	.ae_dev_resetting = hclge_ae_dev_resetting,
12714 	.ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
12715 	.set_gro_en = hclge_gro_en,
12716 	.get_global_queue_id = hclge_covert_handle_qid_global,
12717 	.set_timer_task = hclge_set_timer_task,
12718 	.mac_connect_phy = hclge_mac_connect_phy,
12719 	.mac_disconnect_phy = hclge_mac_disconnect_phy,
12720 	.get_vf_config = hclge_get_vf_config,
12721 	.set_vf_link_state = hclge_set_vf_link_state,
12722 	.set_vf_spoofchk = hclge_set_vf_spoofchk,
12723 	.set_vf_trust = hclge_set_vf_trust,
12724 	.set_vf_rate = hclge_set_vf_rate,
12725 	.set_vf_mac = hclge_set_vf_mac,
12726 	.get_module_eeprom = hclge_get_module_eeprom,
12727 	.get_cmdq_stat = hclge_get_cmdq_stat,
12728 	.add_cls_flower = hclge_add_cls_flower,
12729 	.del_cls_flower = hclge_del_cls_flower,
12730 	.cls_flower_active = hclge_is_cls_flower_active,
12731 	.get_phy_link_ksettings = hclge_get_phy_link_ksettings,
12732 	.set_phy_link_ksettings = hclge_set_phy_link_ksettings,
12733 	.set_tx_hwts_info = hclge_ptp_set_tx_info,
12734 	.get_rx_hwts = hclge_ptp_get_rx_hwts,
12735 	.get_ts_info = hclge_ptp_get_ts_info,
12736 	.get_link_diagnosis_info = hclge_get_link_diagnosis_info,
12737 	.clean_vf_config = hclge_clean_vport_config,
12738 	.get_dscp_prio = hclge_get_dscp_prio,
12739 	.get_wol = hclge_get_wol,
12740 	.set_wol = hclge_set_wol,
12741 };
12742 
12743 static struct hnae3_ae_algo ae_algo = {
12744 	.ops = &hclge_ops,
12745 	.pdev_id_table = ae_algo_pci_tbl,
12746 };
12747 
12748 static int __init hclge_init(void)
12749 {
12750 	pr_info("%s is initializing\n", HCLGE_NAME);
12751 
12752 	hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME);
12753 	if (!hclge_wq) {
12754 		pr_err("%s: failed to create workqueue\n", HCLGE_NAME);
12755 		return -ENOMEM;
12756 	}
12757 
12758 	hnae3_register_ae_algo(&ae_algo);
12759 
12760 	return 0;
12761 }
12762 
12763 static void __exit hclge_exit(void)
12764 {
12765 	hnae3_unregister_ae_algo_prepare(&ae_algo);
12766 	hnae3_unregister_ae_algo(&ae_algo);
12767 	destroy_workqueue(hclge_wq);
12768 }
12769 module_init(hclge_init);
12770 module_exit(hclge_exit);
12771 
12772 MODULE_LICENSE("GPL");
12773 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
12774 MODULE_DESCRIPTION("HCLGE Driver");
12775 MODULE_VERSION(HCLGE_MOD_VERSION);
12776