1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #include "hclge_err.h" 5 6 static const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = { 7 { .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err", 8 .reset_level = HNAE3_NONE_RESET }, 9 { .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err", 10 .reset_level = HNAE3_NONE_RESET }, 11 { .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err", 12 .reset_level = HNAE3_NONE_RESET }, 13 { .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err", 14 .reset_level = HNAE3_NONE_RESET }, 15 { .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err", 16 .reset_level = HNAE3_NONE_RESET }, 17 { .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err", 18 .reset_level = HNAE3_NONE_RESET }, 19 { .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err", 20 .reset_level = HNAE3_NONE_RESET }, 21 { .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err", 22 .reset_level = HNAE3_NONE_RESET }, 23 { .int_msk = BIT(17), .msg = "imp_itcm4_ecc_mbit_err", 24 .reset_level = HNAE3_NONE_RESET }, 25 { /* sentinel */ } 26 }; 27 28 static const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[] = { 29 { .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err", 30 .reset_level = HNAE3_NONE_RESET }, 31 { .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err", 32 .reset_level = HNAE3_NONE_RESET }, 33 { .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err", 34 .reset_level = HNAE3_NONE_RESET }, 35 { .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err", 36 .reset_level = HNAE3_NONE_RESET }, 37 { .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err", 38 .reset_level = HNAE3_NONE_RESET }, 39 { .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err", 40 .reset_level = HNAE3_NONE_RESET }, 41 { .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err", 42 .reset_level = HNAE3_NONE_RESET }, 43 { .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err", 44 .reset_level = HNAE3_NONE_RESET }, 45 { .int_msk = BIT(17), .msg = "cmdq_rocee_rx_depth_ecc_mbit_err", 46 .reset_level = HNAE3_NONE_RESET }, 47 { .int_msk = BIT(19), .msg = "cmdq_rocee_tx_depth_ecc_mbit_err", 48 .reset_level = HNAE3_NONE_RESET }, 49 { .int_msk = BIT(21), .msg = "cmdq_rocee_rx_tail_ecc_mbit_err", 50 .reset_level = HNAE3_NONE_RESET }, 51 { .int_msk = BIT(23), .msg = "cmdq_rocee_tx_tail_ecc_mbit_err", 52 .reset_level = HNAE3_NONE_RESET }, 53 { .int_msk = BIT(25), .msg = "cmdq_rocee_rx_head_ecc_mbit_err", 54 .reset_level = HNAE3_NONE_RESET }, 55 { .int_msk = BIT(27), .msg = "cmdq_rocee_tx_head_ecc_mbit_err", 56 .reset_level = HNAE3_NONE_RESET }, 57 { .int_msk = BIT(29), .msg = "cmdq_rocee_rx_addr_ecc_mbit_err", 58 .reset_level = HNAE3_NONE_RESET }, 59 { .int_msk = BIT(31), .msg = "cmdq_rocee_tx_addr_ecc_mbit_err", 60 .reset_level = HNAE3_NONE_RESET }, 61 { /* sentinel */ } 62 }; 63 64 static const struct hclge_hw_error hclge_tqp_int_ecc_int[] = { 65 { .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err", 66 .reset_level = HNAE3_NONE_RESET }, 67 { .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err", 68 .reset_level = HNAE3_NONE_RESET }, 69 { .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err", 70 .reset_level = HNAE3_NONE_RESET }, 71 { .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err", 72 .reset_level = HNAE3_NONE_RESET }, 73 { .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err", 74 .reset_level = HNAE3_NONE_RESET }, 75 { .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err", 76 .reset_level = HNAE3_NONE_RESET }, 77 { /* sentinel */ } 78 }; 79 80 static const struct hclge_hw_error hclge_msix_sram_ecc_int[] = { 81 { .int_msk = BIT(1), .msg = "msix_nic_ecc_mbit_err", 82 .reset_level = HNAE3_NONE_RESET }, 83 { .int_msk = BIT(3), .msg = "msix_rocee_ecc_mbit_err", 84 .reset_level = HNAE3_NONE_RESET }, 85 { /* sentinel */ } 86 }; 87 88 static const struct hclge_hw_error hclge_igu_int[] = { 89 { .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err", 90 .reset_level = HNAE3_GLOBAL_RESET }, 91 { .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err", 92 .reset_level = HNAE3_GLOBAL_RESET }, 93 { /* sentinel */ } 94 }; 95 96 static const struct hclge_hw_error hclge_igu_egu_tnl_int[] = { 97 { .int_msk = BIT(0), .msg = "rx_buf_overflow", 98 .reset_level = HNAE3_GLOBAL_RESET }, 99 { .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow", 100 .reset_level = HNAE3_GLOBAL_RESET }, 101 { .int_msk = BIT(2), .msg = "rx_stp_fifo_underflow", 102 .reset_level = HNAE3_GLOBAL_RESET }, 103 { .int_msk = BIT(3), .msg = "tx_buf_overflow", 104 .reset_level = HNAE3_GLOBAL_RESET }, 105 { .int_msk = BIT(4), .msg = "tx_buf_underrun", 106 .reset_level = HNAE3_GLOBAL_RESET }, 107 { .int_msk = BIT(5), .msg = "rx_stp_buf_overflow", 108 .reset_level = HNAE3_GLOBAL_RESET }, 109 { /* sentinel */ } 110 }; 111 112 static const struct hclge_hw_error hclge_ncsi_err_int[] = { 113 { .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err", 114 .reset_level = HNAE3_NONE_RESET }, 115 { /* sentinel */ } 116 }; 117 118 static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st1[] = { 119 { .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err", 120 .reset_level = HNAE3_GLOBAL_RESET }, 121 { .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err", 122 .reset_level = HNAE3_GLOBAL_RESET }, 123 { .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err", 124 .reset_level = HNAE3_GLOBAL_RESET }, 125 { .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err", 126 .reset_level = HNAE3_GLOBAL_RESET }, 127 { .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err", 128 .reset_level = HNAE3_GLOBAL_RESET }, 129 { .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err", 130 .reset_level = HNAE3_GLOBAL_RESET }, 131 { .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_err", 132 .reset_level = HNAE3_GLOBAL_RESET }, 133 { .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err", 134 .reset_level = HNAE3_GLOBAL_RESET }, 135 { .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err", 136 .reset_level = HNAE3_GLOBAL_RESET }, 137 { .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err", 138 .reset_level = HNAE3_GLOBAL_RESET }, 139 { .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err", 140 .reset_level = HNAE3_GLOBAL_RESET }, 141 { .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err", 142 .reset_level = HNAE3_GLOBAL_RESET }, 143 { .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err", 144 .reset_level = HNAE3_GLOBAL_RESET }, 145 { .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err", 146 .reset_level = HNAE3_GLOBAL_RESET }, 147 { .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err", 148 .reset_level = HNAE3_GLOBAL_RESET }, 149 { .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err", 150 .reset_level = HNAE3_GLOBAL_RESET }, 151 { .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err", 152 .reset_level = HNAE3_GLOBAL_RESET }, 153 { .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err", 154 .reset_level = HNAE3_GLOBAL_RESET }, 155 { .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err", 156 .reset_level = HNAE3_GLOBAL_RESET }, 157 { .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err", 158 .reset_level = HNAE3_GLOBAL_RESET }, 159 { .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err", 160 .reset_level = HNAE3_GLOBAL_RESET }, 161 { .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err", 162 .reset_level = HNAE3_GLOBAL_RESET }, 163 { .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err", 164 .reset_level = HNAE3_GLOBAL_RESET }, 165 { .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err", 166 .reset_level = HNAE3_GLOBAL_RESET }, 167 { .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err", 168 .reset_level = HNAE3_GLOBAL_RESET }, 169 { .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err", 170 .reset_level = HNAE3_GLOBAL_RESET }, 171 { .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err", 172 .reset_level = HNAE3_GLOBAL_RESET }, 173 { .int_msk = BIT(27), .msg = "flow_director_ad_mem0_ecc_mbit_err", 174 .reset_level = HNAE3_GLOBAL_RESET }, 175 { .int_msk = BIT(28), .msg = "flow_director_ad_mem1_ecc_mbit_err", 176 .reset_level = HNAE3_GLOBAL_RESET }, 177 { .int_msk = BIT(29), .msg = "rx_vlan_tag_memory_ecc_mbit_err", 178 .reset_level = HNAE3_GLOBAL_RESET }, 179 { .int_msk = BIT(30), .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", 180 .reset_level = HNAE3_GLOBAL_RESET }, 181 { /* sentinel */ } 182 }; 183 184 static const struct hclge_hw_error hclge_ppp_pf_abnormal_int[] = { 185 { .int_msk = BIT(0), .msg = "tx_vlan_tag_err", 186 .reset_level = HNAE3_NONE_RESET }, 187 { .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err", 188 .reset_level = HNAE3_NONE_RESET }, 189 { /* sentinel */ } 190 }; 191 192 static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st3[] = { 193 { .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err", 194 .reset_level = HNAE3_GLOBAL_RESET }, 195 { .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err", 196 .reset_level = HNAE3_GLOBAL_RESET }, 197 { .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err", 198 .reset_level = HNAE3_GLOBAL_RESET }, 199 { .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err", 200 .reset_level = HNAE3_GLOBAL_RESET }, 201 { .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err", 202 .reset_level = HNAE3_GLOBAL_RESET }, 203 { .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err", 204 .reset_level = HNAE3_GLOBAL_RESET }, 205 { /* sentinel */ } 206 }; 207 208 static const struct hclge_hw_error hclge_tm_sch_rint[] = { 209 { .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err", 210 .reset_level = HNAE3_GLOBAL_RESET }, 211 { .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_err", 212 .reset_level = HNAE3_GLOBAL_RESET }, 213 { .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_err", 214 .reset_level = HNAE3_GLOBAL_RESET }, 215 { .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", 216 .reset_level = HNAE3_GLOBAL_RESET }, 217 { .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", 218 .reset_level = HNAE3_GLOBAL_RESET }, 219 { .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", 220 .reset_level = HNAE3_GLOBAL_RESET }, 221 { .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", 222 .reset_level = HNAE3_GLOBAL_RESET }, 223 { .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", 224 .reset_level = HNAE3_GLOBAL_RESET }, 225 { .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", 226 .reset_level = HNAE3_GLOBAL_RESET }, 227 { .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", 228 .reset_level = HNAE3_GLOBAL_RESET }, 229 { .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", 230 .reset_level = HNAE3_GLOBAL_RESET }, 231 { .int_msk = BIT(12), .msg = "tm_sch_port_shap_offset_fifo_wr_err", 232 .reset_level = HNAE3_GLOBAL_RESET }, 233 { .int_msk = BIT(13), .msg = "tm_sch_port_shap_offset_fifo_rd_err", 234 .reset_level = HNAE3_GLOBAL_RESET }, 235 { .int_msk = BIT(14), .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", 236 .reset_level = HNAE3_GLOBAL_RESET }, 237 { .int_msk = BIT(15), .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", 238 .reset_level = HNAE3_GLOBAL_RESET }, 239 { .int_msk = BIT(16), .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", 240 .reset_level = HNAE3_GLOBAL_RESET }, 241 { .int_msk = BIT(17), .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", 242 .reset_level = HNAE3_GLOBAL_RESET }, 243 { .int_msk = BIT(18), .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", 244 .reset_level = HNAE3_GLOBAL_RESET }, 245 { .int_msk = BIT(19), .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", 246 .reset_level = HNAE3_GLOBAL_RESET }, 247 { .int_msk = BIT(20), .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", 248 .reset_level = HNAE3_GLOBAL_RESET }, 249 { .int_msk = BIT(21), .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", 250 .reset_level = HNAE3_GLOBAL_RESET }, 251 { .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_err", 252 .reset_level = HNAE3_GLOBAL_RESET }, 253 { .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_err", 254 .reset_level = HNAE3_GLOBAL_RESET }, 255 { .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_err", 256 .reset_level = HNAE3_GLOBAL_RESET }, 257 { .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_err", 258 .reset_level = HNAE3_GLOBAL_RESET }, 259 { .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_err", 260 .reset_level = HNAE3_GLOBAL_RESET }, 261 { .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_err", 262 .reset_level = HNAE3_GLOBAL_RESET }, 263 { .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_err", 264 .reset_level = HNAE3_GLOBAL_RESET }, 265 { .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_err", 266 .reset_level = HNAE3_GLOBAL_RESET }, 267 { .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_err", 268 .reset_level = HNAE3_GLOBAL_RESET }, 269 { .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_err", 270 .reset_level = HNAE3_GLOBAL_RESET }, 271 { /* sentinel */ } 272 }; 273 274 static const struct hclge_hw_error hclge_qcn_fifo_rint[] = { 275 { .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err", 276 .reset_level = HNAE3_GLOBAL_RESET }, 277 { .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err", 278 .reset_level = HNAE3_GLOBAL_RESET }, 279 { .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err", 280 .reset_level = HNAE3_GLOBAL_RESET }, 281 { .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err", 282 .reset_level = HNAE3_GLOBAL_RESET }, 283 { .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err", 284 .reset_level = HNAE3_GLOBAL_RESET }, 285 { .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err", 286 .reset_level = HNAE3_GLOBAL_RESET }, 287 { .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err", 288 .reset_level = HNAE3_GLOBAL_RESET }, 289 { .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err", 290 .reset_level = HNAE3_GLOBAL_RESET }, 291 { .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err", 292 .reset_level = HNAE3_GLOBAL_RESET }, 293 { .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err", 294 .reset_level = HNAE3_GLOBAL_RESET }, 295 { .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err", 296 .reset_level = HNAE3_GLOBAL_RESET }, 297 { .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err", 298 .reset_level = HNAE3_GLOBAL_RESET }, 299 { .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err", 300 .reset_level = HNAE3_GLOBAL_RESET }, 301 { .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err", 302 .reset_level = HNAE3_GLOBAL_RESET }, 303 { .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err", 304 .reset_level = HNAE3_GLOBAL_RESET }, 305 { .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err", 306 .reset_level = HNAE3_GLOBAL_RESET }, 307 { .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err", 308 .reset_level = HNAE3_GLOBAL_RESET }, 309 { .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err", 310 .reset_level = HNAE3_GLOBAL_RESET }, 311 { /* sentinel */ } 312 }; 313 314 static const struct hclge_hw_error hclge_qcn_ecc_rint[] = { 315 { .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err", 316 .reset_level = HNAE3_GLOBAL_RESET }, 317 { .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err", 318 .reset_level = HNAE3_GLOBAL_RESET }, 319 { .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err", 320 .reset_level = HNAE3_GLOBAL_RESET }, 321 { .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err", 322 .reset_level = HNAE3_GLOBAL_RESET }, 323 { .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err", 324 .reset_level = HNAE3_GLOBAL_RESET }, 325 { .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err", 326 .reset_level = HNAE3_GLOBAL_RESET }, 327 { .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err", 328 .reset_level = HNAE3_GLOBAL_RESET }, 329 { .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", 330 .reset_level = HNAE3_GLOBAL_RESET }, 331 { .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", 332 .reset_level = HNAE3_GLOBAL_RESET }, 333 { .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", 334 .reset_level = HNAE3_GLOBAL_RESET }, 335 { .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err", 336 .reset_level = HNAE3_GLOBAL_RESET }, 337 { /* sentinel */ } 338 }; 339 340 static const struct hclge_hw_error hclge_mac_afifo_tnl_int[] = { 341 { .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err", 342 .reset_level = HNAE3_NONE_RESET }, 343 { .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err", 344 .reset_level = HNAE3_GLOBAL_RESET }, 345 { .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err", 346 .reset_level = HNAE3_NONE_RESET }, 347 { .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err", 348 .reset_level = HNAE3_GLOBAL_RESET }, 349 { .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err", 350 .reset_level = HNAE3_NONE_RESET }, 351 { .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err", 352 .reset_level = HNAE3_GLOBAL_RESET }, 353 { .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err", 354 .reset_level = HNAE3_NONE_RESET }, 355 { .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err", 356 .reset_level = HNAE3_GLOBAL_RESET }, 357 { .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err", 358 .reset_level = HNAE3_GLOBAL_RESET }, 359 { .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err", 360 .reset_level = HNAE3_GLOBAL_RESET }, 361 { .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err", 362 .reset_level = HNAE3_GLOBAL_RESET }, 363 { .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err", 364 .reset_level = HNAE3_GLOBAL_RESET }, 365 { .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err", 366 .reset_level = HNAE3_GLOBAL_RESET }, 367 { .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err", 368 .reset_level = HNAE3_GLOBAL_RESET }, 369 { /* sentinel */ } 370 }; 371 372 static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = { 373 { .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", 374 .reset_level = HNAE3_GLOBAL_RESET }, 375 { .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", 376 .reset_level = HNAE3_GLOBAL_RESET }, 377 { .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", 378 .reset_level = HNAE3_GLOBAL_RESET }, 379 { .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", 380 .reset_level = HNAE3_GLOBAL_RESET }, 381 { .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err", 382 .reset_level = HNAE3_GLOBAL_RESET }, 383 { .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err", 384 .reset_level = HNAE3_GLOBAL_RESET }, 385 { .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err", 386 .reset_level = HNAE3_GLOBAL_RESET }, 387 { .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err", 388 .reset_level = HNAE3_GLOBAL_RESET }, 389 { .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err", 390 .reset_level = HNAE3_GLOBAL_RESET }, 391 { .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err", 392 .reset_level = HNAE3_GLOBAL_RESET }, 393 { .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err", 394 .reset_level = HNAE3_GLOBAL_RESET }, 395 { .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err", 396 .reset_level = HNAE3_GLOBAL_RESET }, 397 { .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err", 398 .reset_level = HNAE3_GLOBAL_RESET }, 399 { .int_msk = BIT(26), .msg = "rd_bus_err", 400 .reset_level = HNAE3_GLOBAL_RESET }, 401 { .int_msk = BIT(27), .msg = "wr_bus_err", 402 .reset_level = HNAE3_GLOBAL_RESET }, 403 { .int_msk = BIT(28), .msg = "reg_search_miss", 404 .reset_level = HNAE3_GLOBAL_RESET }, 405 { .int_msk = BIT(29), .msg = "rx_q_search_miss", 406 .reset_level = HNAE3_NONE_RESET }, 407 { .int_msk = BIT(30), .msg = "ooo_ecc_err_detect", 408 .reset_level = HNAE3_NONE_RESET }, 409 { .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl", 410 .reset_level = HNAE3_GLOBAL_RESET }, 411 { /* sentinel */ } 412 }; 413 414 static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = { 415 { .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err", 416 .reset_level = HNAE3_GLOBAL_RESET }, 417 { .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err", 418 .reset_level = HNAE3_GLOBAL_RESET }, 419 { .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err", 420 .reset_level = HNAE3_GLOBAL_RESET }, 421 { .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err", 422 .reset_level = HNAE3_GLOBAL_RESET }, 423 { /* sentinel */ } 424 }; 425 426 static const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = { 427 { .int_msk = BIT(0), .msg = "over_8bd_no_fe", 428 .reset_level = HNAE3_FUNC_RESET }, 429 { .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err", 430 .reset_level = HNAE3_NONE_RESET }, 431 { .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err", 432 .reset_level = HNAE3_NONE_RESET }, 433 { .int_msk = BIT(3), .msg = "tx_rd_fbd_poison", 434 .reset_level = HNAE3_FUNC_RESET }, 435 { .int_msk = BIT(4), .msg = "rx_rd_ebd_poison", 436 .reset_level = HNAE3_FUNC_RESET }, 437 { .int_msk = BIT(5), .msg = "buf_wait_timeout", 438 .reset_level = HNAE3_NONE_RESET }, 439 { /* sentinel */ } 440 }; 441 442 static const struct hclge_hw_error hclge_ssu_com_err_int[] = { 443 { .int_msk = BIT(0), .msg = "buf_sum_err", 444 .reset_level = HNAE3_NONE_RESET }, 445 { .int_msk = BIT(1), .msg = "ppp_mb_num_err", 446 .reset_level = HNAE3_NONE_RESET }, 447 { .int_msk = BIT(2), .msg = "ppp_mbid_err", 448 .reset_level = HNAE3_GLOBAL_RESET }, 449 { .int_msk = BIT(3), .msg = "ppp_rlt_mac_err", 450 .reset_level = HNAE3_GLOBAL_RESET }, 451 { .int_msk = BIT(4), .msg = "ppp_rlt_host_err", 452 .reset_level = HNAE3_GLOBAL_RESET }, 453 { .int_msk = BIT(5), .msg = "cks_edit_position_err", 454 .reset_level = HNAE3_GLOBAL_RESET }, 455 { .int_msk = BIT(6), .msg = "cks_edit_condition_err", 456 .reset_level = HNAE3_GLOBAL_RESET }, 457 { .int_msk = BIT(7), .msg = "vlan_edit_condition_err", 458 .reset_level = HNAE3_GLOBAL_RESET }, 459 { .int_msk = BIT(8), .msg = "vlan_num_ot_err", 460 .reset_level = HNAE3_GLOBAL_RESET }, 461 { .int_msk = BIT(9), .msg = "vlan_num_in_err", 462 .reset_level = HNAE3_GLOBAL_RESET }, 463 { /* sentinel */ } 464 }; 465 466 #define HCLGE_SSU_MEM_ECC_ERR(x) \ 467 { .int_msk = BIT(x), .msg = "ssu_mem" #x "_ecc_mbit_err", \ 468 .reset_level = HNAE3_GLOBAL_RESET } 469 470 static const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = { 471 HCLGE_SSU_MEM_ECC_ERR(0), 472 HCLGE_SSU_MEM_ECC_ERR(1), 473 HCLGE_SSU_MEM_ECC_ERR(2), 474 HCLGE_SSU_MEM_ECC_ERR(3), 475 HCLGE_SSU_MEM_ECC_ERR(4), 476 HCLGE_SSU_MEM_ECC_ERR(5), 477 HCLGE_SSU_MEM_ECC_ERR(6), 478 HCLGE_SSU_MEM_ECC_ERR(7), 479 HCLGE_SSU_MEM_ECC_ERR(8), 480 HCLGE_SSU_MEM_ECC_ERR(9), 481 HCLGE_SSU_MEM_ECC_ERR(10), 482 HCLGE_SSU_MEM_ECC_ERR(11), 483 HCLGE_SSU_MEM_ECC_ERR(12), 484 HCLGE_SSU_MEM_ECC_ERR(13), 485 HCLGE_SSU_MEM_ECC_ERR(14), 486 HCLGE_SSU_MEM_ECC_ERR(15), 487 HCLGE_SSU_MEM_ECC_ERR(16), 488 HCLGE_SSU_MEM_ECC_ERR(17), 489 HCLGE_SSU_MEM_ECC_ERR(18), 490 HCLGE_SSU_MEM_ECC_ERR(19), 491 HCLGE_SSU_MEM_ECC_ERR(20), 492 HCLGE_SSU_MEM_ECC_ERR(21), 493 HCLGE_SSU_MEM_ECC_ERR(22), 494 HCLGE_SSU_MEM_ECC_ERR(23), 495 HCLGE_SSU_MEM_ECC_ERR(24), 496 HCLGE_SSU_MEM_ECC_ERR(25), 497 HCLGE_SSU_MEM_ECC_ERR(26), 498 HCLGE_SSU_MEM_ECC_ERR(27), 499 HCLGE_SSU_MEM_ECC_ERR(28), 500 HCLGE_SSU_MEM_ECC_ERR(29), 501 HCLGE_SSU_MEM_ECC_ERR(30), 502 HCLGE_SSU_MEM_ECC_ERR(31), 503 { /* sentinel */ } 504 }; 505 506 static const struct hclge_hw_error hclge_ssu_port_based_err_int[] = { 507 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port", 508 .reset_level = HNAE3_FUNC_RESET }, 509 { .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port", 510 .reset_level = HNAE3_GLOBAL_RESET }, 511 { .int_msk = BIT(2), .msg = "igu_pkt_without_key_port", 512 .reset_level = HNAE3_GLOBAL_RESET }, 513 { .int_msk = BIT(3), .msg = "roc_eof_mis_match_port", 514 .reset_level = HNAE3_GLOBAL_RESET }, 515 { .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port", 516 .reset_level = HNAE3_GLOBAL_RESET }, 517 { .int_msk = BIT(5), .msg = "igu_eof_mis_match_port", 518 .reset_level = HNAE3_GLOBAL_RESET }, 519 { .int_msk = BIT(6), .msg = "roc_sof_mis_match_port", 520 .reset_level = HNAE3_GLOBAL_RESET }, 521 { .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port", 522 .reset_level = HNAE3_GLOBAL_RESET }, 523 { .int_msk = BIT(8), .msg = "igu_sof_mis_match_port", 524 .reset_level = HNAE3_GLOBAL_RESET }, 525 { .int_msk = BIT(11), .msg = "ets_rd_int_rx_port", 526 .reset_level = HNAE3_GLOBAL_RESET }, 527 { .int_msk = BIT(12), .msg = "ets_wr_int_rx_port", 528 .reset_level = HNAE3_GLOBAL_RESET }, 529 { .int_msk = BIT(13), .msg = "ets_rd_int_tx_port", 530 .reset_level = HNAE3_GLOBAL_RESET }, 531 { .int_msk = BIT(14), .msg = "ets_wr_int_tx_port", 532 .reset_level = HNAE3_GLOBAL_RESET }, 533 { /* sentinel */ } 534 }; 535 536 static const struct hclge_hw_error hclge_ssu_fifo_overflow_int[] = { 537 { .int_msk = BIT(0), .msg = "ig_mac_inf_int", 538 .reset_level = HNAE3_GLOBAL_RESET }, 539 { .int_msk = BIT(1), .msg = "ig_host_inf_int", 540 .reset_level = HNAE3_GLOBAL_RESET }, 541 { .int_msk = BIT(2), .msg = "ig_roc_buf_int", 542 .reset_level = HNAE3_GLOBAL_RESET }, 543 { .int_msk = BIT(3), .msg = "ig_host_data_fifo_int", 544 .reset_level = HNAE3_GLOBAL_RESET }, 545 { .int_msk = BIT(4), .msg = "ig_host_key_fifo_int", 546 .reset_level = HNAE3_GLOBAL_RESET }, 547 { .int_msk = BIT(5), .msg = "tx_qcn_fifo_int", 548 .reset_level = HNAE3_GLOBAL_RESET }, 549 { .int_msk = BIT(6), .msg = "rx_qcn_fifo_int", 550 .reset_level = HNAE3_GLOBAL_RESET }, 551 { .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int", 552 .reset_level = HNAE3_GLOBAL_RESET }, 553 { .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int", 554 .reset_level = HNAE3_GLOBAL_RESET }, 555 { .int_msk = BIT(9), .msg = "qm_eof_fifo_int", 556 .reset_level = HNAE3_GLOBAL_RESET }, 557 { .int_msk = BIT(10), .msg = "mb_rlt_fifo_int", 558 .reset_level = HNAE3_GLOBAL_RESET }, 559 { .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int", 560 .reset_level = HNAE3_GLOBAL_RESET }, 561 { .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int", 562 .reset_level = HNAE3_GLOBAL_RESET }, 563 { .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int", 564 .reset_level = HNAE3_GLOBAL_RESET }, 565 { .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int", 566 .reset_level = HNAE3_GLOBAL_RESET }, 567 { .int_msk = BIT(15), .msg = "host_cmd_fifo_int", 568 .reset_level = HNAE3_GLOBAL_RESET }, 569 { .int_msk = BIT(16), .msg = "mac_cmd_fifo_int", 570 .reset_level = HNAE3_GLOBAL_RESET }, 571 { .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int", 572 .reset_level = HNAE3_GLOBAL_RESET }, 573 { .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int", 574 .reset_level = HNAE3_GLOBAL_RESET }, 575 { .int_msk = BIT(19), .msg = "dup_bitmap_empty_int", 576 .reset_level = HNAE3_GLOBAL_RESET }, 577 { .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int", 578 .reset_level = HNAE3_GLOBAL_RESET }, 579 { .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int", 580 .reset_level = HNAE3_GLOBAL_RESET }, 581 { .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int", 582 .reset_level = HNAE3_GLOBAL_RESET }, 583 { .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int", 584 .reset_level = HNAE3_GLOBAL_RESET }, 585 { /* sentinel */ } 586 }; 587 588 static const struct hclge_hw_error hclge_ssu_ets_tcg_int[] = { 589 { .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg", 590 .reset_level = HNAE3_GLOBAL_RESET }, 591 { .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg", 592 .reset_level = HNAE3_GLOBAL_RESET }, 593 { .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg", 594 .reset_level = HNAE3_GLOBAL_RESET }, 595 { .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg", 596 .reset_level = HNAE3_GLOBAL_RESET }, 597 { /* sentinel */ } 598 }; 599 600 static const struct hclge_hw_error hclge_ssu_port_based_pf_int[] = { 601 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port", 602 .reset_level = HNAE3_FUNC_RESET }, 603 { .int_msk = BIT(9), .msg = "low_water_line_err_port", 604 .reset_level = HNAE3_NONE_RESET }, 605 { .int_msk = BIT(10), .msg = "hi_water_line_err_port", 606 .reset_level = HNAE3_GLOBAL_RESET }, 607 { /* sentinel */ } 608 }; 609 610 static const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = { 611 { .int_msk = 0, .msg = "rocee qmm ovf: sgid invalid err" }, 612 { .int_msk = 0x4, .msg = "rocee qmm ovf: sgid ovf err" }, 613 { .int_msk = 0x8, .msg = "rocee qmm ovf: smac invalid err" }, 614 { .int_msk = 0xC, .msg = "rocee qmm ovf: smac ovf err" }, 615 { .int_msk = 0x10, .msg = "rocee qmm ovf: cqc invalid err" }, 616 { .int_msk = 0x11, .msg = "rocee qmm ovf: cqc ovf err" }, 617 { .int_msk = 0x12, .msg = "rocee qmm ovf: cqc hopnum err" }, 618 { .int_msk = 0x13, .msg = "rocee qmm ovf: cqc ba0 err" }, 619 { .int_msk = 0x14, .msg = "rocee qmm ovf: srqc invalid err" }, 620 { .int_msk = 0x15, .msg = "rocee qmm ovf: srqc ovf err" }, 621 { .int_msk = 0x16, .msg = "rocee qmm ovf: srqc hopnum err" }, 622 { .int_msk = 0x17, .msg = "rocee qmm ovf: srqc ba0 err" }, 623 { .int_msk = 0x18, .msg = "rocee qmm ovf: mpt invalid err" }, 624 { .int_msk = 0x19, .msg = "rocee qmm ovf: mpt ovf err" }, 625 { .int_msk = 0x1A, .msg = "rocee qmm ovf: mpt hopnum err" }, 626 { .int_msk = 0x1B, .msg = "rocee qmm ovf: mpt ba0 err" }, 627 { .int_msk = 0x1C, .msg = "rocee qmm ovf: qpc invalid err" }, 628 { .int_msk = 0x1D, .msg = "rocee qmm ovf: qpc ovf err" }, 629 { .int_msk = 0x1E, .msg = "rocee qmm ovf: qpc hopnum err" }, 630 { .int_msk = 0x1F, .msg = "rocee qmm ovf: qpc ba0 err" }, 631 { /* sentinel */ } 632 }; 633 634 static void hclge_log_error(struct device *dev, char *reg, 635 const struct hclge_hw_error *err, 636 u32 err_sts, unsigned long *reset_requests) 637 { 638 while (err->msg) { 639 if (err->int_msk & err_sts) { 640 dev_err(dev, "%s %s found [error status=0x%x]\n", 641 reg, err->msg, err_sts); 642 if (err->reset_level && 643 err->reset_level != HNAE3_NONE_RESET) 644 set_bit(err->reset_level, reset_requests); 645 } 646 err++; 647 } 648 } 649 650 /* hclge_cmd_query_error: read the error information 651 * @hdev: pointer to struct hclge_dev 652 * @desc: descriptor for describing the command 653 * @cmd: command opcode 654 * @flag: flag for extended command structure 655 * 656 * This function query the error info from hw register/s using command 657 */ 658 static int hclge_cmd_query_error(struct hclge_dev *hdev, 659 struct hclge_desc *desc, u32 cmd, u16 flag) 660 { 661 struct device *dev = &hdev->pdev->dev; 662 int desc_num = 1; 663 int ret; 664 665 hclge_cmd_setup_basic_desc(&desc[0], cmd, true); 666 if (flag) { 667 desc[0].flag |= cpu_to_le16(flag); 668 hclge_cmd_setup_basic_desc(&desc[1], cmd, true); 669 desc_num = 2; 670 } 671 672 ret = hclge_cmd_send(&hdev->hw, &desc[0], desc_num); 673 if (ret) 674 dev_err(dev, "query error cmd failed (%d)\n", ret); 675 676 return ret; 677 } 678 679 static int hclge_clear_mac_tnl_int(struct hclge_dev *hdev) 680 { 681 struct hclge_desc desc; 682 683 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_MAC_TNL_INT, false); 684 desc.data[0] = cpu_to_le32(HCLGE_MAC_TNL_INT_CLR); 685 686 return hclge_cmd_send(&hdev->hw, &desc, 1); 687 } 688 689 static int hclge_config_common_hw_err_int(struct hclge_dev *hdev, bool en) 690 { 691 struct device *dev = &hdev->pdev->dev; 692 struct hclge_desc desc[2]; 693 int ret; 694 695 /* configure common error interrupts */ 696 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_COMMON_ECC_INT_CFG, false); 697 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 698 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_COMMON_ECC_INT_CFG, false); 699 700 if (en) { 701 desc[0].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN); 702 desc[0].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN | 703 HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN); 704 desc[0].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN); 705 desc[0].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN | 706 HCLGE_MSIX_SRAM_ECC_ERR_INT_EN); 707 desc[0].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN); 708 } 709 710 desc[1].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK); 711 desc[1].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK | 712 HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK); 713 desc[1].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK); 714 desc[1].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN_MASK | 715 HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK); 716 desc[1].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK); 717 718 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2); 719 if (ret) 720 dev_err(dev, 721 "fail(%d) to configure common err interrupts\n", ret); 722 723 return ret; 724 } 725 726 static int hclge_config_ncsi_hw_err_int(struct hclge_dev *hdev, bool en) 727 { 728 struct device *dev = &hdev->pdev->dev; 729 struct hclge_desc desc; 730 int ret; 731 732 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 733 return 0; 734 735 /* configure NCSI error interrupts */ 736 hclge_cmd_setup_basic_desc(&desc, HCLGE_NCSI_INT_EN, false); 737 if (en) 738 desc.data[0] = cpu_to_le32(HCLGE_NCSI_ERR_INT_EN); 739 740 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 741 if (ret) 742 dev_err(dev, 743 "fail(%d) to configure NCSI error interrupts\n", ret); 744 745 return ret; 746 } 747 748 static int hclge_config_igu_egu_hw_err_int(struct hclge_dev *hdev, bool en) 749 { 750 struct device *dev = &hdev->pdev->dev; 751 struct hclge_desc desc; 752 int ret; 753 754 /* configure IGU,EGU error interrupts */ 755 hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_COMMON_INT_EN, false); 756 desc.data[0] = cpu_to_le32(HCLGE_IGU_ERR_INT_TYPE); 757 if (en) 758 desc.data[0] |= cpu_to_le32(HCLGE_IGU_ERR_INT_EN); 759 760 desc.data[1] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN_MASK); 761 762 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 763 if (ret) { 764 dev_err(dev, 765 "fail(%d) to configure IGU common interrupts\n", ret); 766 return ret; 767 } 768 769 hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_EGU_TNL_INT_EN, false); 770 if (en) 771 desc.data[0] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN); 772 773 desc.data[1] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN_MASK); 774 775 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 776 if (ret) { 777 dev_err(dev, 778 "fail(%d) to configure IGU-EGU TNL interrupts\n", ret); 779 return ret; 780 } 781 782 ret = hclge_config_ncsi_hw_err_int(hdev, en); 783 784 return ret; 785 } 786 787 static int hclge_config_ppp_error_interrupt(struct hclge_dev *hdev, u32 cmd, 788 bool en) 789 { 790 struct device *dev = &hdev->pdev->dev; 791 struct hclge_desc desc[2]; 792 int ret; 793 794 /* configure PPP error interrupts */ 795 hclge_cmd_setup_basic_desc(&desc[0], cmd, false); 796 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 797 hclge_cmd_setup_basic_desc(&desc[1], cmd, false); 798 799 if (cmd == HCLGE_PPP_CMD0_INT_CMD) { 800 if (en) { 801 desc[0].data[0] = 802 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN); 803 desc[0].data[1] = 804 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN); 805 desc[0].data[4] = cpu_to_le32(HCLGE_PPP_PF_ERR_INT_EN); 806 } 807 808 desc[1].data[0] = 809 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK); 810 desc[1].data[1] = 811 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK); 812 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 813 desc[1].data[2] = 814 cpu_to_le32(HCLGE_PPP_PF_ERR_INT_EN_MASK); 815 } else if (cmd == HCLGE_PPP_CMD1_INT_CMD) { 816 if (en) { 817 desc[0].data[0] = 818 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN); 819 desc[0].data[1] = 820 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN); 821 } 822 823 desc[1].data[0] = 824 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK); 825 desc[1].data[1] = 826 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK); 827 } 828 829 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2); 830 if (ret) 831 dev_err(dev, "fail(%d) to configure PPP error intr\n", ret); 832 833 return ret; 834 } 835 836 static int hclge_config_ppp_hw_err_int(struct hclge_dev *hdev, bool en) 837 { 838 int ret; 839 840 ret = hclge_config_ppp_error_interrupt(hdev, HCLGE_PPP_CMD0_INT_CMD, 841 en); 842 if (ret) 843 return ret; 844 845 ret = hclge_config_ppp_error_interrupt(hdev, HCLGE_PPP_CMD1_INT_CMD, 846 en); 847 848 return ret; 849 } 850 851 static int hclge_config_tm_hw_err_int(struct hclge_dev *hdev, bool en) 852 { 853 struct device *dev = &hdev->pdev->dev; 854 struct hclge_desc desc; 855 int ret; 856 857 /* configure TM SCH hw errors */ 858 hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_SCH_ECC_INT_EN, false); 859 if (en) 860 desc.data[0] = cpu_to_le32(HCLGE_TM_SCH_ECC_ERR_INT_EN); 861 862 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 863 if (ret) { 864 dev_err(dev, "fail(%d) to configure TM SCH errors\n", ret); 865 return ret; 866 } 867 868 /* configure TM QCN hw errors */ 869 hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_QCN_MEM_INT_CFG, false); 870 if (en) 871 desc.data[1] = cpu_to_le32(HCLGE_TM_QCN_MEM_ERR_INT_EN); 872 873 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 874 if (ret) 875 dev_err(dev, 876 "fail(%d) to configure TM QCN mem errors\n", ret); 877 878 return ret; 879 } 880 881 static int hclge_config_mac_err_int(struct hclge_dev *hdev, bool en) 882 { 883 struct device *dev = &hdev->pdev->dev; 884 struct hclge_desc desc; 885 int ret; 886 887 /* configure MAC common error interrupts */ 888 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_COMMON_INT_EN, false); 889 if (en) 890 desc.data[0] = cpu_to_le32(HCLGE_MAC_COMMON_ERR_INT_EN); 891 892 desc.data[1] = cpu_to_le32(HCLGE_MAC_COMMON_ERR_INT_EN_MASK); 893 894 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 895 if (ret) 896 dev_err(dev, 897 "fail(%d) to configure MAC COMMON error intr\n", ret); 898 899 return ret; 900 } 901 902 int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en) 903 { 904 struct hclge_desc desc; 905 906 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_TNL_INT_EN, false); 907 if (en) 908 desc.data[0] = cpu_to_le32(HCLGE_MAC_TNL_INT_EN); 909 else 910 desc.data[0] = 0; 911 912 desc.data[1] = cpu_to_le32(HCLGE_MAC_TNL_INT_EN_MASK); 913 914 return hclge_cmd_send(&hdev->hw, &desc, 1); 915 } 916 917 static int hclge_config_ppu_error_interrupts(struct hclge_dev *hdev, u32 cmd, 918 bool en) 919 { 920 struct device *dev = &hdev->pdev->dev; 921 struct hclge_desc desc[2]; 922 int desc_num = 1; 923 int ret; 924 925 /* configure PPU error interrupts */ 926 if (cmd == HCLGE_PPU_MPF_ECC_INT_CMD) { 927 hclge_cmd_setup_basic_desc(&desc[0], cmd, false); 928 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 929 hclge_cmd_setup_basic_desc(&desc[1], cmd, false); 930 if (en) { 931 desc[0].data[0] = 932 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT0_EN); 933 desc[0].data[1] = 934 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT1_EN); 935 desc[1].data[3] = 936 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT3_EN); 937 desc[1].data[4] = 938 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN); 939 } 940 941 desc[1].data[0] = 942 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK); 943 desc[1].data[1] = 944 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK); 945 desc[1].data[2] = 946 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK); 947 desc[1].data[3] |= 948 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK); 949 desc_num = 2; 950 } else if (cmd == HCLGE_PPU_MPF_OTHER_INT_CMD) { 951 hclge_cmd_setup_basic_desc(&desc[0], cmd, false); 952 if (en) 953 desc[0].data[0] = 954 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN2); 955 956 desc[0].data[2] = 957 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK); 958 } else if (cmd == HCLGE_PPU_PF_OTHER_INT_CMD) { 959 hclge_cmd_setup_basic_desc(&desc[0], cmd, false); 960 if (en) 961 desc[0].data[0] = 962 cpu_to_le32(HCLGE_PPU_PF_ABNORMAL_INT_EN); 963 964 desc[0].data[2] = 965 cpu_to_le32(HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK); 966 } else { 967 dev_err(dev, "Invalid cmd to configure PPU error interrupts\n"); 968 return -EINVAL; 969 } 970 971 ret = hclge_cmd_send(&hdev->hw, &desc[0], desc_num); 972 973 return ret; 974 } 975 976 static int hclge_config_ppu_hw_err_int(struct hclge_dev *hdev, bool en) 977 { 978 struct device *dev = &hdev->pdev->dev; 979 int ret; 980 981 ret = hclge_config_ppu_error_interrupts(hdev, HCLGE_PPU_MPF_ECC_INT_CMD, 982 en); 983 if (ret) { 984 dev_err(dev, "fail(%d) to configure PPU MPF ECC error intr\n", 985 ret); 986 return ret; 987 } 988 989 ret = hclge_config_ppu_error_interrupts(hdev, 990 HCLGE_PPU_MPF_OTHER_INT_CMD, 991 en); 992 if (ret) { 993 dev_err(dev, "fail(%d) to configure PPU MPF other intr\n", ret); 994 return ret; 995 } 996 997 ret = hclge_config_ppu_error_interrupts(hdev, 998 HCLGE_PPU_PF_OTHER_INT_CMD, en); 999 if (ret) 1000 dev_err(dev, "fail(%d) to configure PPU PF error interrupts\n", 1001 ret); 1002 return ret; 1003 } 1004 1005 static int hclge_config_ssu_hw_err_int(struct hclge_dev *hdev, bool en) 1006 { 1007 struct device *dev = &hdev->pdev->dev; 1008 struct hclge_desc desc[2]; 1009 int ret; 1010 1011 /* configure SSU ecc error interrupts */ 1012 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_ECC_INT_CMD, false); 1013 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1014 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_ECC_INT_CMD, false); 1015 if (en) { 1016 desc[0].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN); 1017 desc[0].data[1] = 1018 cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN); 1019 desc[0].data[4] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN); 1020 } 1021 1022 desc[1].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK); 1023 desc[1].data[1] = cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK); 1024 desc[1].data[2] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK); 1025 1026 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2); 1027 if (ret) { 1028 dev_err(dev, 1029 "fail(%d) to configure SSU ECC error interrupt\n", ret); 1030 return ret; 1031 } 1032 1033 /* configure SSU common error interrupts */ 1034 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_COMMON_INT_CMD, false); 1035 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1036 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_COMMON_INT_CMD, false); 1037 1038 if (en) { 1039 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 1040 desc[0].data[0] = 1041 cpu_to_le32(HCLGE_SSU_COMMON_INT_EN); 1042 else 1043 desc[0].data[0] = 1044 cpu_to_le32(HCLGE_SSU_COMMON_INT_EN & ~BIT(5)); 1045 desc[0].data[1] = cpu_to_le32(HCLGE_SSU_PORT_BASED_ERR_INT_EN); 1046 desc[0].data[2] = 1047 cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN); 1048 } 1049 1050 desc[1].data[0] = cpu_to_le32(HCLGE_SSU_COMMON_INT_EN_MASK | 1051 HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK); 1052 desc[1].data[1] = cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK); 1053 1054 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2); 1055 if (ret) 1056 dev_err(dev, 1057 "fail(%d) to configure SSU COMMON error intr\n", ret); 1058 1059 return ret; 1060 } 1061 1062 /* hclge_query_bd_num: query number of buffer descriptors 1063 * @hdev: pointer to struct hclge_dev 1064 * @is_ras: true for ras, false for msix 1065 * @mpf_bd_num: number of main PF interrupt buffer descriptors 1066 * @pf_bd_num: number of not main PF interrupt buffer descriptors 1067 * 1068 * This function querys number of mpf and pf buffer descriptors. 1069 */ 1070 static int hclge_query_bd_num(struct hclge_dev *hdev, bool is_ras, 1071 u32 *mpf_bd_num, u32 *pf_bd_num) 1072 { 1073 struct device *dev = &hdev->pdev->dev; 1074 u32 mpf_min_bd_num, pf_min_bd_num; 1075 enum hclge_opcode_type opcode; 1076 struct hclge_desc desc_bd; 1077 int ret; 1078 1079 if (is_ras) { 1080 opcode = HCLGE_QUERY_RAS_INT_STS_BD_NUM; 1081 mpf_min_bd_num = HCLGE_MPF_RAS_INT_MIN_BD_NUM; 1082 pf_min_bd_num = HCLGE_PF_RAS_INT_MIN_BD_NUM; 1083 } else { 1084 opcode = HCLGE_QUERY_MSIX_INT_STS_BD_NUM; 1085 mpf_min_bd_num = HCLGE_MPF_MSIX_INT_MIN_BD_NUM; 1086 pf_min_bd_num = HCLGE_PF_MSIX_INT_MIN_BD_NUM; 1087 } 1088 1089 hclge_cmd_setup_basic_desc(&desc_bd, opcode, true); 1090 ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1); 1091 if (ret) { 1092 dev_err(dev, "fail(%d) to query msix int status bd num\n", 1093 ret); 1094 return ret; 1095 } 1096 1097 *mpf_bd_num = le32_to_cpu(desc_bd.data[0]); 1098 *pf_bd_num = le32_to_cpu(desc_bd.data[1]); 1099 if (*mpf_bd_num < mpf_min_bd_num || *pf_bd_num < pf_min_bd_num) { 1100 dev_err(dev, "Invalid bd num: mpf(%u), pf(%u)\n", 1101 *mpf_bd_num, *pf_bd_num); 1102 return -EINVAL; 1103 } 1104 1105 return 0; 1106 } 1107 1108 /* hclge_handle_mpf_ras_error: handle all main PF RAS errors 1109 * @hdev: pointer to struct hclge_dev 1110 * @desc: descriptor for describing the command 1111 * @num: number of extended command structures 1112 * 1113 * This function handles all the main PF RAS errors in the 1114 * hw register/s using command. 1115 */ 1116 static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev, 1117 struct hclge_desc *desc, 1118 int num) 1119 { 1120 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1121 struct device *dev = &hdev->pdev->dev; 1122 __le32 *desc_data; 1123 u32 status; 1124 int ret; 1125 1126 /* query all main PF RAS errors */ 1127 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_MPF_RAS_INT, 1128 true); 1129 ret = hclge_cmd_send(&hdev->hw, &desc[0], num); 1130 if (ret) { 1131 dev_err(dev, "query all mpf ras int cmd failed (%d)\n", ret); 1132 return ret; 1133 } 1134 1135 /* log HNS common errors */ 1136 status = le32_to_cpu(desc[0].data[0]); 1137 if (status) 1138 hclge_log_error(dev, "IMP_TCM_ECC_INT_STS", 1139 &hclge_imp_tcm_ecc_int[0], status, 1140 &ae_dev->hw_err_reset_req); 1141 1142 status = le32_to_cpu(desc[0].data[1]); 1143 if (status) 1144 hclge_log_error(dev, "CMDQ_MEM_ECC_INT_STS", 1145 &hclge_cmdq_nic_mem_ecc_int[0], status, 1146 &ae_dev->hw_err_reset_req); 1147 1148 if ((le32_to_cpu(desc[0].data[2])) & BIT(0)) 1149 dev_warn(dev, "imp_rd_data_poison_err found\n"); 1150 1151 status = le32_to_cpu(desc[0].data[3]); 1152 if (status) 1153 hclge_log_error(dev, "TQP_INT_ECC_INT_STS", 1154 &hclge_tqp_int_ecc_int[0], status, 1155 &ae_dev->hw_err_reset_req); 1156 1157 status = le32_to_cpu(desc[0].data[4]); 1158 if (status) 1159 hclge_log_error(dev, "MSIX_ECC_INT_STS", 1160 &hclge_msix_sram_ecc_int[0], status, 1161 &ae_dev->hw_err_reset_req); 1162 1163 /* log SSU(Storage Switch Unit) errors */ 1164 desc_data = (__le32 *)&desc[2]; 1165 status = le32_to_cpu(*(desc_data + 2)); 1166 if (status) 1167 hclge_log_error(dev, "SSU_ECC_MULTI_BIT_INT_0", 1168 &hclge_ssu_mem_ecc_err_int[0], status, 1169 &ae_dev->hw_err_reset_req); 1170 1171 status = le32_to_cpu(*(desc_data + 3)) & BIT(0); 1172 if (status) { 1173 dev_err(dev, "SSU_ECC_MULTI_BIT_INT_1 ssu_mem32_ecc_mbit_err found [error status=0x%x]\n", 1174 status); 1175 set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req); 1176 } 1177 1178 status = le32_to_cpu(*(desc_data + 4)) & HCLGE_SSU_COMMON_ERR_INT_MASK; 1179 if (status) 1180 hclge_log_error(dev, "SSU_COMMON_ERR_INT", 1181 &hclge_ssu_com_err_int[0], status, 1182 &ae_dev->hw_err_reset_req); 1183 1184 /* log IGU(Ingress Unit) errors */ 1185 desc_data = (__le32 *)&desc[3]; 1186 status = le32_to_cpu(*desc_data) & HCLGE_IGU_INT_MASK; 1187 if (status) 1188 hclge_log_error(dev, "IGU_INT_STS", 1189 &hclge_igu_int[0], status, 1190 &ae_dev->hw_err_reset_req); 1191 1192 /* log PPP(Programmable Packet Process) errors */ 1193 desc_data = (__le32 *)&desc[4]; 1194 status = le32_to_cpu(*(desc_data + 1)); 1195 if (status) 1196 hclge_log_error(dev, "PPP_MPF_ABNORMAL_INT_ST1", 1197 &hclge_ppp_mpf_abnormal_int_st1[0], status, 1198 &ae_dev->hw_err_reset_req); 1199 1200 status = le32_to_cpu(*(desc_data + 3)) & HCLGE_PPP_MPF_INT_ST3_MASK; 1201 if (status) 1202 hclge_log_error(dev, "PPP_MPF_ABNORMAL_INT_ST3", 1203 &hclge_ppp_mpf_abnormal_int_st3[0], status, 1204 &ae_dev->hw_err_reset_req); 1205 1206 /* log PPU(RCB) errors */ 1207 desc_data = (__le32 *)&desc[5]; 1208 status = le32_to_cpu(*(desc_data + 1)); 1209 if (status) { 1210 dev_err(dev, 1211 "PPU_MPF_ABNORMAL_INT_ST1 rpu_rx_pkt_ecc_mbit_err found\n"); 1212 set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req); 1213 } 1214 1215 status = le32_to_cpu(*(desc_data + 2)); 1216 if (status) 1217 hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST2", 1218 &hclge_ppu_mpf_abnormal_int_st2[0], status, 1219 &ae_dev->hw_err_reset_req); 1220 1221 status = le32_to_cpu(*(desc_data + 3)) & HCLGE_PPU_MPF_INT_ST3_MASK; 1222 if (status) 1223 hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST3", 1224 &hclge_ppu_mpf_abnormal_int_st3[0], status, 1225 &ae_dev->hw_err_reset_req); 1226 1227 /* log TM(Traffic Manager) errors */ 1228 desc_data = (__le32 *)&desc[6]; 1229 status = le32_to_cpu(*desc_data); 1230 if (status) 1231 hclge_log_error(dev, "TM_SCH_RINT", 1232 &hclge_tm_sch_rint[0], status, 1233 &ae_dev->hw_err_reset_req); 1234 1235 /* log QCN(Quantized Congestion Control) errors */ 1236 desc_data = (__le32 *)&desc[7]; 1237 status = le32_to_cpu(*desc_data) & HCLGE_QCN_FIFO_INT_MASK; 1238 if (status) 1239 hclge_log_error(dev, "QCN_FIFO_RINT", 1240 &hclge_qcn_fifo_rint[0], status, 1241 &ae_dev->hw_err_reset_req); 1242 1243 status = le32_to_cpu(*(desc_data + 1)) & HCLGE_QCN_ECC_INT_MASK; 1244 if (status) 1245 hclge_log_error(dev, "QCN_ECC_RINT", 1246 &hclge_qcn_ecc_rint[0], status, 1247 &ae_dev->hw_err_reset_req); 1248 1249 /* log NCSI errors */ 1250 desc_data = (__le32 *)&desc[9]; 1251 status = le32_to_cpu(*desc_data) & HCLGE_NCSI_ECC_INT_MASK; 1252 if (status) 1253 hclge_log_error(dev, "NCSI_ECC_INT_RPT", 1254 &hclge_ncsi_err_int[0], status, 1255 &ae_dev->hw_err_reset_req); 1256 1257 /* clear all main PF RAS errors */ 1258 hclge_cmd_reuse_desc(&desc[0], false); 1259 ret = hclge_cmd_send(&hdev->hw, &desc[0], num); 1260 if (ret) 1261 dev_err(dev, "clear all mpf ras int cmd failed (%d)\n", ret); 1262 1263 return ret; 1264 } 1265 1266 /* hclge_handle_pf_ras_error: handle all PF RAS errors 1267 * @hdev: pointer to struct hclge_dev 1268 * @desc: descriptor for describing the command 1269 * @num: number of extended command structures 1270 * 1271 * This function handles all the PF RAS errors in the 1272 * hw register/s using command. 1273 */ 1274 static int hclge_handle_pf_ras_error(struct hclge_dev *hdev, 1275 struct hclge_desc *desc, 1276 int num) 1277 { 1278 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1279 struct device *dev = &hdev->pdev->dev; 1280 __le32 *desc_data; 1281 u32 status; 1282 int ret; 1283 1284 /* query all PF RAS errors */ 1285 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_PF_RAS_INT, 1286 true); 1287 ret = hclge_cmd_send(&hdev->hw, &desc[0], num); 1288 if (ret) { 1289 dev_err(dev, "query all pf ras int cmd failed (%d)\n", ret); 1290 return ret; 1291 } 1292 1293 /* log SSU(Storage Switch Unit) errors */ 1294 status = le32_to_cpu(desc[0].data[0]); 1295 if (status) 1296 hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT", 1297 &hclge_ssu_port_based_err_int[0], status, 1298 &ae_dev->hw_err_reset_req); 1299 1300 status = le32_to_cpu(desc[0].data[1]); 1301 if (status) 1302 hclge_log_error(dev, "SSU_FIFO_OVERFLOW_INT", 1303 &hclge_ssu_fifo_overflow_int[0], status, 1304 &ae_dev->hw_err_reset_req); 1305 1306 status = le32_to_cpu(desc[0].data[2]); 1307 if (status) 1308 hclge_log_error(dev, "SSU_ETS_TCG_INT", 1309 &hclge_ssu_ets_tcg_int[0], status, 1310 &ae_dev->hw_err_reset_req); 1311 1312 /* log IGU(Ingress Unit) EGU(Egress Unit) TNL errors */ 1313 desc_data = (__le32 *)&desc[1]; 1314 status = le32_to_cpu(*desc_data) & HCLGE_IGU_EGU_TNL_INT_MASK; 1315 if (status) 1316 hclge_log_error(dev, "IGU_EGU_TNL_INT_STS", 1317 &hclge_igu_egu_tnl_int[0], status, 1318 &ae_dev->hw_err_reset_req); 1319 1320 /* log PPU(RCB) errors */ 1321 desc_data = (__le32 *)&desc[3]; 1322 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_RAS_MASK; 1323 if (status) { 1324 hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST0", 1325 &hclge_ppu_pf_abnormal_int[0], status, 1326 &ae_dev->hw_err_reset_req); 1327 hclge_report_hw_error(hdev, HNAE3_PPU_POISON_ERROR); 1328 } 1329 1330 /* clear all PF RAS errors */ 1331 hclge_cmd_reuse_desc(&desc[0], false); 1332 ret = hclge_cmd_send(&hdev->hw, &desc[0], num); 1333 if (ret) 1334 dev_err(dev, "clear all pf ras int cmd failed (%d)\n", ret); 1335 1336 return ret; 1337 } 1338 1339 static int hclge_handle_all_ras_errors(struct hclge_dev *hdev) 1340 { 1341 u32 mpf_bd_num, pf_bd_num, bd_num; 1342 struct hclge_desc *desc; 1343 int ret; 1344 1345 /* query the number of registers in the RAS int status */ 1346 ret = hclge_query_bd_num(hdev, true, &mpf_bd_num, &pf_bd_num); 1347 if (ret) 1348 return ret; 1349 1350 bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1351 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1352 if (!desc) 1353 return -ENOMEM; 1354 1355 /* handle all main PF RAS errors */ 1356 ret = hclge_handle_mpf_ras_error(hdev, desc, mpf_bd_num); 1357 if (ret) { 1358 kfree(desc); 1359 return ret; 1360 } 1361 memset(desc, 0, bd_num * sizeof(struct hclge_desc)); 1362 1363 /* handle all PF RAS errors */ 1364 ret = hclge_handle_pf_ras_error(hdev, desc, pf_bd_num); 1365 kfree(desc); 1366 1367 return ret; 1368 } 1369 1370 static int hclge_log_rocee_axi_error(struct hclge_dev *hdev) 1371 { 1372 struct device *dev = &hdev->pdev->dev; 1373 struct hclge_desc desc[3]; 1374 int ret; 1375 1376 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD, 1377 true); 1378 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD, 1379 true); 1380 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD, 1381 true); 1382 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1383 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1384 1385 ret = hclge_cmd_send(&hdev->hw, &desc[0], 3); 1386 if (ret) { 1387 dev_err(dev, "failed(%d) to query ROCEE AXI error sts\n", ret); 1388 return ret; 1389 } 1390 1391 dev_err(dev, "AXI1: %08X %08X %08X %08X %08X %08X\n", 1392 le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]), 1393 le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]), 1394 le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5])); 1395 dev_err(dev, "AXI2: %08X %08X %08X %08X %08X %08X\n", 1396 le32_to_cpu(desc[1].data[0]), le32_to_cpu(desc[1].data[1]), 1397 le32_to_cpu(desc[1].data[2]), le32_to_cpu(desc[1].data[3]), 1398 le32_to_cpu(desc[1].data[4]), le32_to_cpu(desc[1].data[5])); 1399 dev_err(dev, "AXI3: %08X %08X %08X %08X\n", 1400 le32_to_cpu(desc[2].data[0]), le32_to_cpu(desc[2].data[1]), 1401 le32_to_cpu(desc[2].data[2]), le32_to_cpu(desc[2].data[3])); 1402 1403 return 0; 1404 } 1405 1406 static int hclge_log_rocee_ecc_error(struct hclge_dev *hdev) 1407 { 1408 struct device *dev = &hdev->pdev->dev; 1409 struct hclge_desc desc[2]; 1410 int ret; 1411 1412 ret = hclge_cmd_query_error(hdev, &desc[0], 1413 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD, 1414 HCLGE_CMD_FLAG_NEXT); 1415 if (ret) { 1416 dev_err(dev, "failed(%d) to query ROCEE ECC error sts\n", ret); 1417 return ret; 1418 } 1419 1420 dev_err(dev, "ECC1: %08X %08X %08X %08X %08X %08X\n", 1421 le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]), 1422 le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]), 1423 le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5])); 1424 dev_err(dev, "ECC2: %08X %08X %08X\n", le32_to_cpu(desc[1].data[0]), 1425 le32_to_cpu(desc[1].data[1]), le32_to_cpu(desc[1].data[2])); 1426 1427 return 0; 1428 } 1429 1430 static int hclge_log_rocee_ovf_error(struct hclge_dev *hdev) 1431 { 1432 struct device *dev = &hdev->pdev->dev; 1433 struct hclge_desc desc[2]; 1434 int ret; 1435 1436 /* read overflow error status */ 1437 ret = hclge_cmd_query_error(hdev, &desc[0], HCLGE_ROCEE_PF_RAS_INT_CMD, 1438 0); 1439 if (ret) { 1440 dev_err(dev, "failed(%d) to query ROCEE OVF error sts\n", ret); 1441 return ret; 1442 } 1443 1444 /* log overflow error */ 1445 if (le32_to_cpu(desc[0].data[0]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) { 1446 const struct hclge_hw_error *err; 1447 u32 err_sts; 1448 1449 err = &hclge_rocee_qmm_ovf_err_int[0]; 1450 err_sts = HCLGE_ROCEE_OVF_ERR_TYPE_MASK & 1451 le32_to_cpu(desc[0].data[0]); 1452 while (err->msg) { 1453 if (err->int_msk == err_sts) { 1454 dev_err(dev, "%s [error status=0x%x] found\n", 1455 err->msg, 1456 le32_to_cpu(desc[0].data[0])); 1457 break; 1458 } 1459 err++; 1460 } 1461 } 1462 1463 if (le32_to_cpu(desc[0].data[1]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) { 1464 dev_err(dev, "ROCEE TSP OVF [error status=0x%x] found\n", 1465 le32_to_cpu(desc[0].data[1])); 1466 } 1467 1468 if (le32_to_cpu(desc[0].data[2]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) { 1469 dev_err(dev, "ROCEE SCC OVF [error status=0x%x] found\n", 1470 le32_to_cpu(desc[0].data[2])); 1471 } 1472 1473 return 0; 1474 } 1475 1476 static enum hnae3_reset_type 1477 hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev) 1478 { 1479 enum hnae3_reset_type reset_type = HNAE3_NONE_RESET; 1480 struct device *dev = &hdev->pdev->dev; 1481 struct hclge_desc desc[2]; 1482 unsigned int status; 1483 int ret; 1484 1485 /* read RAS error interrupt status */ 1486 ret = hclge_cmd_query_error(hdev, &desc[0], 1487 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT, 0); 1488 if (ret) { 1489 dev_err(dev, "failed(%d) to query ROCEE RAS INT SRC\n", ret); 1490 /* reset everything for now */ 1491 return HNAE3_GLOBAL_RESET; 1492 } 1493 1494 status = le32_to_cpu(desc[0].data[0]); 1495 if (status & HCLGE_ROCEE_AXI_ERR_INT_MASK) { 1496 if (status & HCLGE_ROCEE_RERR_INT_MASK) 1497 dev_err(dev, "ROCEE RAS AXI rresp error\n"); 1498 1499 if (status & HCLGE_ROCEE_BERR_INT_MASK) 1500 dev_err(dev, "ROCEE RAS AXI bresp error\n"); 1501 1502 reset_type = HNAE3_FUNC_RESET; 1503 1504 hclge_report_hw_error(hdev, HNAE3_ROCEE_AXI_RESP_ERROR); 1505 1506 ret = hclge_log_rocee_axi_error(hdev); 1507 if (ret) 1508 return HNAE3_GLOBAL_RESET; 1509 } 1510 1511 if (status & HCLGE_ROCEE_ECC_INT_MASK) { 1512 dev_err(dev, "ROCEE RAS 2bit ECC error\n"); 1513 reset_type = HNAE3_GLOBAL_RESET; 1514 1515 ret = hclge_log_rocee_ecc_error(hdev); 1516 if (ret) 1517 return HNAE3_GLOBAL_RESET; 1518 } 1519 1520 if (status & HCLGE_ROCEE_OVF_INT_MASK) { 1521 ret = hclge_log_rocee_ovf_error(hdev); 1522 if (ret) { 1523 dev_err(dev, "failed(%d) to process ovf error\n", ret); 1524 /* reset everything for now */ 1525 return HNAE3_GLOBAL_RESET; 1526 } 1527 } 1528 1529 /* clear error status */ 1530 hclge_cmd_reuse_desc(&desc[0], false); 1531 ret = hclge_cmd_send(&hdev->hw, &desc[0], 1); 1532 if (ret) { 1533 dev_err(dev, "failed(%d) to clear ROCEE RAS error\n", ret); 1534 /* reset everything for now */ 1535 return HNAE3_GLOBAL_RESET; 1536 } 1537 1538 return reset_type; 1539 } 1540 1541 int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en) 1542 { 1543 struct device *dev = &hdev->pdev->dev; 1544 struct hclge_desc desc; 1545 int ret; 1546 1547 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 || 1548 !hnae3_dev_roce_supported(hdev)) 1549 return 0; 1550 1551 hclge_cmd_setup_basic_desc(&desc, HCLGE_CONFIG_ROCEE_RAS_INT_EN, false); 1552 if (en) { 1553 /* enable ROCEE hw error interrupts */ 1554 desc.data[0] = cpu_to_le32(HCLGE_ROCEE_RAS_NFE_INT_EN); 1555 desc.data[1] = cpu_to_le32(HCLGE_ROCEE_RAS_CE_INT_EN); 1556 1557 hclge_log_and_clear_rocee_ras_error(hdev); 1558 } 1559 desc.data[2] = cpu_to_le32(HCLGE_ROCEE_RAS_NFE_INT_EN_MASK); 1560 desc.data[3] = cpu_to_le32(HCLGE_ROCEE_RAS_CE_INT_EN_MASK); 1561 1562 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1563 if (ret) 1564 dev_err(dev, "failed(%d) to config ROCEE RAS interrupt\n", ret); 1565 1566 return ret; 1567 } 1568 1569 static void hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev) 1570 { 1571 struct hclge_dev *hdev = ae_dev->priv; 1572 enum hnae3_reset_type reset_type; 1573 1574 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 1575 return; 1576 1577 reset_type = hclge_log_and_clear_rocee_ras_error(hdev); 1578 if (reset_type != HNAE3_NONE_RESET) 1579 set_bit(reset_type, &ae_dev->hw_err_reset_req); 1580 } 1581 1582 static const struct hclge_hw_blk hw_blk[] = { 1583 { 1584 .msk = BIT(0), .name = "IGU_EGU", 1585 .config_err_int = hclge_config_igu_egu_hw_err_int, 1586 }, 1587 { 1588 .msk = BIT(1), .name = "PPP", 1589 .config_err_int = hclge_config_ppp_hw_err_int, 1590 }, 1591 { 1592 .msk = BIT(2), .name = "SSU", 1593 .config_err_int = hclge_config_ssu_hw_err_int, 1594 }, 1595 { 1596 .msk = BIT(3), .name = "PPU", 1597 .config_err_int = hclge_config_ppu_hw_err_int, 1598 }, 1599 { 1600 .msk = BIT(4), .name = "TM", 1601 .config_err_int = hclge_config_tm_hw_err_int, 1602 }, 1603 { 1604 .msk = BIT(5), .name = "COMMON", 1605 .config_err_int = hclge_config_common_hw_err_int, 1606 }, 1607 { 1608 .msk = BIT(8), .name = "MAC", 1609 .config_err_int = hclge_config_mac_err_int, 1610 }, 1611 { /* sentinel */ } 1612 }; 1613 1614 int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state) 1615 { 1616 const struct hclge_hw_blk *module = hw_blk; 1617 int ret = 0; 1618 1619 while (module->name) { 1620 if (module->config_err_int) { 1621 ret = module->config_err_int(hdev, state); 1622 if (ret) 1623 return ret; 1624 } 1625 module++; 1626 } 1627 1628 return ret; 1629 } 1630 1631 pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev) 1632 { 1633 struct hclge_dev *hdev = ae_dev->priv; 1634 struct device *dev = &hdev->pdev->dev; 1635 u32 status; 1636 1637 if (!test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state)) { 1638 dev_err(dev, 1639 "Can't recover - RAS error reported during dev init\n"); 1640 return PCI_ERS_RESULT_NONE; 1641 } 1642 1643 status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG); 1644 if (status & HCLGE_RAS_REG_NFE_MASK || 1645 status & HCLGE_RAS_REG_ROCEE_ERR_MASK) 1646 ae_dev->hw_err_reset_req = 0; 1647 else 1648 goto out; 1649 1650 /* Handling Non-fatal HNS RAS errors */ 1651 if (status & HCLGE_RAS_REG_NFE_MASK) { 1652 dev_err(dev, 1653 "HNS Non-Fatal RAS error(status=0x%x) identified\n", 1654 status); 1655 hclge_handle_all_ras_errors(hdev); 1656 } 1657 1658 /* Handling Non-fatal Rocee RAS errors */ 1659 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 && 1660 status & HCLGE_RAS_REG_ROCEE_ERR_MASK) { 1661 dev_err(dev, "ROCEE Non-Fatal RAS error identified\n"); 1662 hclge_handle_rocee_ras_error(ae_dev); 1663 } 1664 1665 if (ae_dev->hw_err_reset_req) 1666 return PCI_ERS_RESULT_NEED_RESET; 1667 1668 out: 1669 return PCI_ERS_RESULT_RECOVERED; 1670 } 1671 1672 static int hclge_clear_hw_msix_error(struct hclge_dev *hdev, 1673 struct hclge_desc *desc, bool is_mpf, 1674 u32 bd_num) 1675 { 1676 if (is_mpf) 1677 desc[0].opcode = 1678 cpu_to_le16(HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT); 1679 else 1680 desc[0].opcode = cpu_to_le16(HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT); 1681 1682 desc[0].flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN); 1683 1684 return hclge_cmd_send(&hdev->hw, &desc[0], bd_num); 1685 } 1686 1687 /* hclge_query_8bd_info: query information about over_8bd_nfe_err 1688 * @hdev: pointer to struct hclge_dev 1689 * @vf_id: Index of the virtual function with error 1690 * @q_id: Physical index of the queue with error 1691 * 1692 * This function get specific index of queue and function which causes 1693 * over_8bd_nfe_err by using command. If vf_id is 0, it means error is 1694 * caused by PF instead of VF. 1695 */ 1696 static int hclge_query_over_8bd_err_info(struct hclge_dev *hdev, u16 *vf_id, 1697 u16 *q_id) 1698 { 1699 struct hclge_query_ppu_pf_other_int_dfx_cmd *req; 1700 struct hclge_desc desc; 1701 int ret; 1702 1703 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PPU_PF_OTHER_INT_DFX, true); 1704 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1705 if (ret) 1706 return ret; 1707 1708 req = (struct hclge_query_ppu_pf_other_int_dfx_cmd *)desc.data; 1709 *vf_id = le16_to_cpu(req->over_8bd_no_fe_vf_id); 1710 *q_id = le16_to_cpu(req->over_8bd_no_fe_qid); 1711 1712 return 0; 1713 } 1714 1715 /* hclge_handle_over_8bd_err: handle MSI-X error named over_8bd_nfe_err 1716 * @hdev: pointer to struct hclge_dev 1717 * @reset_requests: reset level that we need to trigger later 1718 * 1719 * over_8bd_nfe_err is a special MSI-X because it may caused by a VF, in 1720 * that case, we need to trigger VF reset. Otherwise, a PF reset is needed. 1721 */ 1722 static void hclge_handle_over_8bd_err(struct hclge_dev *hdev, 1723 unsigned long *reset_requests) 1724 { 1725 struct device *dev = &hdev->pdev->dev; 1726 u16 vf_id; 1727 u16 q_id; 1728 int ret; 1729 1730 ret = hclge_query_over_8bd_err_info(hdev, &vf_id, &q_id); 1731 if (ret) { 1732 dev_err(dev, "fail(%d) to query over_8bd_no_fe info\n", 1733 ret); 1734 return; 1735 } 1736 1737 dev_err(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vf_id(%u), queue_id(%u)\n", 1738 vf_id, q_id); 1739 1740 if (vf_id) { 1741 if (vf_id >= hdev->num_alloc_vport) { 1742 dev_err(dev, "invalid vf id(%u)\n", vf_id); 1743 return; 1744 } 1745 1746 /* If we need to trigger other reset whose level is higher 1747 * than HNAE3_VF_FUNC_RESET, no need to trigger a VF reset 1748 * here. 1749 */ 1750 if (*reset_requests != 0) 1751 return; 1752 1753 ret = hclge_inform_reset_assert_to_vf(&hdev->vport[vf_id]); 1754 if (ret) 1755 dev_err(dev, "inform reset to vf(%u) failed %d!\n", 1756 hdev->vport->vport_id, ret); 1757 } else { 1758 set_bit(HNAE3_FUNC_RESET, reset_requests); 1759 } 1760 } 1761 1762 /* hclge_handle_mpf_msix_error: handle all main PF MSI-X errors 1763 * @hdev: pointer to struct hclge_dev 1764 * @desc: descriptor for describing the command 1765 * @mpf_bd_num: number of extended command structures 1766 * @reset_requests: record of the reset level that we need 1767 * 1768 * This function handles all the main PF MSI-X errors in the hw register/s 1769 * using command. 1770 */ 1771 static int hclge_handle_mpf_msix_error(struct hclge_dev *hdev, 1772 struct hclge_desc *desc, 1773 int mpf_bd_num, 1774 unsigned long *reset_requests) 1775 { 1776 struct device *dev = &hdev->pdev->dev; 1777 __le32 *desc_data; 1778 u32 status; 1779 int ret; 1780 /* query all main PF MSIx errors */ 1781 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT, 1782 true); 1783 ret = hclge_cmd_send(&hdev->hw, &desc[0], mpf_bd_num); 1784 if (ret) { 1785 dev_err(dev, "query all mpf msix int cmd failed (%d)\n", ret); 1786 return ret; 1787 } 1788 1789 /* log MAC errors */ 1790 desc_data = (__le32 *)&desc[1]; 1791 status = le32_to_cpu(*desc_data); 1792 if (status) 1793 hclge_log_error(dev, "MAC_AFIFO_TNL_INT_R", 1794 &hclge_mac_afifo_tnl_int[0], status, 1795 reset_requests); 1796 1797 /* log PPU(RCB) MPF errors */ 1798 desc_data = (__le32 *)&desc[5]; 1799 status = le32_to_cpu(*(desc_data + 2)) & 1800 HCLGE_PPU_MPF_INT_ST2_MSIX_MASK; 1801 if (status) 1802 dev_err(dev, "PPU_MPF_ABNORMAL_INT_ST2 rx_q_search_miss found [dfx status=0x%x\n]", 1803 status); 1804 1805 /* clear all main PF MSIx errors */ 1806 ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num); 1807 if (ret) 1808 dev_err(dev, "clear all mpf msix int cmd failed (%d)\n", ret); 1809 1810 return ret; 1811 } 1812 1813 /* hclge_handle_pf_msix_error: handle all PF MSI-X errors 1814 * @hdev: pointer to struct hclge_dev 1815 * @desc: descriptor for describing the command 1816 * @mpf_bd_num: number of extended command structures 1817 * @reset_requests: record of the reset level that we need 1818 * 1819 * This function handles all the PF MSI-X errors in the hw register/s using 1820 * command. 1821 */ 1822 static int hclge_handle_pf_msix_error(struct hclge_dev *hdev, 1823 struct hclge_desc *desc, 1824 int pf_bd_num, 1825 unsigned long *reset_requests) 1826 { 1827 struct device *dev = &hdev->pdev->dev; 1828 __le32 *desc_data; 1829 u32 status; 1830 int ret; 1831 1832 /* query all PF MSIx errors */ 1833 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT, 1834 true); 1835 ret = hclge_cmd_send(&hdev->hw, &desc[0], pf_bd_num); 1836 if (ret) { 1837 dev_err(dev, "query all pf msix int cmd failed (%d)\n", ret); 1838 return ret; 1839 } 1840 1841 /* log SSU PF errors */ 1842 status = le32_to_cpu(desc[0].data[0]) & HCLGE_SSU_PORT_INT_MSIX_MASK; 1843 if (status) 1844 hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT", 1845 &hclge_ssu_port_based_pf_int[0], 1846 status, reset_requests); 1847 1848 /* read and log PPP PF errors */ 1849 desc_data = (__le32 *)&desc[2]; 1850 status = le32_to_cpu(*desc_data); 1851 if (status) 1852 hclge_log_error(dev, "PPP_PF_ABNORMAL_INT_ST0", 1853 &hclge_ppp_pf_abnormal_int[0], 1854 status, reset_requests); 1855 1856 /* log PPU(RCB) PF errors */ 1857 desc_data = (__le32 *)&desc[3]; 1858 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_MSIX_MASK; 1859 if (status) 1860 hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST", 1861 &hclge_ppu_pf_abnormal_int[0], 1862 status, reset_requests); 1863 1864 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_OVER_8BD_ERR_MASK; 1865 if (status) 1866 hclge_handle_over_8bd_err(hdev, reset_requests); 1867 1868 /* clear all PF MSIx errors */ 1869 ret = hclge_clear_hw_msix_error(hdev, desc, false, pf_bd_num); 1870 if (ret) 1871 dev_err(dev, "clear all pf msix int cmd failed (%d)\n", ret); 1872 1873 return ret; 1874 } 1875 1876 static int hclge_handle_all_hw_msix_error(struct hclge_dev *hdev, 1877 unsigned long *reset_requests) 1878 { 1879 struct hclge_mac_tnl_stats mac_tnl_stats; 1880 struct device *dev = &hdev->pdev->dev; 1881 u32 mpf_bd_num, pf_bd_num, bd_num; 1882 struct hclge_desc *desc; 1883 u32 status; 1884 int ret; 1885 1886 /* query the number of bds for the MSIx int status */ 1887 ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num); 1888 if (ret) 1889 goto out; 1890 1891 bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1892 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1893 if (!desc) 1894 return -ENOMEM; 1895 1896 ret = hclge_handle_mpf_msix_error(hdev, desc, mpf_bd_num, 1897 reset_requests); 1898 if (ret) 1899 goto msi_error; 1900 1901 memset(desc, 0, bd_num * sizeof(struct hclge_desc)); 1902 ret = hclge_handle_pf_msix_error(hdev, desc, pf_bd_num, reset_requests); 1903 if (ret) 1904 goto msi_error; 1905 1906 /* query and clear mac tnl interruptions */ 1907 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_MAC_TNL_INT, 1908 true); 1909 ret = hclge_cmd_send(&hdev->hw, &desc[0], 1); 1910 if (ret) { 1911 dev_err(dev, "query mac tnl int cmd failed (%d)\n", ret); 1912 goto msi_error; 1913 } 1914 1915 status = le32_to_cpu(desc->data[0]); 1916 if (status) { 1917 /* When mac tnl interrupt occurs, we record current time and 1918 * register status here in a fifo, then clear the status. So 1919 * that if link status changes suddenly at some time, we can 1920 * query them by debugfs. 1921 */ 1922 mac_tnl_stats.time = local_clock(); 1923 mac_tnl_stats.status = status; 1924 kfifo_put(&hdev->mac_tnl_log, mac_tnl_stats); 1925 ret = hclge_clear_mac_tnl_int(hdev); 1926 if (ret) 1927 dev_err(dev, "clear mac tnl int failed (%d)\n", ret); 1928 } 1929 1930 msi_error: 1931 kfree(desc); 1932 out: 1933 return ret; 1934 } 1935 1936 int hclge_handle_hw_msix_error(struct hclge_dev *hdev, 1937 unsigned long *reset_requests) 1938 { 1939 struct device *dev = &hdev->pdev->dev; 1940 1941 if (!test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state)) { 1942 dev_err(dev, 1943 "Can't handle - MSIx error reported during dev init\n"); 1944 return 0; 1945 } 1946 1947 return hclge_handle_all_hw_msix_error(hdev, reset_requests); 1948 } 1949 1950 void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev) 1951 { 1952 #define HCLGE_DESC_NO_DATA_LEN 8 1953 1954 struct hclge_dev *hdev = ae_dev->priv; 1955 struct device *dev = &hdev->pdev->dev; 1956 u32 mpf_bd_num, pf_bd_num, bd_num; 1957 struct hclge_desc *desc; 1958 u32 status; 1959 int ret; 1960 1961 ae_dev->hw_err_reset_req = 0; 1962 status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG); 1963 1964 /* query the number of bds for the MSIx int status */ 1965 ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num); 1966 if (ret) 1967 return; 1968 1969 bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1970 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1971 if (!desc) 1972 return; 1973 1974 /* Clear HNS hw errors reported through msix */ 1975 memset(&desc[0].data[0], 0xFF, mpf_bd_num * sizeof(struct hclge_desc) - 1976 HCLGE_DESC_NO_DATA_LEN); 1977 ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num); 1978 if (ret) { 1979 dev_err(dev, "fail(%d) to clear mpf msix int during init\n", 1980 ret); 1981 goto msi_error; 1982 } 1983 1984 memset(&desc[0].data[0], 0xFF, pf_bd_num * sizeof(struct hclge_desc) - 1985 HCLGE_DESC_NO_DATA_LEN); 1986 ret = hclge_clear_hw_msix_error(hdev, desc, false, pf_bd_num); 1987 if (ret) { 1988 dev_err(dev, "fail(%d) to clear pf msix int during init\n", 1989 ret); 1990 goto msi_error; 1991 } 1992 1993 /* Handle Non-fatal HNS RAS errors */ 1994 if (status & HCLGE_RAS_REG_NFE_MASK) { 1995 dev_err(dev, "HNS hw error(RAS) identified during init\n"); 1996 hclge_handle_all_ras_errors(hdev); 1997 } 1998 1999 msi_error: 2000 kfree(desc); 2001 } 2002