1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #ifndef __HCLGE_DEBUGFS_H 5 #define __HCLGE_DEBUGFS_H 6 7 #include <linux/etherdevice.h> 8 #include "hclge_cmd.h" 9 10 #define HCLGE_DBG_MNG_TBL_MAX 64 11 12 #define HCLGE_DBG_MNG_VLAN_MASK_B BIT(0) 13 #define HCLGE_DBG_MNG_MAC_MASK_B BIT(1) 14 #define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2) 15 #define HCLGE_DBG_MNG_E_TYPE_B BIT(11) 16 #define HCLGE_DBG_MNG_DROP_B BIT(13) 17 #define HCLGE_DBG_MNG_VLAN_TAG 0x0FFF 18 #define HCLGE_DBG_MNG_PF_ID 0x0007 19 #define HCLGE_DBG_MNG_VF_ID 0x00FF 20 21 /* Get DFX BD number offset */ 22 #define HCLGE_DBG_DFX_BIOS_OFFSET 1 23 #define HCLGE_DBG_DFX_SSU_0_OFFSET 2 24 #define HCLGE_DBG_DFX_SSU_1_OFFSET 3 25 #define HCLGE_DBG_DFX_IGU_OFFSET 4 26 #define HCLGE_DBG_DFX_RPU_0_OFFSET 5 27 28 #define HCLGE_DBG_DFX_RPU_1_OFFSET 6 29 #define HCLGE_DBG_DFX_NCSI_OFFSET 7 30 #define HCLGE_DBG_DFX_RTC_OFFSET 8 31 #define HCLGE_DBG_DFX_PPP_OFFSET 9 32 #define HCLGE_DBG_DFX_RCB_OFFSET 10 33 #define HCLGE_DBG_DFX_TQP_OFFSET 11 34 35 #define HCLGE_DBG_DFX_SSU_2_OFFSET 12 36 37 struct hclge_qos_pri_map_cmd { 38 u8 pri0_tc : 4, 39 pri1_tc : 4; 40 u8 pri2_tc : 4, 41 pri3_tc : 4; 42 u8 pri4_tc : 4, 43 pri5_tc : 4; 44 u8 pri6_tc : 4, 45 pri7_tc : 4; 46 u8 vlan_pri : 4, 47 rev : 4; 48 }; 49 50 struct hclge_dbg_bitmap_cmd { 51 union { 52 u8 bitmap; 53 struct { 54 u8 bit0 : 1, 55 bit1 : 1, 56 bit2 : 1, 57 bit3 : 1, 58 bit4 : 1, 59 bit5 : 1, 60 bit6 : 1, 61 bit7 : 1; 62 }; 63 }; 64 }; 65 66 struct hclge_dbg_reg_common_msg { 67 int msg_num; 68 int offset; 69 enum hclge_opcode_type cmd; 70 }; 71 72 struct hclge_dbg_tcam_msg { 73 u8 stage; 74 u32 loc; 75 }; 76 77 #define HCLGE_DBG_MAX_DFX_MSG_LEN 60 78 struct hclge_dbg_dfx_message { 79 int flag; 80 char message[HCLGE_DBG_MAX_DFX_MSG_LEN]; 81 }; 82 83 #define HCLGE_DBG_MAC_REG_TYPE_LEN 32 84 struct hclge_dbg_reg_type_info { 85 enum hnae3_dbg_cmd cmd; 86 const struct hclge_dbg_dfx_message *dfx_msg; 87 struct hclge_dbg_reg_common_msg reg_msg; 88 }; 89 90 struct hclge_dbg_func { 91 enum hnae3_dbg_cmd cmd; 92 int (*dbg_dump)(struct hclge_dev *hdev, char *buf, int len); 93 int (*dbg_dump_reg)(struct hclge_dev *hdev, enum hnae3_dbg_cmd cmd, 94 char *buf, int len); 95 }; 96 97 struct hclge_dbg_status_dfx_info { 98 u32 offset; 99 char message[HCLGE_DBG_MAX_DFX_MSG_LEN]; 100 }; 101 102 static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = { 103 {false, "Reserved"}, 104 {true, "BP_CPU_STATE"}, 105 {true, "DFX_MSIX_INFO_NIC_0"}, 106 {true, "DFX_MSIX_INFO_NIC_1"}, 107 {true, "DFX_MSIX_INFO_NIC_2"}, 108 {true, "DFX_MSIX_INFO_NIC_3"}, 109 110 {true, "DFX_MSIX_INFO_ROC_0"}, 111 {true, "DFX_MSIX_INFO_ROC_1"}, 112 {true, "DFX_MSIX_INFO_ROC_2"}, 113 {true, "DFX_MSIX_INFO_ROC_3"}, 114 {false, "Reserved"}, 115 {false, "Reserved"}, 116 }; 117 118 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = { 119 {false, "Reserved"}, 120 {true, "SSU_ETS_PORT_STATUS"}, 121 {true, "SSU_ETS_TCG_STATUS"}, 122 {false, "Reserved"}, 123 {false, "Reserved"}, 124 {true, "SSU_BP_STATUS_0"}, 125 126 {true, "SSU_BP_STATUS_1"}, 127 {true, "SSU_BP_STATUS_2"}, 128 {true, "SSU_BP_STATUS_3"}, 129 {true, "SSU_BP_STATUS_4"}, 130 {true, "SSU_BP_STATUS_5"}, 131 {true, "SSU_MAC_TX_PFC_IND"}, 132 133 {true, "MAC_SSU_RX_PFC_IND"}, 134 {true, "BTMP_AGEING_ST_B0"}, 135 {true, "BTMP_AGEING_ST_B1"}, 136 {true, "BTMP_AGEING_ST_B2"}, 137 {false, "Reserved"}, 138 {false, "Reserved"}, 139 140 {true, "FULL_DROP_NUM"}, 141 {true, "PART_DROP_NUM"}, 142 {true, "PPP_KEY_DROP_NUM"}, 143 {true, "PPP_RLT_DROP_NUM"}, 144 {true, "LO_PRI_UNICAST_RLT_DROP_NUM"}, 145 {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"}, 146 147 {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"}, 148 {true, "NCSI_PACKET_CURR_BUFFER_CNT"}, 149 {true, "BTMP_AGEING_RLS_CNT_BANK0"}, 150 {true, "BTMP_AGEING_RLS_CNT_BANK1"}, 151 {true, "BTMP_AGEING_RLS_CNT_BANK2"}, 152 {true, "SSU_MB_RD_RLT_DROP_CNT"}, 153 154 {true, "SSU_PPP_MAC_KEY_NUM_L"}, 155 {true, "SSU_PPP_MAC_KEY_NUM_H"}, 156 {true, "SSU_PPP_HOST_KEY_NUM_L"}, 157 {true, "SSU_PPP_HOST_KEY_NUM_H"}, 158 {true, "PPP_SSU_MAC_RLT_NUM_L"}, 159 {true, "PPP_SSU_MAC_RLT_NUM_H"}, 160 161 {true, "PPP_SSU_HOST_RLT_NUM_L"}, 162 {true, "PPP_SSU_HOST_RLT_NUM_H"}, 163 {true, "NCSI_RX_PACKET_IN_CNT_L"}, 164 {true, "NCSI_RX_PACKET_IN_CNT_H"}, 165 {true, "NCSI_TX_PACKET_OUT_CNT_L"}, 166 {true, "NCSI_TX_PACKET_OUT_CNT_H"}, 167 168 {true, "SSU_KEY_DROP_NUM"}, 169 {true, "MB_UNCOPY_NUM"}, 170 {true, "RX_OQ_DROP_PKT_CNT"}, 171 {true, "TX_OQ_DROP_PKT_CNT"}, 172 {true, "BANK_UNBALANCE_DROP_CNT"}, 173 {true, "BANK_UNBALANCE_RX_DROP_CNT"}, 174 175 {true, "NIC_L2_ERR_DROP_PKT_CNT"}, 176 {true, "ROC_L2_ERR_DROP_PKT_CNT"}, 177 {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"}, 178 {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"}, 179 {true, "RX_OQ_GLB_DROP_PKT_CNT"}, 180 {false, "Reserved"}, 181 182 {true, "LO_PRI_UNICAST_CUR_CNT"}, 183 {true, "HI_PRI_MULTICAST_CUR_CNT"}, 184 {true, "LO_PRI_MULTICAST_CUR_CNT"}, 185 {false, "Reserved"}, 186 {false, "Reserved"}, 187 {false, "Reserved"}, 188 }; 189 190 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = { 191 {true, "prt_id"}, 192 {true, "PACKET_TC_CURR_BUFFER_CNT_0"}, 193 {true, "PACKET_TC_CURR_BUFFER_CNT_1"}, 194 {true, "PACKET_TC_CURR_BUFFER_CNT_2"}, 195 {true, "PACKET_TC_CURR_BUFFER_CNT_3"}, 196 {true, "PACKET_TC_CURR_BUFFER_CNT_4"}, 197 198 {true, "PACKET_TC_CURR_BUFFER_CNT_5"}, 199 {true, "PACKET_TC_CURR_BUFFER_CNT_6"}, 200 {true, "PACKET_TC_CURR_BUFFER_CNT_7"}, 201 {true, "PACKET_CURR_BUFFER_CNT"}, 202 {false, "Reserved"}, 203 {false, "Reserved"}, 204 205 {true, "RX_PACKET_IN_CNT_L"}, 206 {true, "RX_PACKET_IN_CNT_H"}, 207 {true, "RX_PACKET_OUT_CNT_L"}, 208 {true, "RX_PACKET_OUT_CNT_H"}, 209 {true, "TX_PACKET_IN_CNT_L"}, 210 {true, "TX_PACKET_IN_CNT_H"}, 211 212 {true, "TX_PACKET_OUT_CNT_L"}, 213 {true, "TX_PACKET_OUT_CNT_H"}, 214 {true, "ROC_RX_PACKET_IN_CNT_L"}, 215 {true, "ROC_RX_PACKET_IN_CNT_H"}, 216 {true, "ROC_TX_PACKET_OUT_CNT_L"}, 217 {true, "ROC_TX_PACKET_OUT_CNT_H"}, 218 219 {true, "RX_PACKET_TC_IN_CNT_0_L"}, 220 {true, "RX_PACKET_TC_IN_CNT_0_H"}, 221 {true, "RX_PACKET_TC_IN_CNT_1_L"}, 222 {true, "RX_PACKET_TC_IN_CNT_1_H"}, 223 {true, "RX_PACKET_TC_IN_CNT_2_L"}, 224 {true, "RX_PACKET_TC_IN_CNT_2_H"}, 225 226 {true, "RX_PACKET_TC_IN_CNT_3_L"}, 227 {true, "RX_PACKET_TC_IN_CNT_3_H"}, 228 {true, "RX_PACKET_TC_IN_CNT_4_L"}, 229 {true, "RX_PACKET_TC_IN_CNT_4_H"}, 230 {true, "RX_PACKET_TC_IN_CNT_5_L"}, 231 {true, "RX_PACKET_TC_IN_CNT_5_H"}, 232 233 {true, "RX_PACKET_TC_IN_CNT_6_L"}, 234 {true, "RX_PACKET_TC_IN_CNT_6_H"}, 235 {true, "RX_PACKET_TC_IN_CNT_7_L"}, 236 {true, "RX_PACKET_TC_IN_CNT_7_H"}, 237 {true, "RX_PACKET_TC_OUT_CNT_0_L"}, 238 {true, "RX_PACKET_TC_OUT_CNT_0_H"}, 239 240 {true, "RX_PACKET_TC_OUT_CNT_1_L"}, 241 {true, "RX_PACKET_TC_OUT_CNT_1_H"}, 242 {true, "RX_PACKET_TC_OUT_CNT_2_L"}, 243 {true, "RX_PACKET_TC_OUT_CNT_2_H"}, 244 {true, "RX_PACKET_TC_OUT_CNT_3_L"}, 245 {true, "RX_PACKET_TC_OUT_CNT_3_H"}, 246 247 {true, "RX_PACKET_TC_OUT_CNT_4_L"}, 248 {true, "RX_PACKET_TC_OUT_CNT_4_H"}, 249 {true, "RX_PACKET_TC_OUT_CNT_5_L"}, 250 {true, "RX_PACKET_TC_OUT_CNT_5_H"}, 251 {true, "RX_PACKET_TC_OUT_CNT_6_L"}, 252 {true, "RX_PACKET_TC_OUT_CNT_6_H"}, 253 254 {true, "RX_PACKET_TC_OUT_CNT_7_L"}, 255 {true, "RX_PACKET_TC_OUT_CNT_7_H"}, 256 {true, "TX_PACKET_TC_IN_CNT_0_L"}, 257 {true, "TX_PACKET_TC_IN_CNT_0_H"}, 258 {true, "TX_PACKET_TC_IN_CNT_1_L"}, 259 {true, "TX_PACKET_TC_IN_CNT_1_H"}, 260 261 {true, "TX_PACKET_TC_IN_CNT_2_L"}, 262 {true, "TX_PACKET_TC_IN_CNT_2_H"}, 263 {true, "TX_PACKET_TC_IN_CNT_3_L"}, 264 {true, "TX_PACKET_TC_IN_CNT_3_H"}, 265 {true, "TX_PACKET_TC_IN_CNT_4_L"}, 266 {true, "TX_PACKET_TC_IN_CNT_4_H"}, 267 268 {true, "TX_PACKET_TC_IN_CNT_5_L"}, 269 {true, "TX_PACKET_TC_IN_CNT_5_H"}, 270 {true, "TX_PACKET_TC_IN_CNT_6_L"}, 271 {true, "TX_PACKET_TC_IN_CNT_6_H"}, 272 {true, "TX_PACKET_TC_IN_CNT_7_L"}, 273 {true, "TX_PACKET_TC_IN_CNT_7_H"}, 274 275 {true, "TX_PACKET_TC_OUT_CNT_0_L"}, 276 {true, "TX_PACKET_TC_OUT_CNT_0_H"}, 277 {true, "TX_PACKET_TC_OUT_CNT_1_L"}, 278 {true, "TX_PACKET_TC_OUT_CNT_1_H"}, 279 {true, "TX_PACKET_TC_OUT_CNT_2_L"}, 280 {true, "TX_PACKET_TC_OUT_CNT_2_H"}, 281 282 {true, "TX_PACKET_TC_OUT_CNT_3_L"}, 283 {true, "TX_PACKET_TC_OUT_CNT_3_H"}, 284 {true, "TX_PACKET_TC_OUT_CNT_4_L"}, 285 {true, "TX_PACKET_TC_OUT_CNT_4_H"}, 286 {true, "TX_PACKET_TC_OUT_CNT_5_L"}, 287 {true, "TX_PACKET_TC_OUT_CNT_5_H"}, 288 289 {true, "TX_PACKET_TC_OUT_CNT_6_L"}, 290 {true, "TX_PACKET_TC_OUT_CNT_6_H"}, 291 {true, "TX_PACKET_TC_OUT_CNT_7_L"}, 292 {true, "TX_PACKET_TC_OUT_CNT_7_H"}, 293 {false, "Reserved"}, 294 {false, "Reserved"}, 295 }; 296 297 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = { 298 {true, "OQ_INDEX"}, 299 {true, "QUEUE_CNT"}, 300 {false, "Reserved"}, 301 {false, "Reserved"}, 302 {false, "Reserved"}, 303 {false, "Reserved"}, 304 }; 305 306 static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = { 307 {true, "prt_id"}, 308 {true, "IGU_RX_ERR_PKT"}, 309 {true, "IGU_RX_NO_SOF_PKT"}, 310 {true, "EGU_TX_1588_SHORT_PKT"}, 311 {true, "EGU_TX_1588_PKT"}, 312 {true, "EGU_TX_ERR_PKT"}, 313 314 {true, "IGU_RX_OUT_L2_PKT"}, 315 {true, "IGU_RX_OUT_L3_PKT"}, 316 {true, "IGU_RX_OUT_L4_PKT"}, 317 {true, "IGU_RX_IN_L2_PKT"}, 318 {true, "IGU_RX_IN_L3_PKT"}, 319 {true, "IGU_RX_IN_L4_PKT"}, 320 321 {true, "IGU_RX_EL3E_PKT"}, 322 {true, "IGU_RX_EL4E_PKT"}, 323 {true, "IGU_RX_L3E_PKT"}, 324 {true, "IGU_RX_L4E_PKT"}, 325 {true, "IGU_RX_ROCEE_PKT"}, 326 {true, "IGU_RX_OUT_UDP0_PKT"}, 327 328 {true, "IGU_RX_IN_UDP0_PKT"}, 329 {true, "IGU_MC_CAR_DROP_PKT_L"}, 330 {true, "IGU_MC_CAR_DROP_PKT_H"}, 331 {true, "IGU_BC_CAR_DROP_PKT_L"}, 332 {true, "IGU_BC_CAR_DROP_PKT_H"}, 333 {false, "Reserved"}, 334 335 {true, "IGU_RX_OVERSIZE_PKT_L"}, 336 {true, "IGU_RX_OVERSIZE_PKT_H"}, 337 {true, "IGU_RX_UNDERSIZE_PKT_L"}, 338 {true, "IGU_RX_UNDERSIZE_PKT_H"}, 339 {true, "IGU_RX_OUT_ALL_PKT_L"}, 340 {true, "IGU_RX_OUT_ALL_PKT_H"}, 341 342 {true, "IGU_TX_OUT_ALL_PKT_L"}, 343 {true, "IGU_TX_OUT_ALL_PKT_H"}, 344 {true, "IGU_RX_UNI_PKT_L"}, 345 {true, "IGU_RX_UNI_PKT_H"}, 346 {true, "IGU_RX_MULTI_PKT_L"}, 347 {true, "IGU_RX_MULTI_PKT_H"}, 348 349 {true, "IGU_RX_BROAD_PKT_L"}, 350 {true, "IGU_RX_BROAD_PKT_H"}, 351 {true, "EGU_TX_OUT_ALL_PKT_L"}, 352 {true, "EGU_TX_OUT_ALL_PKT_H"}, 353 {true, "EGU_TX_UNI_PKT_L"}, 354 {true, "EGU_TX_UNI_PKT_H"}, 355 356 {true, "EGU_TX_MULTI_PKT_L"}, 357 {true, "EGU_TX_MULTI_PKT_H"}, 358 {true, "EGU_TX_BROAD_PKT_L"}, 359 {true, "EGU_TX_BROAD_PKT_H"}, 360 {true, "IGU_TX_KEY_NUM_L"}, 361 {true, "IGU_TX_KEY_NUM_H"}, 362 363 {true, "IGU_RX_NON_TUN_PKT_L"}, 364 {true, "IGU_RX_NON_TUN_PKT_H"}, 365 {true, "IGU_RX_TUN_PKT_L"}, 366 {true, "IGU_RX_TUN_PKT_H"}, 367 {false, "Reserved"}, 368 {false, "Reserved"}, 369 }; 370 371 static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = { 372 {true, "tc_queue_num"}, 373 {true, "FSM_DFX_ST0"}, 374 {true, "FSM_DFX_ST1"}, 375 {true, "RPU_RX_PKT_DROP_CNT"}, 376 {true, "BUF_WAIT_TIMEOUT"}, 377 {true, "BUF_WAIT_TIMEOUT_QID"}, 378 }; 379 380 static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = { 381 {false, "Reserved"}, 382 {true, "FIFO_DFX_ST0"}, 383 {true, "FIFO_DFX_ST1"}, 384 {true, "FIFO_DFX_ST2"}, 385 {true, "FIFO_DFX_ST3"}, 386 {true, "FIFO_DFX_ST4"}, 387 388 {true, "FIFO_DFX_ST5"}, 389 {false, "Reserved"}, 390 {false, "Reserved"}, 391 {false, "Reserved"}, 392 {false, "Reserved"}, 393 {false, "Reserved"}, 394 }; 395 396 static const struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = { 397 {false, "Reserved"}, 398 {true, "NCSI_EGU_TX_FIFO_STS"}, 399 {true, "NCSI_PAUSE_STATUS"}, 400 {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"}, 401 {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"}, 402 {true, "NCSI_RX_CTRL_CKS_ERR_CNT"}, 403 404 {true, "NCSI_RX_CTRL_PKT_CNT"}, 405 {true, "NCSI_RX_PT_DMAC_ERR_CNT"}, 406 {true, "NCSI_RX_PT_SMAC_ERR_CNT"}, 407 {true, "NCSI_RX_PT_PKT_CNT"}, 408 {true, "NCSI_RX_FCS_ERR_CNT"}, 409 {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"}, 410 411 {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"}, 412 {true, "NCSI_TX_CTRL_PKT_CNT"}, 413 {true, "NCSI_TX_PT_DMAC_ERR_CNT"}, 414 {true, "NCSI_TX_PT_SMAC_ERR_CNT"}, 415 {true, "NCSI_TX_PT_PKT_CNT"}, 416 {true, "NCSI_TX_PT_PKT_TRUNC_CNT"}, 417 418 {true, "NCSI_TX_PT_PKT_ERR_CNT"}, 419 {true, "NCSI_TX_CTRL_PKT_ERR_CNT"}, 420 {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"}, 421 {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"}, 422 {false, "Reserved"}, 423 {false, "Reserved"}, 424 425 {true, "NCSI_MAC_RX_OCTETS_OK"}, 426 {true, "NCSI_MAC_RX_OCTETS_BAD"}, 427 {true, "NCSI_MAC_RX_UC_PKTS"}, 428 {true, "NCSI_MAC_RX_MC_PKTS"}, 429 {true, "NCSI_MAC_RX_BC_PKTS"}, 430 {true, "NCSI_MAC_RX_PKTS_64OCTETS"}, 431 432 {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"}, 433 {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"}, 434 {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"}, 435 {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"}, 436 {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"}, 437 {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"}, 438 439 {true, "NCSI_MAC_RX_FCS_ERRORS"}, 440 {true, "NCSI_MAC_RX_LONG_ERRORS"}, 441 {true, "NCSI_MAC_RX_JABBER_ERRORS"}, 442 {true, "NCSI_MAC_RX_RUNT_ERR_CNT"}, 443 {true, "NCSI_MAC_RX_SHORT_ERR_CNT"}, 444 {true, "NCSI_MAC_RX_FILT_PKT_CNT"}, 445 446 {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"}, 447 {true, "NCSI_MAC_TX_OCTETS_OK"}, 448 {true, "NCSI_MAC_TX_OCTETS_BAD"}, 449 {true, "NCSI_MAC_TX_UC_PKTS"}, 450 {true, "NCSI_MAC_TX_MC_PKTS"}, 451 {true, "NCSI_MAC_TX_BC_PKTS"}, 452 453 {true, "NCSI_MAC_TX_PKTS_64OCTETS"}, 454 {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"}, 455 {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"}, 456 {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"}, 457 {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"}, 458 {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"}, 459 460 {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"}, 461 {true, "NCSI_MAC_TX_UNDERRUN"}, 462 {true, "NCSI_MAC_TX_CRC_ERROR"}, 463 {true, "NCSI_MAC_TX_PAUSE_FRAMES"}, 464 {true, "NCSI_MAC_RX_PAD_PKTS"}, 465 {true, "NCSI_MAC_RX_PAUSE_FRAMES"}, 466 }; 467 468 static const struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = { 469 {false, "Reserved"}, 470 {true, "LGE_IGU_AFIFO_DFX_0"}, 471 {true, "LGE_IGU_AFIFO_DFX_1"}, 472 {true, "LGE_IGU_AFIFO_DFX_2"}, 473 {true, "LGE_IGU_AFIFO_DFX_3"}, 474 {true, "LGE_IGU_AFIFO_DFX_4"}, 475 476 {true, "LGE_IGU_AFIFO_DFX_5"}, 477 {true, "LGE_IGU_AFIFO_DFX_6"}, 478 {true, "LGE_IGU_AFIFO_DFX_7"}, 479 {true, "LGE_EGU_AFIFO_DFX_0"}, 480 {true, "LGE_EGU_AFIFO_DFX_1"}, 481 {true, "LGE_EGU_AFIFO_DFX_2"}, 482 483 {true, "LGE_EGU_AFIFO_DFX_3"}, 484 {true, "LGE_EGU_AFIFO_DFX_4"}, 485 {true, "LGE_EGU_AFIFO_DFX_5"}, 486 {true, "LGE_EGU_AFIFO_DFX_6"}, 487 {true, "LGE_EGU_AFIFO_DFX_7"}, 488 {true, "CGE_IGU_AFIFO_DFX_0"}, 489 490 {true, "CGE_IGU_AFIFO_DFX_1"}, 491 {true, "CGE_EGU_AFIFO_DFX_0"}, 492 {true, "CGE_EGU_AFIFO_DFX_1"}, 493 {false, "Reserved"}, 494 {false, "Reserved"}, 495 {false, "Reserved"}, 496 }; 497 498 static const struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = { 499 {false, "Reserved"}, 500 {true, "DROP_FROM_PRT_PKT_CNT"}, 501 {true, "DROP_FROM_HOST_PKT_CNT"}, 502 {true, "DROP_TX_VLAN_PROC_CNT"}, 503 {true, "DROP_MNG_CNT"}, 504 {true, "DROP_FD_CNT"}, 505 506 {true, "DROP_NO_DST_CNT"}, 507 {true, "DROP_MC_MBID_FULL_CNT"}, 508 {true, "DROP_SC_FILTERED"}, 509 {true, "PPP_MC_DROP_PKT_CNT"}, 510 {true, "DROP_PT_CNT"}, 511 {true, "DROP_MAC_ANTI_SPOOF_CNT"}, 512 513 {true, "DROP_IG_VFV_CNT"}, 514 {true, "DROP_IG_PRTV_CNT"}, 515 {true, "DROP_CNM_PFC_PAUSE_CNT"}, 516 {true, "DROP_TORUS_TC_CNT"}, 517 {true, "DROP_TORUS_LPBK_CNT"}, 518 {true, "PPP_HFS_STS"}, 519 520 {true, "PPP_MC_RSLT_STS"}, 521 {true, "PPP_P3U_STS"}, 522 {true, "PPP_RSLT_DESCR_STS"}, 523 {true, "PPP_UMV_STS_0"}, 524 {true, "PPP_UMV_STS_1"}, 525 {true, "PPP_VFV_STS"}, 526 527 {true, "PPP_GRO_KEY_CNT"}, 528 {true, "PPP_GRO_INFO_CNT"}, 529 {true, "PPP_GRO_DROP_CNT"}, 530 {true, "PPP_GRO_OUT_CNT"}, 531 {true, "PPP_GRO_KEY_MATCH_DATA_CNT"}, 532 {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"}, 533 534 {true, "PPP_GRO_INFO_MATCH_CNT"}, 535 {true, "PPP_GRO_FREE_ENTRY_CNT"}, 536 {true, "PPP_GRO_INNER_DFX_SIGNAL"}, 537 {false, "Reserved"}, 538 {false, "Reserved"}, 539 {false, "Reserved"}, 540 541 {true, "GET_RX_PKT_CNT_L"}, 542 {true, "GET_RX_PKT_CNT_H"}, 543 {true, "GET_TX_PKT_CNT_L"}, 544 {true, "GET_TX_PKT_CNT_H"}, 545 {true, "SEND_UC_PRT2HOST_PKT_CNT_L"}, 546 {true, "SEND_UC_PRT2HOST_PKT_CNT_H"}, 547 548 {true, "SEND_UC_PRT2PRT_PKT_CNT_L"}, 549 {true, "SEND_UC_PRT2PRT_PKT_CNT_H"}, 550 {true, "SEND_UC_HOST2HOST_PKT_CNT_L"}, 551 {true, "SEND_UC_HOST2HOST_PKT_CNT_H"}, 552 {true, "SEND_UC_HOST2PRT_PKT_CNT_L"}, 553 {true, "SEND_UC_HOST2PRT_PKT_CNT_H"}, 554 555 {true, "SEND_MC_FROM_PRT_CNT_L"}, 556 {true, "SEND_MC_FROM_PRT_CNT_H"}, 557 {true, "SEND_MC_FROM_HOST_CNT_L"}, 558 {true, "SEND_MC_FROM_HOST_CNT_H"}, 559 {true, "SSU_MC_RD_CNT_L"}, 560 {true, "SSU_MC_RD_CNT_H"}, 561 562 {true, "SSU_MC_DROP_CNT_L"}, 563 {true, "SSU_MC_DROP_CNT_H"}, 564 {true, "SSU_MC_RD_PKT_CNT_L"}, 565 {true, "SSU_MC_RD_PKT_CNT_H"}, 566 {true, "PPP_MC_2HOST_PKT_CNT_L"}, 567 {true, "PPP_MC_2HOST_PKT_CNT_H"}, 568 569 {true, "PPP_MC_2PRT_PKT_CNT_L"}, 570 {true, "PPP_MC_2PRT_PKT_CNT_H"}, 571 {true, "NTSNOS_PKT_CNT_L"}, 572 {true, "NTSNOS_PKT_CNT_H"}, 573 {true, "NTUP_PKT_CNT_L"}, 574 {true, "NTUP_PKT_CNT_H"}, 575 576 {true, "NTLCL_PKT_CNT_L"}, 577 {true, "NTLCL_PKT_CNT_H"}, 578 {true, "NTTGT_PKT_CNT_L"}, 579 {true, "NTTGT_PKT_CNT_H"}, 580 {true, "RTNS_PKT_CNT_L"}, 581 {true, "RTNS_PKT_CNT_H"}, 582 583 {true, "RTLPBK_PKT_CNT_L"}, 584 {true, "RTLPBK_PKT_CNT_H"}, 585 {true, "NR_PKT_CNT_L"}, 586 {true, "NR_PKT_CNT_H"}, 587 {true, "RR_PKT_CNT_L"}, 588 {true, "RR_PKT_CNT_H"}, 589 590 {true, "MNG_TBL_HIT_CNT_L"}, 591 {true, "MNG_TBL_HIT_CNT_H"}, 592 {true, "FD_TBL_HIT_CNT_L"}, 593 {true, "FD_TBL_HIT_CNT_H"}, 594 {true, "FD_LKUP_CNT_L"}, 595 {true, "FD_LKUP_CNT_H"}, 596 597 {true, "BC_HIT_CNT_L"}, 598 {true, "BC_HIT_CNT_H"}, 599 {true, "UM_TBL_UC_HIT_CNT_L"}, 600 {true, "UM_TBL_UC_HIT_CNT_H"}, 601 {true, "UM_TBL_MC_HIT_CNT_L"}, 602 {true, "UM_TBL_MC_HIT_CNT_H"}, 603 604 {true, "UM_TBL_VMDQ1_HIT_CNT_L"}, 605 {true, "UM_TBL_VMDQ1_HIT_CNT_H"}, 606 {true, "MTA_TBL_HIT_CNT_L"}, 607 {true, "MTA_TBL_HIT_CNT_H"}, 608 {true, "FWD_BONDING_HIT_CNT_L"}, 609 {true, "FWD_BONDING_HIT_CNT_H"}, 610 611 {true, "PROMIS_TBL_HIT_CNT_L"}, 612 {true, "PROMIS_TBL_HIT_CNT_H"}, 613 {true, "GET_TUNL_PKT_CNT_L"}, 614 {true, "GET_TUNL_PKT_CNT_H"}, 615 {true, "GET_BMC_PKT_CNT_L"}, 616 {true, "GET_BMC_PKT_CNT_H"}, 617 618 {true, "SEND_UC_PRT2BMC_PKT_CNT_L"}, 619 {true, "SEND_UC_PRT2BMC_PKT_CNT_H"}, 620 {true, "SEND_UC_HOST2BMC_PKT_CNT_L"}, 621 {true, "SEND_UC_HOST2BMC_PKT_CNT_H"}, 622 {true, "SEND_UC_BMC2HOST_PKT_CNT_L"}, 623 {true, "SEND_UC_BMC2HOST_PKT_CNT_H"}, 624 625 {true, "SEND_UC_BMC2PRT_PKT_CNT_L"}, 626 {true, "SEND_UC_BMC2PRT_PKT_CNT_H"}, 627 {true, "PPP_MC_2BMC_PKT_CNT_L"}, 628 {true, "PPP_MC_2BMC_PKT_CNT_H"}, 629 {true, "VLAN_MIRR_CNT_L"}, 630 {true, "VLAN_MIRR_CNT_H"}, 631 632 {true, "IG_MIRR_CNT_L"}, 633 {true, "IG_MIRR_CNT_H"}, 634 {true, "EG_MIRR_CNT_L"}, 635 {true, "EG_MIRR_CNT_H"}, 636 {true, "RX_DEFAULT_HOST_HIT_CNT_L"}, 637 {true, "RX_DEFAULT_HOST_HIT_CNT_H"}, 638 639 {true, "LAN_PAIR_CNT_L"}, 640 {true, "LAN_PAIR_CNT_H"}, 641 {true, "UM_TBL_MC_HIT_PKT_CNT_L"}, 642 {true, "UM_TBL_MC_HIT_PKT_CNT_H"}, 643 {true, "MTA_TBL_HIT_PKT_CNT_L"}, 644 {true, "MTA_TBL_HIT_PKT_CNT_H"}, 645 646 {true, "PROMIS_TBL_HIT_PKT_CNT_L"}, 647 {true, "PROMIS_TBL_HIT_PKT_CNT_H"}, 648 {false, "Reserved"}, 649 {false, "Reserved"}, 650 {false, "Reserved"}, 651 {false, "Reserved"}, 652 }; 653 654 static const struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = { 655 {false, "Reserved"}, 656 {true, "FSM_DFX_ST0"}, 657 {true, "FSM_DFX_ST1"}, 658 {true, "FSM_DFX_ST2"}, 659 {true, "FIFO_DFX_ST0"}, 660 {true, "FIFO_DFX_ST1"}, 661 662 {true, "FIFO_DFX_ST2"}, 663 {true, "FIFO_DFX_ST3"}, 664 {true, "FIFO_DFX_ST4"}, 665 {true, "FIFO_DFX_ST5"}, 666 {true, "FIFO_DFX_ST6"}, 667 {true, "FIFO_DFX_ST7"}, 668 669 {true, "FIFO_DFX_ST8"}, 670 {true, "FIFO_DFX_ST9"}, 671 {true, "FIFO_DFX_ST10"}, 672 {true, "FIFO_DFX_ST11"}, 673 {true, "Q_CREDIT_VLD_0"}, 674 {true, "Q_CREDIT_VLD_1"}, 675 676 {true, "Q_CREDIT_VLD_2"}, 677 {true, "Q_CREDIT_VLD_3"}, 678 {true, "Q_CREDIT_VLD_4"}, 679 {true, "Q_CREDIT_VLD_5"}, 680 {true, "Q_CREDIT_VLD_6"}, 681 {true, "Q_CREDIT_VLD_7"}, 682 683 {true, "Q_CREDIT_VLD_8"}, 684 {true, "Q_CREDIT_VLD_9"}, 685 {true, "Q_CREDIT_VLD_10"}, 686 {true, "Q_CREDIT_VLD_11"}, 687 {true, "Q_CREDIT_VLD_12"}, 688 {true, "Q_CREDIT_VLD_13"}, 689 690 {true, "Q_CREDIT_VLD_14"}, 691 {true, "Q_CREDIT_VLD_15"}, 692 {true, "Q_CREDIT_VLD_16"}, 693 {true, "Q_CREDIT_VLD_17"}, 694 {true, "Q_CREDIT_VLD_18"}, 695 {true, "Q_CREDIT_VLD_19"}, 696 697 {true, "Q_CREDIT_VLD_20"}, 698 {true, "Q_CREDIT_VLD_21"}, 699 {true, "Q_CREDIT_VLD_22"}, 700 {true, "Q_CREDIT_VLD_23"}, 701 {true, "Q_CREDIT_VLD_24"}, 702 {true, "Q_CREDIT_VLD_25"}, 703 704 {true, "Q_CREDIT_VLD_26"}, 705 {true, "Q_CREDIT_VLD_27"}, 706 {true, "Q_CREDIT_VLD_28"}, 707 {true, "Q_CREDIT_VLD_29"}, 708 {true, "Q_CREDIT_VLD_30"}, 709 {true, "Q_CREDIT_VLD_31"}, 710 711 {true, "GRO_BD_SERR_CNT"}, 712 {true, "GRO_CONTEXT_SERR_CNT"}, 713 {true, "RX_STASH_CFG_SERR_CNT"}, 714 {true, "AXI_RD_FBD_SERR_CNT"}, 715 {true, "GRO_BD_MERR_CNT"}, 716 {true, "GRO_CONTEXT_MERR_CNT"}, 717 718 {true, "RX_STASH_CFG_MERR_CNT"}, 719 {true, "AXI_RD_FBD_MERR_CNT"}, 720 {false, "Reserved"}, 721 {false, "Reserved"}, 722 {false, "Reserved"}, 723 {false, "Reserved"}, 724 }; 725 726 static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = { 727 {true, "q_num"}, 728 {true, "RCB_CFG_RX_RING_TAIL"}, 729 {true, "RCB_CFG_RX_RING_HEAD"}, 730 {true, "RCB_CFG_RX_RING_FBDNUM"}, 731 {true, "RCB_CFG_RX_RING_OFFSET"}, 732 {true, "RCB_CFG_RX_RING_FBDOFFSET"}, 733 734 {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"}, 735 {true, "RCB_CFG_TX_RING_TAIL"}, 736 {true, "RCB_CFG_TX_RING_HEAD"}, 737 {true, "RCB_CFG_TX_RING_FBDNUM"}, 738 {true, "RCB_CFG_TX_RING_OFFSET"}, 739 {true, "RCB_CFG_TX_RING_EBDNUM"}, 740 }; 741 742 #define HCLGE_DBG_INFO_LEN 256 743 #define HCLGE_DBG_VLAN_FLTR_INFO_LEN 256 744 #define HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN 512 745 #define HCLGE_DBG_ID_LEN 16 746 #define HCLGE_DBG_ITEM_NAME_LEN 32 747 #define HCLGE_DBG_DATA_STR_LEN 32 748 #define HCLGE_DBG_TM_INFO_LEN 256 749 750 #define HCLGE_BILLION_NANO_SECONDS 1000000000 751 752 struct hclge_dbg_item { 753 char name[HCLGE_DBG_ITEM_NAME_LEN]; 754 u16 interval; /* blank numbers after the item */ 755 }; 756 757 struct hclge_dbg_vlan_cfg { 758 u16 pvid; 759 u8 accept_tag1; 760 u8 accept_tag2; 761 u8 accept_untag1; 762 u8 accept_untag2; 763 u8 insert_tag1; 764 u8 insert_tag2; 765 u8 shift_tag; 766 u8 strip_tag1; 767 u8 strip_tag2; 768 u8 drop_tag1; 769 u8 drop_tag2; 770 u8 pri_only1; 771 u8 pri_only2; 772 }; 773 774 #endif 775