1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include "hclge_main.h" 5 #include "hclge_dcb.h" 6 #include "hclge_tm.h" 7 #include "hnae3.h" 8 9 #define BW_PERCENT 100 10 11 static int hclge_ieee_ets_to_tm_info(struct hclge_dev *hdev, 12 struct ieee_ets *ets) 13 { 14 u8 i; 15 16 for (i = 0; i < HNAE3_MAX_TC; i++) { 17 switch (ets->tc_tsa[i]) { 18 case IEEE_8021QAZ_TSA_STRICT: 19 hdev->tm_info.tc_info[i].tc_sch_mode = 20 HCLGE_SCH_MODE_SP; 21 hdev->tm_info.pg_info[0].tc_dwrr[i] = 0; 22 break; 23 case IEEE_8021QAZ_TSA_ETS: 24 hdev->tm_info.tc_info[i].tc_sch_mode = 25 HCLGE_SCH_MODE_DWRR; 26 hdev->tm_info.pg_info[0].tc_dwrr[i] = 27 ets->tc_tx_bw[i]; 28 break; 29 default: 30 /* Hardware only supports SP (strict priority) 31 * or ETS (enhanced transmission selection) 32 * algorithms, if we receive some other value 33 * from dcbnl, then throw an error. 34 */ 35 return -EINVAL; 36 } 37 } 38 39 hclge_tm_prio_tc_info_update(hdev, ets->prio_tc); 40 41 return 0; 42 } 43 44 static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev, 45 struct ieee_ets *ets) 46 { 47 u32 i; 48 49 memset(ets, 0, sizeof(*ets)); 50 ets->willing = 1; 51 ets->ets_cap = hdev->tc_max; 52 53 for (i = 0; i < HNAE3_MAX_TC; i++) { 54 ets->prio_tc[i] = hdev->tm_info.prio_tc[i]; 55 ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i]; 56 57 if (hdev->tm_info.tc_info[i].tc_sch_mode == 58 HCLGE_SCH_MODE_SP) 59 ets->tc_tsa[i] = IEEE_8021QAZ_TSA_STRICT; 60 else 61 ets->tc_tsa[i] = IEEE_8021QAZ_TSA_ETS; 62 } 63 } 64 65 /* IEEE std */ 66 static int hclge_ieee_getets(struct hnae3_handle *h, struct ieee_ets *ets) 67 { 68 struct hclge_vport *vport = hclge_get_vport(h); 69 struct hclge_dev *hdev = vport->back; 70 71 hclge_tm_info_to_ieee_ets(hdev, ets); 72 73 return 0; 74 } 75 76 static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc, 77 u8 *prio_tc) 78 { 79 int i; 80 81 if (num_tc > hdev->tc_max) { 82 dev_err(&hdev->pdev->dev, 83 "tc num checking failed, %u > tc_max(%u)\n", 84 num_tc, hdev->tc_max); 85 return -EINVAL; 86 } 87 88 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 89 if (prio_tc[i] >= num_tc) { 90 dev_err(&hdev->pdev->dev, 91 "prio_tc[%d] checking failed, %u >= num_tc(%u)\n", 92 i, prio_tc[i], num_tc); 93 return -EINVAL; 94 } 95 } 96 97 if (num_tc > hdev->vport[0].alloc_tqps) { 98 dev_err(&hdev->pdev->dev, 99 "allocated tqp checking failed, %u > tqp(%u)\n", 100 num_tc, hdev->vport[0].alloc_tqps); 101 return -EINVAL; 102 } 103 104 return 0; 105 } 106 107 static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets, 108 u8 *tc, bool *changed) 109 { 110 bool has_ets_tc = false; 111 u32 total_ets_bw = 0; 112 u8 max_tc = 0; 113 int ret; 114 u8 i; 115 116 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 117 if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i]) 118 *changed = true; 119 120 if (ets->prio_tc[i] > max_tc) 121 max_tc = ets->prio_tc[i]; 122 } 123 124 ret = hclge_dcb_common_validate(hdev, max_tc + 1, ets->prio_tc); 125 if (ret) 126 return ret; 127 128 for (i = 0; i < hdev->tc_max; i++) { 129 switch (ets->tc_tsa[i]) { 130 case IEEE_8021QAZ_TSA_STRICT: 131 if (hdev->tm_info.tc_info[i].tc_sch_mode != 132 HCLGE_SCH_MODE_SP) 133 *changed = true; 134 break; 135 case IEEE_8021QAZ_TSA_ETS: 136 if (hdev->tm_info.tc_info[i].tc_sch_mode != 137 HCLGE_SCH_MODE_DWRR) 138 *changed = true; 139 140 total_ets_bw += ets->tc_tx_bw[i]; 141 has_ets_tc = true; 142 break; 143 default: 144 return -EINVAL; 145 } 146 } 147 148 if (has_ets_tc && total_ets_bw != BW_PERCENT) 149 return -EINVAL; 150 151 *tc = max_tc + 1; 152 if (*tc != hdev->tm_info.num_tc) 153 *changed = true; 154 155 return 0; 156 } 157 158 static int hclge_map_update(struct hclge_dev *hdev) 159 { 160 int ret; 161 162 ret = hclge_tm_schd_setup_hw(hdev); 163 if (ret) 164 return ret; 165 166 ret = hclge_pause_setup_hw(hdev, false); 167 if (ret) 168 return ret; 169 170 ret = hclge_buffer_alloc(hdev); 171 if (ret) 172 return ret; 173 174 hclge_rss_indir_init_cfg(hdev); 175 176 return hclge_rss_init_hw(hdev); 177 } 178 179 static int hclge_client_setup_tc(struct hclge_dev *hdev) 180 { 181 struct hclge_vport *vport = hdev->vport; 182 struct hnae3_client *client; 183 struct hnae3_handle *handle; 184 int ret; 185 u32 i; 186 187 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 188 handle = &vport[i].nic; 189 client = handle->client; 190 191 if (!client || !client->ops || !client->ops->setup_tc) 192 continue; 193 194 ret = client->ops->setup_tc(handle, hdev->tm_info.num_tc); 195 if (ret) 196 return ret; 197 } 198 199 return 0; 200 } 201 202 static int hclge_notify_down_uinit(struct hclge_dev *hdev) 203 { 204 int ret; 205 206 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 207 if (ret) 208 return ret; 209 210 return hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 211 } 212 213 static int hclge_notify_init_up(struct hclge_dev *hdev) 214 { 215 int ret; 216 217 ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 218 if (ret) 219 return ret; 220 221 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 222 } 223 224 static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets) 225 { 226 struct hclge_vport *vport = hclge_get_vport(h); 227 struct net_device *netdev = h->kinfo.netdev; 228 struct hclge_dev *hdev = vport->back; 229 bool map_changed = false; 230 u8 num_tc = 0; 231 int ret; 232 233 if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) || 234 hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE) 235 return -EINVAL; 236 237 ret = hclge_ets_validate(hdev, ets, &num_tc, &map_changed); 238 if (ret) 239 return ret; 240 241 if (map_changed) { 242 netif_dbg(h, drv, netdev, "set ets\n"); 243 244 ret = hclge_notify_down_uinit(hdev); 245 if (ret) 246 return ret; 247 } 248 249 hclge_tm_schd_info_update(hdev, num_tc); 250 251 ret = hclge_ieee_ets_to_tm_info(hdev, ets); 252 if (ret) 253 goto err_out; 254 255 if (map_changed) { 256 ret = hclge_map_update(hdev); 257 if (ret) 258 goto err_out; 259 260 ret = hclge_client_setup_tc(hdev); 261 if (ret) 262 goto err_out; 263 264 ret = hclge_notify_init_up(hdev); 265 if (ret) 266 return ret; 267 } 268 269 return hclge_tm_dwrr_cfg(hdev); 270 271 err_out: 272 if (!map_changed) 273 return ret; 274 275 hclge_notify_init_up(hdev); 276 277 return ret; 278 } 279 280 static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc) 281 { 282 u64 requests[HNAE3_MAX_TC], indications[HNAE3_MAX_TC]; 283 struct hclge_vport *vport = hclge_get_vport(h); 284 struct hclge_dev *hdev = vport->back; 285 u8 i, j, pfc_map, *prio_tc; 286 int ret; 287 288 memset(pfc, 0, sizeof(*pfc)); 289 pfc->pfc_cap = hdev->pfc_max; 290 prio_tc = hdev->tm_info.prio_tc; 291 pfc_map = hdev->tm_info.hw_pfc_map; 292 293 /* Pfc setting is based on TC */ 294 for (i = 0; i < hdev->tm_info.num_tc; i++) { 295 for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) { 296 if ((prio_tc[j] == i) && (pfc_map & BIT(i))) 297 pfc->pfc_en |= BIT(j); 298 } 299 } 300 301 ret = hclge_pfc_tx_stats_get(hdev, requests); 302 if (ret) 303 return ret; 304 305 ret = hclge_pfc_rx_stats_get(hdev, indications); 306 if (ret) 307 return ret; 308 309 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 310 pfc->requests[i] = requests[i]; 311 pfc->indications[i] = indications[i]; 312 } 313 return 0; 314 } 315 316 static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc) 317 { 318 struct hclge_vport *vport = hclge_get_vport(h); 319 struct net_device *netdev = h->kinfo.netdev; 320 struct hclge_dev *hdev = vport->back; 321 u8 i, j, pfc_map, *prio_tc; 322 int ret; 323 324 if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) || 325 hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE) 326 return -EINVAL; 327 328 if (pfc->pfc_en == hdev->tm_info.pfc_en) 329 return 0; 330 331 prio_tc = hdev->tm_info.prio_tc; 332 pfc_map = 0; 333 334 for (i = 0; i < hdev->tm_info.num_tc; i++) { 335 for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) { 336 if ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) { 337 pfc_map |= BIT(i); 338 break; 339 } 340 } 341 } 342 343 hdev->tm_info.hw_pfc_map = pfc_map; 344 hdev->tm_info.pfc_en = pfc->pfc_en; 345 346 netif_dbg(h, drv, netdev, 347 "set pfc: pfc_en=%x, pfc_map=%x, num_tc=%u\n", 348 pfc->pfc_en, pfc_map, hdev->tm_info.num_tc); 349 350 hclge_tm_pfc_info_update(hdev); 351 352 ret = hclge_pause_setup_hw(hdev, false); 353 if (ret) 354 return ret; 355 356 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 357 if (ret) 358 return ret; 359 360 ret = hclge_buffer_alloc(hdev); 361 if (ret) { 362 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 363 return ret; 364 } 365 366 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 367 } 368 369 /* DCBX configuration */ 370 static u8 hclge_getdcbx(struct hnae3_handle *h) 371 { 372 struct hclge_vport *vport = hclge_get_vport(h); 373 struct hclge_dev *hdev = vport->back; 374 375 if (hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE) 376 return 0; 377 378 return hdev->dcbx_cap; 379 } 380 381 static u8 hclge_setdcbx(struct hnae3_handle *h, u8 mode) 382 { 383 struct hclge_vport *vport = hclge_get_vport(h); 384 struct net_device *netdev = h->kinfo.netdev; 385 struct hclge_dev *hdev = vport->back; 386 387 netif_dbg(h, drv, netdev, "set dcbx: mode=%u\n", mode); 388 389 /* No support for LLD_MANAGED modes or CEE */ 390 if ((mode & DCB_CAP_DCBX_LLD_MANAGED) || 391 (mode & DCB_CAP_DCBX_VER_CEE) || 392 !(mode & DCB_CAP_DCBX_HOST)) 393 return 1; 394 395 hdev->dcbx_cap = mode; 396 397 return 0; 398 } 399 400 /* Set up TC for hardware offloaded mqprio in channel mode */ 401 static int hclge_setup_tc(struct hnae3_handle *h, u8 tc, u8 *prio_tc) 402 { 403 struct hclge_vport *vport = hclge_get_vport(h); 404 struct hclge_dev *hdev = vport->back; 405 int ret; 406 407 if (hdev->flag & HCLGE_FLAG_DCB_ENABLE) 408 return -EINVAL; 409 410 ret = hclge_dcb_common_validate(hdev, tc, prio_tc); 411 if (ret) 412 return -EINVAL; 413 414 ret = hclge_notify_down_uinit(hdev); 415 if (ret) 416 return ret; 417 418 hclge_tm_schd_info_update(hdev, tc); 419 hclge_tm_prio_tc_info_update(hdev, prio_tc); 420 421 ret = hclge_tm_init_hw(hdev, false); 422 if (ret) 423 goto err_out; 424 425 ret = hclge_client_setup_tc(hdev); 426 if (ret) 427 goto err_out; 428 429 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE; 430 431 if (tc > 1) 432 hdev->flag |= HCLGE_FLAG_MQPRIO_ENABLE; 433 else 434 hdev->flag &= ~HCLGE_FLAG_MQPRIO_ENABLE; 435 436 return hclge_notify_init_up(hdev); 437 438 err_out: 439 hclge_notify_init_up(hdev); 440 441 return ret; 442 } 443 444 static const struct hnae3_dcb_ops hns3_dcb_ops = { 445 .ieee_getets = hclge_ieee_getets, 446 .ieee_setets = hclge_ieee_setets, 447 .ieee_getpfc = hclge_ieee_getpfc, 448 .ieee_setpfc = hclge_ieee_setpfc, 449 .getdcbx = hclge_getdcbx, 450 .setdcbx = hclge_setdcbx, 451 .setup_tc = hclge_setup_tc, 452 }; 453 454 void hclge_dcb_ops_set(struct hclge_dev *hdev) 455 { 456 struct hclge_vport *vport = hdev->vport; 457 struct hnae3_knic_private_info *kinfo; 458 459 /* Hdev does not support DCB or vport is 460 * not a pf, then dcb_ops is not set. 461 */ 462 if (!hnae3_dev_dcb_supported(hdev) || 463 vport->vport_id != 0) 464 return; 465 466 kinfo = &vport->nic.kinfo; 467 kinfo->dcb_ops = &hns3_dcb_ops; 468 hdev->dcbx_cap = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_HOST; 469 } 470