1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 9 #define HCLGE_CMDQ_TX_TIMEOUT 30000 10 11 struct hclge_dev; 12 struct hclge_desc { 13 __le16 opcode; 14 15 #define HCLGE_CMDQ_RX_INVLD_B 0 16 #define HCLGE_CMDQ_RX_OUTVLD_B 1 17 18 __le16 flag; 19 __le16 retval; 20 __le16 rsv; 21 __le32 data[6]; 22 }; 23 24 struct hclge_cmq_ring { 25 dma_addr_t desc_dma_addr; 26 struct hclge_desc *desc; 27 struct hclge_dev *dev; 28 u32 head; 29 u32 tail; 30 31 u16 buf_size; 32 u16 desc_num; 33 int next_to_use; 34 int next_to_clean; 35 u8 ring_type; /* cmq ring type */ 36 spinlock_t lock; /* Command queue lock */ 37 }; 38 39 enum hclge_cmd_return_status { 40 HCLGE_CMD_EXEC_SUCCESS = 0, 41 HCLGE_CMD_NO_AUTH = 1, 42 HCLGE_CMD_NOT_EXEC = 2, 43 HCLGE_CMD_QUEUE_FULL = 3, 44 }; 45 46 enum hclge_cmd_status { 47 HCLGE_STATUS_SUCCESS = 0, 48 HCLGE_ERR_CSQ_FULL = -1, 49 HCLGE_ERR_CSQ_TIMEOUT = -2, 50 HCLGE_ERR_CSQ_ERROR = -3, 51 }; 52 53 struct hclge_misc_vector { 54 u8 __iomem *addr; 55 int vector_irq; 56 }; 57 58 struct hclge_cmq { 59 struct hclge_cmq_ring csq; 60 struct hclge_cmq_ring crq; 61 u16 tx_timeout; 62 enum hclge_cmd_status last_status; 63 }; 64 65 #define HCLGE_CMD_FLAG_IN BIT(0) 66 #define HCLGE_CMD_FLAG_OUT BIT(1) 67 #define HCLGE_CMD_FLAG_NEXT BIT(2) 68 #define HCLGE_CMD_FLAG_WR BIT(3) 69 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 71 72 enum hclge_opcode_type { 73 /* Generic commands */ 74 HCLGE_OPC_QUERY_FW_VER = 0x0001, 75 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 76 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 77 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 78 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 79 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 80 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 81 82 HCLGE_OPC_STATS_64_BIT = 0x0030, 83 HCLGE_OPC_STATS_32_BIT = 0x0031, 84 HCLGE_OPC_STATS_MAC = 0x0032, 85 86 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 87 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 88 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 89 90 /* MAC command */ 91 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 92 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 93 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 94 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 95 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 96 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 97 98 /* PFC/Pause commands */ 99 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 100 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 101 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 102 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 103 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 104 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 105 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 106 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 107 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 108 HCLGE_OPC_QOS_MAP = 0x070A, 109 110 /* ETS/scheduler commands */ 111 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 112 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 113 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 114 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 115 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 116 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 117 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 118 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 119 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 120 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 121 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 122 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 123 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 124 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 125 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 126 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 127 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 128 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 129 130 /* Packet buffer allocate commands */ 131 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 132 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 133 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 134 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 135 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 136 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 137 138 /* TQP management command */ 139 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 140 141 /* TQP commands */ 142 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 143 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 144 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 145 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 146 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 147 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 148 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 149 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 150 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 151 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 152 153 /* TSO command */ 154 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 155 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 156 157 /* RSS commands */ 158 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 159 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 160 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 161 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 162 163 /* Promisuous mode command */ 164 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 165 166 /* Vlan offload commands */ 167 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 168 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 169 170 /* Interrupts commands */ 171 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 172 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 173 174 /* MAC commands */ 175 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 176 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 177 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 178 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 179 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 180 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 181 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 182 183 /* VLAN commands */ 184 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 185 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 186 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 187 188 /* Flow Director commands */ 189 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 190 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 191 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 192 HCLGE_OPC_FD_TCAM_OP = 0x1203, 193 HCLGE_OPC_FD_AD_OP = 0x1204, 194 195 /* MDIO command */ 196 HCLGE_OPC_MDIO_CONFIG = 0x1900, 197 198 /* QCN commands */ 199 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 200 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 201 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 202 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 203 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 204 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 205 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 206 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 207 208 /* Mailbox command */ 209 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 210 211 /* Led command */ 212 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 213 214 /* SFP command */ 215 HCLGE_OPC_SFP_GET_SPEED = 0x7104, 216 217 /* Error INT commands */ 218 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 219 HCLGE_TM_SCH_ECC_ERR_RINT_CMD = 0x082d, 220 HCLGE_TM_SCH_ECC_ERR_RINT_CE = 0x082f, 221 HCLGE_TM_SCH_ECC_ERR_RINT_NFE = 0x0830, 222 HCLGE_TM_SCH_ECC_ERR_RINT_FE = 0x0831, 223 HCLGE_TM_SCH_MBIT_ECC_INFO_CMD = 0x0833, 224 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 225 HCLGE_IGU_EGU_TNL_INT_QUERY = 0x1802, 226 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 227 HCLGE_IGU_EGU_TNL_INT_CLR = 0x1804, 228 HCLGE_IGU_COMMON_INT_QUERY = 0x1805, 229 HCLGE_IGU_COMMON_INT_EN = 0x1806, 230 HCLGE_IGU_COMMON_INT_CLR = 0x1807, 231 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 232 HCLGE_TM_QCN_MEM_INT_INFO_CMD = 0x1A17, 233 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 234 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 235 HCLGE_NCSI_INT_QUERY = 0x2400, 236 HCLGE_NCSI_INT_EN = 0x2401, 237 HCLGE_NCSI_INT_CLR = 0x2402, 238 }; 239 240 #define HCLGE_TQP_REG_OFFSET 0x80000 241 #define HCLGE_TQP_REG_SIZE 0x200 242 243 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 244 #define HCLGE_RCB_INIT_FLAG_EN_B 0 245 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 246 struct hclge_config_rcb_init_cmd { 247 __le16 rcb_init_flag; 248 u8 rsv[22]; 249 }; 250 251 struct hclge_tqp_map_cmd { 252 __le16 tqp_id; /* Absolute tqp id for in this pf */ 253 u8 tqp_vf; /* VF id */ 254 #define HCLGE_TQP_MAP_TYPE_PF 0 255 #define HCLGE_TQP_MAP_TYPE_VF 1 256 #define HCLGE_TQP_MAP_TYPE_B 0 257 #define HCLGE_TQP_MAP_EN_B 1 258 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 259 __le16 tqp_vid; /* Virtual id in this pf/vf */ 260 u8 rsv[18]; 261 }; 262 263 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 264 265 enum hclge_int_type { 266 HCLGE_INT_TX, 267 HCLGE_INT_RX, 268 HCLGE_INT_EVENT, 269 }; 270 271 struct hclge_ctrl_vector_chain_cmd { 272 u8 int_vector_id; 273 u8 int_cause_num; 274 #define HCLGE_INT_TYPE_S 0 275 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 276 #define HCLGE_TQP_ID_S 2 277 #define HCLGE_TQP_ID_M GENMASK(12, 2) 278 #define HCLGE_INT_GL_IDX_S 13 279 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 280 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 281 u8 vfid; 282 u8 rsv; 283 }; 284 285 #define HCLGE_TC_NUM 8 286 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 287 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 288 struct hclge_tx_buff_alloc_cmd { 289 __le16 tx_pkt_buff[HCLGE_TC_NUM]; 290 u8 tx_buff_rsv[8]; 291 }; 292 293 struct hclge_rx_priv_buff_cmd { 294 __le16 buf_num[HCLGE_TC_NUM]; 295 __le16 shared_buf; 296 u8 rsv[6]; 297 }; 298 299 struct hclge_query_version_cmd { 300 __le32 firmware; 301 __le32 firmware_rsv[5]; 302 }; 303 304 #define HCLGE_RX_PRIV_EN_B 15 305 #define HCLGE_TC_NUM_ONE_DESC 4 306 struct hclge_priv_wl { 307 __le16 high; 308 __le16 low; 309 }; 310 311 struct hclge_rx_priv_wl_buf { 312 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 313 }; 314 315 struct hclge_rx_com_thrd { 316 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 317 }; 318 319 struct hclge_rx_com_wl { 320 struct hclge_priv_wl com_wl; 321 }; 322 323 struct hclge_waterline { 324 u32 low; 325 u32 high; 326 }; 327 328 struct hclge_tc_thrd { 329 u32 low; 330 u32 high; 331 }; 332 333 struct hclge_priv_buf { 334 struct hclge_waterline wl; /* Waterline for low and high*/ 335 u32 buf_size; /* TC private buffer size */ 336 u32 tx_buf_size; 337 u32 enable; /* Enable TC private buffer or not */ 338 }; 339 340 #define HCLGE_MAX_TC_NUM 8 341 struct hclge_shared_buf { 342 struct hclge_waterline self; 343 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 344 u32 buf_size; 345 }; 346 347 struct hclge_pkt_buf_alloc { 348 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 349 struct hclge_shared_buf s_buf; 350 }; 351 352 #define HCLGE_RX_COM_WL_EN_B 15 353 struct hclge_rx_com_wl_buf_cmd { 354 __le16 high_wl; 355 __le16 low_wl; 356 u8 rsv[20]; 357 }; 358 359 #define HCLGE_RX_PKT_EN_B 15 360 struct hclge_rx_pkt_buf_cmd { 361 __le16 high_pkt; 362 __le16 low_pkt; 363 u8 rsv[20]; 364 }; 365 366 #define HCLGE_PF_STATE_DONE_B 0 367 #define HCLGE_PF_STATE_MAIN_B 1 368 #define HCLGE_PF_STATE_BOND_B 2 369 #define HCLGE_PF_STATE_MAC_N_B 6 370 #define HCLGE_PF_MAC_NUM_MASK 0x3 371 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 372 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 373 struct hclge_func_status_cmd { 374 __le32 vf_rst_state[4]; 375 u8 pf_state; 376 u8 mac_id; 377 u8 rsv1; 378 u8 pf_cnt_in_mac; 379 u8 pf_num; 380 u8 vf_num; 381 u8 rsv[2]; 382 }; 383 384 struct hclge_pf_res_cmd { 385 __le16 tqp_num; 386 __le16 buf_size; 387 __le16 msixcap_localid_ba_nic; 388 __le16 msixcap_localid_ba_rocee; 389 #define HCLGE_MSIX_OFT_ROCEE_S 0 390 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) 391 #define HCLGE_PF_VEC_NUM_S 0 392 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) 393 __le16 pf_intr_vector_number; 394 __le16 pf_own_fun_number; 395 __le32 rsv[3]; 396 }; 397 398 #define HCLGE_CFG_OFFSET_S 0 399 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 400 #define HCLGE_CFG_RD_LEN_S 24 401 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 402 #define HCLGE_CFG_RD_LEN_BYTES 16 403 #define HCLGE_CFG_RD_LEN_UNIT 4 404 405 #define HCLGE_CFG_VMDQ_S 0 406 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 407 #define HCLGE_CFG_TC_NUM_S 8 408 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 409 #define HCLGE_CFG_TQP_DESC_N_S 16 410 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 411 #define HCLGE_CFG_PHY_ADDR_S 0 412 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 413 #define HCLGE_CFG_MEDIA_TP_S 8 414 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 415 #define HCLGE_CFG_RX_BUF_LEN_S 16 416 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 417 #define HCLGE_CFG_MAC_ADDR_H_S 0 418 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 419 #define HCLGE_CFG_DEFAULT_SPEED_S 16 420 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 421 #define HCLGE_CFG_RSS_SIZE_S 24 422 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 423 #define HCLGE_CFG_SPEED_ABILITY_S 0 424 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 425 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 426 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 427 428 struct hclge_cfg_param_cmd { 429 __le32 offset; 430 __le32 rsv; 431 __le32 param[4]; 432 }; 433 434 #define HCLGE_MAC_MODE 0x0 435 #define HCLGE_DESC_NUM 0x40 436 437 #define HCLGE_ALLOC_VALID_B 0 438 struct hclge_vf_num_cmd { 439 u8 alloc_valid; 440 u8 rsv[23]; 441 }; 442 443 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 444 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 445 #define HCLGE_RSS_HASH_KEY_NUM 16 446 struct hclge_rss_config_cmd { 447 u8 hash_config; 448 u8 rsv[7]; 449 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 450 }; 451 452 struct hclge_rss_input_tuple_cmd { 453 u8 ipv4_tcp_en; 454 u8 ipv4_udp_en; 455 u8 ipv4_sctp_en; 456 u8 ipv4_fragment_en; 457 u8 ipv6_tcp_en; 458 u8 ipv6_udp_en; 459 u8 ipv6_sctp_en; 460 u8 ipv6_fragment_en; 461 u8 rsv[16]; 462 }; 463 464 #define HCLGE_RSS_CFG_TBL_SIZE 16 465 466 struct hclge_rss_indirection_table_cmd { 467 __le16 start_table_index; 468 __le16 rss_set_bitmap; 469 u8 rsv[4]; 470 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 471 }; 472 473 #define HCLGE_RSS_TC_OFFSET_S 0 474 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 475 #define HCLGE_RSS_TC_SIZE_S 12 476 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 477 #define HCLGE_RSS_TC_VALID_B 15 478 struct hclge_rss_tc_mode_cmd { 479 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 480 u8 rsv[8]; 481 }; 482 483 #define HCLGE_LINK_STATUS_UP_B 0 484 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 485 struct hclge_link_status_cmd { 486 u8 status; 487 u8 rsv[23]; 488 }; 489 490 struct hclge_promisc_param { 491 u8 vf_id; 492 u8 enable; 493 }; 494 495 #define HCLGE_PROMISC_TX_EN_B BIT(4) 496 #define HCLGE_PROMISC_RX_EN_B BIT(5) 497 #define HCLGE_PROMISC_EN_B 1 498 #define HCLGE_PROMISC_EN_ALL 0x7 499 #define HCLGE_PROMISC_EN_UC 0x1 500 #define HCLGE_PROMISC_EN_MC 0x2 501 #define HCLGE_PROMISC_EN_BC 0x4 502 struct hclge_promisc_cfg_cmd { 503 u8 flag; 504 u8 vf_id; 505 __le16 rsv0; 506 u8 rsv1[20]; 507 }; 508 509 enum hclge_promisc_type { 510 HCLGE_UNICAST = 1, 511 HCLGE_MULTICAST = 2, 512 HCLGE_BROADCAST = 3, 513 }; 514 515 #define HCLGE_MAC_TX_EN_B 6 516 #define HCLGE_MAC_RX_EN_B 7 517 #define HCLGE_MAC_PAD_TX_B 11 518 #define HCLGE_MAC_PAD_RX_B 12 519 #define HCLGE_MAC_1588_TX_B 13 520 #define HCLGE_MAC_1588_RX_B 14 521 #define HCLGE_MAC_APP_LP_B 15 522 #define HCLGE_MAC_LINE_LP_B 16 523 #define HCLGE_MAC_FCS_TX_B 17 524 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 525 #define HCLGE_MAC_RX_FCS_STRIP_B 19 526 #define HCLGE_MAC_RX_FCS_B 20 527 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 528 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 529 530 struct hclge_config_mac_mode_cmd { 531 __le32 txrx_pad_fcs_loop_en; 532 u8 rsv[20]; 533 }; 534 535 #define HCLGE_CFG_SPEED_S 0 536 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 537 538 #define HCLGE_CFG_DUPLEX_B 7 539 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 540 541 struct hclge_config_mac_speed_dup_cmd { 542 u8 speed_dup; 543 544 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 545 u8 mac_change_fec_en; 546 u8 rsv[22]; 547 }; 548 549 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 550 #define HCLGE_TQP_ENABLE_B 0 551 552 #define HCLGE_MAC_CFG_AN_EN_B 0 553 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 554 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 555 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 556 #define HCLGE_MAC_CFG_AN_RST_B 4 557 558 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 559 560 struct hclge_config_auto_neg_cmd { 561 __le32 cfg_an_cmd_flag; 562 u8 rsv[20]; 563 }; 564 565 struct hclge_sfp_speed_cmd { 566 __le32 sfp_speed; 567 u32 rsv[5]; 568 }; 569 570 #define HCLGE_MAC_UPLINK_PORT 0x100 571 572 struct hclge_config_max_frm_size_cmd { 573 __le16 max_frm_size; 574 u8 min_frm_size; 575 u8 rsv[21]; 576 }; 577 578 enum hclge_mac_vlan_tbl_opcode { 579 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 580 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 581 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 582 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 583 }; 584 585 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 586 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 587 #define HCLGE_MAC_EPORT_SW_EN_B 12 588 #define HCLGE_MAC_EPORT_TYPE_B 11 589 #define HCLGE_MAC_EPORT_VFID_S 3 590 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 591 #define HCLGE_MAC_EPORT_PFID_S 0 592 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 593 struct hclge_mac_vlan_tbl_entry_cmd { 594 u8 flags; 595 u8 resp_code; 596 __le16 vlan_tag; 597 __le32 mac_addr_hi32; 598 __le16 mac_addr_lo16; 599 __le16 rsv1; 600 u8 entry_type; 601 u8 mc_mac_en; 602 __le16 egress_port; 603 __le16 egress_queue; 604 u8 rsv2[6]; 605 }; 606 607 #define HCLGE_UMV_SPC_ALC_B 0 608 struct hclge_umv_spc_alc_cmd { 609 u8 allocate; 610 u8 rsv1[3]; 611 __le32 space_size; 612 u8 rsv2[16]; 613 }; 614 615 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 616 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 617 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 618 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc 619 620 struct hclge_mac_mgr_tbl_entry_cmd { 621 u8 flags; 622 u8 resp_code; 623 __le16 vlan_tag; 624 __le32 mac_addr_hi32; 625 __le16 mac_addr_lo16; 626 __le16 rsv1; 627 __le16 ethter_type; 628 __le16 egress_port; 629 __le16 egress_queue; 630 u8 sw_port_id_aware; 631 u8 rsv2; 632 u8 i_port_bitmap; 633 u8 i_port_direction; 634 u8 rsv3[2]; 635 }; 636 637 struct hclge_mac_vlan_add_cmd { 638 __le16 flags; 639 __le16 mac_addr_hi16; 640 __le32 mac_addr_lo32; 641 __le32 mac_addr_msk_hi32; 642 __le16 mac_addr_msk_lo16; 643 __le16 vlan_tag; 644 __le16 ingress_port; 645 __le16 egress_port; 646 u8 rsv[4]; 647 }; 648 649 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 650 struct hclge_mac_vlan_remove_cmd { 651 __le16 flags; 652 __le16 mac_addr_hi16; 653 __le32 mac_addr_lo32; 654 __le32 mac_addr_msk_hi32; 655 __le16 mac_addr_msk_lo16; 656 __le16 vlan_tag; 657 __le16 ingress_port; 658 __le16 egress_port; 659 u8 rsv[4]; 660 }; 661 662 struct hclge_vlan_filter_ctrl_cmd { 663 u8 vlan_type; 664 u8 vlan_fe; 665 u8 rsv[22]; 666 }; 667 668 struct hclge_vlan_filter_pf_cfg_cmd { 669 u8 vlan_offset; 670 u8 vlan_cfg; 671 u8 rsv[2]; 672 u8 vlan_offset_bitmap[20]; 673 }; 674 675 struct hclge_vlan_filter_vf_cfg_cmd { 676 __le16 vlan_id; 677 u8 resp_code; 678 u8 rsv; 679 u8 vlan_cfg; 680 u8 rsv1[3]; 681 u8 vf_bitmap[16]; 682 }; 683 684 #define HCLGE_ACCEPT_TAG1_B 0 685 #define HCLGE_ACCEPT_UNTAG1_B 1 686 #define HCLGE_PORT_INS_TAG1_EN_B 2 687 #define HCLGE_PORT_INS_TAG2_EN_B 3 688 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 689 #define HCLGE_ACCEPT_TAG2_B 5 690 #define HCLGE_ACCEPT_UNTAG2_B 6 691 692 struct hclge_vport_vtag_tx_cfg_cmd { 693 u8 vport_vlan_cfg; 694 u8 vf_offset; 695 u8 rsv1[2]; 696 __le16 def_vlan_tag1; 697 __le16 def_vlan_tag2; 698 u8 vf_bitmap[8]; 699 u8 rsv2[8]; 700 }; 701 702 #define HCLGE_REM_TAG1_EN_B 0 703 #define HCLGE_REM_TAG2_EN_B 1 704 #define HCLGE_SHOW_TAG1_EN_B 2 705 #define HCLGE_SHOW_TAG2_EN_B 3 706 struct hclge_vport_vtag_rx_cfg_cmd { 707 u8 vport_vlan_cfg; 708 u8 vf_offset; 709 u8 rsv1[6]; 710 u8 vf_bitmap[8]; 711 u8 rsv2[8]; 712 }; 713 714 struct hclge_tx_vlan_type_cfg_cmd { 715 __le16 ot_vlan_type; 716 __le16 in_vlan_type; 717 u8 rsv[20]; 718 }; 719 720 struct hclge_rx_vlan_type_cfg_cmd { 721 __le16 ot_fst_vlan_type; 722 __le16 ot_sec_vlan_type; 723 __le16 in_fst_vlan_type; 724 __le16 in_sec_vlan_type; 725 u8 rsv[16]; 726 }; 727 728 struct hclge_cfg_com_tqp_queue_cmd { 729 __le16 tqp_id; 730 __le16 stream_id; 731 u8 enable; 732 u8 rsv[19]; 733 }; 734 735 struct hclge_cfg_tx_queue_pointer_cmd { 736 __le16 tqp_id; 737 __le16 tx_tail; 738 __le16 tx_head; 739 __le16 fbd_num; 740 __le16 ring_offset; 741 u8 rsv[14]; 742 }; 743 744 #define HCLGE_TSO_MSS_MIN_S 0 745 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 746 747 #define HCLGE_TSO_MSS_MAX_S 16 748 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 749 750 struct hclge_cfg_tso_status_cmd { 751 __le16 tso_mss_min; 752 __le16 tso_mss_max; 753 u8 rsv[20]; 754 }; 755 756 #define HCLGE_GRO_EN_B 0 757 struct hclge_cfg_gro_status_cmd { 758 __le16 gro_en; 759 u8 rsv[22]; 760 }; 761 762 #define HCLGE_TSO_MSS_MIN 256 763 #define HCLGE_TSO_MSS_MAX 9668 764 765 #define HCLGE_TQP_RESET_B 0 766 struct hclge_reset_tqp_queue_cmd { 767 __le16 tqp_id; 768 u8 reset_req; 769 u8 ready_to_reset; 770 u8 rsv[20]; 771 }; 772 773 #define HCLGE_CFG_RESET_MAC_B 3 774 #define HCLGE_CFG_RESET_FUNC_B 7 775 struct hclge_reset_cmd { 776 u8 mac_func_reset; 777 u8 fun_reset_vfid; 778 u8 rsv[22]; 779 }; 780 781 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 782 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 783 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 784 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 785 struct hclge_serdes_lb_cmd { 786 u8 mask; 787 u8 enable; 788 u8 result; 789 u8 rsv[21]; 790 }; 791 792 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 793 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 794 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 795 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 796 797 #define HCLGE_TYPE_CRQ 0 798 #define HCLGE_TYPE_CSQ 1 799 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 800 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 801 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 802 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 803 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 804 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 805 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 806 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 807 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 808 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 809 #define HCLGE_NIC_CMQ_EN_B 16 810 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 811 #define HCLGE_NIC_CMQ_DESC_NUM 1024 812 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 813 814 #define HCLGE_LED_LOCATE_STATE_S 0 815 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 816 817 struct hclge_set_led_state_cmd { 818 u8 rsv1[3]; 819 u8 locate_led_config; 820 u8 rsv2[20]; 821 }; 822 823 struct hclge_get_fd_mode_cmd { 824 u8 mode; 825 u8 enable; 826 u8 rsv[22]; 827 }; 828 829 struct hclge_get_fd_allocation_cmd { 830 __le32 stage1_entry_num; 831 __le32 stage2_entry_num; 832 __le16 stage1_counter_num; 833 __le16 stage2_counter_num; 834 u8 rsv[12]; 835 }; 836 837 struct hclge_set_fd_key_config_cmd { 838 u8 stage; 839 u8 key_select; 840 u8 inner_sipv6_word_en; 841 u8 inner_dipv6_word_en; 842 u8 outer_sipv6_word_en; 843 u8 outer_dipv6_word_en; 844 u8 rsv1[2]; 845 __le32 tuple_mask; 846 __le32 meta_data_mask; 847 u8 rsv2[8]; 848 }; 849 850 #define HCLGE_FD_EPORT_SW_EN_B 0 851 struct hclge_fd_tcam_config_1_cmd { 852 u8 stage; 853 u8 xy_sel; 854 u8 port_info; 855 u8 rsv1[1]; 856 __le32 index; 857 u8 entry_vld; 858 u8 rsv2[7]; 859 u8 tcam_data[8]; 860 }; 861 862 struct hclge_fd_tcam_config_2_cmd { 863 u8 tcam_data[24]; 864 }; 865 866 struct hclge_fd_tcam_config_3_cmd { 867 u8 tcam_data[20]; 868 u8 rsv[4]; 869 }; 870 871 #define HCLGE_FD_AD_DROP_B 0 872 #define HCLGE_FD_AD_DIRECT_QID_B 1 873 #define HCLGE_FD_AD_QID_S 2 874 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 875 #define HCLGE_FD_AD_USE_COUNTER_B 12 876 #define HCLGE_FD_AD_COUNTER_NUM_S 13 877 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 878 #define HCLGE_FD_AD_NXT_STEP_B 20 879 #define HCLGE_FD_AD_NXT_KEY_S 21 880 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 881 #define HCLGE_FD_AD_WR_RULE_ID_B 0 882 #define HCLGE_FD_AD_RULE_ID_S 1 883 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 884 885 struct hclge_fd_ad_config_cmd { 886 u8 stage; 887 u8 rsv1[3]; 888 __le32 index; 889 __le64 ad_data; 890 u8 rsv2[8]; 891 }; 892 893 int hclge_cmd_init(struct hclge_dev *hdev); 894 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 895 { 896 writel(value, base + reg); 897 } 898 899 #define hclge_write_dev(a, reg, value) \ 900 hclge_write_reg((a)->io_base, (reg), (value)) 901 #define hclge_read_dev(a, reg) \ 902 hclge_read_reg((a)->io_base, (reg)) 903 904 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 905 { 906 u8 __iomem *reg_addr = READ_ONCE(base); 907 908 return readl(reg_addr + reg); 909 } 910 911 #define HCLGE_SEND_SYNC(flag) \ 912 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 913 914 struct hclge_hw; 915 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 916 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 917 enum hclge_opcode_type opcode, bool is_read); 918 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 919 920 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 921 struct hclge_promisc_param *param); 922 923 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 924 struct hclge_desc *desc); 925 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 926 struct hclge_desc *desc); 927 928 void hclge_destroy_cmd_queue(struct hclge_hw *hw); 929 int hclge_cmd_queue_init(struct hclge_dev *hdev); 930 #endif 931