1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 9 #define HCLGE_CMDQ_TX_TIMEOUT 30000 10 11 struct hclge_dev; 12 struct hclge_desc { 13 __le16 opcode; 14 15 #define HCLGE_CMDQ_RX_INVLD_B 0 16 #define HCLGE_CMDQ_RX_OUTVLD_B 1 17 18 __le16 flag; 19 __le16 retval; 20 __le16 rsv; 21 __le32 data[6]; 22 }; 23 24 struct hclge_cmq_ring { 25 dma_addr_t desc_dma_addr; 26 struct hclge_desc *desc; 27 struct hclge_dev *dev; 28 u32 head; 29 u32 tail; 30 31 u16 buf_size; 32 u16 desc_num; 33 int next_to_use; 34 int next_to_clean; 35 u8 ring_type; /* cmq ring type */ 36 spinlock_t lock; /* Command queue lock */ 37 }; 38 39 enum hclge_cmd_return_status { 40 HCLGE_CMD_EXEC_SUCCESS = 0, 41 HCLGE_CMD_NO_AUTH = 1, 42 HCLGE_CMD_NOT_SUPPORTED = 2, 43 HCLGE_CMD_QUEUE_FULL = 3, 44 }; 45 46 enum hclge_cmd_status { 47 HCLGE_STATUS_SUCCESS = 0, 48 HCLGE_ERR_CSQ_FULL = -1, 49 HCLGE_ERR_CSQ_TIMEOUT = -2, 50 HCLGE_ERR_CSQ_ERROR = -3, 51 }; 52 53 struct hclge_misc_vector { 54 u8 __iomem *addr; 55 int vector_irq; 56 }; 57 58 struct hclge_cmq { 59 struct hclge_cmq_ring csq; 60 struct hclge_cmq_ring crq; 61 u16 tx_timeout; 62 enum hclge_cmd_status last_status; 63 }; 64 65 #define HCLGE_CMD_FLAG_IN BIT(0) 66 #define HCLGE_CMD_FLAG_OUT BIT(1) 67 #define HCLGE_CMD_FLAG_NEXT BIT(2) 68 #define HCLGE_CMD_FLAG_WR BIT(3) 69 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 71 72 enum hclge_opcode_type { 73 /* Generic commands */ 74 HCLGE_OPC_QUERY_FW_VER = 0x0001, 75 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 76 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 77 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 78 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 79 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 80 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 81 82 HCLGE_OPC_STATS_64_BIT = 0x0030, 83 HCLGE_OPC_STATS_32_BIT = 0x0031, 84 HCLGE_OPC_STATS_MAC = 0x0032, 85 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 86 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 87 88 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 89 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 90 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 91 HCLGE_OPC_DFX_BD_NUM = 0x0043, 92 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 93 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 94 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 95 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 96 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 97 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 98 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 99 HCLGE_OPC_DFX_RTC_REG = 0x004B, 100 HCLGE_OPC_DFX_PPP_REG = 0x004C, 101 HCLGE_OPC_DFX_RCB_REG = 0x004D, 102 HCLGE_OPC_DFX_TQP_REG = 0x004E, 103 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 104 HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050, 105 106 /* MAC command */ 107 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 108 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 109 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 110 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 111 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 112 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 113 114 /* PFC/Pause commands */ 115 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 116 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 117 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 118 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 119 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 120 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 121 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 122 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 123 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 124 HCLGE_OPC_QOS_MAP = 0x070A, 125 126 /* ETS/scheduler commands */ 127 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 128 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 129 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 130 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 131 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 132 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 133 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 134 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 135 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 136 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 137 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 138 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 139 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 140 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 141 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 142 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 143 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 144 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 145 HCLGE_OPC_QSET_DFX_STS = 0x0844, 146 HCLGE_OPC_PRI_DFX_STS = 0x0845, 147 HCLGE_OPC_PG_DFX_STS = 0x0846, 148 HCLGE_OPC_PORT_DFX_STS = 0x0847, 149 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 150 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 151 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 152 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 153 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 154 155 /* Packet buffer allocate commands */ 156 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 157 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 158 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 159 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 160 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 161 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 162 163 /* TQP management command */ 164 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 165 166 /* TQP commands */ 167 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 168 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 169 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 170 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 171 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 172 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 173 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 174 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 175 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 176 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 177 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 178 179 /* TSO command */ 180 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 181 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 182 183 /* RSS commands */ 184 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 185 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 186 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 187 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 188 189 /* Promisuous mode command */ 190 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 191 192 /* Vlan offload commands */ 193 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 194 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 195 196 /* Interrupts commands */ 197 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 198 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 199 200 /* MAC commands */ 201 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 202 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 203 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 204 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 205 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 206 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 207 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 208 209 /* VLAN commands */ 210 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 211 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 212 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 213 214 /* Flow Director commands */ 215 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 216 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 217 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 218 HCLGE_OPC_FD_TCAM_OP = 0x1203, 219 HCLGE_OPC_FD_AD_OP = 0x1204, 220 221 /* MDIO command */ 222 HCLGE_OPC_MDIO_CONFIG = 0x1900, 223 224 /* QCN commands */ 225 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 226 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 227 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 228 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 229 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 230 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 231 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 232 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 233 234 /* Mailbox command */ 235 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 236 237 /* Led command */ 238 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 239 240 /* SFP command */ 241 HCLGE_OPC_SFP_GET_SPEED = 0x7104, 242 243 /* Error INT commands */ 244 HCLGE_MAC_COMMON_INT_EN = 0x030E, 245 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 246 HCLGE_SSU_ECC_INT_CMD = 0x0989, 247 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 248 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 249 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 250 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 251 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 252 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 253 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 254 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 255 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 256 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 257 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 258 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 259 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 260 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 261 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 262 HCLGE_IGU_COMMON_INT_EN = 0x1806, 263 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 264 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 265 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 266 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 267 HCLGE_NCSI_INT_EN = 0x2401, 268 }; 269 270 #define HCLGE_TQP_REG_OFFSET 0x80000 271 #define HCLGE_TQP_REG_SIZE 0x200 272 273 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 274 #define HCLGE_RCB_INIT_FLAG_EN_B 0 275 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 276 struct hclge_config_rcb_init_cmd { 277 __le16 rcb_init_flag; 278 u8 rsv[22]; 279 }; 280 281 struct hclge_tqp_map_cmd { 282 __le16 tqp_id; /* Absolute tqp id for in this pf */ 283 u8 tqp_vf; /* VF id */ 284 #define HCLGE_TQP_MAP_TYPE_PF 0 285 #define HCLGE_TQP_MAP_TYPE_VF 1 286 #define HCLGE_TQP_MAP_TYPE_B 0 287 #define HCLGE_TQP_MAP_EN_B 1 288 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 289 __le16 tqp_vid; /* Virtual id in this pf/vf */ 290 u8 rsv[18]; 291 }; 292 293 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 294 295 enum hclge_int_type { 296 HCLGE_INT_TX, 297 HCLGE_INT_RX, 298 HCLGE_INT_EVENT, 299 }; 300 301 struct hclge_ctrl_vector_chain_cmd { 302 u8 int_vector_id; 303 u8 int_cause_num; 304 #define HCLGE_INT_TYPE_S 0 305 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 306 #define HCLGE_TQP_ID_S 2 307 #define HCLGE_TQP_ID_M GENMASK(12, 2) 308 #define HCLGE_INT_GL_IDX_S 13 309 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 310 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 311 u8 vfid; 312 u8 rsv; 313 }; 314 315 #define HCLGE_MAX_TC_NUM 8 316 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 317 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 318 struct hclge_tx_buff_alloc_cmd { 319 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 320 u8 tx_buff_rsv[8]; 321 }; 322 323 struct hclge_rx_priv_buff_cmd { 324 __le16 buf_num[HCLGE_MAX_TC_NUM]; 325 __le16 shared_buf; 326 u8 rsv[6]; 327 }; 328 329 struct hclge_query_version_cmd { 330 __le32 firmware; 331 __le32 firmware_rsv[5]; 332 }; 333 334 #define HCLGE_RX_PRIV_EN_B 15 335 #define HCLGE_TC_NUM_ONE_DESC 4 336 struct hclge_priv_wl { 337 __le16 high; 338 __le16 low; 339 }; 340 341 struct hclge_rx_priv_wl_buf { 342 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 343 }; 344 345 struct hclge_rx_com_thrd { 346 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 347 }; 348 349 struct hclge_rx_com_wl { 350 struct hclge_priv_wl com_wl; 351 }; 352 353 struct hclge_waterline { 354 u32 low; 355 u32 high; 356 }; 357 358 struct hclge_tc_thrd { 359 u32 low; 360 u32 high; 361 }; 362 363 struct hclge_priv_buf { 364 struct hclge_waterline wl; /* Waterline for low and high*/ 365 u32 buf_size; /* TC private buffer size */ 366 u32 tx_buf_size; 367 u32 enable; /* Enable TC private buffer or not */ 368 }; 369 370 struct hclge_shared_buf { 371 struct hclge_waterline self; 372 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 373 u32 buf_size; 374 }; 375 376 struct hclge_pkt_buf_alloc { 377 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 378 struct hclge_shared_buf s_buf; 379 }; 380 381 #define HCLGE_RX_COM_WL_EN_B 15 382 struct hclge_rx_com_wl_buf_cmd { 383 __le16 high_wl; 384 __le16 low_wl; 385 u8 rsv[20]; 386 }; 387 388 #define HCLGE_RX_PKT_EN_B 15 389 struct hclge_rx_pkt_buf_cmd { 390 __le16 high_pkt; 391 __le16 low_pkt; 392 u8 rsv[20]; 393 }; 394 395 #define HCLGE_PF_STATE_DONE_B 0 396 #define HCLGE_PF_STATE_MAIN_B 1 397 #define HCLGE_PF_STATE_BOND_B 2 398 #define HCLGE_PF_STATE_MAC_N_B 6 399 #define HCLGE_PF_MAC_NUM_MASK 0x3 400 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 401 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 402 struct hclge_func_status_cmd { 403 __le32 vf_rst_state[4]; 404 u8 pf_state; 405 u8 mac_id; 406 u8 rsv1; 407 u8 pf_cnt_in_mac; 408 u8 pf_num; 409 u8 vf_num; 410 u8 rsv[2]; 411 }; 412 413 struct hclge_pf_res_cmd { 414 __le16 tqp_num; 415 __le16 buf_size; 416 __le16 msixcap_localid_ba_nic; 417 __le16 msixcap_localid_ba_rocee; 418 #define HCLGE_MSIX_OFT_ROCEE_S 0 419 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) 420 #define HCLGE_PF_VEC_NUM_S 0 421 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) 422 __le16 pf_intr_vector_number; 423 __le16 pf_own_fun_number; 424 __le16 tx_buf_size; 425 __le16 dv_buf_size; 426 __le32 rsv[2]; 427 }; 428 429 #define HCLGE_CFG_OFFSET_S 0 430 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 431 #define HCLGE_CFG_RD_LEN_S 24 432 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 433 #define HCLGE_CFG_RD_LEN_BYTES 16 434 #define HCLGE_CFG_RD_LEN_UNIT 4 435 436 #define HCLGE_CFG_VMDQ_S 0 437 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 438 #define HCLGE_CFG_TC_NUM_S 8 439 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 440 #define HCLGE_CFG_TQP_DESC_N_S 16 441 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 442 #define HCLGE_CFG_PHY_ADDR_S 0 443 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 444 #define HCLGE_CFG_MEDIA_TP_S 8 445 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 446 #define HCLGE_CFG_RX_BUF_LEN_S 16 447 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 448 #define HCLGE_CFG_MAC_ADDR_H_S 0 449 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 450 #define HCLGE_CFG_DEFAULT_SPEED_S 16 451 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 452 #define HCLGE_CFG_RSS_SIZE_S 24 453 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 454 #define HCLGE_CFG_SPEED_ABILITY_S 0 455 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 456 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 457 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 458 459 struct hclge_cfg_param_cmd { 460 __le32 offset; 461 __le32 rsv; 462 __le32 param[4]; 463 }; 464 465 #define HCLGE_MAC_MODE 0x0 466 #define HCLGE_DESC_NUM 0x40 467 468 #define HCLGE_ALLOC_VALID_B 0 469 struct hclge_vf_num_cmd { 470 u8 alloc_valid; 471 u8 rsv[23]; 472 }; 473 474 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 475 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 476 #define HCLGE_RSS_HASH_KEY_NUM 16 477 struct hclge_rss_config_cmd { 478 u8 hash_config; 479 u8 rsv[7]; 480 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 481 }; 482 483 struct hclge_rss_input_tuple_cmd { 484 u8 ipv4_tcp_en; 485 u8 ipv4_udp_en; 486 u8 ipv4_sctp_en; 487 u8 ipv4_fragment_en; 488 u8 ipv6_tcp_en; 489 u8 ipv6_udp_en; 490 u8 ipv6_sctp_en; 491 u8 ipv6_fragment_en; 492 u8 rsv[16]; 493 }; 494 495 #define HCLGE_RSS_CFG_TBL_SIZE 16 496 497 struct hclge_rss_indirection_table_cmd { 498 __le16 start_table_index; 499 __le16 rss_set_bitmap; 500 u8 rsv[4]; 501 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 502 }; 503 504 #define HCLGE_RSS_TC_OFFSET_S 0 505 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 506 #define HCLGE_RSS_TC_SIZE_S 12 507 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 508 #define HCLGE_RSS_TC_VALID_B 15 509 struct hclge_rss_tc_mode_cmd { 510 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 511 u8 rsv[8]; 512 }; 513 514 #define HCLGE_LINK_STATUS_UP_B 0 515 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 516 struct hclge_link_status_cmd { 517 u8 status; 518 u8 rsv[23]; 519 }; 520 521 struct hclge_promisc_param { 522 u8 vf_id; 523 u8 enable; 524 }; 525 526 #define HCLGE_PROMISC_TX_EN_B BIT(4) 527 #define HCLGE_PROMISC_RX_EN_B BIT(5) 528 #define HCLGE_PROMISC_EN_B 1 529 #define HCLGE_PROMISC_EN_ALL 0x7 530 #define HCLGE_PROMISC_EN_UC 0x1 531 #define HCLGE_PROMISC_EN_MC 0x2 532 #define HCLGE_PROMISC_EN_BC 0x4 533 struct hclge_promisc_cfg_cmd { 534 u8 flag; 535 u8 vf_id; 536 __le16 rsv0; 537 u8 rsv1[20]; 538 }; 539 540 enum hclge_promisc_type { 541 HCLGE_UNICAST = 1, 542 HCLGE_MULTICAST = 2, 543 HCLGE_BROADCAST = 3, 544 }; 545 546 #define HCLGE_MAC_TX_EN_B 6 547 #define HCLGE_MAC_RX_EN_B 7 548 #define HCLGE_MAC_PAD_TX_B 11 549 #define HCLGE_MAC_PAD_RX_B 12 550 #define HCLGE_MAC_1588_TX_B 13 551 #define HCLGE_MAC_1588_RX_B 14 552 #define HCLGE_MAC_APP_LP_B 15 553 #define HCLGE_MAC_LINE_LP_B 16 554 #define HCLGE_MAC_FCS_TX_B 17 555 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 556 #define HCLGE_MAC_RX_FCS_STRIP_B 19 557 #define HCLGE_MAC_RX_FCS_B 20 558 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 559 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 560 561 struct hclge_config_mac_mode_cmd { 562 __le32 txrx_pad_fcs_loop_en; 563 u8 rsv[20]; 564 }; 565 566 #define HCLGE_CFG_SPEED_S 0 567 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 568 569 #define HCLGE_CFG_DUPLEX_B 7 570 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 571 572 struct hclge_config_mac_speed_dup_cmd { 573 u8 speed_dup; 574 575 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 576 u8 mac_change_fec_en; 577 u8 rsv[22]; 578 }; 579 580 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 581 #define HCLGE_TQP_ENABLE_B 0 582 583 #define HCLGE_MAC_CFG_AN_EN_B 0 584 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 585 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 586 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 587 #define HCLGE_MAC_CFG_AN_RST_B 4 588 589 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 590 591 struct hclge_config_auto_neg_cmd { 592 __le32 cfg_an_cmd_flag; 593 u8 rsv[20]; 594 }; 595 596 struct hclge_sfp_speed_cmd { 597 __le32 sfp_speed; 598 u32 rsv[5]; 599 }; 600 601 #define HCLGE_MAC_UPLINK_PORT 0x100 602 603 struct hclge_config_max_frm_size_cmd { 604 __le16 max_frm_size; 605 u8 min_frm_size; 606 u8 rsv[21]; 607 }; 608 609 enum hclge_mac_vlan_tbl_opcode { 610 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 611 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 612 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 613 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 614 }; 615 616 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 617 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 618 #define HCLGE_MAC_EPORT_SW_EN_B 12 619 #define HCLGE_MAC_EPORT_TYPE_B 11 620 #define HCLGE_MAC_EPORT_VFID_S 3 621 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 622 #define HCLGE_MAC_EPORT_PFID_S 0 623 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 624 struct hclge_mac_vlan_tbl_entry_cmd { 625 u8 flags; 626 u8 resp_code; 627 __le16 vlan_tag; 628 __le32 mac_addr_hi32; 629 __le16 mac_addr_lo16; 630 __le16 rsv1; 631 u8 entry_type; 632 u8 mc_mac_en; 633 __le16 egress_port; 634 __le16 egress_queue; 635 u8 rsv2[6]; 636 }; 637 638 #define HCLGE_UMV_SPC_ALC_B 0 639 struct hclge_umv_spc_alc_cmd { 640 u8 allocate; 641 u8 rsv1[3]; 642 __le32 space_size; 643 u8 rsv2[16]; 644 }; 645 646 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 647 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 648 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 649 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc 650 651 struct hclge_mac_mgr_tbl_entry_cmd { 652 u8 flags; 653 u8 resp_code; 654 __le16 vlan_tag; 655 __le32 mac_addr_hi32; 656 __le16 mac_addr_lo16; 657 __le16 rsv1; 658 __le16 ethter_type; 659 __le16 egress_port; 660 __le16 egress_queue; 661 u8 sw_port_id_aware; 662 u8 rsv2; 663 u8 i_port_bitmap; 664 u8 i_port_direction; 665 u8 rsv3[2]; 666 }; 667 668 struct hclge_mac_vlan_add_cmd { 669 __le16 flags; 670 __le16 mac_addr_hi16; 671 __le32 mac_addr_lo32; 672 __le32 mac_addr_msk_hi32; 673 __le16 mac_addr_msk_lo16; 674 __le16 vlan_tag; 675 __le16 ingress_port; 676 __le16 egress_port; 677 u8 rsv[4]; 678 }; 679 680 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 681 struct hclge_mac_vlan_remove_cmd { 682 __le16 flags; 683 __le16 mac_addr_hi16; 684 __le32 mac_addr_lo32; 685 __le32 mac_addr_msk_hi32; 686 __le16 mac_addr_msk_lo16; 687 __le16 vlan_tag; 688 __le16 ingress_port; 689 __le16 egress_port; 690 u8 rsv[4]; 691 }; 692 693 struct hclge_vlan_filter_ctrl_cmd { 694 u8 vlan_type; 695 u8 vlan_fe; 696 u8 rsv[22]; 697 }; 698 699 struct hclge_vlan_filter_pf_cfg_cmd { 700 u8 vlan_offset; 701 u8 vlan_cfg; 702 u8 rsv[2]; 703 u8 vlan_offset_bitmap[20]; 704 }; 705 706 struct hclge_vlan_filter_vf_cfg_cmd { 707 __le16 vlan_id; 708 u8 resp_code; 709 u8 rsv; 710 u8 vlan_cfg; 711 u8 rsv1[3]; 712 u8 vf_bitmap[16]; 713 }; 714 715 #define HCLGE_ACCEPT_TAG1_B 0 716 #define HCLGE_ACCEPT_UNTAG1_B 1 717 #define HCLGE_PORT_INS_TAG1_EN_B 2 718 #define HCLGE_PORT_INS_TAG2_EN_B 3 719 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 720 #define HCLGE_ACCEPT_TAG2_B 5 721 #define HCLGE_ACCEPT_UNTAG2_B 6 722 723 struct hclge_vport_vtag_tx_cfg_cmd { 724 u8 vport_vlan_cfg; 725 u8 vf_offset; 726 u8 rsv1[2]; 727 __le16 def_vlan_tag1; 728 __le16 def_vlan_tag2; 729 u8 vf_bitmap[8]; 730 u8 rsv2[8]; 731 }; 732 733 #define HCLGE_REM_TAG1_EN_B 0 734 #define HCLGE_REM_TAG2_EN_B 1 735 #define HCLGE_SHOW_TAG1_EN_B 2 736 #define HCLGE_SHOW_TAG2_EN_B 3 737 struct hclge_vport_vtag_rx_cfg_cmd { 738 u8 vport_vlan_cfg; 739 u8 vf_offset; 740 u8 rsv1[6]; 741 u8 vf_bitmap[8]; 742 u8 rsv2[8]; 743 }; 744 745 struct hclge_tx_vlan_type_cfg_cmd { 746 __le16 ot_vlan_type; 747 __le16 in_vlan_type; 748 u8 rsv[20]; 749 }; 750 751 struct hclge_rx_vlan_type_cfg_cmd { 752 __le16 ot_fst_vlan_type; 753 __le16 ot_sec_vlan_type; 754 __le16 in_fst_vlan_type; 755 __le16 in_sec_vlan_type; 756 u8 rsv[16]; 757 }; 758 759 struct hclge_cfg_com_tqp_queue_cmd { 760 __le16 tqp_id; 761 __le16 stream_id; 762 u8 enable; 763 u8 rsv[19]; 764 }; 765 766 struct hclge_cfg_tx_queue_pointer_cmd { 767 __le16 tqp_id; 768 __le16 tx_tail; 769 __le16 tx_head; 770 __le16 fbd_num; 771 __le16 ring_offset; 772 u8 rsv[14]; 773 }; 774 775 #pragma pack(1) 776 struct hclge_mac_ethertype_idx_rd_cmd { 777 u8 flags; 778 u8 resp_code; 779 __le16 vlan_tag; 780 u8 mac_add[6]; 781 __le16 index; 782 __le16 ethter_type; 783 __le16 egress_port; 784 __le16 egress_queue; 785 __le16 rev0; 786 u8 i_port_bitmap; 787 u8 i_port_direction; 788 u8 rev1[2]; 789 }; 790 791 #pragma pack() 792 793 #define HCLGE_TSO_MSS_MIN_S 0 794 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 795 796 #define HCLGE_TSO_MSS_MAX_S 16 797 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 798 799 struct hclge_cfg_tso_status_cmd { 800 __le16 tso_mss_min; 801 __le16 tso_mss_max; 802 u8 rsv[20]; 803 }; 804 805 #define HCLGE_GRO_EN_B 0 806 struct hclge_cfg_gro_status_cmd { 807 __le16 gro_en; 808 u8 rsv[22]; 809 }; 810 811 #define HCLGE_TSO_MSS_MIN 256 812 #define HCLGE_TSO_MSS_MAX 9668 813 814 #define HCLGE_TQP_RESET_B 0 815 struct hclge_reset_tqp_queue_cmd { 816 __le16 tqp_id; 817 u8 reset_req; 818 u8 ready_to_reset; 819 u8 rsv[20]; 820 }; 821 822 #define HCLGE_CFG_RESET_MAC_B 3 823 #define HCLGE_CFG_RESET_FUNC_B 7 824 struct hclge_reset_cmd { 825 u8 mac_func_reset; 826 u8 fun_reset_vfid; 827 u8 rsv[22]; 828 }; 829 830 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 831 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 832 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 833 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 834 struct hclge_serdes_lb_cmd { 835 u8 mask; 836 u8 enable; 837 u8 result; 838 u8 rsv[21]; 839 }; 840 841 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 842 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 843 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 844 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 845 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x200 /* 512 byte */ 846 847 #define HCLGE_TYPE_CRQ 0 848 #define HCLGE_TYPE_CSQ 1 849 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 850 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 851 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 852 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 853 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 854 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 855 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 856 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 857 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 858 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 859 #define HCLGE_NIC_CMQ_EN_B 16 860 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 861 #define HCLGE_NIC_CMQ_DESC_NUM 1024 862 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 863 864 #define HCLGE_LED_LOCATE_STATE_S 0 865 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 866 867 struct hclge_set_led_state_cmd { 868 u8 rsv1[3]; 869 u8 locate_led_config; 870 u8 rsv2[20]; 871 }; 872 873 struct hclge_get_fd_mode_cmd { 874 u8 mode; 875 u8 enable; 876 u8 rsv[22]; 877 }; 878 879 struct hclge_get_fd_allocation_cmd { 880 __le32 stage1_entry_num; 881 __le32 stage2_entry_num; 882 __le16 stage1_counter_num; 883 __le16 stage2_counter_num; 884 u8 rsv[12]; 885 }; 886 887 struct hclge_set_fd_key_config_cmd { 888 u8 stage; 889 u8 key_select; 890 u8 inner_sipv6_word_en; 891 u8 inner_dipv6_word_en; 892 u8 outer_sipv6_word_en; 893 u8 outer_dipv6_word_en; 894 u8 rsv1[2]; 895 __le32 tuple_mask; 896 __le32 meta_data_mask; 897 u8 rsv2[8]; 898 }; 899 900 #define HCLGE_FD_EPORT_SW_EN_B 0 901 struct hclge_fd_tcam_config_1_cmd { 902 u8 stage; 903 u8 xy_sel; 904 u8 port_info; 905 u8 rsv1[1]; 906 __le32 index; 907 u8 entry_vld; 908 u8 rsv2[7]; 909 u8 tcam_data[8]; 910 }; 911 912 struct hclge_fd_tcam_config_2_cmd { 913 u8 tcam_data[24]; 914 }; 915 916 struct hclge_fd_tcam_config_3_cmd { 917 u8 tcam_data[20]; 918 u8 rsv[4]; 919 }; 920 921 #define HCLGE_FD_AD_DROP_B 0 922 #define HCLGE_FD_AD_DIRECT_QID_B 1 923 #define HCLGE_FD_AD_QID_S 2 924 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 925 #define HCLGE_FD_AD_USE_COUNTER_B 12 926 #define HCLGE_FD_AD_COUNTER_NUM_S 13 927 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 928 #define HCLGE_FD_AD_NXT_STEP_B 20 929 #define HCLGE_FD_AD_NXT_KEY_S 21 930 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 931 #define HCLGE_FD_AD_WR_RULE_ID_B 0 932 #define HCLGE_FD_AD_RULE_ID_S 1 933 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 934 935 struct hclge_fd_ad_config_cmd { 936 u8 stage; 937 u8 rsv1[3]; 938 __le32 index; 939 __le64 ad_data; 940 u8 rsv2[8]; 941 }; 942 943 int hclge_cmd_init(struct hclge_dev *hdev); 944 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 945 { 946 writel(value, base + reg); 947 } 948 949 #define hclge_write_dev(a, reg, value) \ 950 hclge_write_reg((a)->io_base, (reg), (value)) 951 #define hclge_read_dev(a, reg) \ 952 hclge_read_reg((a)->io_base, (reg)) 953 954 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 955 { 956 u8 __iomem *reg_addr = READ_ONCE(base); 957 958 return readl(reg_addr + reg); 959 } 960 961 #define HCLGE_SEND_SYNC(flag) \ 962 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 963 964 struct hclge_hw; 965 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 966 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 967 enum hclge_opcode_type opcode, bool is_read); 968 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 969 970 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 971 struct hclge_promisc_param *param); 972 973 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 974 struct hclge_desc *desc); 975 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 976 struct hclge_desc *desc); 977 978 void hclge_destroy_cmd_queue(struct hclge_hw *hw); 979 int hclge_cmd_queue_init(struct hclge_dev *hdev); 980 #endif 981