1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 #include <linux/etherdevice.h> 9 #include "hnae3.h" 10 11 #define HCLGE_CMDQ_TX_TIMEOUT 30000 12 #define HCLGE_DESC_DATA_LEN 6 13 14 struct hclge_dev; 15 struct hclge_desc { 16 __le16 opcode; 17 18 #define HCLGE_CMDQ_RX_INVLD_B 0 19 #define HCLGE_CMDQ_RX_OUTVLD_B 1 20 21 __le16 flag; 22 __le16 retval; 23 __le16 rsv; 24 __le32 data[HCLGE_DESC_DATA_LEN]; 25 }; 26 27 struct hclge_cmq_ring { 28 dma_addr_t desc_dma_addr; 29 struct hclge_desc *desc; 30 struct hclge_dev *dev; 31 u32 head; 32 u32 tail; 33 34 u16 buf_size; 35 u16 desc_num; 36 int next_to_use; 37 int next_to_clean; 38 u8 ring_type; /* cmq ring type */ 39 spinlock_t lock; /* Command queue lock */ 40 }; 41 42 enum hclge_cmd_return_status { 43 HCLGE_CMD_EXEC_SUCCESS = 0, 44 HCLGE_CMD_NO_AUTH = 1, 45 HCLGE_CMD_NOT_SUPPORTED = 2, 46 HCLGE_CMD_QUEUE_FULL = 3, 47 HCLGE_CMD_NEXT_ERR = 4, 48 HCLGE_CMD_UNEXE_ERR = 5, 49 HCLGE_CMD_PARA_ERR = 6, 50 HCLGE_CMD_RESULT_ERR = 7, 51 HCLGE_CMD_TIMEOUT = 8, 52 HCLGE_CMD_HILINK_ERR = 9, 53 HCLGE_CMD_QUEUE_ILLEGAL = 10, 54 HCLGE_CMD_INVALID = 11, 55 }; 56 57 enum hclge_cmd_status { 58 HCLGE_STATUS_SUCCESS = 0, 59 HCLGE_ERR_CSQ_FULL = -1, 60 HCLGE_ERR_CSQ_TIMEOUT = -2, 61 HCLGE_ERR_CSQ_ERROR = -3, 62 }; 63 64 struct hclge_misc_vector { 65 u8 __iomem *addr; 66 int vector_irq; 67 char name[HNAE3_INT_NAME_LEN]; 68 }; 69 70 struct hclge_cmq { 71 struct hclge_cmq_ring csq; 72 struct hclge_cmq_ring crq; 73 u16 tx_timeout; 74 enum hclge_cmd_status last_status; 75 }; 76 77 #define HCLGE_CMD_FLAG_IN BIT(0) 78 #define HCLGE_CMD_FLAG_OUT BIT(1) 79 #define HCLGE_CMD_FLAG_NEXT BIT(2) 80 #define HCLGE_CMD_FLAG_WR BIT(3) 81 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 83 84 enum hclge_opcode_type { 85 /* Generic commands */ 86 HCLGE_OPC_QUERY_FW_VER = 0x0001, 87 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 88 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 89 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 90 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 91 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 92 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 93 HCLGE_OPC_PF_RST_DONE = 0x0026, 94 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027, 95 96 HCLGE_OPC_STATS_64_BIT = 0x0030, 97 HCLGE_OPC_STATS_32_BIT = 0x0031, 98 HCLGE_OPC_STATS_MAC = 0x0032, 99 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 100 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 101 102 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 103 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 104 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 105 HCLGE_OPC_DFX_BD_NUM = 0x0043, 106 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 107 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 108 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 109 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 110 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 111 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 112 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 113 HCLGE_OPC_DFX_RTC_REG = 0x004B, 114 HCLGE_OPC_DFX_PPP_REG = 0x004C, 115 HCLGE_OPC_DFX_RCB_REG = 0x004D, 116 HCLGE_OPC_DFX_TQP_REG = 0x004E, 117 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 118 119 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050, 120 121 /* MAC command */ 122 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 123 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 124 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 125 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 126 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 127 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, 128 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, 129 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, 130 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 131 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, 132 133 /* PFC/Pause commands */ 134 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 135 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 136 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 137 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 138 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 139 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 140 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 141 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 142 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 143 HCLGE_OPC_QOS_MAP = 0x070A, 144 145 /* ETS/scheduler commands */ 146 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 147 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 148 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 149 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 150 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 151 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 152 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 153 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 154 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 155 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 156 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 157 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 158 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 159 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 160 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 161 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 162 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 163 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 164 HCLGE_OPC_QSET_DFX_STS = 0x0844, 165 HCLGE_OPC_PRI_DFX_STS = 0x0845, 166 HCLGE_OPC_PG_DFX_STS = 0x0846, 167 HCLGE_OPC_PORT_DFX_STS = 0x0847, 168 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 169 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 170 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 171 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 172 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 173 174 /* Packet buffer allocate commands */ 175 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 176 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 177 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 178 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 179 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 180 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 181 182 /* TQP management command */ 183 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 184 185 /* TQP commands */ 186 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 187 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 188 HCLGE_OPC_QUERY_TX_STATS = 0x0B03, 189 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 190 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 191 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 192 HCLGE_OPC_QUERY_RX_STATS = 0x0B13, 193 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 194 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 195 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 196 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 197 198 /* PPU commands */ 199 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A, 200 201 /* TSO command */ 202 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 203 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 204 205 /* RSS commands */ 206 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 207 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 208 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 209 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 210 211 /* Promisuous mode command */ 212 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 213 214 /* Vlan offload commands */ 215 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 216 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 217 218 /* Interrupts commands */ 219 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 220 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 221 222 /* MAC commands */ 223 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 224 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 225 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 226 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 227 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 228 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 229 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 230 231 /* MAC VLAN commands */ 232 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033, 233 234 /* VLAN commands */ 235 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 236 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 237 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 238 239 /* Flow Director commands */ 240 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 241 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 242 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 243 HCLGE_OPC_FD_TCAM_OP = 0x1203, 244 HCLGE_OPC_FD_AD_OP = 0x1204, 245 246 /* MDIO command */ 247 HCLGE_OPC_MDIO_CONFIG = 0x1900, 248 249 /* QCN commands */ 250 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 251 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 252 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03, 253 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 254 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 255 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 256 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 257 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 258 259 /* Mailbox command */ 260 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 261 262 /* Led command */ 263 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 264 265 /* NCL config command */ 266 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, 267 268 /* M7 stats command */ 269 HCLGE_OPC_M7_STATS_BD = 0x7012, 270 HCLGE_OPC_M7_STATS_INFO = 0x7013, 271 HCLGE_OPC_M7_COMPAT_CFG = 0x701A, 272 273 /* SFP command */ 274 HCLGE_OPC_GET_SFP_EEPROM = 0x7100, 275 HCLGE_OPC_GET_SFP_EXIST = 0x7101, 276 HCLGE_OPC_GET_SFP_INFO = 0x7104, 277 278 /* Error INT commands */ 279 HCLGE_MAC_COMMON_INT_EN = 0x030E, 280 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 281 HCLGE_SSU_ECC_INT_CMD = 0x0989, 282 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 283 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 284 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 285 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 286 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 287 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 288 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 289 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 290 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 291 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 292 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 293 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 294 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 295 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 296 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585, 297 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586, 298 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 299 HCLGE_IGU_COMMON_INT_EN = 0x1806, 300 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 301 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 302 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 303 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 304 HCLGE_NCSI_INT_EN = 0x2401, 305 }; 306 307 #define HCLGE_TQP_REG_OFFSET 0x80000 308 #define HCLGE_TQP_REG_SIZE 0x200 309 310 #define HCLGE_TQP_MAX_SIZE_DEV_V2 1024 311 #define HCLGE_TQP_EXT_REG_OFFSET 0x100 312 313 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 314 #define HCLGE_RCB_INIT_FLAG_EN_B 0 315 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 316 struct hclge_config_rcb_init_cmd { 317 __le16 rcb_init_flag; 318 u8 rsv[22]; 319 }; 320 321 struct hclge_tqp_map_cmd { 322 __le16 tqp_id; /* Absolute tqp id for in this pf */ 323 u8 tqp_vf; /* VF id */ 324 #define HCLGE_TQP_MAP_TYPE_PF 0 325 #define HCLGE_TQP_MAP_TYPE_VF 1 326 #define HCLGE_TQP_MAP_TYPE_B 0 327 #define HCLGE_TQP_MAP_EN_B 1 328 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 329 __le16 tqp_vid; /* Virtual id in this pf/vf */ 330 u8 rsv[18]; 331 }; 332 333 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 334 335 enum hclge_int_type { 336 HCLGE_INT_TX, 337 HCLGE_INT_RX, 338 HCLGE_INT_EVENT, 339 }; 340 341 struct hclge_ctrl_vector_chain_cmd { 342 #define HCLGE_VECTOR_ID_L_S 0 343 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0) 344 u8 int_vector_id_l; 345 u8 int_cause_num; 346 #define HCLGE_INT_TYPE_S 0 347 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 348 #define HCLGE_TQP_ID_S 2 349 #define HCLGE_TQP_ID_M GENMASK(12, 2) 350 #define HCLGE_INT_GL_IDX_S 13 351 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 352 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 353 u8 vfid; 354 #define HCLGE_VECTOR_ID_H_S 8 355 #define HCLGE_VECTOR_ID_H_M GENMASK(15, 8) 356 u8 int_vector_id_h; 357 }; 358 359 #define HCLGE_MAX_TC_NUM 8 360 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 361 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 362 struct hclge_tx_buff_alloc_cmd { 363 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 364 u8 tx_buff_rsv[8]; 365 }; 366 367 struct hclge_rx_priv_buff_cmd { 368 __le16 buf_num[HCLGE_MAX_TC_NUM]; 369 __le16 shared_buf; 370 u8 rsv[6]; 371 }; 372 373 enum HCLGE_CAP_BITS { 374 HCLGE_CAP_UDP_GSO_B, 375 HCLGE_CAP_QB_B, 376 HCLGE_CAP_FD_FORWARD_TC_B, 377 HCLGE_CAP_PTP_B, 378 HCLGE_CAP_INT_QL_B, 379 HCLGE_CAP_SIMPLE_BD_B, 380 HCLGE_CAP_TX_PUSH_B, 381 HCLGE_CAP_PHY_IMP_B, 382 HCLGE_CAP_TQP_TXRX_INDEP_B, 383 HCLGE_CAP_HW_PAD_B, 384 HCLGE_CAP_STASH_B, 385 }; 386 387 #define HCLGE_QUERY_CAP_LENGTH 3 388 struct hclge_query_version_cmd { 389 __le32 firmware; 390 __le32 hardware; 391 __le32 rsv; 392 __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */ 393 }; 394 395 #define HCLGE_RX_PRIV_EN_B 15 396 #define HCLGE_TC_NUM_ONE_DESC 4 397 struct hclge_priv_wl { 398 __le16 high; 399 __le16 low; 400 }; 401 402 struct hclge_rx_priv_wl_buf { 403 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 404 }; 405 406 struct hclge_rx_com_thrd { 407 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 408 }; 409 410 struct hclge_rx_com_wl { 411 struct hclge_priv_wl com_wl; 412 }; 413 414 struct hclge_waterline { 415 u32 low; 416 u32 high; 417 }; 418 419 struct hclge_tc_thrd { 420 u32 low; 421 u32 high; 422 }; 423 424 struct hclge_priv_buf { 425 struct hclge_waterline wl; /* Waterline for low and high*/ 426 u32 buf_size; /* TC private buffer size */ 427 u32 tx_buf_size; 428 u32 enable; /* Enable TC private buffer or not */ 429 }; 430 431 struct hclge_shared_buf { 432 struct hclge_waterline self; 433 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 434 u32 buf_size; 435 }; 436 437 struct hclge_pkt_buf_alloc { 438 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 439 struct hclge_shared_buf s_buf; 440 }; 441 442 #define HCLGE_RX_COM_WL_EN_B 15 443 struct hclge_rx_com_wl_buf_cmd { 444 __le16 high_wl; 445 __le16 low_wl; 446 u8 rsv[20]; 447 }; 448 449 #define HCLGE_RX_PKT_EN_B 15 450 struct hclge_rx_pkt_buf_cmd { 451 __le16 high_pkt; 452 __le16 low_pkt; 453 u8 rsv[20]; 454 }; 455 456 #define HCLGE_PF_STATE_DONE_B 0 457 #define HCLGE_PF_STATE_MAIN_B 1 458 #define HCLGE_PF_STATE_BOND_B 2 459 #define HCLGE_PF_STATE_MAC_N_B 6 460 #define HCLGE_PF_MAC_NUM_MASK 0x3 461 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 462 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 463 #define HCLGE_VF_RST_STATUS_CMD 4 464 465 struct hclge_func_status_cmd { 466 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD]; 467 u8 pf_state; 468 u8 mac_id; 469 u8 rsv1; 470 u8 pf_cnt_in_mac; 471 u8 pf_num; 472 u8 vf_num; 473 u8 rsv[2]; 474 }; 475 476 struct hclge_pf_res_cmd { 477 __le16 tqp_num; 478 __le16 buf_size; 479 __le16 msixcap_localid_ba_nic; 480 __le16 msixcap_localid_number_nic; 481 __le16 pf_intr_vector_number_roce; 482 __le16 pf_own_fun_number; 483 __le16 tx_buf_size; 484 __le16 dv_buf_size; 485 __le16 ext_tqp_num; 486 u8 rsv[6]; 487 }; 488 489 #define HCLGE_CFG_OFFSET_S 0 490 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 491 #define HCLGE_CFG_RD_LEN_S 24 492 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 493 #define HCLGE_CFG_RD_LEN_BYTES 16 494 #define HCLGE_CFG_RD_LEN_UNIT 4 495 496 #define HCLGE_CFG_VMDQ_S 0 497 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 498 #define HCLGE_CFG_TC_NUM_S 8 499 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 500 #define HCLGE_CFG_TQP_DESC_N_S 16 501 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 502 #define HCLGE_CFG_PHY_ADDR_S 0 503 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 504 #define HCLGE_CFG_MEDIA_TP_S 8 505 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 506 #define HCLGE_CFG_RX_BUF_LEN_S 16 507 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 508 #define HCLGE_CFG_MAC_ADDR_H_S 0 509 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 510 #define HCLGE_CFG_DEFAULT_SPEED_S 16 511 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 512 #define HCLGE_CFG_RSS_SIZE_S 24 513 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 514 #define HCLGE_CFG_SPEED_ABILITY_S 0 515 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 516 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10 517 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10) 518 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 519 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 520 521 #define HCLGE_CFG_CMD_CNT 4 522 523 struct hclge_cfg_param_cmd { 524 __le32 offset; 525 __le32 rsv; 526 __le32 param[HCLGE_CFG_CMD_CNT]; 527 }; 528 529 #define HCLGE_MAC_MODE 0x0 530 #define HCLGE_DESC_NUM 0x40 531 532 #define HCLGE_ALLOC_VALID_B 0 533 struct hclge_vf_num_cmd { 534 u8 alloc_valid; 535 u8 rsv[23]; 536 }; 537 538 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 539 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 540 #define HCLGE_RSS_HASH_KEY_NUM 16 541 struct hclge_rss_config_cmd { 542 u8 hash_config; 543 u8 rsv[7]; 544 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 545 }; 546 547 struct hclge_rss_input_tuple_cmd { 548 u8 ipv4_tcp_en; 549 u8 ipv4_udp_en; 550 u8 ipv4_sctp_en; 551 u8 ipv4_fragment_en; 552 u8 ipv6_tcp_en; 553 u8 ipv6_udp_en; 554 u8 ipv6_sctp_en; 555 u8 ipv6_fragment_en; 556 u8 rsv[16]; 557 }; 558 559 #define HCLGE_RSS_CFG_TBL_SIZE 16 560 561 struct hclge_rss_indirection_table_cmd { 562 __le16 start_table_index; 563 __le16 rss_set_bitmap; 564 u8 rsv[4]; 565 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 566 }; 567 568 #define HCLGE_RSS_TC_OFFSET_S 0 569 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 570 #define HCLGE_RSS_TC_SIZE_S 12 571 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 572 #define HCLGE_RSS_TC_VALID_B 15 573 struct hclge_rss_tc_mode_cmd { 574 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 575 u8 rsv[8]; 576 }; 577 578 #define HCLGE_LINK_STATUS_UP_B 0 579 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 580 struct hclge_link_status_cmd { 581 u8 status; 582 u8 rsv[23]; 583 }; 584 585 struct hclge_promisc_param { 586 u8 vf_id; 587 u8 enable; 588 }; 589 590 #define HCLGE_PROMISC_TX_EN_B BIT(4) 591 #define HCLGE_PROMISC_RX_EN_B BIT(5) 592 #define HCLGE_PROMISC_EN_B 1 593 #define HCLGE_PROMISC_EN_ALL 0x7 594 #define HCLGE_PROMISC_EN_UC 0x1 595 #define HCLGE_PROMISC_EN_MC 0x2 596 #define HCLGE_PROMISC_EN_BC 0x4 597 struct hclge_promisc_cfg_cmd { 598 u8 flag; 599 u8 vf_id; 600 __le16 rsv0; 601 u8 rsv1[20]; 602 }; 603 604 enum hclge_promisc_type { 605 HCLGE_UNICAST = 1, 606 HCLGE_MULTICAST = 2, 607 HCLGE_BROADCAST = 3, 608 }; 609 610 #define HCLGE_MAC_TX_EN_B 6 611 #define HCLGE_MAC_RX_EN_B 7 612 #define HCLGE_MAC_PAD_TX_B 11 613 #define HCLGE_MAC_PAD_RX_B 12 614 #define HCLGE_MAC_1588_TX_B 13 615 #define HCLGE_MAC_1588_RX_B 14 616 #define HCLGE_MAC_APP_LP_B 15 617 #define HCLGE_MAC_LINE_LP_B 16 618 #define HCLGE_MAC_FCS_TX_B 17 619 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 620 #define HCLGE_MAC_RX_FCS_STRIP_B 19 621 #define HCLGE_MAC_RX_FCS_B 20 622 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 623 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 624 625 struct hclge_config_mac_mode_cmd { 626 __le32 txrx_pad_fcs_loop_en; 627 u8 rsv[20]; 628 }; 629 630 struct hclge_pf_rst_sync_cmd { 631 #define HCLGE_PF_RST_ALL_VF_RDY_B 0 632 u8 all_vf_ready; 633 u8 rsv[23]; 634 }; 635 636 #define HCLGE_CFG_SPEED_S 0 637 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 638 639 #define HCLGE_CFG_DUPLEX_B 7 640 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 641 642 struct hclge_config_mac_speed_dup_cmd { 643 u8 speed_dup; 644 645 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 646 u8 mac_change_fec_en; 647 u8 rsv[22]; 648 }; 649 650 #define HCLGE_TQP_ENABLE_B 0 651 652 #define HCLGE_MAC_CFG_AN_EN_B 0 653 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 654 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 655 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 656 #define HCLGE_MAC_CFG_AN_RST_B 4 657 658 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 659 660 struct hclge_config_auto_neg_cmd { 661 __le32 cfg_an_cmd_flag; 662 u8 rsv[20]; 663 }; 664 665 struct hclge_sfp_info_cmd { 666 __le32 speed; 667 u8 query_type; /* 0: sfp speed, 1: active speed */ 668 u8 active_fec; 669 u8 autoneg; /* autoneg state */ 670 u8 autoneg_ability; /* whether support autoneg */ 671 __le32 speed_ability; /* speed ability for current media */ 672 __le32 module_type; 673 u8 rsv[8]; 674 }; 675 676 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 677 #define HCLGE_MAC_CFG_FEC_MODE_S 1 678 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 679 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 680 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 681 682 #define HCLGE_MAC_FEC_OFF 0 683 #define HCLGE_MAC_FEC_BASER 1 684 #define HCLGE_MAC_FEC_RS 2 685 struct hclge_config_fec_cmd { 686 u8 fec_mode; 687 u8 default_config; 688 u8 rsv[22]; 689 }; 690 691 #define HCLGE_MAC_UPLINK_PORT 0x100 692 693 struct hclge_config_max_frm_size_cmd { 694 __le16 max_frm_size; 695 u8 min_frm_size; 696 u8 rsv[21]; 697 }; 698 699 enum hclge_mac_vlan_tbl_opcode { 700 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 701 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 702 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 703 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 704 }; 705 706 enum hclge_mac_vlan_add_resp_code { 707 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 708 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 709 }; 710 711 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 712 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 713 #define HCLGE_MAC_EPORT_SW_EN_B 12 714 #define HCLGE_MAC_EPORT_TYPE_B 11 715 #define HCLGE_MAC_EPORT_VFID_S 3 716 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 717 #define HCLGE_MAC_EPORT_PFID_S 0 718 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 719 struct hclge_mac_vlan_tbl_entry_cmd { 720 u8 flags; 721 u8 resp_code; 722 __le16 vlan_tag; 723 __le32 mac_addr_hi32; 724 __le16 mac_addr_lo16; 725 __le16 rsv1; 726 u8 entry_type; 727 u8 mc_mac_en; 728 __le16 egress_port; 729 __le16 egress_queue; 730 u8 rsv2[6]; 731 }; 732 733 #define HCLGE_UMV_SPC_ALC_B 0 734 struct hclge_umv_spc_alc_cmd { 735 u8 allocate; 736 u8 rsv1[3]; 737 __le32 space_size; 738 u8 rsv2[16]; 739 }; 740 741 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 742 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 743 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 744 745 struct hclge_mac_mgr_tbl_entry_cmd { 746 u8 flags; 747 u8 resp_code; 748 __le16 vlan_tag; 749 u8 mac_addr[ETH_ALEN]; 750 __le16 rsv1; 751 __le16 ethter_type; 752 __le16 egress_port; 753 __le16 egress_queue; 754 u8 sw_port_id_aware; 755 u8 rsv2; 756 u8 i_port_bitmap; 757 u8 i_port_direction; 758 u8 rsv3[2]; 759 }; 760 761 struct hclge_vlan_filter_ctrl_cmd { 762 u8 vlan_type; 763 u8 vlan_fe; 764 u8 rsv1[2]; 765 u8 vf_id; 766 u8 rsv2[19]; 767 }; 768 769 #define HCLGE_VLAN_ID_OFFSET_STEP 160 770 #define HCLGE_VLAN_BYTE_SIZE 8 771 #define HCLGE_VLAN_OFFSET_BITMAP \ 772 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE) 773 774 struct hclge_vlan_filter_pf_cfg_cmd { 775 u8 vlan_offset; 776 u8 vlan_cfg; 777 u8 rsv[2]; 778 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP]; 779 }; 780 781 #define HCLGE_MAX_VF_BYTES 16 782 783 struct hclge_vlan_filter_vf_cfg_cmd { 784 __le16 vlan_id; 785 u8 resp_code; 786 u8 rsv; 787 u8 vlan_cfg; 788 u8 rsv1[3]; 789 u8 vf_bitmap[HCLGE_MAX_VF_BYTES]; 790 }; 791 792 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U 793 #define HCLGE_SWITCH_ALW_LPBK_B 1U 794 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U 795 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U 796 #define HCLGE_SWITCH_NO_MASK 0x0 797 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE 798 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD 799 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB 800 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7 801 802 struct hclge_mac_vlan_switch_cmd { 803 u8 roce_sel; 804 u8 rsv1[3]; 805 __le32 func_id; 806 u8 switch_param; 807 u8 rsv2[3]; 808 u8 param_mask; 809 u8 rsv3[11]; 810 }; 811 812 enum hclge_mac_vlan_cfg_sel { 813 HCLGE_MAC_VLAN_NIC_SEL = 0, 814 HCLGE_MAC_VLAN_ROCE_SEL, 815 }; 816 817 #define HCLGE_ACCEPT_TAG1_B 0 818 #define HCLGE_ACCEPT_UNTAG1_B 1 819 #define HCLGE_PORT_INS_TAG1_EN_B 2 820 #define HCLGE_PORT_INS_TAG2_EN_B 3 821 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 822 #define HCLGE_ACCEPT_TAG2_B 5 823 #define HCLGE_ACCEPT_UNTAG2_B 6 824 #define HCLGE_VF_NUM_PER_BYTE 8 825 826 struct hclge_vport_vtag_tx_cfg_cmd { 827 u8 vport_vlan_cfg; 828 u8 vf_offset; 829 u8 rsv1[2]; 830 __le16 def_vlan_tag1; 831 __le16 def_vlan_tag2; 832 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 833 u8 rsv2[8]; 834 }; 835 836 #define HCLGE_REM_TAG1_EN_B 0 837 #define HCLGE_REM_TAG2_EN_B 1 838 #define HCLGE_SHOW_TAG1_EN_B 2 839 #define HCLGE_SHOW_TAG2_EN_B 3 840 struct hclge_vport_vtag_rx_cfg_cmd { 841 u8 vport_vlan_cfg; 842 u8 vf_offset; 843 u8 rsv1[6]; 844 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 845 u8 rsv2[8]; 846 }; 847 848 struct hclge_tx_vlan_type_cfg_cmd { 849 __le16 ot_vlan_type; 850 __le16 in_vlan_type; 851 u8 rsv[20]; 852 }; 853 854 struct hclge_rx_vlan_type_cfg_cmd { 855 __le16 ot_fst_vlan_type; 856 __le16 ot_sec_vlan_type; 857 __le16 in_fst_vlan_type; 858 __le16 in_sec_vlan_type; 859 u8 rsv[16]; 860 }; 861 862 struct hclge_cfg_com_tqp_queue_cmd { 863 __le16 tqp_id; 864 __le16 stream_id; 865 u8 enable; 866 u8 rsv[19]; 867 }; 868 869 struct hclge_cfg_tx_queue_pointer_cmd { 870 __le16 tqp_id; 871 __le16 tx_tail; 872 __le16 tx_head; 873 __le16 fbd_num; 874 __le16 ring_offset; 875 u8 rsv[14]; 876 }; 877 878 #pragma pack(1) 879 struct hclge_mac_ethertype_idx_rd_cmd { 880 u8 flags; 881 u8 resp_code; 882 __le16 vlan_tag; 883 u8 mac_addr[ETH_ALEN]; 884 __le16 index; 885 __le16 ethter_type; 886 __le16 egress_port; 887 __le16 egress_queue; 888 __le16 rev0; 889 u8 i_port_bitmap; 890 u8 i_port_direction; 891 u8 rev1[2]; 892 }; 893 894 #pragma pack() 895 896 #define HCLGE_TSO_MSS_MIN_S 0 897 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 898 899 #define HCLGE_TSO_MSS_MAX_S 16 900 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 901 902 struct hclge_cfg_tso_status_cmd { 903 __le16 tso_mss_min; 904 __le16 tso_mss_max; 905 u8 rsv[20]; 906 }; 907 908 #define HCLGE_GRO_EN_B 0 909 struct hclge_cfg_gro_status_cmd { 910 u8 gro_en; 911 u8 rsv[23]; 912 }; 913 914 #define HCLGE_TSO_MSS_MIN 256 915 #define HCLGE_TSO_MSS_MAX 9668 916 917 #define HCLGE_TQP_RESET_B 0 918 struct hclge_reset_tqp_queue_cmd { 919 __le16 tqp_id; 920 u8 reset_req; 921 u8 ready_to_reset; 922 u8 rsv[20]; 923 }; 924 925 #define HCLGE_CFG_RESET_MAC_B 3 926 #define HCLGE_CFG_RESET_FUNC_B 7 927 struct hclge_reset_cmd { 928 u8 mac_func_reset; 929 u8 fun_reset_vfid; 930 u8 rsv[22]; 931 }; 932 933 #define HCLGE_PF_RESET_DONE_BIT BIT(0) 934 935 struct hclge_pf_rst_done_cmd { 936 u8 pf_rst_done; 937 u8 rsv[23]; 938 }; 939 940 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 941 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 942 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 943 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 944 struct hclge_serdes_lb_cmd { 945 u8 mask; 946 u8 enable; 947 u8 result; 948 u8 rsv[21]; 949 }; 950 951 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 952 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 953 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 954 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 955 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ 956 957 #define HCLGE_TYPE_CRQ 0 958 #define HCLGE_TYPE_CSQ 1 959 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 960 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 961 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 962 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 963 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 964 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 965 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 966 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 967 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 968 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 969 970 /* this bit indicates that the driver is ready for hardware reset */ 971 #define HCLGE_NIC_SW_RST_RDY_B 16 972 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B) 973 974 #define HCLGE_NIC_CMQ_DESC_NUM 1024 975 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 976 977 #define HCLGE_LED_LOCATE_STATE_S 0 978 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 979 980 struct hclge_set_led_state_cmd { 981 u8 rsv1[3]; 982 u8 locate_led_config; 983 u8 rsv2[20]; 984 }; 985 986 struct hclge_get_fd_mode_cmd { 987 u8 mode; 988 u8 enable; 989 u8 rsv[22]; 990 }; 991 992 struct hclge_get_fd_allocation_cmd { 993 __le32 stage1_entry_num; 994 __le32 stage2_entry_num; 995 __le16 stage1_counter_num; 996 __le16 stage2_counter_num; 997 u8 rsv[12]; 998 }; 999 1000 struct hclge_set_fd_key_config_cmd { 1001 u8 stage; 1002 u8 key_select; 1003 u8 inner_sipv6_word_en; 1004 u8 inner_dipv6_word_en; 1005 u8 outer_sipv6_word_en; 1006 u8 outer_dipv6_word_en; 1007 u8 rsv1[2]; 1008 __le32 tuple_mask; 1009 __le32 meta_data_mask; 1010 u8 rsv2[8]; 1011 }; 1012 1013 #define HCLGE_FD_EPORT_SW_EN_B 0 1014 struct hclge_fd_tcam_config_1_cmd { 1015 u8 stage; 1016 u8 xy_sel; 1017 u8 port_info; 1018 u8 rsv1[1]; 1019 __le32 index; 1020 u8 entry_vld; 1021 u8 rsv2[7]; 1022 u8 tcam_data[8]; 1023 }; 1024 1025 struct hclge_fd_tcam_config_2_cmd { 1026 u8 tcam_data[24]; 1027 }; 1028 1029 struct hclge_fd_tcam_config_3_cmd { 1030 u8 tcam_data[20]; 1031 u8 rsv[4]; 1032 }; 1033 1034 #define HCLGE_FD_AD_DROP_B 0 1035 #define HCLGE_FD_AD_DIRECT_QID_B 1 1036 #define HCLGE_FD_AD_QID_S 2 1037 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 1038 #define HCLGE_FD_AD_USE_COUNTER_B 12 1039 #define HCLGE_FD_AD_COUNTER_NUM_S 13 1040 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 1041 #define HCLGE_FD_AD_NXT_STEP_B 20 1042 #define HCLGE_FD_AD_NXT_KEY_S 21 1043 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 1044 #define HCLGE_FD_AD_WR_RULE_ID_B 0 1045 #define HCLGE_FD_AD_RULE_ID_S 1 1046 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 1047 1048 struct hclge_fd_ad_config_cmd { 1049 u8 stage; 1050 u8 rsv1[3]; 1051 __le32 index; 1052 __le64 ad_data; 1053 u8 rsv2[8]; 1054 }; 1055 1056 struct hclge_get_m7_bd_cmd { 1057 __le32 bd_num; 1058 u8 rsv[20]; 1059 }; 1060 1061 struct hclge_query_ppu_pf_other_int_dfx_cmd { 1062 __le16 over_8bd_no_fe_qid; 1063 __le16 over_8bd_no_fe_vf_id; 1064 __le16 tso_mss_cmp_min_err_qid; 1065 __le16 tso_mss_cmp_min_err_vf_id; 1066 __le16 tso_mss_cmp_max_err_qid; 1067 __le16 tso_mss_cmp_max_err_vf_id; 1068 __le16 tx_rd_fbd_poison_qid; 1069 __le16 tx_rd_fbd_poison_vf_id; 1070 __le16 rx_rd_fbd_poison_qid; 1071 __le16 rx_rd_fbd_poison_vf_id; 1072 u8 rsv[4]; 1073 }; 1074 1075 #define HCLGE_LINK_EVENT_REPORT_EN_B 0 1076 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1 1077 struct hclge_firmware_compat_cmd { 1078 __le32 compat; 1079 u8 rsv[20]; 1080 }; 1081 1082 #define HCLGE_SFP_INFO_CMD_NUM 6 1083 #define HCLGE_SFP_INFO_BD0_LEN 20 1084 #define HCLGE_SFP_INFO_BDX_LEN 24 1085 #define HCLGE_SFP_INFO_MAX_LEN \ 1086 (HCLGE_SFP_INFO_BD0_LEN + \ 1087 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN) 1088 1089 struct hclge_sfp_info_bd0_cmd { 1090 __le16 offset; 1091 __le16 read_len; 1092 u8 data[HCLGE_SFP_INFO_BD0_LEN]; 1093 }; 1094 1095 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4 1096 1097 struct hclge_dev_specs_0_cmd { 1098 __le32 rsv0; 1099 __le32 mac_entry_num; 1100 __le32 mng_entry_num; 1101 __le16 rss_ind_tbl_size; 1102 __le16 rss_key_size; 1103 __le16 int_ql_max; 1104 u8 max_non_tso_bd_num; 1105 u8 rsv1; 1106 __le32 max_tm_rate; 1107 }; 1108 1109 #define HCLGE_DEF_MAX_INT_GL 0x1FE0U 1110 1111 struct hclge_dev_specs_1_cmd { 1112 __le32 rsv0; 1113 __le16 max_int_gl; 1114 u8 rsv1[18]; 1115 }; 1116 1117 int hclge_cmd_init(struct hclge_dev *hdev); 1118 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 1119 { 1120 writel(value, base + reg); 1121 } 1122 1123 #define hclge_write_dev(a, reg, value) \ 1124 hclge_write_reg((a)->io_base, (reg), (value)) 1125 #define hclge_read_dev(a, reg) \ 1126 hclge_read_reg((a)->io_base, (reg)) 1127 1128 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 1129 { 1130 u8 __iomem *reg_addr = READ_ONCE(base); 1131 1132 return readl(reg_addr + reg); 1133 } 1134 1135 #define HCLGE_SEND_SYNC(flag) \ 1136 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 1137 1138 struct hclge_hw; 1139 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 1140 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 1141 enum hclge_opcode_type opcode, bool is_read); 1142 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 1143 1144 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 1145 struct hclge_desc *desc); 1146 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 1147 struct hclge_desc *desc); 1148 1149 void hclge_cmd_uninit(struct hclge_dev *hdev); 1150 int hclge_cmd_queue_init(struct hclge_dev *hdev); 1151 #endif 1152