1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HCLGE_CMD_H 11 #define __HCLGE_CMD_H 12 #include <linux/types.h> 13 #include <linux/io.h> 14 15 #define HCLGE_CMDQ_TX_TIMEOUT 1000 16 17 struct hclge_dev; 18 struct hclge_desc { 19 __le16 opcode; 20 21 #define HCLGE_CMDQ_RX_INVLD_B 0 22 #define HCLGE_CMDQ_RX_OUTVLD_B 1 23 24 __le16 flag; 25 __le16 retval; 26 __le16 rsv; 27 __le32 data[6]; 28 }; 29 30 struct hclge_desc_cb { 31 dma_addr_t dma; 32 void *va; 33 u32 length; 34 }; 35 36 struct hclge_cmq_ring { 37 dma_addr_t desc_dma_addr; 38 struct hclge_desc *desc; 39 struct hclge_desc_cb *desc_cb; 40 struct hclge_dev *dev; 41 u32 head; 42 u32 tail; 43 44 u16 buf_size; 45 u16 desc_num; 46 int next_to_use; 47 int next_to_clean; 48 u8 flag; 49 spinlock_t lock; /* Command queue lock */ 50 }; 51 52 enum hclge_cmd_return_status { 53 HCLGE_CMD_EXEC_SUCCESS = 0, 54 HCLGE_CMD_NO_AUTH = 1, 55 HCLGE_CMD_NOT_EXEC = 2, 56 HCLGE_CMD_QUEUE_FULL = 3, 57 }; 58 59 enum hclge_cmd_status { 60 HCLGE_STATUS_SUCCESS = 0, 61 HCLGE_ERR_CSQ_FULL = -1, 62 HCLGE_ERR_CSQ_TIMEOUT = -2, 63 HCLGE_ERR_CSQ_ERROR = -3, 64 }; 65 66 struct hclge_misc_vector { 67 u8 __iomem *addr; 68 int vector_irq; 69 }; 70 71 struct hclge_cmq { 72 struct hclge_cmq_ring csq; 73 struct hclge_cmq_ring crq; 74 u16 tx_timeout; /* Tx timeout */ 75 enum hclge_cmd_status last_status; 76 }; 77 78 #define HCLGE_CMD_FLAG_IN_VALID_SHIFT 0 79 #define HCLGE_CMD_FLAG_OUT_VALID_SHIFT 1 80 #define HCLGE_CMD_FLAG_NEXT_SHIFT 2 81 #define HCLGE_CMD_FLAG_WR_OR_RD_SHIFT 3 82 #define HCLGE_CMD_FLAG_NO_INTR_SHIFT 4 83 #define HCLGE_CMD_FLAG_ERR_INTR_SHIFT 5 84 85 #define HCLGE_CMD_FLAG_IN BIT(HCLGE_CMD_FLAG_IN_VALID_SHIFT) 86 #define HCLGE_CMD_FLAG_OUT BIT(HCLGE_CMD_FLAG_OUT_VALID_SHIFT) 87 #define HCLGE_CMD_FLAG_NEXT BIT(HCLGE_CMD_FLAG_NEXT_SHIFT) 88 #define HCLGE_CMD_FLAG_WR BIT(HCLGE_CMD_FLAG_WR_OR_RD_SHIFT) 89 #define HCLGE_CMD_FLAG_NO_INTR BIT(HCLGE_CMD_FLAG_NO_INTR_SHIFT) 90 #define HCLGE_CMD_FLAG_ERR_INTR BIT(HCLGE_CMD_FLAG_ERR_INTR_SHIFT) 91 92 enum hclge_opcode_type { 93 /* Generic command */ 94 HCLGE_OPC_QUERY_FW_VER = 0x0001, 95 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 96 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 97 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 98 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 99 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 100 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 101 102 HCLGE_OPC_STATS_64_BIT = 0x0030, 103 HCLGE_OPC_STATS_32_BIT = 0x0031, 104 HCLGE_OPC_STATS_MAC = 0x0032, 105 /* Device management command */ 106 107 /* MAC commond */ 108 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 109 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 110 HCLGE_OPC_QUERY_AN_RESULT = 0x0306, 111 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 112 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 113 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 114 /* MACSEC command */ 115 116 /* PFC/Pause CMD*/ 117 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 118 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 119 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 120 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 121 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 122 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 123 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 124 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 125 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 126 HCLGE_OPC_QOS_MAP = 0x070A, 127 128 /* ETS/scheduler commands */ 129 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 130 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 131 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 132 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 133 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 134 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 135 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 136 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 137 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 138 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 139 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 140 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 141 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 142 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 143 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 144 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 145 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 146 147 /* Packet buffer allocate command */ 148 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 149 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 150 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 151 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 152 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 153 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 154 155 /* PTP command */ 156 /* TQP management command */ 157 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 158 159 /* TQP command */ 160 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 161 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 162 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 163 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 164 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 165 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 166 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 167 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 168 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 169 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 170 171 /* TSO cmd */ 172 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 173 174 /* RSS cmd */ 175 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 176 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 177 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 178 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 179 180 /* Promisuous mode command */ 181 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 182 183 /* Vlan offload command */ 184 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 185 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 186 187 /* Interrupts cmd */ 188 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 189 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 190 191 /* MAC command */ 192 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 193 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 194 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 195 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 196 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 197 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 198 HCLGE_OPC_MAC_VLAN_MASK_SET = 0x1012, 199 200 /* Multicast linear table cmd */ 201 HCLGE_OPC_MTA_MAC_MODE_CFG = 0x1020, 202 HCLGE_OPC_MTA_MAC_FUNC_CFG = 0x1021, 203 HCLGE_OPC_MTA_TBL_ITEM_CFG = 0x1022, 204 HCLGE_OPC_MTA_TBL_ITEM_QUERY = 0x1023, 205 206 /* VLAN command */ 207 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 208 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 209 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 210 211 /* MDIO command */ 212 HCLGE_OPC_MDIO_CONFIG = 0x1900, 213 214 /* QCN command */ 215 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 216 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 217 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 218 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 219 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 220 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 221 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 222 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 223 224 /* Mailbox cmd */ 225 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 226 }; 227 228 #define HCLGE_TQP_REG_OFFSET 0x80000 229 #define HCLGE_TQP_REG_SIZE 0x200 230 231 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 232 #define HCLGE_RCB_INIT_FLAG_EN_B 0 233 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 234 struct hclge_config_rcb_init_cmd { 235 __le16 rcb_init_flag; 236 u8 rsv[22]; 237 }; 238 239 struct hclge_tqp_map_cmd { 240 __le16 tqp_id; /* Absolute tqp id for in this pf */ 241 u8 tqp_vf; /* VF id */ 242 #define HCLGE_TQP_MAP_TYPE_PF 0 243 #define HCLGE_TQP_MAP_TYPE_VF 1 244 #define HCLGE_TQP_MAP_TYPE_B 0 245 #define HCLGE_TQP_MAP_EN_B 1 246 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 247 __le16 tqp_vid; /* Virtual id in this pf/vf */ 248 u8 rsv[18]; 249 }; 250 251 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 252 253 enum hclge_int_type { 254 HCLGE_INT_TX, 255 HCLGE_INT_RX, 256 HCLGE_INT_EVENT, 257 }; 258 259 struct hclge_ctrl_vector_chain_cmd { 260 u8 int_vector_id; 261 u8 int_cause_num; 262 #define HCLGE_INT_TYPE_S 0 263 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 264 #define HCLGE_TQP_ID_S 2 265 #define HCLGE_TQP_ID_M GENMASK(12, 2) 266 #define HCLGE_INT_GL_IDX_S 13 267 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 268 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 269 u8 vfid; 270 u8 rsv; 271 }; 272 273 #define HCLGE_TC_NUM 8 274 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 275 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 276 struct hclge_tx_buff_alloc_cmd { 277 __le16 tx_pkt_buff[HCLGE_TC_NUM]; 278 u8 tx_buff_rsv[8]; 279 }; 280 281 struct hclge_rx_priv_buff_cmd { 282 __le16 buf_num[HCLGE_TC_NUM]; 283 __le16 shared_buf; 284 u8 rsv[6]; 285 }; 286 287 struct hclge_query_version_cmd { 288 __le32 firmware; 289 __le32 firmware_rsv[5]; 290 }; 291 292 #define HCLGE_RX_PRIV_EN_B 15 293 #define HCLGE_TC_NUM_ONE_DESC 4 294 struct hclge_priv_wl { 295 __le16 high; 296 __le16 low; 297 }; 298 299 struct hclge_rx_priv_wl_buf { 300 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 301 }; 302 303 struct hclge_rx_com_thrd { 304 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 305 }; 306 307 struct hclge_rx_com_wl { 308 struct hclge_priv_wl com_wl; 309 }; 310 311 struct hclge_waterline { 312 u32 low; 313 u32 high; 314 }; 315 316 struct hclge_tc_thrd { 317 u32 low; 318 u32 high; 319 }; 320 321 struct hclge_priv_buf { 322 struct hclge_waterline wl; /* Waterline for low and high*/ 323 u32 buf_size; /* TC private buffer size */ 324 u32 tx_buf_size; 325 u32 enable; /* Enable TC private buffer or not */ 326 }; 327 328 #define HCLGE_MAX_TC_NUM 8 329 struct hclge_shared_buf { 330 struct hclge_waterline self; 331 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 332 u32 buf_size; 333 }; 334 335 struct hclge_pkt_buf_alloc { 336 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 337 struct hclge_shared_buf s_buf; 338 }; 339 340 #define HCLGE_RX_COM_WL_EN_B 15 341 struct hclge_rx_com_wl_buf_cmd { 342 __le16 high_wl; 343 __le16 low_wl; 344 u8 rsv[20]; 345 }; 346 347 #define HCLGE_RX_PKT_EN_B 15 348 struct hclge_rx_pkt_buf_cmd { 349 __le16 high_pkt; 350 __le16 low_pkt; 351 u8 rsv[20]; 352 }; 353 354 #define HCLGE_PF_STATE_DONE_B 0 355 #define HCLGE_PF_STATE_MAIN_B 1 356 #define HCLGE_PF_STATE_BOND_B 2 357 #define HCLGE_PF_STATE_MAC_N_B 6 358 #define HCLGE_PF_MAC_NUM_MASK 0x3 359 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 360 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 361 struct hclge_func_status_cmd { 362 __le32 vf_rst_state[4]; 363 u8 pf_state; 364 u8 mac_id; 365 u8 rsv1; 366 u8 pf_cnt_in_mac; 367 u8 pf_num; 368 u8 vf_num; 369 u8 rsv[2]; 370 }; 371 372 struct hclge_pf_res_cmd { 373 __le16 tqp_num; 374 __le16 buf_size; 375 __le16 msixcap_localid_ba_nic; 376 __le16 msixcap_localid_ba_rocee; 377 #define HCLGE_PF_VEC_NUM_S 0 378 #define HCLGE_PF_VEC_NUM_M (0xff << HCLGE_PF_VEC_NUM_S) 379 __le16 pf_intr_vector_number; 380 __le16 pf_own_fun_number; 381 __le32 rsv[3]; 382 }; 383 384 #define HCLGE_CFG_OFFSET_S 0 385 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 386 #define HCLGE_CFG_RD_LEN_S 24 387 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 388 #define HCLGE_CFG_RD_LEN_BYTES 16 389 #define HCLGE_CFG_RD_LEN_UNIT 4 390 391 #define HCLGE_CFG_VMDQ_S 0 392 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 393 #define HCLGE_CFG_TC_NUM_S 8 394 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 395 #define HCLGE_CFG_TQP_DESC_N_S 16 396 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 397 #define HCLGE_CFG_PHY_ADDR_S 0 398 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 399 #define HCLGE_CFG_MEDIA_TP_S 8 400 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 401 #define HCLGE_CFG_RX_BUF_LEN_S 16 402 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 403 #define HCLGE_CFG_MAC_ADDR_H_S 0 404 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 405 #define HCLGE_CFG_DEFAULT_SPEED_S 16 406 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 407 #define HCLGE_CFG_RSS_SIZE_S 24 408 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 409 410 struct hclge_cfg_param_cmd { 411 __le32 offset; 412 __le32 rsv; 413 __le32 param[4]; 414 }; 415 416 #define HCLGE_MAC_MODE 0x0 417 #define HCLGE_DESC_NUM 0x40 418 419 #define HCLGE_ALLOC_VALID_B 0 420 struct hclge_vf_num_cmd { 421 u8 alloc_valid; 422 u8 rsv[23]; 423 }; 424 425 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 426 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 427 #define HCLGE_RSS_HASH_KEY_NUM 16 428 struct hclge_rss_config_cmd { 429 u8 hash_config; 430 u8 rsv[7]; 431 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 432 }; 433 434 struct hclge_rss_input_tuple_cmd { 435 u8 ipv4_tcp_en; 436 u8 ipv4_udp_en; 437 u8 ipv4_sctp_en; 438 u8 ipv4_fragment_en; 439 u8 ipv6_tcp_en; 440 u8 ipv6_udp_en; 441 u8 ipv6_sctp_en; 442 u8 ipv6_fragment_en; 443 u8 rsv[16]; 444 }; 445 446 #define HCLGE_RSS_CFG_TBL_SIZE 16 447 448 struct hclge_rss_indirection_table_cmd { 449 __le16 start_table_index; 450 __le16 rss_set_bitmap; 451 u8 rsv[4]; 452 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 453 }; 454 455 #define HCLGE_RSS_TC_OFFSET_S 0 456 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 457 #define HCLGE_RSS_TC_SIZE_S 12 458 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 459 #define HCLGE_RSS_TC_VALID_B 15 460 struct hclge_rss_tc_mode_cmd { 461 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 462 u8 rsv[8]; 463 }; 464 465 #define HCLGE_LINK_STS_B 0 466 #define HCLGE_LINK_STATUS BIT(HCLGE_LINK_STS_B) 467 struct hclge_link_status_cmd { 468 u8 status; 469 u8 rsv[23]; 470 }; 471 472 struct hclge_promisc_param { 473 u8 vf_id; 474 u8 enable; 475 }; 476 477 #define HCLGE_PROMISC_EN_B 1 478 #define HCLGE_PROMISC_EN_ALL 0x7 479 #define HCLGE_PROMISC_EN_UC 0x1 480 #define HCLGE_PROMISC_EN_MC 0x2 481 #define HCLGE_PROMISC_EN_BC 0x4 482 struct hclge_promisc_cfg_cmd { 483 u8 flag; 484 u8 vf_id; 485 __le16 rsv0; 486 u8 rsv1[20]; 487 }; 488 489 enum hclge_promisc_type { 490 HCLGE_UNICAST = 1, 491 HCLGE_MULTICAST = 2, 492 HCLGE_BROADCAST = 3, 493 }; 494 495 #define HCLGE_MAC_TX_EN_B 6 496 #define HCLGE_MAC_RX_EN_B 7 497 #define HCLGE_MAC_PAD_TX_B 11 498 #define HCLGE_MAC_PAD_RX_B 12 499 #define HCLGE_MAC_1588_TX_B 13 500 #define HCLGE_MAC_1588_RX_B 14 501 #define HCLGE_MAC_APP_LP_B 15 502 #define HCLGE_MAC_LINE_LP_B 16 503 #define HCLGE_MAC_FCS_TX_B 17 504 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 505 #define HCLGE_MAC_RX_FCS_STRIP_B 19 506 #define HCLGE_MAC_RX_FCS_B 20 507 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 508 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 509 510 struct hclge_config_mac_mode_cmd { 511 __le32 txrx_pad_fcs_loop_en; 512 u8 rsv[20]; 513 }; 514 515 #define HCLGE_CFG_SPEED_S 0 516 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 517 518 #define HCLGE_CFG_DUPLEX_B 7 519 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 520 521 struct hclge_config_mac_speed_dup_cmd { 522 u8 speed_dup; 523 524 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 525 u8 mac_change_fec_en; 526 u8 rsv[22]; 527 }; 528 529 #define HCLGE_QUERY_SPEED_S 3 530 #define HCLGE_QUERY_AN_B 0 531 #define HCLGE_QUERY_DUPLEX_B 2 532 533 #define HCLGE_QUERY_SPEED_M GENMASK(4, 0) 534 #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B) 535 #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B) 536 537 struct hclge_query_an_speed_dup_cmd { 538 u8 an_syn_dup_speed; 539 u8 pause; 540 u8 rsv[23]; 541 }; 542 543 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 544 #define HCLGE_TQP_ENABLE_B 0 545 546 #define HCLGE_MAC_CFG_AN_EN_B 0 547 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 548 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 549 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 550 #define HCLGE_MAC_CFG_AN_RST_B 4 551 552 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 553 554 struct hclge_config_auto_neg_cmd { 555 __le32 cfg_an_cmd_flag; 556 u8 rsv[20]; 557 }; 558 559 #define HCLGE_MAC_MIN_MTU 64 560 #define HCLGE_MAC_MAX_MTU 9728 561 #define HCLGE_MAC_UPLINK_PORT 0x100 562 563 struct hclge_config_max_frm_size_cmd { 564 __le16 max_frm_size; 565 u8 rsv[22]; 566 }; 567 568 enum hclge_mac_vlan_tbl_opcode { 569 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 570 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 571 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 572 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 573 }; 574 575 #define HCLGE_MAC_VLAN_BIT0_EN_B 0x0 576 #define HCLGE_MAC_VLAN_BIT1_EN_B 0x1 577 #define HCLGE_MAC_EPORT_SW_EN_B 0xc 578 #define HCLGE_MAC_EPORT_TYPE_B 0xb 579 #define HCLGE_MAC_EPORT_VFID_S 0x3 580 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 581 #define HCLGE_MAC_EPORT_PFID_S 0x0 582 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 583 struct hclge_mac_vlan_tbl_entry_cmd { 584 u8 flags; 585 u8 resp_code; 586 __le16 vlan_tag; 587 __le32 mac_addr_hi32; 588 __le16 mac_addr_lo16; 589 __le16 rsv1; 590 u8 entry_type; 591 u8 mc_mac_en; 592 __le16 egress_port; 593 __le16 egress_queue; 594 u8 rsv2[6]; 595 }; 596 597 #define HCLGE_VLAN_MASK_EN_B 0x0 598 struct hclge_mac_vlan_mask_entry_cmd { 599 u8 rsv0[2]; 600 u8 vlan_mask; 601 u8 rsv1; 602 u8 mac_mask[6]; 603 u8 rsv2[14]; 604 }; 605 606 #define HCLGE_CFG_MTA_MAC_SEL_S 0x0 607 #define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0) 608 #define HCLGE_CFG_MTA_MAC_EN_B 0x7 609 struct hclge_mta_filter_mode_cmd { 610 u8 dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */ 611 u8 rsv[23]; 612 }; 613 614 #define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0x0 615 struct hclge_cfg_func_mta_filter_cmd { 616 u8 accept; /* Only used lowest 1 bit */ 617 u8 function_id; 618 u8 rsv[22]; 619 }; 620 621 #define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0x0 622 #define HCLGE_CFG_MTA_ITEM_IDX_S 0x0 623 #define HCLGE_CFG_MTA_ITEM_IDX_M GENMASK(11, 0) 624 struct hclge_cfg_func_mta_item_cmd { 625 __le16 item_idx; /* Only used lowest 12 bit */ 626 u8 accept; /* Only used lowest 1 bit */ 627 u8 rsv[21]; 628 }; 629 630 struct hclge_mac_vlan_add_cmd { 631 __le16 flags; 632 __le16 mac_addr_hi16; 633 __le32 mac_addr_lo32; 634 __le32 mac_addr_msk_hi32; 635 __le16 mac_addr_msk_lo16; 636 __le16 vlan_tag; 637 __le16 ingress_port; 638 __le16 egress_port; 639 u8 rsv[4]; 640 }; 641 642 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 643 struct hclge_mac_vlan_remove_cmd { 644 __le16 flags; 645 __le16 mac_addr_hi16; 646 __le32 mac_addr_lo32; 647 __le32 mac_addr_msk_hi32; 648 __le16 mac_addr_msk_lo16; 649 __le16 vlan_tag; 650 __le16 ingress_port; 651 __le16 egress_port; 652 u8 rsv[4]; 653 }; 654 655 struct hclge_vlan_filter_ctrl_cmd { 656 u8 vlan_type; 657 u8 vlan_fe; 658 u8 rsv[22]; 659 }; 660 661 struct hclge_vlan_filter_pf_cfg_cmd { 662 u8 vlan_offset; 663 u8 vlan_cfg; 664 u8 rsv[2]; 665 u8 vlan_offset_bitmap[20]; 666 }; 667 668 struct hclge_vlan_filter_vf_cfg_cmd { 669 __le16 vlan_id; 670 u8 resp_code; 671 u8 rsv; 672 u8 vlan_cfg; 673 u8 rsv1[3]; 674 u8 vf_bitmap[16]; 675 }; 676 677 #define HCLGE_ACCEPT_TAG_B 0 678 #define HCLGE_ACCEPT_UNTAG_B 1 679 #define HCLGE_PORT_INS_TAG1_EN_B 2 680 #define HCLGE_PORT_INS_TAG2_EN_B 3 681 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 682 struct hclge_vport_vtag_tx_cfg_cmd { 683 u8 vport_vlan_cfg; 684 u8 vf_offset; 685 u8 rsv1[2]; 686 __le16 def_vlan_tag1; 687 __le16 def_vlan_tag2; 688 u8 vf_bitmap[8]; 689 u8 rsv2[8]; 690 }; 691 692 #define HCLGE_REM_TAG1_EN_B 0 693 #define HCLGE_REM_TAG2_EN_B 1 694 #define HCLGE_SHOW_TAG1_EN_B 2 695 #define HCLGE_SHOW_TAG2_EN_B 3 696 struct hclge_vport_vtag_rx_cfg_cmd { 697 u8 vport_vlan_cfg; 698 u8 vf_offset; 699 u8 rsv1[6]; 700 u8 vf_bitmap[8]; 701 u8 rsv2[8]; 702 }; 703 704 struct hclge_tx_vlan_type_cfg_cmd { 705 __le16 ot_vlan_type; 706 __le16 in_vlan_type; 707 u8 rsv[20]; 708 }; 709 710 struct hclge_rx_vlan_type_cfg_cmd { 711 __le16 ot_fst_vlan_type; 712 __le16 ot_sec_vlan_type; 713 __le16 in_fst_vlan_type; 714 __le16 in_sec_vlan_type; 715 u8 rsv[16]; 716 }; 717 718 struct hclge_cfg_com_tqp_queue_cmd { 719 __le16 tqp_id; 720 __le16 stream_id; 721 u8 enable; 722 u8 rsv[19]; 723 }; 724 725 struct hclge_cfg_tx_queue_pointer_cmd { 726 __le16 tqp_id; 727 __le16 tx_tail; 728 __le16 tx_head; 729 __le16 fbd_num; 730 __le16 ring_offset; 731 u8 rsv[14]; 732 }; 733 734 #define HCLGE_TSO_MSS_MIN_S 0 735 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 736 737 #define HCLGE_TSO_MSS_MAX_S 16 738 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 739 740 struct hclge_cfg_tso_status_cmd { 741 __le16 tso_mss_min; 742 __le16 tso_mss_max; 743 u8 rsv[20]; 744 }; 745 746 #define HCLGE_TSO_MSS_MIN 256 747 #define HCLGE_TSO_MSS_MAX 9668 748 749 #define HCLGE_TQP_RESET_B 0 750 struct hclge_reset_tqp_queue_cmd { 751 __le16 tqp_id; 752 u8 reset_req; 753 u8 ready_to_reset; 754 u8 rsv[20]; 755 }; 756 757 #define HCLGE_CFG_RESET_MAC_B 3 758 #define HCLGE_CFG_RESET_FUNC_B 7 759 struct hclge_reset_cmd { 760 u8 mac_func_reset; 761 u8 fun_reset_vfid; 762 u8 rsv[22]; 763 }; 764 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 765 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 766 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 767 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 768 769 #define HCLGE_TYPE_CRQ 0 770 #define HCLGE_TYPE_CSQ 1 771 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 772 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 773 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 774 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 775 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 776 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 777 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 778 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 779 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 780 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 781 #define HCLGE_NIC_CMQ_EN_B 16 782 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 783 #define HCLGE_NIC_CMQ_DESC_NUM 1024 784 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 785 786 int hclge_cmd_init(struct hclge_dev *hdev); 787 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 788 { 789 writel(value, base + reg); 790 } 791 792 #define hclge_write_dev(a, reg, value) \ 793 hclge_write_reg((a)->io_base, (reg), (value)) 794 #define hclge_read_dev(a, reg) \ 795 hclge_read_reg((a)->io_base, (reg)) 796 797 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 798 { 799 u8 __iomem *reg_addr = READ_ONCE(base); 800 801 return readl(reg_addr + reg); 802 } 803 804 #define HCLGE_SEND_SYNC(flag) \ 805 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 806 807 struct hclge_hw; 808 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 809 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 810 enum hclge_opcode_type opcode, bool is_read); 811 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 812 813 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 814 struct hclge_promisc_param *param); 815 816 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 817 struct hclge_desc *desc); 818 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 819 struct hclge_desc *desc); 820 821 void hclge_destroy_cmd_queue(struct hclge_hw *hw); 822 int hclge_cmd_queue_init(struct hclge_dev *hdev); 823 #endif 824